1 #include <linux/init.h>
2 #include <linux/kernel.h>
4 #include <linux/string.h>
5 #include <linux/bitops.h>
7 #include <linux/sched.h>
8 #include <linux/thread_info.h>
9 #include <linux/module.h>
11 #include <asm/processor.h>
12 #include <asm/pgtable.h>
14 #include <asm/uaccess.h>
20 #include <asm/topology.h>
21 #include <asm/numa_64.h>
26 #ifdef CONFIG_X86_LOCAL_APIC
27 #include <asm/mpspec.h>
31 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
33 /* Unmask CPUID levels if masked: */
34 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
37 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
39 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
40 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
41 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
42 c->cpuid_level = cpuid_eax(0);
46 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
47 (c->x86 == 0x6 && c->x86_model >= 0x0e))
48 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
51 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
53 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
54 if (c->x86 == 15 && c->x86_cache_alignment == 64)
55 c->x86_cache_alignment = 128;
59 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
60 * with P/T states and does not stop in deep C-states.
62 * It is also reliable across cores and sockets. (but not across
63 * cabinets - we turn it off in that case explicitly.)
65 if (c->x86_power & (1 << 8)) {
66 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
67 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
68 set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
69 sched_clock_stable = 1;
73 * There is a known erratum on Pentium III and Core Solo
75 * " Page with PAT set to WC while associated MTRR is UC
76 * may consolidate to UC "
77 * Because of this erratum, it is better to stick with
78 * setting WC in MTRR rather than using PAT on these CPUs.
80 * Enable PAT WC only on P4, Core 2 or later CPUs.
82 if (c->x86 == 6 && c->x86_model < 15)
83 clear_cpu_cap(c, X86_FEATURE_PAT);
88 * Early probe support logic for ppro memory erratum #50
90 * This is called before we do cpu ident work
93 int __cpuinit ppro_with_ram_bug(void)
95 /* Uses data from early_cpu_detect now */
96 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
97 boot_cpu_data.x86 == 6 &&
98 boot_cpu_data.x86_model == 1 &&
99 boot_cpu_data.x86_mask < 8) {
100 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
106 #ifdef CONFIG_X86_F00F_BUG
107 static void __cpuinit trap_init_f00f_bug(void)
109 __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
112 * Update the IDT descriptor and reload the IDT so that
113 * it uses the read-only mapped virtual address.
115 idt_descr.address = fix_to_virt(FIX_F00F_IDT);
116 load_idt(&idt_descr);
120 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
123 /* calling is from identify_secondary_cpu() ? */
124 if (c->cpu_index == boot_cpu_id)
128 * Mask B, Pentium, but not Pentium MMX
131 c->x86_mask >= 1 && c->x86_mask <= 4 &&
134 * Remember we have B step Pentia with bugs
136 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
137 "with B stepping processors.\n");
142 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
144 unsigned long lo, hi;
146 #ifdef CONFIG_X86_F00F_BUG
148 * All current models of Pentium and Pentium with MMX technology CPUs
149 * have the F0 0F bug, which lets nonprivileged users lock up the system.
150 * Note that the workaround only should be initialized once...
153 if (!paravirt_enabled() && c->x86 == 5) {
154 static int f00f_workaround_enabled;
157 if (!f00f_workaround_enabled) {
158 trap_init_f00f_bug();
159 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
160 f00f_workaround_enabled = 1;
166 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
169 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
170 clear_cpu_cap(c, X86_FEATURE_SEP);
173 * P4 Xeon errata 037 workaround.
174 * Hardware prefetcher may cause stale data to be loaded into the cache.
176 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
177 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
178 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
179 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
180 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
181 lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
182 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
187 * See if we have a good local APIC by checking for buggy Pentia,
188 * i.e. all B steppings and the C2 stepping of P54C when using their
189 * integrated APIC (see 11AP erratum in "Pentium Processor
190 * Specification Update").
192 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
193 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
194 set_cpu_cap(c, X86_FEATURE_11AP);
197 #ifdef CONFIG_X86_INTEL_USERCOPY
199 * Set up the preferred alignment for movsl bulk memory moves
202 case 4: /* 486: untested */
204 case 5: /* Old Pentia: untested */
206 case 6: /* PII/PIII only like movsl with 8-byte alignment */
209 case 15: /* P4 is OK down to 8-byte alignment */
215 #ifdef CONFIG_X86_NUMAQ
222 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
227 static void __cpuinit srat_detect_node(void)
229 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
231 int cpu = smp_processor_id();
232 int apicid = hard_smp_processor_id();
234 /* Don't do the funky fallback heuristics the AMD version employs
236 node = apicid_to_node[apicid];
237 if (node == NUMA_NO_NODE || !node_online(node))
238 node = first_node(node_online_map);
239 numa_set_node(cpu, node);
241 printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
246 * find out the number of processor cores on the die
248 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
250 unsigned int eax, ebx, ecx, edx;
252 if (c->cpuid_level < 4)
255 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
256 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
258 return ((eax >> 26) + 1);
263 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
265 /* Intel VMX MSR indicated features */
266 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
267 #define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
268 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
269 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
270 #define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
271 #define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
273 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
275 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
276 clear_cpu_cap(c, X86_FEATURE_VNMI);
277 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
278 clear_cpu_cap(c, X86_FEATURE_EPT);
279 clear_cpu_cap(c, X86_FEATURE_VPID);
281 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
282 msr_ctl = vmx_msr_high | vmx_msr_low;
283 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
284 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
285 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
286 set_cpu_cap(c, X86_FEATURE_VNMI);
287 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
288 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
289 vmx_msr_low, vmx_msr_high);
290 msr_ctl2 = vmx_msr_high | vmx_msr_low;
291 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
292 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
293 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
294 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
295 set_cpu_cap(c, X86_FEATURE_EPT);
296 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
297 set_cpu_cap(c, X86_FEATURE_VPID);
301 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
307 intel_workarounds(c);
310 * Detect the extended topology information if available. This
311 * will reinitialise the initial_apicid which will be used
312 * in init_intel_cacheinfo()
314 detect_extended_topology(c);
316 l2 = init_intel_cacheinfo(c);
317 if (c->cpuid_level > 9) {
318 unsigned eax = cpuid_eax(10);
319 /* Check for version and the number of counters */
320 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
321 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
325 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
328 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
330 set_cpu_cap(c, X86_FEATURE_BTS);
332 set_cpu_cap(c, X86_FEATURE_PEBS);
336 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
337 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
341 c->x86_cache_alignment = c->x86_clflush_size * 2;
343 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
346 * Names for the Pentium II/Celeron processors
347 * detectable only by also checking the cache size.
348 * Dixon is NOT a Celeron.
353 switch (c->x86_model) {
355 if (c->x86_mask == 0) {
357 p = "Celeron (Covington)";
359 p = "Mobile Pentium II (Dixon)";
365 p = "Celeron (Mendocino)";
366 else if (c->x86_mask == 0 || c->x86_mask == 5)
372 p = "Celeron (Coppermine)";
377 strcpy(c->x86_model_id, p);
381 set_cpu_cap(c, X86_FEATURE_P4);
383 set_cpu_cap(c, X86_FEATURE_P3);
386 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
388 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
391 c->x86_max_cores = intel_num_cpu_cores(c);
397 /* Work around errata */
400 if (cpu_has(c, X86_FEATURE_VMX))
401 detect_vmx_virtcap(c);
405 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
408 * Intel PIII Tualatin. This comes in two flavours.
409 * One has 256kb of cache, the other 512. We have no way
410 * to determine which, so we use a boottime override
411 * for the 512kb model, and assume 256 otherwise.
413 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
419 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
421 .c_ident = { "GenuineIntel" },
424 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
426 [0] = "486 DX-25/33",
437 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
439 [0] = "Pentium 60/66 A-step",
440 [1] = "Pentium 60/66",
441 [2] = "Pentium 75 - 200",
442 [3] = "OverDrive PODP5V83",
444 [7] = "Mobile Pentium 75 - 200",
445 [8] = "Mobile Pentium MMX"
448 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
450 [0] = "Pentium Pro A-step",
452 [3] = "Pentium II (Klamath)",
453 [4] = "Pentium II (Deschutes)",
454 [5] = "Pentium II (Deschutes)",
455 [6] = "Mobile Pentium II",
456 [7] = "Pentium III (Katmai)",
457 [8] = "Pentium III (Coppermine)",
458 [10] = "Pentium III (Cascades)",
459 [11] = "Pentium III (Tualatin)",
462 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
464 [0] = "Pentium 4 (Unknown)",
465 [1] = "Pentium 4 (Willamette)",
466 [2] = "Pentium 4 (Northwood)",
467 [4] = "Pentium 4 (Foster)",
468 [5] = "Pentium 4 (Foster)",
472 .c_size_cache = intel_size_cache,
474 .c_early_init = early_init_intel,
475 .c_init = init_intel,
476 .c_x86_vendor = X86_VENDOR_INTEL,
479 cpu_dev_register(intel_cpu_dev);