Merge branch 'v2.6.24-lockdep' of git://git.kernel.org/pub/scm/linux/kernel/git/peter...
[linux-2.6] / drivers / char / drm / via_dma.c
1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
2  *
3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4  * All Rights Reserved.
5  *
6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7  * All Rights Reserved.
8  *
9  * Copyright 2004 The Unichrome project.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the
20  * next paragraph) shall be included in all copies or substantial portions
21  * of the Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
30  *
31  * Authors:
32  *    Tungsten Graphics,
33  *    Erdi Chen,
34  *    Thomas Hellstrom.
35  */
36
37 #include "drmP.h"
38 #include "drm.h"
39 #include "via_drm.h"
40 #include "via_drv.h"
41 #include "via_3d_reg.h"
42
43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
45
46 /* defines for VIA 3D registers */
47 #define VIA_REG_STATUS          0x400
48 #define VIA_REG_TRANSET         0x43C
49 #define VIA_REG_TRANSPACE       0x440
50
51 /* VIA_REG_STATUS(0x400): Engine Status */
52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
53 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
54 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
56
57 #define SetReg2DAGP(nReg, nData) {                              \
58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
59         *((uint32_t *)(vb) + 1) = (nData);                      \
60         vb = ((uint32_t *)vb) + 2;                              \
61         dev_priv->dma_low +=8;                                  \
62 }
63
64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
65
66 #define VIA_OUT_RING_QW(w1,w2)                  \
67         *vb++ = (w1);                           \
68         *vb++ = (w2);                           \
69         dev_priv->dma_low += 8;
70
71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
75 static int via_wait_idle(drm_via_private_t * dev_priv);
76 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
77
78 /*
79  * Free space in command buffer.
80  */
81
82 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
83 {
84         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
85         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
86
87         return ((hw_addr <= dev_priv->dma_low) ?
88                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
89                 (hw_addr - dev_priv->dma_low));
90 }
91
92 /*
93  * How much does the command regulator lag behind?
94  */
95
96 static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
97 {
98         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
99         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
100
101         return ((hw_addr <= dev_priv->dma_low) ?
102                 (dev_priv->dma_low - hw_addr) :
103                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
104 }
105
106 /*
107  * Check that the given size fits in the buffer, otherwise wait.
108  */
109
110 static inline int
111 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
112 {
113         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
114         uint32_t cur_addr, hw_addr, next_addr;
115         volatile uint32_t *hw_addr_ptr;
116         uint32_t count;
117         hw_addr_ptr = dev_priv->hw_addr_ptr;
118         cur_addr = dev_priv->dma_low;
119         next_addr = cur_addr + size + 512 * 1024;
120         count = 1000000;
121         do {
122                 hw_addr = *hw_addr_ptr - agp_base;
123                 if (count-- == 0) {
124                         DRM_ERROR
125                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126                              hw_addr, cur_addr, next_addr);
127                         return -1;
128                 }
129         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
130         return 0;
131 }
132
133 /*
134  * Checks whether buffer head has reach the end. Rewind the ring buffer
135  * when necessary.
136  *
137  * Returns virtual pointer to ring buffer.
138  */
139
140 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
141                                       unsigned int size)
142 {
143         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
144             dev_priv->dma_high) {
145                 via_cmdbuf_rewind(dev_priv);
146         }
147         if (via_cmdbuf_wait(dev_priv, size) != 0) {
148                 return NULL;
149         }
150
151         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
152 }
153
154 int via_dma_cleanup(struct drm_device * dev)
155 {
156         if (dev->dev_private) {
157                 drm_via_private_t *dev_priv =
158                     (drm_via_private_t *) dev->dev_private;
159
160                 if (dev_priv->ring.virtual_start) {
161                         via_cmdbuf_reset(dev_priv);
162
163                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
164                         dev_priv->ring.virtual_start = NULL;
165                 }
166
167         }
168
169         return 0;
170 }
171
172 static int via_initialize(struct drm_device * dev,
173                           drm_via_private_t * dev_priv,
174                           drm_via_dma_init_t * init)
175 {
176         if (!dev_priv || !dev_priv->mmio) {
177                 DRM_ERROR("via_dma_init called before via_map_init\n");
178                 return -EFAULT;
179         }
180
181         if (dev_priv->ring.virtual_start != NULL) {
182                 DRM_ERROR("%s called again without calling cleanup\n",
183                           __FUNCTION__);
184                 return -EFAULT;
185         }
186
187         if (!dev->agp || !dev->agp->base) {
188                 DRM_ERROR("%s called with no agp memory available\n",
189                           __FUNCTION__);
190                 return -EFAULT;
191         }
192
193         if (dev_priv->chipset == VIA_DX9_0) {
194                 DRM_ERROR("AGP DMA is not supported on this chip\n");
195                 return -EINVAL;
196         }
197
198         dev_priv->ring.map.offset = dev->agp->base + init->offset;
199         dev_priv->ring.map.size = init->size;
200         dev_priv->ring.map.type = 0;
201         dev_priv->ring.map.flags = 0;
202         dev_priv->ring.map.mtrr = 0;
203
204         drm_core_ioremap(&dev_priv->ring.map, dev);
205
206         if (dev_priv->ring.map.handle == NULL) {
207                 via_dma_cleanup(dev);
208                 DRM_ERROR("can not ioremap virtual address for"
209                           " ring buffer\n");
210                 return -ENOMEM;
211         }
212
213         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
214
215         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
216         dev_priv->dma_low = 0;
217         dev_priv->dma_high = init->size;
218         dev_priv->dma_wrap = init->size;
219         dev_priv->dma_offset = init->offset;
220         dev_priv->last_pause_ptr = NULL;
221         dev_priv->hw_addr_ptr =
222                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
223                 init->reg_pause_addr);
224
225         via_cmdbuf_start(dev_priv);
226
227         return 0;
228 }
229
230 static int via_dma_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
231 {
232         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
233         drm_via_dma_init_t *init = data;
234         int retcode = 0;
235
236         switch (init->func) {
237         case VIA_INIT_DMA:
238                 if (!DRM_SUSER(DRM_CURPROC))
239                         retcode = -EPERM;
240                 else
241                         retcode = via_initialize(dev, dev_priv, init);
242                 break;
243         case VIA_CLEANUP_DMA:
244                 if (!DRM_SUSER(DRM_CURPROC))
245                         retcode = -EPERM;
246                 else
247                         retcode = via_dma_cleanup(dev);
248                 break;
249         case VIA_DMA_INITIALIZED:
250                 retcode = (dev_priv->ring.virtual_start != NULL) ?
251                         0 : -EFAULT;
252                 break;
253         default:
254                 retcode = -EINVAL;
255                 break;
256         }
257
258         return retcode;
259 }
260
261 static int via_dispatch_cmdbuffer(struct drm_device * dev, drm_via_cmdbuffer_t * cmd)
262 {
263         drm_via_private_t *dev_priv;
264         uint32_t *vb;
265         int ret;
266
267         dev_priv = (drm_via_private_t *) dev->dev_private;
268
269         if (dev_priv->ring.virtual_start == NULL) {
270                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
271                           __FUNCTION__);
272                 return -EFAULT;
273         }
274
275         if (cmd->size > VIA_PCI_BUF_SIZE) {
276                 return -ENOMEM;
277         }
278
279         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
280                 return -EFAULT;
281
282         /*
283          * Running this function on AGP memory is dead slow. Therefore
284          * we run it on a temporary cacheable system memory buffer and
285          * copy it to AGP memory when ready.
286          */
287
288         if ((ret =
289              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
290                                        cmd->size, dev, 1))) {
291                 return ret;
292         }
293
294         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
295         if (vb == NULL) {
296                 return -EAGAIN;
297         }
298
299         memcpy(vb, dev_priv->pci_buf, cmd->size);
300
301         dev_priv->dma_low += cmd->size;
302
303         /*
304          * Small submissions somehow stalls the CPU. (AGP cache effects?)
305          * pad to greater size.
306          */
307
308         if (cmd->size < 0x100)
309                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
310         via_cmdbuf_pause(dev_priv);
311
312         return 0;
313 }
314
315 int via_driver_dma_quiescent(struct drm_device * dev)
316 {
317         drm_via_private_t *dev_priv = dev->dev_private;
318
319         if (!via_wait_idle(dev_priv)) {
320                 return -EBUSY;
321         }
322         return 0;
323 }
324
325 static int via_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
326 {
327
328         LOCK_TEST_WITH_RETURN(dev, file_priv);
329
330         return via_driver_dma_quiescent(dev);
331 }
332
333 static int via_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
334 {
335         drm_via_cmdbuffer_t *cmdbuf = data;
336         int ret;
337
338         LOCK_TEST_WITH_RETURN(dev, file_priv);
339
340         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf->buf,
341                   cmdbuf->size);
342
343         ret = via_dispatch_cmdbuffer(dev, cmdbuf);
344         if (ret) {
345                 return ret;
346         }
347
348         return 0;
349 }
350
351 static int via_dispatch_pci_cmdbuffer(struct drm_device * dev,
352                                       drm_via_cmdbuffer_t * cmd)
353 {
354         drm_via_private_t *dev_priv = dev->dev_private;
355         int ret;
356
357         if (cmd->size > VIA_PCI_BUF_SIZE) {
358                 return -ENOMEM;
359         }
360         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
361                 return -EFAULT;
362
363         if ((ret =
364              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
365                                        cmd->size, dev, 0))) {
366                 return ret;
367         }
368
369         ret =
370             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
371                                      cmd->size);
372         return ret;
373 }
374
375 static int via_pci_cmdbuffer(struct drm_device *dev, void *data, struct drm_file *file_priv)
376 {
377         drm_via_cmdbuffer_t *cmdbuf = data;
378         int ret;
379
380         LOCK_TEST_WITH_RETURN(dev, file_priv);
381
382         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf->buf,
383                   cmdbuf->size);
384
385         ret = via_dispatch_pci_cmdbuffer(dev, cmdbuf);
386         if (ret) {
387                 return ret;
388         }
389
390         return 0;
391 }
392
393 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
394                                          uint32_t * vb, int qw_count)
395 {
396         for (; qw_count > 0; --qw_count) {
397                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
398         }
399         return vb;
400 }
401
402 /*
403  * This function is used internally by ring buffer mangement code.
404  *
405  * Returns virtual pointer to ring buffer.
406  */
407 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
408 {
409         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
410 }
411
412 /*
413  * Hooks a segment of data into the tail of the ring-buffer by
414  * modifying the pause address stored in the buffer itself. If
415  * the regulator has already paused, restart it.
416  */
417 static int via_hook_segment(drm_via_private_t * dev_priv,
418                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
419                             int no_pci_fire)
420 {
421         int paused, count;
422         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
423         uint32_t reader,ptr;
424
425         paused = 0;
426         via_flush_write_combine();
427         (void) *(volatile uint32_t *)(via_get_dma(dev_priv) -1);
428         *paused_at = pause_addr_lo;
429         via_flush_write_combine();
430         (void) *paused_at;
431         reader = *(dev_priv->hw_addr_ptr);
432         ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
433                 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
434         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
435
436         if ((ptr - reader) <= dev_priv->dma_diff ) {
437                 count = 10000000;
438                 while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--);
439         }
440
441         if (paused && !no_pci_fire) {
442                 reader = *(dev_priv->hw_addr_ptr);
443                 if ((ptr - reader) == dev_priv->dma_diff) {
444
445                         /*
446                          * There is a concern that these writes may stall the PCI bus
447                          * if the GPU is not idle. However, idling the GPU first
448                          * doesn't make a difference.
449                          */
450
451                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
452                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
453                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
454                         VIA_READ(VIA_REG_TRANSPACE);
455                 }
456         }
457         return paused;
458 }
459
460 static int via_wait_idle(drm_via_private_t * dev_priv)
461 {
462         int count = 10000000;
463
464         while (!(VIA_READ(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) && count--);
465
466         while (count-- && (VIA_READ(VIA_REG_STATUS) &
467                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
468                             VIA_3D_ENG_BUSY))) ;
469         return count;
470 }
471
472 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
473                                uint32_t addr, uint32_t * cmd_addr_hi,
474                                uint32_t * cmd_addr_lo, int skip_wait)
475 {
476         uint32_t agp_base;
477         uint32_t cmd_addr, addr_lo, addr_hi;
478         uint32_t *vb;
479         uint32_t qw_pad_count;
480
481         if (!skip_wait)
482                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
483
484         vb = via_get_dma(dev_priv);
485         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
486                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
487         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
488         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
489             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
490
491         cmd_addr = (addr) ? addr :
492             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
493         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
494                    (cmd_addr & HC_HAGPBpL_MASK));
495         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
496
497         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
498         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
499         return vb;
500 }
501
502 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
503 {
504         uint32_t pause_addr_lo, pause_addr_hi;
505         uint32_t start_addr, start_addr_lo;
506         uint32_t end_addr, end_addr_lo;
507         uint32_t command;
508         uint32_t agp_base;
509         uint32_t ptr;
510         uint32_t reader;
511         int count;
512
513         dev_priv->dma_low = 0;
514
515         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
516         start_addr = agp_base;
517         end_addr = agp_base + dev_priv->dma_high;
518
519         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
520         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
521         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
522                    ((end_addr & 0xff000000) >> 16));
523
524         dev_priv->last_pause_ptr =
525             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
526                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
527
528         via_flush_write_combine();
529         (void) *(volatile uint32_t *)dev_priv->last_pause_ptr;
530
531         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
532         VIA_WRITE(VIA_REG_TRANSPACE, command);
533         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
534         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
535
536         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
537         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
538         DRM_WRITEMEMORYBARRIER();
539         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
540         VIA_READ(VIA_REG_TRANSPACE);
541
542         dev_priv->dma_diff = 0;
543
544         count = 10000000;
545         while (!(VIA_READ(0x41c) & 0x80000000) && count--);
546
547         reader = *(dev_priv->hw_addr_ptr);
548         ptr = ((volatile char *)dev_priv->last_pause_ptr - dev_priv->dma_ptr) +
549             dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
550
551         /*
552          * This is the difference between where we tell the
553          * command reader to pause and where it actually pauses.
554          * This differs between hw implementation so we need to
555          * detect it.
556          */
557
558         dev_priv->dma_diff = ptr - reader;
559 }
560
561 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
562 {
563         uint32_t *vb;
564
565         via_cmdbuf_wait(dev_priv, qwords + 2);
566         vb = via_get_dma(dev_priv);
567         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
568         via_align_buffer(dev_priv, vb, qwords);
569 }
570
571 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
572 {
573         uint32_t *vb = via_get_dma(dev_priv);
574         SetReg2DAGP(0x0C, (0 | (0 << 16)));
575         SetReg2DAGP(0x10, 0 | (0 << 16));
576         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
577 }
578
579 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
580 {
581         uint32_t agp_base;
582         uint32_t pause_addr_lo, pause_addr_hi;
583         uint32_t jump_addr_lo, jump_addr_hi;
584         volatile uint32_t *last_pause_ptr;
585
586         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
587         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
588                       &jump_addr_lo, 0);
589
590         dev_priv->dma_wrap = dev_priv->dma_low;
591
592         /*
593          * Wrap command buffer to the beginning.
594          */
595
596         dev_priv->dma_low = 0;
597         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
598                 DRM_ERROR("via_cmdbuf_jump failed\n");
599         }
600
601         via_dummy_bitblt(dev_priv);
602         via_dummy_bitblt(dev_priv);
603
604         last_pause_ptr =
605             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
606                           &pause_addr_lo, 0) - 1;
607         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
608                       &pause_addr_lo, 0);
609
610         *last_pause_ptr = pause_addr_lo;
611
612         via_hook_segment( dev_priv, jump_addr_hi, jump_addr_lo, 0);
613 }
614
615
616 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
617 {
618         via_cmdbuf_jump(dev_priv);
619 }
620
621 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
622 {
623         uint32_t pause_addr_lo, pause_addr_hi;
624
625         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
626         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
627 }
628
629 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
630 {
631         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
632 }
633
634 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
635 {
636         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
637         via_wait_idle(dev_priv);
638 }
639
640 /*
641  * User interface to the space and lag functions.
642  */
643
644 static int via_cmdbuf_size(struct drm_device *dev, void *data, struct drm_file *file_priv)
645 {
646         drm_via_cmdbuf_size_t *d_siz = data;
647         int ret = 0;
648         uint32_t tmp_size, count;
649         drm_via_private_t *dev_priv;
650
651         DRM_DEBUG("via cmdbuf_size\n");
652         LOCK_TEST_WITH_RETURN(dev, file_priv);
653
654         dev_priv = (drm_via_private_t *) dev->dev_private;
655
656         if (dev_priv->ring.virtual_start == NULL) {
657                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
658                           __FUNCTION__);
659                 return -EFAULT;
660         }
661
662         count = 1000000;
663         tmp_size = d_siz->size;
664         switch (d_siz->func) {
665         case VIA_CMDBUF_SPACE:
666                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz->size)
667                        && count--) {
668                         if (!d_siz->wait) {
669                                 break;
670                         }
671                 }
672                 if (!count) {
673                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
674                         ret = -EAGAIN;
675                 }
676                 break;
677         case VIA_CMDBUF_LAG:
678                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz->size)
679                        && count--) {
680                         if (!d_siz->wait) {
681                                 break;
682                         }
683                 }
684                 if (!count) {
685                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
686                         ret = -EAGAIN;
687                 }
688                 break;
689         default:
690                 ret = -EFAULT;
691         }
692         d_siz->size = tmp_size;
693
694         return ret;
695 }
696
697 struct drm_ioctl_desc via_ioctls[] = {
698         DRM_IOCTL_DEF(DRM_VIA_ALLOCMEM, via_mem_alloc, DRM_AUTH),
699         DRM_IOCTL_DEF(DRM_VIA_FREEMEM, via_mem_free, DRM_AUTH),
700         DRM_IOCTL_DEF(DRM_VIA_AGP_INIT, via_agp_init, DRM_AUTH|DRM_MASTER),
701         DRM_IOCTL_DEF(DRM_VIA_FB_INIT, via_fb_init, DRM_AUTH|DRM_MASTER),
702         DRM_IOCTL_DEF(DRM_VIA_MAP_INIT, via_map_init, DRM_AUTH|DRM_MASTER),
703         DRM_IOCTL_DEF(DRM_VIA_DEC_FUTEX, via_decoder_futex, DRM_AUTH),
704         DRM_IOCTL_DEF(DRM_VIA_DMA_INIT, via_dma_init, DRM_AUTH),
705         DRM_IOCTL_DEF(DRM_VIA_CMDBUFFER, via_cmdbuffer, DRM_AUTH),
706         DRM_IOCTL_DEF(DRM_VIA_FLUSH, via_flush_ioctl, DRM_AUTH),
707         DRM_IOCTL_DEF(DRM_VIA_PCICMD, via_pci_cmdbuffer, DRM_AUTH),
708         DRM_IOCTL_DEF(DRM_VIA_CMDBUF_SIZE, via_cmdbuf_size, DRM_AUTH),
709         DRM_IOCTL_DEF(DRM_VIA_WAIT_IRQ, via_wait_irq, DRM_AUTH),
710         DRM_IOCTL_DEF(DRM_VIA_DMA_BLIT, via_dma_blit, DRM_AUTH),
711         DRM_IOCTL_DEF(DRM_VIA_BLIT_SYNC, via_dma_blit_sync, DRM_AUTH)
712 };
713
714 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);