Merge commit 'v2.6.30-rc5' into core/iommu
[linux-2.6] / drivers / net / ixgbe / ixgbe_phy.c
1 /*******************************************************************************
2
3   Intel 10 Gigabit PCI Express Linux driver
4   Copyright(c) 1999 - 2009 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
34
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50
51 /**
52  *  ixgbe_identify_phy_generic - Get physical layer module
53  *  @hw: pointer to hardware structure
54  *
55  *  Determines the physical layer module found on the current adapter.
56  **/
57 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
58 {
59         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
60         u32 phy_addr;
61
62         if (hw->phy.type == ixgbe_phy_unknown) {
63                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
64                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
65                                 hw->phy.addr = phy_addr;
66                                 ixgbe_get_phy_id(hw);
67                                 hw->phy.type =
68                                         ixgbe_get_phy_type_from_id(hw->phy.id);
69                                 status = 0;
70                                 break;
71                         }
72                 }
73         } else {
74                 status = 0;
75         }
76
77         return status;
78 }
79
80 /**
81  *  ixgbe_validate_phy_addr - Determines phy address is valid
82  *  @hw: pointer to hardware structure
83  *
84  **/
85 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
86 {
87         u16 phy_id = 0;
88         bool valid = false;
89
90         hw->phy.addr = phy_addr;
91         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
92                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
93
94         if (phy_id != 0xFFFF && phy_id != 0x0)
95                 valid = true;
96
97         return valid;
98 }
99
100 /**
101  *  ixgbe_get_phy_id - Get the phy type
102  *  @hw: pointer to hardware structure
103  *
104  **/
105 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
106 {
107         u32 status;
108         u16 phy_id_high = 0;
109         u16 phy_id_low = 0;
110
111         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
112                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
113                                       &phy_id_high);
114
115         if (status == 0) {
116                 hw->phy.id = (u32)(phy_id_high << 16);
117                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
118                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
119                                               &phy_id_low);
120                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
121                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
122         }
123         return status;
124 }
125
126 /**
127  *  ixgbe_get_phy_type_from_id - Get the phy type
128  *  @hw: pointer to hardware structure
129  *
130  **/
131 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
132 {
133         enum ixgbe_phy_type phy_type;
134
135         switch (phy_id) {
136         case TN1010_PHY_ID:
137                 phy_type = ixgbe_phy_tn;
138                 break;
139         case QT2022_PHY_ID:
140                 phy_type = ixgbe_phy_qt;
141                 break;
142         case ATH_PHY_ID:
143                 phy_type = ixgbe_phy_nl;
144                 break;
145         default:
146                 phy_type = ixgbe_phy_unknown;
147                 break;
148         }
149
150         return phy_type;
151 }
152
153 /**
154  *  ixgbe_reset_phy_generic - Performs a PHY reset
155  *  @hw: pointer to hardware structure
156  **/
157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
158 {
159         /*
160          * Perform soft PHY reset to the PHY_XS.
161          * This will cause a soft reset to the PHY
162          */
163         return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
164                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
165                                      IXGBE_MDIO_PHY_XS_RESET);
166 }
167
168 /**
169  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
170  *  @hw: pointer to hardware structure
171  *  @reg_addr: 32 bit address of PHY register to read
172  *  @phy_data: Pointer to read data from PHY register
173  **/
174 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
175                                u32 device_type, u16 *phy_data)
176 {
177         u32 command;
178         u32 i;
179         u32 data;
180         s32 status = 0;
181         u16 gssr;
182
183         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
184                 gssr = IXGBE_GSSR_PHY1_SM;
185         else
186                 gssr = IXGBE_GSSR_PHY0_SM;
187
188         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
189                 status = IXGBE_ERR_SWFW_SYNC;
190
191         if (status == 0) {
192                 /* Setup and write the address cycle command */
193                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
194                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
195                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
196                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
197
198                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
199
200                 /*
201                  * Check every 10 usec to see if the address cycle completed.
202                  * The MDI Command bit will clear when the operation is
203                  * complete
204                  */
205                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
206                         udelay(10);
207
208                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
209
210                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
211                                 break;
212                 }
213
214                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
215                         hw_dbg(hw, "PHY address command did not complete.\n");
216                         status = IXGBE_ERR_PHY;
217                 }
218
219                 if (status == 0) {
220                         /*
221                          * Address cycle complete, setup and write the read
222                          * command
223                          */
224                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
225                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
226                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
227                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
228
229                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
230
231                         /*
232                          * Check every 10 usec to see if the address cycle
233                          * completed. The MDI Command bit will clear when the
234                          * operation is complete
235                          */
236                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
237                                 udelay(10);
238
239                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
240
241                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
242                                         break;
243                         }
244
245                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
246                                 hw_dbg(hw, "PHY read command didn't complete\n");
247                                 status = IXGBE_ERR_PHY;
248                         } else {
249                                 /*
250                                  * Read operation is complete.  Get the data
251                                  * from MSRWD
252                                  */
253                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
254                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
255                                 *phy_data = (u16)(data);
256                         }
257                 }
258
259                 ixgbe_release_swfw_sync(hw, gssr);
260         }
261
262         return status;
263 }
264
265 /**
266  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
267  *  @hw: pointer to hardware structure
268  *  @reg_addr: 32 bit PHY register to write
269  *  @device_type: 5 bit device type
270  *  @phy_data: Data to write to the PHY register
271  **/
272 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
273                                 u32 device_type, u16 phy_data)
274 {
275         u32 command;
276         u32 i;
277         s32 status = 0;
278         u16 gssr;
279
280         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
281                 gssr = IXGBE_GSSR_PHY1_SM;
282         else
283                 gssr = IXGBE_GSSR_PHY0_SM;
284
285         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
286                 status = IXGBE_ERR_SWFW_SYNC;
287
288         if (status == 0) {
289                 /* Put the data in the MDI single read and write data register*/
290                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
291
292                 /* Setup and write the address cycle command */
293                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
294                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
295                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
296                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
297
298                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
299
300                 /*
301                  * Check every 10 usec to see if the address cycle completed.
302                  * The MDI Command bit will clear when the operation is
303                  * complete
304                  */
305                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
306                         udelay(10);
307
308                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
309
310                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
311                                 break;
312                 }
313
314                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
315                         hw_dbg(hw, "PHY address cmd didn't complete\n");
316                         status = IXGBE_ERR_PHY;
317                 }
318
319                 if (status == 0) {
320                         /*
321                          * Address cycle complete, setup and write the write
322                          * command
323                          */
324                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
325                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
326                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
327                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
328
329                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
330
331                         /*
332                          * Check every 10 usec to see if the address cycle
333                          * completed. The MDI Command bit will clear when the
334                          * operation is complete
335                          */
336                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
337                                 udelay(10);
338
339                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
340
341                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
342                                         break;
343                         }
344
345                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
346                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
347                                 status = IXGBE_ERR_PHY;
348                         }
349                 }
350
351                 ixgbe_release_swfw_sync(hw, gssr);
352         }
353
354         return status;
355 }
356
357 /**
358  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
359  *  @hw: pointer to hardware structure
360  *
361  *  Restart autonegotiation and PHY and waits for completion.
362  **/
363 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
364 {
365         s32 status = IXGBE_NOT_IMPLEMENTED;
366         u32 time_out;
367         u32 max_time_out = 10;
368         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
369
370         /*
371          * Set advertisement settings in PHY based on autoneg_advertised
372          * settings. If autoneg_advertised = 0, then advertise default values
373          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
374          * for a 1G.
375          */
376         hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
377                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
378
379         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
380                 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
381         else
382                 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
383
384         hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
385                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
386
387         /* Restart PHY autonegotiation and wait for completion */
388         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
389                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
390
391         autoneg_reg |= IXGBE_MII_RESTART;
392
393         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
394                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
395
396         /* Wait for autonegotiation to finish */
397         for (time_out = 0; time_out < max_time_out; time_out++) {
398                 udelay(10);
399                 /* Restart PHY autonegotiation and wait for completion */
400                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
401                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
402                                               &autoneg_reg);
403
404                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
405                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
406                         status = 0;
407                         break;
408                 }
409         }
410
411         if (time_out == max_time_out)
412                 status = IXGBE_ERR_LINK_SETUP;
413
414         return status;
415 }
416
417 /**
418  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
419  *  @hw: pointer to hardware structure
420  *  @speed: new link speed
421  *  @autoneg: true if autonegotiation enabled
422  **/
423 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
424                                        ixgbe_link_speed speed,
425                                        bool autoneg,
426                                        bool autoneg_wait_to_complete)
427 {
428
429         /*
430          * Clear autoneg_advertised and set new values based on input link
431          * speed.
432          */
433         hw->phy.autoneg_advertised = 0;
434
435         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
436                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
437
438         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
439                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
440
441         /* Setup link based on the new speed settings */
442         hw->phy.ops.setup_link(hw);
443
444         return 0;
445 }
446
447 /**
448  *  ixgbe_reset_phy_nl - Performs a PHY reset
449  *  @hw: pointer to hardware structure
450  **/
451 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
452 {
453         u16 phy_offset, control, eword, edata, block_crc;
454         bool end_data = false;
455         u16 list_offset, data_offset;
456         u16 phy_data = 0;
457         s32 ret_val = 0;
458         u32 i;
459
460         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
461                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
462
463         /* reset the PHY and poll for completion */
464         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
465                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
466                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
467
468         for (i = 0; i < 100; i++) {
469                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
470                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
471                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
472                         break;
473                 msleep(10);
474         }
475
476         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
477                 hw_dbg(hw, "PHY reset did not complete.\n");
478                 ret_val = IXGBE_ERR_PHY;
479                 goto out;
480         }
481
482         /* Get init offsets */
483         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
484                                                       &data_offset);
485         if (ret_val != 0)
486                 goto out;
487
488         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
489         data_offset++;
490         while (!end_data) {
491                 /*
492                  * Read control word from PHY init contents offset
493                  */
494                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
495                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
496                            IXGBE_CONTROL_SHIFT_NL;
497                 edata = eword & IXGBE_DATA_MASK_NL;
498                 switch (control) {
499                 case IXGBE_DELAY_NL:
500                         data_offset++;
501                         hw_dbg(hw, "DELAY: %d MS\n", edata);
502                         msleep(edata);
503                         break;
504                 case IXGBE_DATA_NL:
505                         hw_dbg(hw, "DATA:  \n");
506                         data_offset++;
507                         hw->eeprom.ops.read(hw, data_offset++,
508                                             &phy_offset);
509                         for (i = 0; i < edata; i++) {
510                                 hw->eeprom.ops.read(hw, data_offset, &eword);
511                                 hw->phy.ops.write_reg(hw, phy_offset,
512                                                       IXGBE_TWINAX_DEV, eword);
513                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
514                                        phy_offset);
515                                 data_offset++;
516                                 phy_offset++;
517                         }
518                         break;
519                 case IXGBE_CONTROL_NL:
520                         data_offset++;
521                         hw_dbg(hw, "CONTROL: \n");
522                         if (edata == IXGBE_CONTROL_EOL_NL) {
523                                 hw_dbg(hw, "EOL\n");
524                                 end_data = true;
525                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
526                                 hw_dbg(hw, "SOL\n");
527                         } else {
528                                 hw_dbg(hw, "Bad control value\n");
529                                 ret_val = IXGBE_ERR_PHY;
530                                 goto out;
531                         }
532                         break;
533                 default:
534                         hw_dbg(hw, "Bad control type\n");
535                         ret_val = IXGBE_ERR_PHY;
536                         goto out;
537                 }
538         }
539
540 out:
541         return ret_val;
542 }
543
544 /**
545  *  ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
546  *                                      the PHY type.
547  *  @hw: pointer to hardware structure
548  *
549  *  Searches for and indentifies the SFP module.  Assings appropriate PHY type.
550  **/
551 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
552 {
553         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
554         u32 vendor_oui = 0;
555         u8 identifier = 0;
556         u8 comp_codes_1g = 0;
557         u8 comp_codes_10g = 0;
558         u8 oui_bytes[3] = {0, 0, 0};
559         u8 transmission_media = 0;
560         u16 enforce_sfp = 0;
561
562         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
563                                              &identifier);
564
565         if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
566                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
567                 goto out;
568         }
569
570         if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
571                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
572                                             &comp_codes_1g);
573                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
574                                             &comp_codes_10g);
575                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
576                                             &transmission_media);
577
578                 /* ID Module
579                  * =========
580                  * 0    SFP_DA_CU
581                  * 1    SFP_SR
582                  * 2    SFP_LR
583                  * 3    SFP_DA_CORE0 - 82599-specific
584                  * 4    SFP_DA_CORE1 - 82599-specific
585                  * 5    SFP_SR/LR_CORE0 - 82599-specific
586                  * 6    SFP_SR/LR_CORE1 - 82599-specific
587                  */
588                 if (hw->mac.type == ixgbe_mac_82598EB) {
589                         if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
590                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
591                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
592                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
593                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
594                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
595                         else
596                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
597                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
598                         if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
599                                 if (hw->bus.lan_id == 0)
600                                         hw->phy.sfp_type =
601                                                      ixgbe_sfp_type_da_cu_core0;
602                                 else
603                                         hw->phy.sfp_type =
604                                                      ixgbe_sfp_type_da_cu_core1;
605                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
606                                 if (hw->bus.lan_id == 0)
607                                         hw->phy.sfp_type =
608                                                       ixgbe_sfp_type_srlr_core0;
609                                 else
610                                         hw->phy.sfp_type =
611                                                       ixgbe_sfp_type_srlr_core1;
612                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
613                                 if (hw->bus.lan_id == 0)
614                                         hw->phy.sfp_type =
615                                                       ixgbe_sfp_type_srlr_core0;
616                                 else
617                                         hw->phy.sfp_type =
618                                                       ixgbe_sfp_type_srlr_core1;
619                         else
620                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
621                 }
622
623                 /* Determine PHY vendor */
624                 if (hw->phy.type == ixgbe_phy_unknown) {
625                         hw->phy.id = identifier;
626                         hw->phy.ops.read_i2c_eeprom(hw,
627                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
628                                                     &oui_bytes[0]);
629                         hw->phy.ops.read_i2c_eeprom(hw,
630                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
631                                                     &oui_bytes[1]);
632                         hw->phy.ops.read_i2c_eeprom(hw,
633                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
634                                                     &oui_bytes[2]);
635
636                         vendor_oui =
637                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
638                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
639                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
640
641                         switch (vendor_oui) {
642                         case IXGBE_SFF_VENDOR_OUI_TYCO:
643                                 if (transmission_media &
644                                     IXGBE_SFF_TWIN_AX_CAPABLE)
645                                         hw->phy.type = ixgbe_phy_tw_tyco;
646                                 break;
647                         case IXGBE_SFF_VENDOR_OUI_FTL:
648                                 hw->phy.type = ixgbe_phy_sfp_ftl;
649                                 break;
650                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
651                                 hw->phy.type = ixgbe_phy_sfp_avago;
652                                 break;
653                         case IXGBE_SFF_VENDOR_OUI_INTEL:
654                                 hw->phy.type = ixgbe_phy_sfp_intel;
655                                 break;
656                         default:
657                                 if (transmission_media &
658                                     IXGBE_SFF_TWIN_AX_CAPABLE)
659                                         hw->phy.type = ixgbe_phy_tw_unknown;
660                                 else
661                                         hw->phy.type = ixgbe_phy_sfp_unknown;
662                                 break;
663                         }
664                 }
665                 if (hw->mac.type == ixgbe_mac_82598EB ||
666                     (hw->phy.sfp_type != ixgbe_sfp_type_sr &&
667                      hw->phy.sfp_type != ixgbe_sfp_type_lr &&
668                      hw->phy.sfp_type != ixgbe_sfp_type_srlr_core0 &&
669                      hw->phy.sfp_type != ixgbe_sfp_type_srlr_core1)) {
670                         status = 0;
671                         goto out;
672                 }
673
674                 hw->eeprom.ops.read(hw, IXGBE_PHY_ENFORCE_INTEL_SFP_OFFSET,
675                                     &enforce_sfp);
676                 if (!(enforce_sfp & IXGBE_PHY_ALLOW_ANY_SFP)) {
677                         /* Make sure we're a supported PHY type */
678                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
679                                 status = 0;
680                         } else {
681                                 hw_dbg(hw, "SFP+ module not supported\n");
682                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
683                         }
684                 } else {
685                         status = 0;
686                 }
687         }
688
689 out:
690         return status;
691 }
692
693 /**
694  *  ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
695  *  if it supports a given SFP+ module type, if so it returns the offsets to the
696  *  phy init sequence block.
697  *  @hw: pointer to hardware structure
698  *  @list_offset: offset to the SFP ID list
699  *  @data_offset: offset to the SFP data block
700  **/
701 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
702                                         u16 *list_offset,
703                                         u16 *data_offset)
704 {
705         u16 sfp_id;
706
707         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
708                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
709
710         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
711                 return IXGBE_ERR_SFP_NOT_PRESENT;
712
713         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
714             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
715                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
716
717         /* Read offset to PHY init contents */
718         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
719
720         if ((!*list_offset) || (*list_offset == 0xFFFF))
721                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
722
723         /* Shift offset to first ID word */
724         (*list_offset)++;
725
726         /*
727          * Find the matching SFP ID in the EEPROM
728          * and program the init sequence
729          */
730         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
731
732         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
733                 if (sfp_id == hw->phy.sfp_type) {
734                         (*list_offset)++;
735                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
736                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
737                                 hw_dbg(hw, "SFP+ module not supported\n");
738                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
739                         } else {
740                                 break;
741                         }
742                 } else {
743                         (*list_offset) += 2;
744                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
745                                 return IXGBE_ERR_PHY;
746                 }
747         }
748
749         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
750                 hw_dbg(hw, "No matching SFP+ module found\n");
751                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
752         }
753
754         return 0;
755 }
756
757 /**
758  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
759  *  @hw: pointer to hardware structure
760  *  @byte_offset: EEPROM byte offset to read
761  *  @eeprom_data: value read
762  *
763  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
764  **/
765 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
766                                   u8 *eeprom_data)
767 {
768         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
769                                          IXGBE_I2C_EEPROM_DEV_ADDR,
770                                          eeprom_data);
771 }
772
773 /**
774  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
775  *  @hw: pointer to hardware structure
776  *  @byte_offset: EEPROM byte offset to write
777  *  @eeprom_data: value to write
778  *
779  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
780  **/
781 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
782                                    u8 eeprom_data)
783 {
784         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
785                                           IXGBE_I2C_EEPROM_DEV_ADDR,
786                                           eeprom_data);
787 }
788
789 /**
790  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
791  *  @hw: pointer to hardware structure
792  *  @byte_offset: byte offset to read
793  *  @data: value read
794  *
795  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
796  *  a specified deivce address.
797  **/
798 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
799                                 u8 dev_addr, u8 *data)
800 {
801         s32 status = 0;
802         u32 max_retry = 1;
803         u32 retry = 0;
804         bool nack = 1;
805
806         do {
807                 ixgbe_i2c_start(hw);
808
809                 /* Device Address and write indication */
810                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
811                 if (status != 0)
812                         goto fail;
813
814                 status = ixgbe_get_i2c_ack(hw);
815                 if (status != 0)
816                         goto fail;
817
818                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
819                 if (status != 0)
820                         goto fail;
821
822                 status = ixgbe_get_i2c_ack(hw);
823                 if (status != 0)
824                         goto fail;
825
826                 ixgbe_i2c_start(hw);
827
828                 /* Device Address and read indication */
829                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
830                 if (status != 0)
831                         goto fail;
832
833                 status = ixgbe_get_i2c_ack(hw);
834                 if (status != 0)
835                         goto fail;
836
837                 status = ixgbe_clock_in_i2c_byte(hw, data);
838                 if (status != 0)
839                         goto fail;
840
841                 status = ixgbe_clock_out_i2c_bit(hw, nack);
842                 if (status != 0)
843                         goto fail;
844
845                 ixgbe_i2c_stop(hw);
846                 break;
847
848 fail:
849                 ixgbe_i2c_bus_clear(hw);
850                 retry++;
851                 if (retry < max_retry)
852                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
853                 else
854                         hw_dbg(hw, "I2C byte read error.\n");
855
856         } while (retry < max_retry);
857
858         return status;
859 }
860
861 /**
862  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
863  *  @hw: pointer to hardware structure
864  *  @byte_offset: byte offset to write
865  *  @data: value to write
866  *
867  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
868  *  a specified device address.
869  **/
870 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
871                                  u8 dev_addr, u8 data)
872 {
873         s32 status = 0;
874         u32 max_retry = 1;
875         u32 retry = 0;
876
877         do {
878                 ixgbe_i2c_start(hw);
879
880                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
881                 if (status != 0)
882                         goto fail;
883
884                 status = ixgbe_get_i2c_ack(hw);
885                 if (status != 0)
886                         goto fail;
887
888                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
889                 if (status != 0)
890                         goto fail;
891
892                 status = ixgbe_get_i2c_ack(hw);
893                 if (status != 0)
894                         goto fail;
895
896                 status = ixgbe_clock_out_i2c_byte(hw, data);
897                 if (status != 0)
898                         goto fail;
899
900                 status = ixgbe_get_i2c_ack(hw);
901                 if (status != 0)
902                         goto fail;
903
904                 ixgbe_i2c_stop(hw);
905                 break;
906
907 fail:
908                 ixgbe_i2c_bus_clear(hw);
909                 retry++;
910                 if (retry < max_retry)
911                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
912                 else
913                         hw_dbg(hw, "I2C byte write error.\n");
914         } while (retry < max_retry);
915
916         return status;
917 }
918
919 /**
920  *  ixgbe_i2c_start - Sets I2C start condition
921  *  @hw: pointer to hardware structure
922  *
923  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
924  **/
925 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
926 {
927         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
928
929         /* Start condition must begin with data and clock high */
930         ixgbe_set_i2c_data(hw, &i2cctl, 1);
931         ixgbe_raise_i2c_clk(hw, &i2cctl);
932
933         /* Setup time for start condition (4.7us) */
934         udelay(IXGBE_I2C_T_SU_STA);
935
936         ixgbe_set_i2c_data(hw, &i2cctl, 0);
937
938         /* Hold time for start condition (4us) */
939         udelay(IXGBE_I2C_T_HD_STA);
940
941         ixgbe_lower_i2c_clk(hw, &i2cctl);
942
943         /* Minimum low period of clock is 4.7 us */
944         udelay(IXGBE_I2C_T_LOW);
945
946 }
947
948 /**
949  *  ixgbe_i2c_stop - Sets I2C stop condition
950  *  @hw: pointer to hardware structure
951  *
952  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
953  **/
954 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
955 {
956         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
957
958         /* Stop condition must begin with data low and clock high */
959         ixgbe_set_i2c_data(hw, &i2cctl, 0);
960         ixgbe_raise_i2c_clk(hw, &i2cctl);
961
962         /* Setup time for stop condition (4us) */
963         udelay(IXGBE_I2C_T_SU_STO);
964
965         ixgbe_set_i2c_data(hw, &i2cctl, 1);
966
967         /* bus free time between stop and start (4.7us)*/
968         udelay(IXGBE_I2C_T_BUF);
969 }
970
971 /**
972  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
973  *  @hw: pointer to hardware structure
974  *  @data: data byte to clock in
975  *
976  *  Clocks in one byte data via I2C data/clock
977  **/
978 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
979 {
980         s32 status = 0;
981         s32 i;
982         bool bit = 0;
983
984         for (i = 7; i >= 0; i--) {
985                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
986                 *data |= bit << i;
987
988                 if (status != 0)
989                         break;
990         }
991
992         return status;
993 }
994
995 /**
996  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
997  *  @hw: pointer to hardware structure
998  *  @data: data byte clocked out
999  *
1000  *  Clocks out one byte data via I2C data/clock
1001  **/
1002 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1003 {
1004         s32 status = 0;
1005         s32 i;
1006         u32 i2cctl;
1007         bool bit = 0;
1008
1009         for (i = 7; i >= 0; i--) {
1010                 bit = (data >> i) & 0x1;
1011                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1012
1013                 if (status != 0)
1014                         break;
1015         }
1016
1017         /* Release SDA line (set high) */
1018         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1019         i2cctl |= IXGBE_I2C_DATA_OUT;
1020         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1021
1022         return status;
1023 }
1024
1025 /**
1026  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1027  *  @hw: pointer to hardware structure
1028  *
1029  *  Clocks in/out one bit via I2C data/clock
1030  **/
1031 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1032 {
1033         s32 status;
1034         u32 i = 0;
1035         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1036         u32 timeout = 10;
1037         bool ack = 1;
1038
1039         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1040
1041         if (status != 0)
1042                 goto out;
1043
1044         /* Minimum high period of clock is 4us */
1045         udelay(IXGBE_I2C_T_HIGH);
1046
1047         /* Poll for ACK.  Note that ACK in I2C spec is
1048          * transition from 1 to 0 */
1049         for (i = 0; i < timeout; i++) {
1050                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1051                 ack = ixgbe_get_i2c_data(&i2cctl);
1052
1053                 udelay(1);
1054                 if (ack == 0)
1055                         break;
1056         }
1057
1058         if (ack == 1) {
1059                 hw_dbg(hw, "I2C ack was not received.\n");
1060                 status = IXGBE_ERR_I2C;
1061         }
1062
1063         ixgbe_lower_i2c_clk(hw, &i2cctl);
1064
1065         /* Minimum low period of clock is 4.7 us */
1066         udelay(IXGBE_I2C_T_LOW);
1067
1068 out:
1069         return status;
1070 }
1071
1072 /**
1073  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1074  *  @hw: pointer to hardware structure
1075  *  @data: read data value
1076  *
1077  *  Clocks in one bit via I2C data/clock
1078  **/
1079 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1080 {
1081         s32 status;
1082         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1083
1084         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1085
1086         /* Minimum high period of clock is 4us */
1087         udelay(IXGBE_I2C_T_HIGH);
1088
1089         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1090         *data = ixgbe_get_i2c_data(&i2cctl);
1091
1092         ixgbe_lower_i2c_clk(hw, &i2cctl);
1093
1094         /* Minimum low period of clock is 4.7 us */
1095         udelay(IXGBE_I2C_T_LOW);
1096
1097         return status;
1098 }
1099
1100 /**
1101  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1102  *  @hw: pointer to hardware structure
1103  *  @data: data value to write
1104  *
1105  *  Clocks out one bit via I2C data/clock
1106  **/
1107 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1108 {
1109         s32 status;
1110         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1111
1112         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1113         if (status == 0) {
1114                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1115
1116                 /* Minimum high period of clock is 4us */
1117                 udelay(IXGBE_I2C_T_HIGH);
1118
1119                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1120
1121                 /* Minimum low period of clock is 4.7 us.
1122                  * This also takes care of the data hold time.
1123                  */
1124                 udelay(IXGBE_I2C_T_LOW);
1125         } else {
1126                 status = IXGBE_ERR_I2C;
1127                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1128         }
1129
1130         return status;
1131 }
1132 /**
1133  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1134  *  @hw: pointer to hardware structure
1135  *  @i2cctl: Current value of I2CCTL register
1136  *
1137  *  Raises the I2C clock line '0'->'1'
1138  **/
1139 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1140 {
1141         s32 status = 0;
1142
1143         *i2cctl |= IXGBE_I2C_CLK_OUT;
1144
1145         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1146
1147         /* SCL rise time (1000ns) */
1148         udelay(IXGBE_I2C_T_RISE);
1149
1150         return status;
1151 }
1152
1153 /**
1154  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1155  *  @hw: pointer to hardware structure
1156  *  @i2cctl: Current value of I2CCTL register
1157  *
1158  *  Lowers the I2C clock line '1'->'0'
1159  **/
1160 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1161 {
1162
1163         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1164
1165         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1166
1167         /* SCL fall time (300ns) */
1168         udelay(IXGBE_I2C_T_FALL);
1169 }
1170
1171 /**
1172  *  ixgbe_set_i2c_data - Sets the I2C data bit
1173  *  @hw: pointer to hardware structure
1174  *  @i2cctl: Current value of I2CCTL register
1175  *  @data: I2C data value (0 or 1) to set
1176  *
1177  *  Sets the I2C data bit
1178  **/
1179 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1180 {
1181         s32 status = 0;
1182
1183         if (data)
1184                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1185         else
1186                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1187
1188         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1189
1190         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1191         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1192
1193         /* Verify data was set correctly */
1194         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1195         if (data != ixgbe_get_i2c_data(i2cctl)) {
1196                 status = IXGBE_ERR_I2C;
1197                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1198         }
1199
1200         return status;
1201 }
1202
1203 /**
1204  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1205  *  @hw: pointer to hardware structure
1206  *  @i2cctl: Current value of I2CCTL register
1207  *
1208  *  Returns the I2C data bit value
1209  **/
1210 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1211 {
1212         bool data;
1213
1214         if (*i2cctl & IXGBE_I2C_DATA_IN)
1215                 data = 1;
1216         else
1217                 data = 0;
1218
1219         return data;
1220 }
1221
1222 /**
1223  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1224  *  @hw: pointer to hardware structure
1225  *
1226  *  Clears the I2C bus by sending nine clock pulses.
1227  *  Used when data line is stuck low.
1228  **/
1229 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1230 {
1231         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1232         u32 i;
1233
1234         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1235
1236         for (i = 0; i < 9; i++) {
1237                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1238
1239                 /* Min high period of clock is 4us */
1240                 udelay(IXGBE_I2C_T_HIGH);
1241
1242                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1243
1244                 /* Min low period of clock is 4.7us*/
1245                 udelay(IXGBE_I2C_T_LOW);
1246         }
1247
1248         /* Put the i2c bus back to default state */
1249         ixgbe_i2c_stop(hw);
1250 }
1251
1252 /**
1253  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1254  *  @hw: pointer to hardware structure
1255  *
1256  *  Reads the VS1 register to determine if link is up and the current speed for
1257  *  the PHY.
1258  **/
1259 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1260                              bool *link_up)
1261 {
1262         s32 status = 0;
1263         u32 time_out;
1264         u32 max_time_out = 10;
1265         u16 phy_link = 0;
1266         u16 phy_speed = 0;
1267         u16 phy_data = 0;
1268
1269         /* Initialize speed and link to default case */
1270         *link_up = false;
1271         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1272
1273         /*
1274          * Check current speed and link status of the PHY register.
1275          * This is a vendor specific register and may have to
1276          * be changed for other copper PHYs.
1277          */
1278         for (time_out = 0; time_out < max_time_out; time_out++) {
1279                 udelay(10);
1280                 status = hw->phy.ops.read_reg(hw,
1281                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1282                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1283                                         &phy_data);
1284                 phy_link = phy_data &
1285                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1286                 phy_speed = phy_data &
1287                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1288                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1289                         *link_up = true;
1290                         if (phy_speed ==
1291                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1292                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1293                         break;
1294                 }
1295         }
1296
1297         return status;
1298 }
1299
1300 /**
1301  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1302  *  @hw: pointer to hardware structure
1303  *  @firmware_version: pointer to the PHY Firmware Version
1304  **/
1305 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1306                                        u16 *firmware_version)
1307 {
1308         s32 status = 0;
1309
1310         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1311                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1312                                       firmware_version);
1313
1314         return status;
1315 }
1316