git.oblomov.eu Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/idle.h>
  40 #include <asm/io.h>
  41 #include <asm/smp.h>
  42 #include <asm/desc.h>
  43 #include <asm/proto.h>
  44 #include <asm/mach_apic.h>
  45 #include <asm/acpi.h>
  46 #include <asm/dma.h>
  47 #include <asm/nmi.h>
  48 #include <asm/msidef.h>
  49 #include <asm/hypertransport.h>
  50
  51 struct irq_cfg {
  52         cpumask_t domain;
  53         cpumask_t old_domain;
  54         unsigned move_cleanup_count;
  55         u8 vector;
  56         u8 move_in_progress : 1;
  57 };
  58
  59 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
  60 struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
  61         [0]  = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR,  },
  62         [1]  = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR,  },
  63         [2]  = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR,  },
  64         [3]  = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR,  },
  65         [4]  = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR,  },
  66         [5]  = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR,  },
  67         [6]  = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR,  },
  68         [7]  = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR,  },
  69         [8]  = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR,  },
  70         [9]  = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR,  },
  71         [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
  72         [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
  73         [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
  74         [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
  75         [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
  76         [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
  77 };
  78
  79 static int assign_irq_vector(int irq, cpumask_t mask);
  80
  81 #define __apicdebuginit  __init
  82
  83 int sis_apic_bug; /* not actually supported, dummy for compile */
  84
  85 static int no_timer_check;
  86
  87 static int disable_timer_pin_1 __initdata;
  88
  89 int timer_over_8254 __initdata = 1;
  90
  91 /* Where if anywhere is the i8259 connect in external int mode */
  92 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  93
  94 static DEFINE_SPINLOCK(ioapic_lock);
  95 DEFINE_SPINLOCK(vector_lock);
  96
  97 /*
  98  * # of IRQ routing registers
  99  */
 100 int nr_ioapic_registers[MAX_IO_APICS];
 101
 102 /*
 103  * Rough estimation of how many shared IRQs there are, can
 104  * be changed anytime.
 105  */
 106 #define MAX_PLUS_SHARED_IRQS NR_IRQS
 107 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
 108
 109 /*
 110  * This is performance-critical, we want to do it O(1)
 111  *
 112  * the indexing order of this array favors 1:1 mappings
 113  * between pins and IRQs.
 114  */
 115
 116 static struct irq_pin_list {
 117         short apic, pin, next;
 118 } irq_2_pin[PIN_MAP_SIZE];
 119
 120 struct io_apic {
 121         unsigned int index;
 122         unsigned int unused[3];
 123         unsigned int data;
 124 };
 125
 126 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 127 {
 128         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 129                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 130 }
 131
 132 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 133 {
 134         struct io_apic __iomem *io_apic = io_apic_base(apic);
 135         writel(reg, &io_apic->index);
 136         return readl(&io_apic->data);
 137 }
 138
 139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 140 {
 141         struct io_apic __iomem *io_apic = io_apic_base(apic);
 142         writel(reg, &io_apic->index);
 143         writel(value, &io_apic->data);
 144 }
 145
 146 /*
 147  * Re-write a value: to be used for read-modify-write
 148  * cycles where the read already set up the index register.
 149  */
 150 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 151 {
 152         struct io_apic __iomem *io_apic = io_apic_base(apic);
 153         writel(value, &io_apic->data);
 154 }
 155
 156 /*
 157  * Synchronize the IO-APIC and the CPU by doing
 158  * a dummy read from the IO-APIC
 159  */
 160 static inline void io_apic_sync(unsigned int apic)
 161 {
 162         struct io_apic __iomem *io_apic = io_apic_base(apic);
 163         readl(&io_apic->data);
 164 }
 165
 166 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 167                                                                         \
 168 {                                                                       \
 169         int pin;                                                        \
 170         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 171                                                                         \
 172         BUG_ON(irq >= NR_IRQS);                                         \
 173         for (;;) {                                                      \
 174                 unsigned int reg;                                       \
 175                 pin = entry->pin;                                       \
 176                 if (pin == -1)                                          \
 177                         break;                                          \
 178                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 179                 reg ACTION;                                             \
 180                 io_apic_modify(entry->apic, reg);                       \
 181                 FINAL;                                                  \
 182                 if (!entry->next)                                       \
 183                         break;                                          \
 184                 entry = irq_2_pin + entry->next;                        \
 185         }                                                               \
 186 }
 187
 188 union entry_union {
 189         struct { u32 w1, w2; };
 190         struct IO_APIC_route_entry entry;
 191 };
 192
 193 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 194 {
 195         union entry_union eu;
 196         unsigned long flags;
 197         spin_lock_irqsave(&ioapic_lock, flags);
 198         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 199         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 200         spin_unlock_irqrestore(&ioapic_lock, flags);
 201         return eu.entry;
 202 }
 203
 204 /*
 205  * When we write a new IO APIC routing entry, we need to write the high
 206  * word first! If the mask bit in the low word is clear, we will enable
 207  * the interrupt, and we need to make sure the entry is fully populated
 208  * before that happens.
 209  */
 210 static void
 211 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 212 {
 213         union entry_union eu;
 214         eu.entry = e;
 215         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 216         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 217 }
 218
 219 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 220 {
 221         unsigned long flags;
 222         spin_lock_irqsave(&ioapic_lock, flags);
 223         __ioapic_write_entry(apic, pin, e);
 224         spin_unlock_irqrestore(&ioapic_lock, flags);
 225 }
 226
 227 /*
 228  * When we mask an IO APIC routing entry, we need to write the low
 229  * word first, in order to set the mask bit before we change the
 230  * high bits!
 231  */
 232 static void ioapic_mask_entry(int apic, int pin)
 233 {
 234         unsigned long flags;
 235         union entry_union eu = { .entry.mask = 1 };
 236
 237         spin_lock_irqsave(&ioapic_lock, flags);
 238         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 239         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 240         spin_unlock_irqrestore(&ioapic_lock, flags);
 241 }
 242
 243 #ifdef CONFIG_SMP
 244 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 245 {
 246         int apic, pin;
 247         struct irq_pin_list *entry = irq_2_pin + irq;
 248
 249         BUG_ON(irq >= NR_IRQS);
 250         for (;;) {
 251                 unsigned int reg;
 252                 apic = entry->apic;
 253                 pin = entry->pin;
 254                 if (pin == -1)
 255                         break;
 256                 io_apic_write(apic, 0x11 + pin*2, dest);
 257                 reg = io_apic_read(apic, 0x10 + pin*2);
 258                 reg &= ~0x000000ff;
 259                 reg |= vector;
 260                 io_apic_modify(apic, reg);
 261                 if (!entry->next)
 262                         break;
 263                 entry = irq_2_pin + entry->next;
 264         }
 265 }
 266
 267 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 268 {
 269         struct irq_cfg *cfg = irq_cfg + irq;
 270         unsigned long flags;
 271         unsigned int dest;
 272         cpumask_t tmp;
 273
 274         cpus_and(tmp, mask, cpu_online_map);
 275         if (cpus_empty(tmp))
 276                 return;
 277
 278         if (assign_irq_vector(irq, mask))
 279                 return;
 280
 281         cpus_and(tmp, cfg->domain, mask);
 282         dest = cpu_mask_to_apicid(tmp);
 283
 284         /*
 285          * Only the high 8 bits are valid.
 286          */
 287         dest = SET_APIC_LOGICAL_ID(dest);
 288
 289         spin_lock_irqsave(&ioapic_lock, flags);
 290         __target_IO_APIC_irq(irq, dest, cfg->vector);
 291         irq_desc[irq].affinity = mask;
 292         spin_unlock_irqrestore(&ioapic_lock, flags);
 293 }
 294 #endif
 295
 296 /*
 297  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 298  * shared ISA-space IRQs, so we have to support them. We are super
 299  * fast in the common case, and fast for shared ISA-space IRQs.
 300  */
 301 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 302 {
 303         static int first_free_entry = NR_IRQS;
 304         struct irq_pin_list *entry = irq_2_pin + irq;
 305
 306         BUG_ON(irq >= NR_IRQS);
 307         while (entry->next)
 308                 entry = irq_2_pin + entry->next;
 309
 310         if (entry->pin != -1) {
 311                 entry->next = first_free_entry;
 312                 entry = irq_2_pin + entry->next;
 313                 if (++first_free_entry >= PIN_MAP_SIZE)
 314                         panic("io_apic.c: ran out of irq_2_pin entries!");
 315         }
 316         entry->apic = apic;
 317         entry->pin = pin;
 318 }
 319
 320
 321 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 322                                                                         \
 323         static void name##_IO_APIC_irq (unsigned int irq)               \
 324         __DO_ACTION(R, ACTION, FINAL)
 325
 326 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 327                                                 /* mask = 1 */
 328 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 329                                                 /* mask = 0 */
 330
 331 static void mask_IO_APIC_irq (unsigned int irq)
 332 {
 333         unsigned long flags;
 334
 335         spin_lock_irqsave(&ioapic_lock, flags);
 336         __mask_IO_APIC_irq(irq);
 337         spin_unlock_irqrestore(&ioapic_lock, flags);
 338 }
 339
 340 static void unmask_IO_APIC_irq (unsigned int irq)
 341 {
 342         unsigned long flags;
 343
 344         spin_lock_irqsave(&ioapic_lock, flags);
 345         __unmask_IO_APIC_irq(irq);
 346         spin_unlock_irqrestore(&ioapic_lock, flags);
 347 }
 348
 349 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 350 {
 351         struct IO_APIC_route_entry entry;
 352
 353         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 354         entry = ioapic_read_entry(apic, pin);
 355         if (entry.delivery_mode == dest_SMI)
 356                 return;
 357         /*
 358          * Disable it in the IO-APIC irq-routing table:
 359          */
 360         ioapic_mask_entry(apic, pin);
 361 }
 362
 363 static void clear_IO_APIC (void)
 364 {
 365         int apic, pin;
 366
 367         for (apic = 0; apic < nr_ioapics; apic++)
 368                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 369                         clear_IO_APIC_pin(apic, pin);
 370 }
 371
 372 int skip_ioapic_setup;
 373 int ioapic_force;
 374
 375 /* dummy parsing: see setup.c */
 376
 377 static int __init disable_ioapic_setup(char *str)
 378 {
 379         skip_ioapic_setup = 1;
 380         return 0;
 381 }
 382 early_param("noapic", disable_ioapic_setup);
 383
 384 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 385 static int __init disable_timer_pin_setup(char *arg)
 386 {
 387         disable_timer_pin_1 = 1;
 388         return 1;
 389 }
 390 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 391
 392 static int __init setup_disable_8254_timer(char *s)
 393 {
 394         timer_over_8254 = -1;
 395         return 1;
 396 }
 397 static int __init setup_enable_8254_timer(char *s)
 398 {
 399         timer_over_8254 = 2;
 400         return 1;
 401 }
 402
 403 __setup("disable_8254_timer", setup_disable_8254_timer);
 404 __setup("enable_8254_timer", setup_enable_8254_timer);
 405
 406
 407 /*
 408  * Find the IRQ entry number of a certain pin.
 409  */
 410 static int find_irq_entry(int apic, int pin, int type)
 411 {
 412         int i;
 413
 414         for (i = 0; i < mp_irq_entries; i++)
 415                 if (mp_irqs[i].mpc_irqtype == type &&
 416                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 417                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 418                     mp_irqs[i].mpc_dstirq == pin)
 419                         return i;
 420
 421         return -1;
 422 }
 423
 424 /*
 425  * Find the pin to which IRQ[irq] (ISA) is connected
 426  */
 427 static int __init find_isa_irq_pin(int irq, int type)
 428 {
 429         int i;
 430
 431         for (i = 0; i < mp_irq_entries; i++) {
 432                 int lbus = mp_irqs[i].mpc_srcbus;
 433
 434                 if (test_bit(lbus, mp_bus_not_pci) &&
 435                     (mp_irqs[i].mpc_irqtype == type) &&
 436                     (mp_irqs[i].mpc_srcbusirq == irq))
 437
 438                         return mp_irqs[i].mpc_dstirq;
 439         }
 440         return -1;
 441 }
 442
 443 static int __init find_isa_irq_apic(int irq, int type)
 444 {
 445         int i;
 446
 447         for (i = 0; i < mp_irq_entries; i++) {
 448                 int lbus = mp_irqs[i].mpc_srcbus;
 449
 450                 if (test_bit(lbus, mp_bus_not_pci) &&
 451                     (mp_irqs[i].mpc_irqtype == type) &&
 452                     (mp_irqs[i].mpc_srcbusirq == irq))
 453                         break;
 454         }
 455         if (i < mp_irq_entries) {
 456                 int apic;
 457                 for(apic = 0; apic < nr_ioapics; apic++) {
 458                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 459                                 return apic;
 460                 }
 461         }
 462
 463         return -1;
 464 }
 465
 466 /*
 467  * Find a specific PCI IRQ entry.
 468  * Not an __init, possibly needed by modules
 469  */
 470 static int pin_2_irq(int idx, int apic, int pin);
 471
 472 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 473 {
 474         int apic, i, best_guess = -1;
 475
 476         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 477                 bus, slot, pin);
 478         if (mp_bus_id_to_pci_bus[bus] == -1) {
 479                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 480                 return -1;
 481         }
 482         for (i = 0; i < mp_irq_entries; i++) {
 483                 int lbus = mp_irqs[i].mpc_srcbus;
 484
 485                 for (apic = 0; apic < nr_ioapics; apic++)
 486                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 487                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 488                                 break;
 489
 490                 if (!test_bit(lbus, mp_bus_not_pci) &&
 491                     !mp_irqs[i].mpc_irqtype &&
 492                     (bus == lbus) &&
 493                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 494                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 495
 496                         if (!(apic || IO_APIC_IRQ(irq)))
 497                                 continue;
 498
 499                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 500                                 return irq;
 501                         /*
 502                          * Use the first all-but-pin matching entry as a
 503                          * best-guess fuzzy result for broken mptables.
 504                          */
 505                         if (best_guess < 0)
 506                                 best_guess = irq;
 507                 }
 508         }
 509         BUG_ON(best_guess >= NR_IRQS);
 510         return best_guess;
 511 }
 512
 513 /* ISA interrupts are always polarity zero edge triggered,
 514  * when listed as conforming in the MP table. */
 515
 516 #define default_ISA_trigger(idx)        (0)
 517 #define default_ISA_polarity(idx)       (0)
 518
 519 /* PCI interrupts are always polarity one level triggered,
 520  * when listed as conforming in the MP table. */
 521
 522 #define default_PCI_trigger(idx)        (1)
 523 #define default_PCI_polarity(idx)       (1)
 524
 525 static int __init MPBIOS_polarity(int idx)
 526 {
 527         int bus = mp_irqs[idx].mpc_srcbus;
 528         int polarity;
 529
 530         /*
 531          * Determine IRQ line polarity (high active or low active):
 532          */
 533         switch (mp_irqs[idx].mpc_irqflag & 3)
 534         {
 535                 case 0: /* conforms, ie. bus-type dependent polarity */
 536                         if (test_bit(bus, mp_bus_not_pci))
 537                                 polarity = default_ISA_polarity(idx);
 538                         else
 539                                 polarity = default_PCI_polarity(idx);
 540                         break;
 541                 case 1: /* high active */
 542                 {
 543                         polarity = 0;
 544                         break;
 545                 }
 546                 case 2: /* reserved */
 547                 {
 548                         printk(KERN_WARNING "broken BIOS!!\n");
 549                         polarity = 1;
 550                         break;
 551                 }
 552                 case 3: /* low active */
 553                 {
 554                         polarity = 1;
 555                         break;
 556                 }
 557                 default: /* invalid */
 558                 {
 559                         printk(KERN_WARNING "broken BIOS!!\n");
 560                         polarity = 1;
 561                         break;
 562                 }
 563         }
 564         return polarity;
 565 }
 566
 567 static int MPBIOS_trigger(int idx)
 568 {
 569         int bus = mp_irqs[idx].mpc_srcbus;
 570         int trigger;
 571
 572         /*
 573          * Determine IRQ trigger mode (edge or level sensitive):
 574          */
 575         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 576         {
 577                 case 0: /* conforms, ie. bus-type dependent */
 578                         if (test_bit(bus, mp_bus_not_pci))
 579                                 trigger = default_ISA_trigger(idx);
 580                         else
 581                                 trigger = default_PCI_trigger(idx);
 582                         break;
 583                 case 1: /* edge */
 584                 {
 585                         trigger = 0;
 586                         break;
 587                 }
 588                 case 2: /* reserved */
 589                 {
 590                         printk(KERN_WARNING "broken BIOS!!\n");
 591                         trigger = 1;
 592                         break;
 593                 }
 594                 case 3: /* level */
 595                 {
 596                         trigger = 1;
 597                         break;
 598                 }
 599                 default: /* invalid */
 600                 {
 601                         printk(KERN_WARNING "broken BIOS!!\n");
 602                         trigger = 0;
 603                         break;
 604                 }
 605         }
 606         return trigger;
 607 }
 608
 609 static inline int irq_polarity(int idx)
 610 {
 611         return MPBIOS_polarity(idx);
 612 }
 613
 614 static inline int irq_trigger(int idx)
 615 {
 616         return MPBIOS_trigger(idx);
 617 }
 618
 619 static int pin_2_irq(int idx, int apic, int pin)
 620 {
 621         int irq, i;
 622         int bus = mp_irqs[idx].mpc_srcbus;
 623
 624         /*
 625          * Debugging check, we are in big trouble if this message pops up!
 626          */
 627         if (mp_irqs[idx].mpc_dstirq != pin)
 628                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 629
 630         if (test_bit(bus, mp_bus_not_pci)) {
 631                 irq = mp_irqs[idx].mpc_srcbusirq;
 632         } else {
 633                 /*
 634                  * PCI IRQs are mapped in order
 635                  */
 636                 i = irq = 0;
 637                 while (i < apic)
 638                         irq += nr_ioapic_registers[i++];
 639                 irq += pin;
 640         }
 641         BUG_ON(irq >= NR_IRQS);
 642         return irq;
 643 }
 644
 645 static int __assign_irq_vector(int irq, cpumask_t mask)
 646 {
 647         /*
 648          * NOTE! The local APIC isn't very good at handling
 649          * multiple interrupts at the same interrupt level.
 650          * As the interrupt level is determined by taking the
 651          * vector number and shifting that right by 4, we
 652          * want to spread these out a bit so that they don't
 653          * all fall in the same interrupt level.
 654          *
 655          * Also, we've got to be careful not to trash gate
 656          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 657          */
 658         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 659         unsigned int old_vector;
 660         int cpu;
 661         struct irq_cfg *cfg;
 662
 663         BUG_ON((unsigned)irq >= NR_IRQS);
 664         cfg = &irq_cfg[irq];
 665
 666         /* Only try and allocate irqs on cpus that are present */
 667         cpus_and(mask, mask, cpu_online_map);
 668
 669         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
 670                 return -EBUSY;
 671
 672         old_vector = cfg->vector;
 673         if (old_vector) {
 674                 cpumask_t tmp;
 675                 cpus_and(tmp, cfg->domain, mask);
 676                 if (!cpus_empty(tmp))
 677                         return 0;
 678         }
 679
 680         for_each_cpu_mask(cpu, mask) {
 681                 cpumask_t domain, new_mask;
 682                 int new_cpu;
 683                 int vector, offset;
 684
 685                 domain = vector_allocation_domain(cpu);
 686                 cpus_and(new_mask, domain, cpu_online_map);
 687
 688                 vector = current_vector;
 689                 offset = current_offset;
 690 next:
 691                 vector += 8;
 692                 if (vector >= FIRST_SYSTEM_VECTOR) {
 693                         /* If we run out of vectors on large boxen, must share them. */
 694                         offset = (offset + 1) % 8;
 695                         vector = FIRST_DEVICE_VECTOR + offset;
 696                 }
 697                 if (unlikely(current_vector == vector))
 698                         continue;
 699                 if (vector == IA32_SYSCALL_VECTOR)
 700                         goto next;
 701                 for_each_cpu_mask(new_cpu, new_mask)
 702                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 703                                 goto next;
 704                 /* Found one! */
 705                 current_vector = vector;
 706                 current_offset = offset;
 707                 if (old_vector) {
 708                         cfg->move_in_progress = 1;
 709                         cfg->old_domain = cfg->domain;
 710                 }
 711                 for_each_cpu_mask(new_cpu, new_mask)
 712                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 713                 cfg->vector = vector;
 714                 cfg->domain = domain;
 715                 return 0;
 716         }
 717         return -ENOSPC;
 718 }
 719
 720 static int assign_irq_vector(int irq, cpumask_t mask)
 721 {
 722         int err;
 723         unsigned long flags;
 724
 725         spin_lock_irqsave(&vector_lock, flags);
 726         err = __assign_irq_vector(irq, mask);
 727         spin_unlock_irqrestore(&vector_lock, flags);
 728         return err;
 729 }
 730
 731 static void __clear_irq_vector(int irq)
 732 {
 733         struct irq_cfg *cfg;
 734         cpumask_t mask;
 735         int cpu, vector;
 736
 737         BUG_ON((unsigned)irq >= NR_IRQS);
 738         cfg = &irq_cfg[irq];
 739         BUG_ON(!cfg->vector);
 740
 741         vector = cfg->vector;
 742         cpus_and(mask, cfg->domain, cpu_online_map);
 743         for_each_cpu_mask(cpu, mask)
 744                 per_cpu(vector_irq, cpu)[vector] = -1;
 745
 746         cfg->vector = 0;
 747         cfg->domain = CPU_MASK_NONE;
 748 }
 749
 750 void __setup_vector_irq(int cpu)
 751 {
 752         /* Initialize vector_irq on a new cpu */
 753         /* This function must be called with vector_lock held */
 754         int irq, vector;
 755
 756         /* Mark the inuse vectors */
 757         for (irq = 0; irq < NR_IRQS; ++irq) {
 758                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 759                         continue;
 760                 vector = irq_cfg[irq].vector;
 761                 per_cpu(vector_irq, cpu)[vector] = irq;
 762         }
 763         /* Mark the free vectors */
 764         for (vector = 0; vector < NR_VECTORS; ++vector) {
 765                 irq = per_cpu(vector_irq, cpu)[vector];
 766                 if (irq < 0)
 767                         continue;
 768                 if (!cpu_isset(cpu, irq_cfg[irq].domain))
 769                         per_cpu(vector_irq, cpu)[vector] = -1;
 770         }
 771 }
 772
 773
 774 static struct irq_chip ioapic_chip;
 775
 776 static void ioapic_register_intr(int irq, unsigned long trigger)
 777 {
 778         if (trigger)
 779                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 780                                               handle_fasteoi_irq, "fasteoi");
 781         else
 782                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 783                                               handle_edge_irq, "edge");
 784 }
 785
 786 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
 787                               int trigger, int polarity)
 788 {
 789         struct irq_cfg *cfg = irq_cfg + irq;
 790         struct IO_APIC_route_entry entry;
 791         cpumask_t mask;
 792         unsigned long flags;
 793
 794         if (!IO_APIC_IRQ(irq))
 795                 return;
 796
 797         mask = TARGET_CPUS;
 798         if (assign_irq_vector(irq, mask))
 799                 return;
 800
 801         cpus_and(mask, cfg->domain, mask);
 802
 803         apic_printk(APIC_VERBOSE,KERN_DEBUG
 804                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
 805                     "IRQ %d Mode:%i Active:%i)\n",
 806                     apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
 807                     irq, trigger, polarity);
 808
 809         /*
 810          * add it to the IO-APIC irq-routing table:
 811          */
 812         memset(&entry,0,sizeof(entry));
 813
 814         entry.delivery_mode = INT_DELIVERY_MODE;
 815         entry.dest_mode = INT_DEST_MODE;
 816         entry.dest = cpu_mask_to_apicid(mask);
 817         entry.mask = 0;                         /* enable IRQ */
 818         entry.trigger = trigger;
 819         entry.polarity = polarity;
 820         entry.vector = cfg->vector;
 821
 822         /* Mask level triggered irqs.
 823          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
 824          */
 825         if (trigger)
 826                 entry.mask = 1;
 827
 828         ioapic_register_intr(irq, trigger);
 829         if (irq < 16)
 830                 disable_8259A_irq(irq);
 831
 832         ioapic_write_entry(apic, pin, entry);
 833
 834         spin_lock_irqsave(&ioapic_lock, flags);
 835         irq_desc[irq].affinity = TARGET_CPUS;
 836         spin_unlock_irqrestore(&ioapic_lock, flags);
 837 }
 838
 839 static void __init setup_IO_APIC_irqs(void)
 840 {
 841         int apic, pin, idx, irq, first_notcon = 1;
 842
 843         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 844
 845         for (apic = 0; apic < nr_ioapics; apic++) {
 846         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 847
 848                 idx = find_irq_entry(apic,pin,mp_INT);
 849                 if (idx == -1) {
 850                         if (first_notcon) {
 851                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 852                                 first_notcon = 0;
 853                         } else
 854                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 855                         continue;
 856                 }
 857
 858                 irq = pin_2_irq(idx, apic, pin);
 859                 add_pin_to_irq(irq, apic, pin);
 860
 861                 setup_IO_APIC_irq(apic, pin, irq,
 862                                   irq_trigger(idx), irq_polarity(idx));
 863         }
 864         }
 865
 866         if (!first_notcon)
 867                 apic_printk(APIC_VERBOSE," not connected.\n");
 868 }
 869
 870 /*
 871  * Set up the 8259A-master output pin as broadcast to all
 872  * CPUs.
 873  */
 874 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 875 {
 876         struct IO_APIC_route_entry entry;
 877         unsigned long flags;
 878
 879         memset(&entry,0,sizeof(entry));
 880
 881         disable_8259A_irq(0);
 882
 883         /* mask LVT0 */
 884         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 885
 886         /*
 887          * We use logical delivery to get the timer IRQ
 888          * to the first CPU.
 889          */
 890         entry.dest_mode = INT_DEST_MODE;
 891         entry.mask = 0;                                 /* unmask IRQ now */
 892         entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
 893         entry.delivery_mode = INT_DELIVERY_MODE;
 894         entry.polarity = 0;
 895         entry.trigger = 0;
 896         entry.vector = vector;
 897
 898         /*
 899          * The timer IRQ doesn't have to know that behind the
 900          * scene we have a 8259A-master in AEOI mode ...
 901          */
 902         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 903
 904         /*
 905          * Add it to the IO-APIC irq-routing table:
 906          */
 907         spin_lock_irqsave(&ioapic_lock, flags);
 908         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 909         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 910         spin_unlock_irqrestore(&ioapic_lock, flags);
 911
 912         enable_8259A_irq(0);
 913 }
 914
 915 void __init UNEXPECTED_IO_APIC(void)
 916 {
 917 }
 918
 919 void __apicdebuginit print_IO_APIC(void)
 920 {
 921         int apic, i;
 922         union IO_APIC_reg_00 reg_00;
 923         union IO_APIC_reg_01 reg_01;
 924         union IO_APIC_reg_02 reg_02;
 925         unsigned long flags;
 926
 927         if (apic_verbosity == APIC_QUIET)
 928                 return;
 929
 930         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 931         for (i = 0; i < nr_ioapics; i++)
 932                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 933                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 934
 935         /*
 936          * We are a bit conservative about what we expect.  We have to
 937          * know about every hardware change ASAP.
 938          */
 939         printk(KERN_INFO "testing the IO APIC.......................\n");
 940
 941         for (apic = 0; apic < nr_ioapics; apic++) {
 942
 943         spin_lock_irqsave(&ioapic_lock, flags);
 944         reg_00.raw = io_apic_read(apic, 0);
 945         reg_01.raw = io_apic_read(apic, 1);
 946         if (reg_01.bits.version >= 0x10)
 947                 reg_02.raw = io_apic_read(apic, 2);
 948         spin_unlock_irqrestore(&ioapic_lock, flags);
 949
 950         printk("\n");
 951         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 952         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 953         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 954         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 955                 UNEXPECTED_IO_APIC();
 956
 957         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 958         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 959         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 960                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 961                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 962                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 963                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 964                 (reg_01.bits.entries != 0x2E) &&
 965                 (reg_01.bits.entries != 0x3F) &&
 966                 (reg_01.bits.entries != 0x03)
 967         )
 968                 UNEXPECTED_IO_APIC();
 969
 970         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 971         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 972         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 973                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 974                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 975                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 976                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 977                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 978         )
 979                 UNEXPECTED_IO_APIC();
 980         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 981                 UNEXPECTED_IO_APIC();
 982
 983         if (reg_01.bits.version >= 0x10) {
 984                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 985                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 986                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 987                         UNEXPECTED_IO_APIC();
 988         }
 989
 990         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 991
 992         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
 993                           " Stat Dmod Deli Vect:   \n");
 994
 995         for (i = 0; i <= reg_01.bits.entries; i++) {
 996                 struct IO_APIC_route_entry entry;
 997
 998                 entry = ioapic_read_entry(apic, i);
 999
1000                 printk(KERN_DEBUG " %02x %03X ",
1001                         i,
1002                         entry.dest
1003                 );
1004
1005                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1006                         entry.mask,
1007                         entry.trigger,
1008                         entry.irr,
1009                         entry.polarity,
1010                         entry.delivery_status,
1011                         entry.dest_mode,
1012                         entry.delivery_mode,
1013                         entry.vector
1014                 );
1015         }
1016         }
1017         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1018         for (i = 0; i < NR_IRQS; i++) {
1019                 struct irq_pin_list *entry = irq_2_pin + i;
1020                 if (entry->pin < 0)
1021                         continue;
1022                 printk(KERN_DEBUG "IRQ%d ", i);
1023                 for (;;) {
1024                         printk("-> %d:%d", entry->apic, entry->pin);
1025                         if (!entry->next)
1026                                 break;
1027                         entry = irq_2_pin + entry->next;
1028                 }
1029                 printk("\n");
1030         }
1031
1032         printk(KERN_INFO ".................................... done.\n");
1033
1034         return;
1035 }
1036
1037 #if 0
1038
1039 static __apicdebuginit void print_APIC_bitfield (int base)
1040 {
1041         unsigned int v;
1042         int i, j;
1043
1044         if (apic_verbosity == APIC_QUIET)
1045                 return;
1046
1047         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1048         for (i = 0; i < 8; i++) {
1049                 v = apic_read(base + i*0x10);
1050                 for (j = 0; j < 32; j++) {
1051                         if (v & (1<<j))
1052                                 printk("1");
1053                         else
1054                                 printk("0");
1055                 }
1056                 printk("\n");
1057         }
1058 }
1059
1060 void __apicdebuginit print_local_APIC(void * dummy)
1061 {
1062         unsigned int v, ver, maxlvt;
1063
1064         if (apic_verbosity == APIC_QUIET)
1065                 return;
1066
1067         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1068                 smp_processor_id(), hard_smp_processor_id());
1069         v = apic_read(APIC_ID);
1070         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1071         v = apic_read(APIC_LVR);
1072         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1073         ver = GET_APIC_VERSION(v);
1074         maxlvt = get_maxlvt();
1075
1076         v = apic_read(APIC_TASKPRI);
1077         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1078
1079         v = apic_read(APIC_ARBPRI);
1080         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1081                 v & APIC_ARBPRI_MASK);
1082         v = apic_read(APIC_PROCPRI);
1083         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1084
1085         v = apic_read(APIC_EOI);
1086         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1087         v = apic_read(APIC_RRR);
1088         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1089         v = apic_read(APIC_LDR);
1090         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1091         v = apic_read(APIC_DFR);
1092         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1093         v = apic_read(APIC_SPIV);
1094         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1095
1096         printk(KERN_DEBUG "... APIC ISR field:\n");
1097         print_APIC_bitfield(APIC_ISR);
1098         printk(KERN_DEBUG "... APIC TMR field:\n");
1099         print_APIC_bitfield(APIC_TMR);
1100         printk(KERN_DEBUG "... APIC IRR field:\n");
1101         print_APIC_bitfield(APIC_IRR);
1102
1103         v = apic_read(APIC_ESR);
1104         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1105
1106         v = apic_read(APIC_ICR);
1107         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1108         v = apic_read(APIC_ICR2);
1109         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1110
1111         v = apic_read(APIC_LVTT);
1112         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1113
1114         if (maxlvt > 3) {                       /* PC is LVT#4. */
1115                 v = apic_read(APIC_LVTPC);
1116                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1117         }
1118         v = apic_read(APIC_LVT0);
1119         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1120         v = apic_read(APIC_LVT1);
1121         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1122
1123         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1124                 v = apic_read(APIC_LVTERR);
1125                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1126         }
1127
1128         v = apic_read(APIC_TMICT);
1129         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1130         v = apic_read(APIC_TMCCT);
1131         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1132         v = apic_read(APIC_TDCR);
1133         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1134         printk("\n");
1135 }
1136
1137 void print_all_local_APICs (void)
1138 {
1139         on_each_cpu(print_local_APIC, NULL, 1, 1);
1140 }
1141
1142 void __apicdebuginit print_PIC(void)
1143 {
1144         unsigned int v;
1145         unsigned long flags;
1146
1147         if (apic_verbosity == APIC_QUIET)
1148                 return;
1149
1150         printk(KERN_DEBUG "\nprinting PIC contents\n");
1151
1152         spin_lock_irqsave(&i8259A_lock, flags);
1153
1154         v = inb(0xa1) << 8 | inb(0x21);
1155         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1156
1157         v = inb(0xa0) << 8 | inb(0x20);
1158         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1159
1160         outb(0x0b,0xa0);
1161         outb(0x0b,0x20);
1162         v = inb(0xa0) << 8 | inb(0x20);
1163         outb(0x0a,0xa0);
1164         outb(0x0a,0x20);
1165
1166         spin_unlock_irqrestore(&i8259A_lock, flags);
1167
1168         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1169
1170         v = inb(0x4d1) << 8 | inb(0x4d0);
1171         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1172 }
1173
1174 #endif  /*  0  */
1175
1176 static void __init enable_IO_APIC(void)
1177 {
1178         union IO_APIC_reg_01 reg_01;
1179         int i8259_apic, i8259_pin;
1180         int i, apic;
1181         unsigned long flags;
1182
1183         for (i = 0; i < PIN_MAP_SIZE; i++) {
1184                 irq_2_pin[i].pin = -1;
1185                 irq_2_pin[i].next = 0;
1186         }
1187
1188         /*
1189          * The number of IO-APIC IRQ registers (== #pins):
1190          */
1191         for (apic = 0; apic < nr_ioapics; apic++) {
1192                 spin_lock_irqsave(&ioapic_lock, flags);
1193                 reg_01.raw = io_apic_read(apic, 1);
1194                 spin_unlock_irqrestore(&ioapic_lock, flags);
1195                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1196         }
1197         for(apic = 0; apic < nr_ioapics; apic++) {
1198                 int pin;
1199                 /* See if any of the pins is in ExtINT mode */
1200                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1201                         struct IO_APIC_route_entry entry;
1202                         entry = ioapic_read_entry(apic, pin);
1203
1204                         /* If the interrupt line is enabled and in ExtInt mode
1205                          * I have found the pin where the i8259 is connected.
1206                          */
1207                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1208                                 ioapic_i8259.apic = apic;
1209                                 ioapic_i8259.pin  = pin;
1210                                 goto found_i8259;
1211                         }
1212                 }
1213         }
1214  found_i8259:
1215         /* Look to see what if the MP table has reported the ExtINT */
1216         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1217         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1218         /* Trust the MP table if nothing is setup in the hardware */
1219         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1220                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1221                 ioapic_i8259.pin  = i8259_pin;
1222                 ioapic_i8259.apic = i8259_apic;
1223         }
1224         /* Complain if the MP table and the hardware disagree */
1225         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1226                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1227         {
1228                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1229         }
1230
1231         /*
1232          * Do not trust the IO-APIC being empty at bootup
1233          */
1234         clear_IO_APIC();
1235 }
1236
1237 /*
1238  * Not an __init, needed by the reboot code
1239  */
1240 void disable_IO_APIC(void)
1241 {
1242         /*
1243          * Clear the IO-APIC before rebooting:
1244          */
1245         clear_IO_APIC();
1246
1247         /*
1248          * If the i8259 is routed through an IOAPIC
1249          * Put that IOAPIC in virtual wire mode
1250          * so legacy interrupts can be delivered.
1251          */
1252         if (ioapic_i8259.pin != -1) {
1253                 struct IO_APIC_route_entry entry;
1254
1255                 memset(&entry, 0, sizeof(entry));
1256                 entry.mask            = 0; /* Enabled */
1257                 entry.trigger         = 0; /* Edge */
1258                 entry.irr             = 0;
1259                 entry.polarity        = 0; /* High */
1260                 entry.delivery_status = 0;
1261                 entry.dest_mode       = 0; /* Physical */
1262                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1263                 entry.vector          = 0;
1264                 entry.dest          = GET_APIC_ID(apic_read(APIC_ID));
1265
1266                 /*
1267                  * Add it to the IO-APIC irq-routing table:
1268                  */
1269                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1270         }
1271
1272         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1273 }
1274
1275 /*
1276  * There is a nasty bug in some older SMP boards, their mptable lies
1277  * about the timer IRQ. We do the following to work around the situation:
1278  *
1279  *      - timer IRQ defaults to IO-APIC IRQ
1280  *      - if this function detects that timer IRQs are defunct, then we fall
1281  *        back to ISA timer IRQs
1282  */
1283 static int __init timer_irq_works(void)
1284 {
1285         unsigned long t1 = jiffies;
1286
1287         local_irq_enable();
1288         /* Let ten ticks pass... */
1289         mdelay((10 * 1000) / HZ);
1290
1291         /*
1292          * Expect a few ticks at least, to be sure some possible
1293          * glue logic does not lock up after one or two first
1294          * ticks in a non-ExtINT mode.  Also the local APIC
1295          * might have cached one ExtINT interrupt.  Finally, at
1296          * least one tick may be lost due to delays.
1297          */
1298
1299         /* jiffies wrap? */
1300         if (jiffies - t1 > 4)
1301                 return 1;
1302         return 0;
1303 }
1304
1305 /*
1306  * In the SMP+IOAPIC case it might happen that there are an unspecified
1307  * number of pending IRQ events unhandled. These cases are very rare,
1308  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1309  * better to do it this way as thus we do not have to be aware of
1310  * 'pending' interrupts in the IRQ path, except at this point.
1311  */
1312 /*
1313  * Edge triggered needs to resend any interrupt
1314  * that was delayed but this is now handled in the device
1315  * independent code.
1316  */
1317
1318 /*
1319  * Starting up a edge-triggered IO-APIC interrupt is
1320  * nasty - we need to make sure that we get the edge.
1321  * If it is already asserted for some reason, we need
1322  * return 1 to indicate that is was pending.
1323  *
1324  * This is not complete - we should be able to fake
1325  * an edge even if it isn't on the 8259A...
1326  */
1327
1328 static unsigned int startup_ioapic_irq(unsigned int irq)
1329 {
1330         int was_pending = 0;
1331         unsigned long flags;
1332
1333         spin_lock_irqsave(&ioapic_lock, flags);
1334         if (irq < 16) {
1335                 disable_8259A_irq(irq);
1336                 if (i8259A_irq_pending(irq))
1337                         was_pending = 1;
1338         }
1339         __unmask_IO_APIC_irq(irq);
1340         spin_unlock_irqrestore(&ioapic_lock, flags);
1341
1342         return was_pending;
1343 }
1344
1345 static int ioapic_retrigger_irq(unsigned int irq)
1346 {
1347         struct irq_cfg *cfg = &irq_cfg[irq];
1348         cpumask_t mask;
1349         unsigned long flags;
1350
1351         spin_lock_irqsave(&vector_lock, flags);
1352         cpus_clear(mask);
1353         cpu_set(first_cpu(cfg->domain), mask);
1354
1355         send_IPI_mask(mask, cfg->vector);
1356         spin_unlock_irqrestore(&vector_lock, flags);
1357
1358         return 1;
1359 }
1360
1361 /*
1362  * Level and edge triggered IO-APIC interrupts need different handling,
1363  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1364  * handled with the level-triggered descriptor, but that one has slightly
1365  * more overhead. Level-triggered interrupts cannot be handled with the
1366  * edge-triggered handler, without risking IRQ storms and other ugly
1367  * races.
1368  */
1369
1370 #ifdef CONFIG_SMP
1371 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1372 {
1373         unsigned vector, me;
1374         ack_APIC_irq();
1375         exit_idle();
1376         irq_enter();
1377
1378         me = smp_processor_id();
1379         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1380                 unsigned int irq;
1381                 struct irq_desc *desc;
1382                 struct irq_cfg *cfg;
1383                 irq = __get_cpu_var(vector_irq)[vector];
1384                 if (irq >= NR_IRQS)
1385                         continue;
1386
1387                 desc = irq_desc + irq;
1388                 cfg = irq_cfg + irq;
1389                 spin_lock(&desc->lock);
1390                 if (!cfg->move_cleanup_count)
1391                         goto unlock;
1392
1393                 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1394                         goto unlock;
1395
1396                 __get_cpu_var(vector_irq)[vector] = -1;
1397                 cfg->move_cleanup_count--;
1398 unlock:
1399                 spin_unlock(&desc->lock);
1400         }
1401
1402         irq_exit();
1403 }
1404
1405 static void irq_complete_move(unsigned int irq)
1406 {
1407         struct irq_cfg *cfg = irq_cfg + irq;
1408         unsigned vector, me;
1409
1410         if (likely(!cfg->move_in_progress))
1411                 return;
1412
1413         vector = ~get_irq_regs()->orig_rax;
1414         me = smp_processor_id();
1415         if ((vector == cfg->vector) &&
1416             cpu_isset(smp_processor_id(), cfg->domain)) {
1417                 cpumask_t cleanup_mask;
1418
1419                 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1420                 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1421                 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1422                 cfg->move_in_progress = 0;
1423         }
1424 }
1425 #else
1426 static inline void irq_complete_move(unsigned int irq) {}
1427 #endif
1428
1429 static void ack_apic_edge(unsigned int irq)
1430 {
1431         irq_complete_move(irq);
1432         move_native_irq(irq);
1433         ack_APIC_irq();
1434 }
1435
1436 static void ack_apic_level(unsigned int irq)
1437 {
1438         int do_unmask_irq = 0;
1439
1440         irq_complete_move(irq);
1441 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1442         /* If we are moving the irq we need to mask it */
1443         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1444                 do_unmask_irq = 1;
1445                 mask_IO_APIC_irq(irq);
1446         }
1447 #endif
1448
1449         /*
1450          * We must acknowledge the irq before we move it or the acknowledge will
1451          * not propogate properly.
1452          */
1453         ack_APIC_irq();
1454
1455         /* Now we can move and renable the irq */
1456         move_masked_irq(irq);
1457         if (unlikely(do_unmask_irq))
1458                 unmask_IO_APIC_irq(irq);
1459 }
1460
1461 static struct irq_chip ioapic_chip __read_mostly = {
1462         .name           = "IO-APIC",
1463         .startup        = startup_ioapic_irq,
1464         .mask           = mask_IO_APIC_irq,
1465         .unmask         = unmask_IO_APIC_irq,
1466         .ack            = ack_apic_edge,
1467         .eoi            = ack_apic_level,
1468 #ifdef CONFIG_SMP
1469         .set_affinity   = set_ioapic_affinity_irq,
1470 #endif
1471         .retrigger      = ioapic_retrigger_irq,
1472 };
1473
1474 static inline void init_IO_APIC_traps(void)
1475 {
1476         int irq;
1477
1478         /*
1479          * NOTE! The local APIC isn't very good at handling
1480          * multiple interrupts at the same interrupt level.
1481          * As the interrupt level is determined by taking the
1482          * vector number and shifting that right by 4, we
1483          * want to spread these out a bit so that they don't
1484          * all fall in the same interrupt level.
1485          *
1486          * Also, we've got to be careful not to trash gate
1487          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1488          */
1489         for (irq = 0; irq < NR_IRQS ; irq++) {
1490                 int tmp = irq;
1491                 if (IO_APIC_IRQ(tmp) && !irq_cfg[tmp].vector) {
1492                         /*
1493                          * Hmm.. We don't have an entry for this,
1494                          * so default to an old-fashioned 8259
1495                          * interrupt if we can..
1496                          */
1497                         if (irq < 16)
1498                                 make_8259A_irq(irq);
1499                         else
1500                                 /* Strange. Oh, well.. */
1501                                 irq_desc[irq].chip = &no_irq_chip;
1502                 }
1503         }
1504 }
1505
1506 static void enable_lapic_irq (unsigned int irq)
1507 {
1508         unsigned long v;
1509
1510         v = apic_read(APIC_LVT0);
1511         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1512 }
1513
1514 static void disable_lapic_irq (unsigned int irq)
1515 {
1516         unsigned long v;
1517
1518         v = apic_read(APIC_LVT0);
1519         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1520 }
1521
1522 static void ack_lapic_irq (unsigned int irq)
1523 {
1524         ack_APIC_irq();
1525 }
1526
1527 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1528
1529 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1530         .typename = "local-APIC-edge",
1531         .startup = NULL, /* startup_irq() not used for IRQ0 */
1532         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1533         .enable = enable_lapic_irq,
1534         .disable = disable_lapic_irq,
1535         .ack = ack_lapic_irq,
1536         .end = end_lapic_irq,
1537 };
1538
1539 static void setup_nmi (void)
1540 {
1541         /*
1542          * Dirty trick to enable the NMI watchdog ...
1543          * We put the 8259A master into AEOI mode and
1544          * unmask on all local APICs LVT0 as NMI.
1545          *
1546          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1547          * is from Maciej W. Rozycki - so we do not have to EOI from
1548          * the NMI handler or the timer interrupt.
1549          */
1550         printk(KERN_INFO "activating NMI Watchdog ...");
1551
1552         enable_NMI_through_LVT0(NULL);
1553
1554         printk(" done.\n");
1555 }
1556
1557 /*
1558  * This looks a bit hackish but it's about the only one way of sending
1559  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1560  * not support the ExtINT mode, unfortunately.  We need to send these
1561  * cycles as some i82489DX-based boards have glue logic that keeps the
1562  * 8259A interrupt line asserted until INTA.  --macro
1563  */
1564 static inline void unlock_ExtINT_logic(void)
1565 {
1566         int apic, pin, i;
1567         struct IO_APIC_route_entry entry0, entry1;
1568         unsigned char save_control, save_freq_select;
1569         unsigned long flags;
1570
1571         pin  = find_isa_irq_pin(8, mp_INT);
1572         apic = find_isa_irq_apic(8, mp_INT);
1573         if (pin == -1)
1574                 return;
1575
1576         spin_lock_irqsave(&ioapic_lock, flags);
1577         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1578         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1579         spin_unlock_irqrestore(&ioapic_lock, flags);
1580         clear_IO_APIC_pin(apic, pin);
1581
1582         memset(&entry1, 0, sizeof(entry1));
1583
1584         entry1.dest_mode = 0;                   /* physical delivery */
1585         entry1.mask = 0;                        /* unmask IRQ now */
1586         entry1.dest = hard_smp_processor_id();
1587         entry1.delivery_mode = dest_ExtINT;
1588         entry1.polarity = entry0.polarity;
1589         entry1.trigger = 0;
1590         entry1.vector = 0;
1591
1592         spin_lock_irqsave(&ioapic_lock, flags);
1593         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1594         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1595         spin_unlock_irqrestore(&ioapic_lock, flags);
1596
1597         save_control = CMOS_READ(RTC_CONTROL);
1598         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1599         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1600                    RTC_FREQ_SELECT);
1601         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1602
1603         i = 100;
1604         while (i-- > 0) {
1605                 mdelay(10);
1606                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1607                         i -= 10;
1608         }
1609
1610         CMOS_WRITE(save_control, RTC_CONTROL);
1611         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1612         clear_IO_APIC_pin(apic, pin);
1613
1614         spin_lock_irqsave(&ioapic_lock, flags);
1615         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1616         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1617         spin_unlock_irqrestore(&ioapic_lock, flags);
1618 }
1619
1620 /*
1621  * This code may look a bit paranoid, but it's supposed to cooperate with
1622  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1623  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1624  * fanatically on his truly buggy board.
1625  *
1626  * FIXME: really need to revamp this for modern platforms only.
1627  */
1628 static inline void check_timer(void)
1629 {
1630         struct irq_cfg *cfg = irq_cfg + 0;
1631         int apic1, pin1, apic2, pin2;
1632
1633         /*
1634          * get/set the timer IRQ vector:
1635          */
1636         disable_8259A_irq(0);
1637         assign_irq_vector(0, TARGET_CPUS);
1638
1639         /*
1640          * Subtle, code in do_timer_interrupt() expects an AEOI
1641          * mode for the 8259A whenever interrupts are routed
1642          * through I/O APICs.  Also IRQ0 has to be enabled in
1643          * the 8259A which implies the virtual wire has to be
1644          * disabled in the local APIC.
1645          */
1646         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1647         init_8259A(1);
1648         if (timer_over_8254 > 0)
1649                 enable_8259A_irq(0);
1650
1651         pin1  = find_isa_irq_pin(0, mp_INT);
1652         apic1 = find_isa_irq_apic(0, mp_INT);
1653         pin2  = ioapic_i8259.pin;
1654         apic2 = ioapic_i8259.apic;
1655
1656         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1657                 cfg->vector, apic1, pin1, apic2, pin2);
1658
1659         if (pin1 != -1) {
1660                 /*
1661                  * Ok, does IRQ0 through the IOAPIC work?
1662                  */
1663                 unmask_IO_APIC_irq(0);
1664                 if (!no_timer_check && timer_irq_works()) {
1665                         nmi_watchdog_default();
1666                         if (nmi_watchdog == NMI_IO_APIC) {
1667                                 disable_8259A_irq(0);
1668                                 setup_nmi();
1669                                 enable_8259A_irq(0);
1670                         }
1671                         if (disable_timer_pin_1 > 0)
1672                                 clear_IO_APIC_pin(0, pin1);
1673                         return;
1674                 }
1675                 clear_IO_APIC_pin(apic1, pin1);
1676                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1677                                 "connected to IO-APIC\n");
1678         }
1679
1680         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1681                                 "through the 8259A ... ");
1682         if (pin2 != -1) {
1683                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1684                         apic2, pin2);
1685                 /*
1686                  * legacy devices should be connected to IO APIC #0
1687                  */
1688                 setup_ExtINT_IRQ0_pin(apic2, pin2, cfg->vector);
1689                 if (timer_irq_works()) {
1690                         apic_printk(APIC_VERBOSE," works.\n");
1691                         nmi_watchdog_default();
1692                         if (nmi_watchdog == NMI_IO_APIC) {
1693                                 setup_nmi();
1694                         }
1695                         return;
1696                 }
1697                 /*
1698                  * Cleanup, just in case ...
1699                  */
1700                 clear_IO_APIC_pin(apic2, pin2);
1701         }
1702         apic_printk(APIC_VERBOSE," failed.\n");
1703
1704         if (nmi_watchdog == NMI_IO_APIC) {
1705                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1706                 nmi_watchdog = 0;
1707         }
1708
1709         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1710
1711         disable_8259A_irq(0);
1712         irq_desc[0].chip = &lapic_irq_type;
1713         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
1714         enable_8259A_irq(0);
1715
1716         if (timer_irq_works()) {
1717                 apic_printk(APIC_VERBOSE," works.\n");
1718                 return;
1719         }
1720         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1721         apic_printk(APIC_VERBOSE," failed.\n");
1722
1723         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1724
1725         init_8259A(0);
1726         make_8259A_irq(0);
1727         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1728
1729         unlock_ExtINT_logic();
1730
1731         if (timer_irq_works()) {
1732                 apic_printk(APIC_VERBOSE," works.\n");
1733                 return;
1734         }
1735         apic_printk(APIC_VERBOSE," failed :(.\n");
1736         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1737 }
1738
1739 static int __init notimercheck(char *s)
1740 {
1741         no_timer_check = 1;
1742         return 1;
1743 }
1744 __setup("no_timer_check", notimercheck);
1745
1746 /*
1747  *
1748  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1749  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1750  *   Linux doesn't really care, as it's not actually used
1751  *   for any interrupt handling anyway.
1752  */
1753 #define PIC_IRQS        (1<<2)
1754
1755 void __init setup_IO_APIC(void)
1756 {
1757         enable_IO_APIC();
1758
1759         if (acpi_ioapic)
1760                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1761         else
1762                 io_apic_irqs = ~PIC_IRQS;
1763
1764         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1765
1766         sync_Arb_IDs();
1767         setup_IO_APIC_irqs();
1768         init_IO_APIC_traps();
1769         check_timer();
1770         if (!acpi_ioapic)
1771                 print_IO_APIC();
1772 }
1773
1774 struct sysfs_ioapic_data {
1775         struct sys_device dev;
1776         struct IO_APIC_route_entry entry[0];
1777 };
1778 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1779
1780 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1781 {
1782         struct IO_APIC_route_entry *entry;
1783         struct sysfs_ioapic_data *data;
1784         int i;
1785
1786         data = container_of(dev, struct sysfs_ioapic_data, dev);
1787         entry = data->entry;
1788         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1789                 *entry = ioapic_read_entry(dev->id, i);
1790
1791         return 0;
1792 }
1793
1794 static int ioapic_resume(struct sys_device *dev)
1795 {
1796         struct IO_APIC_route_entry *entry;
1797         struct sysfs_ioapic_data *data;
1798         unsigned long flags;
1799         union IO_APIC_reg_00 reg_00;
1800         int i;
1801
1802         data = container_of(dev, struct sysfs_ioapic_data, dev);
1803         entry = data->entry;
1804
1805         spin_lock_irqsave(&ioapic_lock, flags);
1806         reg_00.raw = io_apic_read(dev->id, 0);
1807         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1808                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1809                 io_apic_write(dev->id, 0, reg_00.raw);
1810         }
1811         spin_unlock_irqrestore(&ioapic_lock, flags);
1812         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1813                 ioapic_write_entry(dev->id, i, entry[i]);
1814
1815         return 0;
1816 }
1817
1818 static struct sysdev_class ioapic_sysdev_class = {
1819         set_kset_name("ioapic"),
1820         .suspend = ioapic_suspend,
1821         .resume = ioapic_resume,
1822 };
1823
1824 static int __init ioapic_init_sysfs(void)
1825 {
1826         struct sys_device * dev;
1827         int i, size, error = 0;
1828
1829         error = sysdev_class_register(&ioapic_sysdev_class);
1830         if (error)
1831                 return error;
1832
1833         for (i = 0; i < nr_ioapics; i++ ) {
1834                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1835                         * sizeof(struct IO_APIC_route_entry);
1836                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1837                 if (!mp_ioapic_data[i]) {
1838                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1839                         continue;
1840                 }
1841                 memset(mp_ioapic_data[i], 0, size);
1842                 dev = &mp_ioapic_data[i]->dev;
1843                 dev->id = i;
1844                 dev->cls = &ioapic_sysdev_class;
1845                 error = sysdev_register(dev);
1846                 if (error) {
1847                         kfree(mp_ioapic_data[i]);
1848                         mp_ioapic_data[i] = NULL;
1849                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1850                         continue;
1851                 }
1852         }
1853
1854         return 0;
1855 }
1856
1857 device_initcall(ioapic_init_sysfs);
1858
1859 /*
1860  * Dynamic irq allocate and deallocation
1861  */
1862 int create_irq(void)
1863 {
1864         /* Allocate an unused irq */
1865         int irq;
1866         int new;
1867         unsigned long flags;
1868
1869         irq = -ENOSPC;
1870         spin_lock_irqsave(&vector_lock, flags);
1871         for (new = (NR_IRQS - 1); new >= 0; new--) {
1872                 if (platform_legacy_irq(new))
1873                         continue;
1874                 if (irq_cfg[new].vector != 0)
1875                         continue;
1876                 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1877                         irq = new;
1878                 break;
1879         }
1880         spin_unlock_irqrestore(&vector_lock, flags);
1881
1882         if (irq >= 0) {
1883                 dynamic_irq_init(irq);
1884         }
1885         return irq;
1886 }
1887
1888 void destroy_irq(unsigned int irq)
1889 {
1890         unsigned long flags;
1891
1892         dynamic_irq_cleanup(irq);
1893
1894         spin_lock_irqsave(&vector_lock, flags);
1895         __clear_irq_vector(irq);
1896         spin_unlock_irqrestore(&vector_lock, flags);
1897 }
1898
1899 /*
1900  * MSI mesage composition
1901  */
1902 #ifdef CONFIG_PCI_MSI
1903 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1904 {
1905         struct irq_cfg *cfg = irq_cfg + irq;
1906         int err;
1907         unsigned dest;
1908         cpumask_t tmp;
1909
1910         tmp = TARGET_CPUS;
1911         err = assign_irq_vector(irq, tmp);
1912         if (!err) {
1913                 cpus_and(tmp, cfg->domain, tmp);
1914                 dest = cpu_mask_to_apicid(tmp);
1915
1916                 msg->address_hi = MSI_ADDR_BASE_HI;
1917                 msg->address_lo =
1918                         MSI_ADDR_BASE_LO |
1919                         ((INT_DEST_MODE == 0) ?
1920                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1921                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1922                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1923                                 MSI_ADDR_REDIRECTION_CPU:
1924                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1925                         MSI_ADDR_DEST_ID(dest);
1926
1927                 msg->data =
1928                         MSI_DATA_TRIGGER_EDGE |
1929                         MSI_DATA_LEVEL_ASSERT |
1930                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1931                                 MSI_DATA_DELIVERY_FIXED:
1932                                 MSI_DATA_DELIVERY_LOWPRI) |
1933                         MSI_DATA_VECTOR(cfg->vector);
1934         }
1935         return err;
1936 }
1937
1938 #ifdef CONFIG_SMP
1939 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1940 {
1941         struct irq_cfg *cfg = irq_cfg + irq;
1942         struct msi_msg msg;
1943         unsigned int dest;
1944         cpumask_t tmp;
1945
1946         cpus_and(tmp, mask, cpu_online_map);
1947         if (cpus_empty(tmp))
1948                 return;
1949
1950         if (assign_irq_vector(irq, mask))
1951                 return;
1952
1953         cpus_and(tmp, cfg->domain, mask);
1954         dest = cpu_mask_to_apicid(tmp);
1955
1956         read_msi_msg(irq, &msg);
1957
1958         msg.data &= ~MSI_DATA_VECTOR_MASK;
1959         msg.data |= MSI_DATA_VECTOR(cfg->vector);
1960         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1961         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1962
1963         write_msi_msg(irq, &msg);
1964         irq_desc[irq].affinity = mask;
1965 }
1966 #endif /* CONFIG_SMP */
1967
1968 /*
1969  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1970  * which implement the MSI or MSI-X Capability Structure.
1971  */
1972 static struct irq_chip msi_chip = {
1973         .name           = "PCI-MSI",
1974         .unmask         = unmask_msi_irq,
1975         .mask           = mask_msi_irq,
1976         .ack            = ack_apic_edge,
1977 #ifdef CONFIG_SMP
1978         .set_affinity   = set_msi_irq_affinity,
1979 #endif
1980         .retrigger      = ioapic_retrigger_irq,
1981 };
1982
1983 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1984 {
1985         struct msi_msg msg;
1986         int irq, ret;
1987         irq = create_irq();
1988         if (irq < 0)
1989                 return irq;
1990
1991         set_irq_msi(irq, desc);
1992         ret = msi_compose_msg(dev, irq, &msg);
1993         if (ret < 0) {
1994                 destroy_irq(irq);
1995                 return ret;
1996         }
1997
1998         write_msi_msg(irq, &msg);
1999
2000         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2001
2002         return irq;
2003 }
2004
2005 void arch_teardown_msi_irq(unsigned int irq)
2006 {
2007         destroy_irq(irq);
2008 }
2009
2010 #endif /* CONFIG_PCI_MSI */
2011
2012 /*
2013  * Hypertransport interrupt support
2014  */
2015 #ifdef CONFIG_HT_IRQ
2016
2017 #ifdef CONFIG_SMP
2018
2019 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2020 {
2021         struct ht_irq_msg msg;
2022         fetch_ht_irq_msg(irq, &msg);
2023
2024         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2025         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2026
2027         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2028         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2029
2030         write_ht_irq_msg(irq, &msg);
2031 }
2032
2033 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2034 {
2035         struct irq_cfg *cfg = irq_cfg + irq;
2036         unsigned int dest;
2037         cpumask_t tmp;
2038
2039         cpus_and(tmp, mask, cpu_online_map);
2040         if (cpus_empty(tmp))
2041                 return;
2042
2043         if (assign_irq_vector(irq, mask))
2044                 return;
2045
2046         cpus_and(tmp, cfg->domain, mask);
2047         dest = cpu_mask_to_apicid(tmp);
2048
2049         target_ht_irq(irq, dest, cfg->vector);
2050         irq_desc[irq].affinity = mask;
2051 }
2052 #endif
2053
2054 static struct irq_chip ht_irq_chip = {
2055         .name           = "PCI-HT",
2056         .mask           = mask_ht_irq,
2057         .unmask         = unmask_ht_irq,
2058         .ack            = ack_apic_edge,
2059 #ifdef CONFIG_SMP
2060         .set_affinity   = set_ht_irq_affinity,
2061 #endif
2062         .retrigger      = ioapic_retrigger_irq,
2063 };
2064
2065 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2066 {
2067         struct irq_cfg *cfg = irq_cfg + irq;
2068         int err;
2069         cpumask_t tmp;
2070
2071         tmp = TARGET_CPUS;
2072         err = assign_irq_vector(irq, tmp);
2073         if (!err) {
2074                 struct ht_irq_msg msg;
2075                 unsigned dest;
2076
2077                 cpus_and(tmp, cfg->domain, tmp);
2078                 dest = cpu_mask_to_apicid(tmp);
2079
2080                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2081
2082                 msg.address_lo =
2083                         HT_IRQ_LOW_BASE |
2084                         HT_IRQ_LOW_DEST_ID(dest) |
2085                         HT_IRQ_LOW_VECTOR(cfg->vector) |
2086                         ((INT_DEST_MODE == 0) ?
2087                                 HT_IRQ_LOW_DM_PHYSICAL :
2088                                 HT_IRQ_LOW_DM_LOGICAL) |
2089                         HT_IRQ_LOW_RQEOI_EDGE |
2090                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2091                                 HT_IRQ_LOW_MT_FIXED :
2092                                 HT_IRQ_LOW_MT_ARBITRATED) |
2093                         HT_IRQ_LOW_IRQ_MASKED;
2094
2095                 write_ht_irq_msg(irq, &msg);
2096
2097                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2098                                               handle_edge_irq, "edge");
2099         }
2100         return err;
2101 }
2102 #endif /* CONFIG_HT_IRQ */
2103
2104 /* --------------------------------------------------------------------------
2105                           ACPI-based IOAPIC Configuration
2106    -------------------------------------------------------------------------- */
2107
2108 #ifdef CONFIG_ACPI
2109
2110 #define IO_APIC_MAX_ID          0xFE
2111
2112 int __init io_apic_get_redir_entries (int ioapic)
2113 {
2114         union IO_APIC_reg_01    reg_01;
2115         unsigned long flags;
2116
2117         spin_lock_irqsave(&ioapic_lock, flags);
2118         reg_01.raw = io_apic_read(ioapic, 1);
2119         spin_unlock_irqrestore(&ioapic_lock, flags);
2120
2121         return reg_01.bits.entries;
2122 }
2123
2124
2125 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2126 {
2127         if (!IO_APIC_IRQ(irq)) {
2128                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2129                         ioapic);
2130                 return -EINVAL;
2131         }
2132
2133         /*
2134          * IRQs < 16 are already in the irq_2_pin[] map
2135          */
2136         if (irq >= 16)
2137                 add_pin_to_irq(irq, ioapic, pin);
2138
2139         setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2140
2141         return 0;
2142 }
2143
2144 #endif /* CONFIG_ACPI */
2145
2146
2147 /*
2148  * This function currently is only a helper for the i386 smp boot process where
2149  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2150  * so mask in all cases should simply be TARGET_CPUS
2151  */
2152 #ifdef CONFIG_SMP
2153 void __init setup_ioapic_dest(void)
2154 {
2155         int pin, ioapic, irq, irq_entry;
2156
2157         if (skip_ioapic_setup == 1)
2158                 return;
2159
2160         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2161                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2162                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2163                         if (irq_entry == -1)
2164                                 continue;
2165                         irq = pin_2_irq(irq_entry, ioapic, pin);
2166
2167                         /* setup_IO_APIC_irqs could fail to get vector for some device
2168                          * when you have too many devices, because at that time only boot
2169                          * cpu is online.
2170                          */
2171                         if (!irq_cfg[irq].vector)
2172                                 setup_IO_APIC_irq(ioapic, pin, irq,
2173                                                   irq_trigger(irq_entry),
2174                                                   irq_polarity(irq_entry));
2175                         else
2176                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2177                 }
2178
2179         }
2180 }
2181 #endif