2 * tdo24m - SPI-based drivers for Toppoly TDO24M series LCD panels
4 * Copyright (C) 2008 Marvell International Ltd.
5 * Eric Miao <eric.miao@marvell.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * publishhed by the Free Software Foundation.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/tdo24m.h>
19 #include <linux/lcd.h>
21 #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
23 #define TDO24M_SPI_BUFF_SIZE (4)
28 struct spi_device *spi_dev;
29 struct lcd_device *lcd_dev;
31 struct spi_message msg;
32 struct spi_transfer xfer;
35 int (*adj_mode)(struct tdo24m *lcd, int mode);
42 /* use bit 30, 31 as the indicator of command parameter number */
43 #define CMD0(x) ((0 << 30) | (x))
44 #define CMD1(x, x1) ((1 << 30) | ((x) << 9) | 0x100 | (x1))
45 #define CMD2(x, x1, x2) ((2 << 30) | ((x) << 18) | 0x20000 |\
46 ((x1) << 9) | 0x100 | (x2))
49 static uint32_t lcd_panel_reset[] = {
50 CMD0(0x1), /* reset */
57 static uint32_t lcd_panel_on[] = {
58 CMD0(0x29), /* Display ON */
59 CMD2(0xB8, 0xFF, 0xF9), /* Output Control */
60 CMD0(0x11), /* Sleep out */
61 CMD1(0xB0, 0x16), /* Wake */
65 static uint32_t lcd_panel_off[] = {
66 CMD0(0x28), /* Display OFF */
67 CMD2(0xB8, 0x80, 0x02), /* Output Control */
68 CMD0(0x10), /* Sleep in */
69 CMD1(0xB0, 0x00), /* Deep stand by in */
73 static uint32_t lcd_vga_pass_through_tdo24m[] = {
82 static uint32_t lcd_qvga_pass_through_tdo24m[] = {
91 static uint32_t lcd_vga_transfer_tdo24m[] = {
92 CMD1(0xcf, 0x02), /* Blanking period control (1) */
93 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
94 CMD1(0xd1, 0x01), /* CKV timing control on/off */
95 CMD2(0xd2, 0x14, 0x00), /* CKV 1,2 timing control */
96 CMD2(0xd3, 0x1a, 0x0f), /* OEV timing control */
97 CMD2(0xd4, 0x1f, 0xaf), /* ASW timing control (1) */
98 CMD1(0xd5, 0x14), /* ASW timing control (2) */
99 CMD0(0x21), /* Invert for normally black display */
100 CMD0(0x29), /* Display on */
104 static uint32_t lcd_qvga_transfer[] = {
105 CMD1(0xd6, 0x02), /* Blanking period control (1) */
106 CMD2(0xd7, 0x08, 0x04), /* Blanking period control (2) */
107 CMD1(0xd8, 0x01), /* CKV timing control on/off */
108 CMD2(0xd9, 0x00, 0x08), /* CKV 1,2 timing control */
109 CMD2(0xde, 0x05, 0x0a), /* OEV timing control */
110 CMD2(0xdf, 0x0a, 0x19), /* ASW timing control (1) */
111 CMD1(0xe0, 0x0a), /* ASW timing control (2) */
112 CMD0(0x21), /* Invert for normally black display */
113 CMD0(0x29), /* Display on */
117 static uint32_t lcd_vga_pass_through_tdo35s[] = {
125 static uint32_t lcd_qvga_pass_through_tdo35s[] = {
133 static uint32_t lcd_vga_transfer_tdo35s[] = {
134 CMD1(0xcf, 0x02), /* Blanking period control (1) */
135 CMD2(0xd0, 0x08, 0x04), /* Blanking period control (2) */
136 CMD1(0xd1, 0x01), /* CKV timing control on/off */
137 CMD2(0xd2, 0x00, 0x1e), /* CKV 1,2 timing control */
138 CMD2(0xd3, 0x14, 0x28), /* OEV timing control */
139 CMD2(0xd4, 0x28, 0x64), /* ASW timing control (1) */
140 CMD1(0xd5, 0x28), /* ASW timing control (2) */
141 CMD0(0x21), /* Invert for normally black display */
142 CMD0(0x29), /* Display on */
146 static uint32_t lcd_panel_config[] = {
147 CMD2(0xb8, 0xff, 0xf9), /* Output control */
148 CMD0(0x11), /* sleep out */
149 CMD1(0xba, 0x01), /* Display mode (1) */
150 CMD1(0xbb, 0x00), /* Display mode (2) */
151 CMD1(0x3a, 0x60), /* Display mode 18-bit RGB */
152 CMD1(0xbf, 0x10), /* Drive system change control */
153 CMD1(0xb1, 0x56), /* Booster operation setup */
154 CMD1(0xb2, 0x33), /* Booster mode setup */
155 CMD1(0xb3, 0x11), /* Booster frequency setup */
156 CMD1(0xb4, 0x02), /* Op amp/system clock */
157 CMD1(0xb5, 0x35), /* VCS voltage */
158 CMD1(0xb6, 0x40), /* VCOM voltage */
159 CMD1(0xb7, 0x03), /* External display signal */
160 CMD1(0xbd, 0x00), /* ASW slew rate */
161 CMD1(0xbe, 0x00), /* Dummy data for QuadData operation */
162 CMD1(0xc0, 0x11), /* Sleep out FR count (A) */
163 CMD1(0xc1, 0x11), /* Sleep out FR count (B) */
164 CMD1(0xc2, 0x11), /* Sleep out FR count (C) */
165 CMD2(0xc3, 0x20, 0x40), /* Sleep out FR count (D) */
166 CMD2(0xc4, 0x60, 0xc0), /* Sleep out FR count (E) */
167 CMD2(0xc5, 0x10, 0x20), /* Sleep out FR count (F) */
168 CMD1(0xc6, 0xc0), /* Sleep out FR count (G) */
169 CMD2(0xc7, 0x33, 0x43), /* Gamma 1 fine tuning (1) */
170 CMD1(0xc8, 0x44), /* Gamma 1 fine tuning (2) */
171 CMD1(0xc9, 0x33), /* Gamma 1 inclination adjustment */
172 CMD1(0xca, 0x00), /* Gamma 1 blue offset adjustment */
173 CMD2(0xec, 0x01, 0xf0), /* Horizontal clock cycles */
177 static int tdo24m_writes(struct tdo24m *lcd, uint32_t *array)
179 struct spi_transfer *x = &lcd->xfer;
180 uint32_t data, *p = array;
181 int nparams, err = 0;
183 for (; *p != CMD_NULL; p++) {
184 if (!lcd->color_invert && *p == CMD0(0x21))
187 nparams = (*p >> 30) & 0x3;
189 data = *p << (7 - nparams);
192 lcd->buf[0] = (data >> 8) & 0xff;
193 lcd->buf[1] = data & 0xff;
196 lcd->buf[0] = (data >> 16) & 0xff;
197 lcd->buf[1] = (data >> 8) & 0xff;
198 lcd->buf[2] = data & 0xff;
201 lcd->buf[0] = (data >> 24) & 0xff;
202 lcd->buf[1] = (data >> 16) & 0xff;
203 lcd->buf[2] = (data >> 8) & 0xff;
204 lcd->buf[3] = data & 0xff;
209 x->len = nparams + 2;
210 err = spi_sync(lcd->spi_dev, &lcd->msg);
218 static int tdo24m_adj_mode(struct tdo24m *lcd, int mode)
222 tdo24m_writes(lcd, lcd_vga_pass_through_tdo24m);
223 tdo24m_writes(lcd, lcd_panel_config);
224 tdo24m_writes(lcd, lcd_vga_transfer_tdo24m);
227 tdo24m_writes(lcd, lcd_qvga_pass_through_tdo24m);
228 tdo24m_writes(lcd, lcd_panel_config);
229 tdo24m_writes(lcd, lcd_qvga_transfer);
239 static int tdo35s_adj_mode(struct tdo24m *lcd, int mode)
243 tdo24m_writes(lcd, lcd_vga_pass_through_tdo35s);
244 tdo24m_writes(lcd, lcd_panel_config);
245 tdo24m_writes(lcd, lcd_vga_transfer_tdo35s);
248 tdo24m_writes(lcd, lcd_qvga_pass_through_tdo35s);
249 tdo24m_writes(lcd, lcd_panel_config);
250 tdo24m_writes(lcd, lcd_qvga_transfer);
260 static int tdo24m_power_on(struct tdo24m *lcd)
264 err = tdo24m_writes(lcd, lcd_panel_on);
268 err = tdo24m_writes(lcd, lcd_panel_reset);
272 err = lcd->adj_mode(lcd, lcd->mode);
277 static int tdo24m_power_off(struct tdo24m *lcd)
279 return tdo24m_writes(lcd, lcd_panel_off);
282 static int tdo24m_power(struct tdo24m *lcd, int power)
286 if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
287 ret = tdo24m_power_on(lcd);
288 else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
289 ret = tdo24m_power_off(lcd);
298 static int tdo24m_set_power(struct lcd_device *ld, int power)
300 struct tdo24m *lcd = lcd_get_data(ld);
301 return tdo24m_power(lcd, power);
304 static int tdo24m_get_power(struct lcd_device *ld)
306 struct tdo24m *lcd = lcd_get_data(ld);
310 static int tdo24m_set_mode(struct lcd_device *ld, struct fb_videomode *m)
312 struct tdo24m *lcd = lcd_get_data(ld);
313 int mode = MODE_QVGA;
315 if (m->xres == 640 || m->xres == 480)
318 if (lcd->mode == mode)
321 return lcd->adj_mode(lcd, mode);
324 static struct lcd_ops tdo24m_ops = {
325 .get_power = tdo24m_get_power,
326 .set_power = tdo24m_set_power,
327 .set_mode = tdo24m_set_mode,
330 static int __devinit tdo24m_probe(struct spi_device *spi)
333 struct spi_message *m;
334 struct spi_transfer *x;
335 struct tdo24m_platform_data *pdata;
336 enum tdo24m_model model;
339 pdata = spi->dev.platform_data;
341 model = pdata->model;
345 spi->bits_per_word = 8;
346 spi->mode = SPI_MODE_3;
347 err = spi_setup(spi);
351 lcd = kzalloc(sizeof(struct tdo24m), GFP_KERNEL);
356 lcd->power = FB_BLANK_POWERDOWN;
357 lcd->mode = MODE_VGA; /* default to VGA */
359 lcd->buf = kmalloc(TDO24M_SPI_BUFF_SIZE, sizeof(GFP_KERNEL));
360 if (lcd->buf == NULL) {
370 x->tx_buf = &lcd->buf[0];
371 spi_message_add_tail(x, m);
375 lcd->color_invert = 1;
376 lcd->adj_mode = tdo24m_adj_mode;
379 lcd->adj_mode = tdo35s_adj_mode;
380 lcd->color_invert = 0;
383 dev_err(&spi->dev, "Unsupported model");
387 lcd->lcd_dev = lcd_device_register("tdo24m", &spi->dev,
389 if (IS_ERR(lcd->lcd_dev)) {
390 err = PTR_ERR(lcd->lcd_dev);
394 dev_set_drvdata(&spi->dev, lcd);
395 err = tdo24m_power(lcd, FB_BLANK_UNBLANK);
402 lcd_device_unregister(lcd->lcd_dev);
409 static int __devexit tdo24m_remove(struct spi_device *spi)
411 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
413 tdo24m_power(lcd, FB_BLANK_POWERDOWN);
414 lcd_device_unregister(lcd->lcd_dev);
422 static int tdo24m_suspend(struct spi_device *spi, pm_message_t state)
424 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
426 return tdo24m_power(lcd, FB_BLANK_POWERDOWN);
429 static int tdo24m_resume(struct spi_device *spi)
431 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
433 return tdo24m_power(lcd, FB_BLANK_UNBLANK);
436 #define tdo24m_suspend NULL
437 #define tdo24m_resume NULL
440 /* Power down all displays on reboot, poweroff or halt */
441 static void tdo24m_shutdown(struct spi_device *spi)
443 struct tdo24m *lcd = dev_get_drvdata(&spi->dev);
445 tdo24m_power(lcd, FB_BLANK_POWERDOWN);
448 static struct spi_driver tdo24m_driver = {
451 .owner = THIS_MODULE,
453 .probe = tdo24m_probe,
454 .remove = __devexit_p(tdo24m_remove),
455 .shutdown = tdo24m_shutdown,
456 .suspend = tdo24m_suspend,
457 .resume = tdo24m_resume,
460 static int __init tdo24m_init(void)
462 return spi_register_driver(&tdo24m_driver);
464 module_init(tdo24m_init);
466 static void __exit tdo24m_exit(void)
468 spi_unregister_driver(&tdo24m_driver);
470 module_exit(tdo24m_exit);
472 MODULE_AUTHOR("Eric Miao <eric.miao@marvell.com>");
473 MODULE_DESCRIPTION("Driver for Toppoly TDO24M LCD Panel");
474 MODULE_LICENSE("GPL");