Merge branch 'hwmon-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc8548cds.dts
1 /*
2  * MPC8555 CDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  */
11
12
13 / {
14         model = "MPC8548CDS";
15         compatible = "MPC8548CDS", "MPC85xxCDS";
16         #address-cells = <1>;
17         #size-cells = <1>;
18
19         cpus {
20                 #cpus = <1>;
21                 #address-cells = <1>;
22                 #size-cells = <0>;
23
24                 PowerPC,8548@0 {
25                         device_type = "cpu";
26                         reg = <0>;
27                         d-cache-line-size = <20>;       // 32 bytes
28                         i-cache-line-size = <20>;       // 32 bytes
29                         d-cache-size = <8000>;          // L1, 32K
30                         i-cache-size = <8000>;          // L1, 32K
31                         timebase-frequency = <0>;       //  33 MHz, from uboot
32                         bus-frequency = <0>;    // 166 MHz
33                         clock-frequency = <0>;  // 825 MHz, from uboot
34                         32-bit;
35                 };
36         };
37
38         memory {
39                 device_type = "memory";
40                 reg = <00000000 08000000>;      // 128M at 0x0
41         };
42
43         soc8548@e0000000 {
44                 #address-cells = <1>;
45                 #size-cells = <1>;
46                 #interrupt-cells = <2>;
47                 device_type = "soc";
48                 ranges = <0 e0000000 00100000>;
49                 reg = <e0000000 00100000>;      // CCSRBAR 1M
50                 bus-frequency = <0>;
51
52                 i2c@3000 {
53                         device_type = "i2c";
54                         compatible = "fsl-i2c";
55                         reg = <3000 100>;
56                         interrupts = <1b 2>;
57                         interrupt-parent = <&mpic>;
58                         dfsrr;
59                 };
60
61                 mdio@24520 {
62                         #address-cells = <1>;
63                         #size-cells = <0>;
64                         device_type = "mdio";
65                         compatible = "gianfar";
66                         reg = <24520 20>;
67                         phy0: ethernet-phy@0 {
68                                 interrupt-parent = <&mpic>;
69                                 interrupts = <35 0>;
70                                 reg = <0>;
71                                 device_type = "ethernet-phy";
72                         };
73                         phy1: ethernet-phy@1 {
74                                 interrupt-parent = <&mpic>;
75                                 interrupts = <35 0>;
76                                 reg = <1>;
77                                 device_type = "ethernet-phy";
78                         };
79                         phy2: ethernet-phy@2 {
80                                 interrupt-parent = <&mpic>;
81                                 interrupts = <35 0>;
82                                 reg = <2>;
83                                 device_type = "ethernet-phy";
84                         };
85                         phy3: ethernet-phy@3 {
86                                 interrupt-parent = <&mpic>;
87                                 interrupts = <35 0>;
88                                 reg = <3>;
89                                 device_type = "ethernet-phy";
90                         };
91                 };
92
93                 ethernet@24000 {
94                         #address-cells = <1>;
95                         #size-cells = <0>;
96                         device_type = "network";
97                         model = "eTSEC";
98                         compatible = "gianfar";
99                         reg = <24000 1000>;
100                         local-mac-address = [ 00 E0 0C 00 73 00 ];
101                         interrupts = <d 2 e 2 12 2>;
102                         interrupt-parent = <&mpic>;
103                         phy-handle = <&phy0>;
104                 };
105
106                 ethernet@25000 {
107                         #address-cells = <1>;
108                         #size-cells = <0>;
109                         device_type = "network";
110                         model = "eTSEC";
111                         compatible = "gianfar";
112                         reg = <25000 1000>;
113                         local-mac-address = [ 00 E0 0C 00 73 01 ];
114                         interrupts = <13 2 14 2 18 2>;
115                         interrupt-parent = <&mpic>;
116                         phy-handle = <&phy1>;
117                 };
118
119 /* eTSEC 3/4 are currently broken
120                 ethernet@26000 {
121                         #address-cells = <1>;
122                         #size-cells = <0>;
123                         device_type = "network";
124                         model = "eTSEC";
125                         compatible = "gianfar";
126                         reg = <26000 1000>;
127                         local-mac-address = [ 00 E0 0C 00 73 02 ];
128                         interrupts = <f 2 10 2 11 2>;
129                         interrupt-parent = <&mpic>;
130                         phy-handle = <&phy2>;
131                 };
132
133                 ethernet@27000 {
134                         #address-cells = <1>;
135                         #size-cells = <0>;
136                         device_type = "network";
137                         model = "eTSEC";
138                         compatible = "gianfar";
139                         reg = <27000 1000>;
140                         local-mac-address = [ 00 E0 0C 00 73 03 ];
141                         interrupts = <15 2 16 2 17 2>;
142                         interrupt-parent = <&mpic>;
143                         phy-handle = <&phy3>;
144                 };
145  */
146
147                 serial@4500 {
148                         device_type = "serial";
149                         compatible = "ns16550";
150                         reg = <4500 100>;       // reg base, size
151                         clock-frequency = <0>;  // should we fill in in uboot?
152                         interrupts = <1a 2>;
153                         interrupt-parent = <&mpic>;
154                 };
155
156                 serial@4600 {
157                         device_type = "serial";
158                         compatible = "ns16550";
159                         reg = <4600 100>;       // reg base, size
160                         clock-frequency = <0>;  // should we fill in in uboot?
161                         interrupts = <1a 2>;
162                         interrupt-parent = <&mpic>;
163                 };
164
165                 pci1: pci@8000 {
166                         interrupt-map-mask = <1f800 0 0 7>;
167                         interrupt-map = <
168
169                                 /* IDSEL 0x10 */
170                                 08000 0 0 1 &mpic 30 1
171                                 08000 0 0 2 &mpic 31 1
172                                 08000 0 0 3 &mpic 32 1
173                                 08000 0 0 4 &mpic 33 1
174
175                                 /* IDSEL 0x11 */
176                                 08800 0 0 1 &mpic 30 1
177                                 08800 0 0 2 &mpic 31 1
178                                 08800 0 0 3 &mpic 32 1
179                                 08800 0 0 4 &mpic 33 1
180
181                                 /* IDSEL 0x12 (Slot 1) */
182                                 09000 0 0 1 &mpic 30 1
183                                 09000 0 0 2 &mpic 31 1
184                                 09000 0 0 3 &mpic 32 1
185                                 09000 0 0 4 &mpic 33 1
186
187                                 /* IDSEL 0x13 (Slot 2) */
188                                 09800 0 0 1 &mpic 31 1
189                                 09800 0 0 2 &mpic 32 1
190                                 09800 0 0 3 &mpic 33 1
191                                 09800 0 0 4 &mpic 30 1
192
193                                 /* IDSEL 0x14 (Slot 3) */
194                                 0a000 0 0 1 &mpic 32 1
195                                 0a000 0 0 2 &mpic 33 1
196                                 0a000 0 0 3 &mpic 30 1
197                                 0a000 0 0 4 &mpic 31 1
198
199                                 /* IDSEL 0x15 (Slot 4) */
200                                 0a800 0 0 1 &mpic 33 1
201                                 0a800 0 0 2 &mpic 30 1
202                                 0a800 0 0 3 &mpic 31 1
203                                 0a800 0 0 4 &mpic 32 1
204
205                                 /* Bus 1 (Tundra Bridge) */
206                                 /* IDSEL 0x12 (ISA bridge) */
207                                 19000 0 0 1 &mpic 30 1
208                                 19000 0 0 2 &mpic 31 1
209                                 19000 0 0 3 &mpic 32 1
210                                 19000 0 0 4 &mpic 33 1>;
211                         interrupt-parent = <&mpic>;
212                         interrupts = <08 2>;
213                         bus-range = <0 0>;
214                         ranges = <02000000 0 80000000 80000000 0 20000000
215                                   01000000 0 00000000 e2000000 0 00100000>;
216                         clock-frequency = <3f940aa>;
217                         #interrupt-cells = <1>;
218                         #size-cells = <2>;
219                         #address-cells = <3>;
220                         reg = <8000 1000>;
221                         compatible = "85xx";
222                         device_type = "pci";
223
224                         i8259@19000 {
225                                 clock-frequency = <0>;
226                                 interrupt-controller;
227                                 device_type = "interrupt-controller";
228                                 reg = <19000 0 0 0 1>;
229                                 #address-cells = <0>;
230                                 #interrupt-cells = <2>;
231                                 built-in;
232                                 compatible = "chrp,iic";
233                                 big-endian;
234                                 interrupts = <1>;
235                                 interrupt-parent = <&pci1>;
236                         };
237                 };
238
239                 pci@9000 {
240                         interrupt-map-mask = <f800 0 0 7>;
241                         interrupt-map = <
242
243                                 /* IDSEL 0x15 */
244                                 a800 0 0 1 &mpic 3b 1
245                                 a800 0 0 2 &mpic 3b 1
246                                 a800 0 0 3 &mpic 3b 1
247                                 a800 0 0 4 &mpic 3b 1>;
248                         interrupt-parent = <&mpic>;
249                         interrupts = <09 2>;
250                         bus-range = <0 0>;
251                         ranges = <02000000 0 a0000000 a0000000 0 20000000
252                                   01000000 0 00000000 e3000000 0 00100000>;
253                         clock-frequency = <3f940aa>;
254                         #interrupt-cells = <1>;
255                         #size-cells = <2>;
256                         #address-cells = <3>;
257                         reg = <9000 1000>;
258                         compatible = "85xx";
259                         device_type = "pci";
260                 };
261
262                 mpic: pic@40000 {
263                         clock-frequency = <0>;
264                         interrupt-controller;
265                         #address-cells = <0>;
266                         #interrupt-cells = <2>;
267                         reg = <40000 40000>;
268                         built-in;
269                         compatible = "chrp,open-pic";
270                         device_type = "open-pic";
271                         big-endian;
272                 };
273         };
274 };