2 * linux/drivers/ide/arm/icside.c
4 * Copyright (c) 1996-2004 Russell King.
6 * Please note that this platform does not support 32-bit IDE IO.
9 #include <linux/string.h>
10 #include <linux/module.h>
11 #include <linux/ioport.h>
12 #include <linux/slab.h>
13 #include <linux/blkdev.h>
14 #include <linux/errno.h>
15 #include <linux/hdreg.h>
16 #include <linux/ide.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/scatterlist.h>
23 #include <asm/ecard.h>
26 #define ICS_IDENT_OFFSET 0x2280
28 #define ICS_ARCIN_V5_INTRSTAT 0x0000
29 #define ICS_ARCIN_V5_INTROFFSET 0x0004
30 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
31 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
32 #define ICS_ARCIN_V5_IDESTEPPING 6
34 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
35 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
36 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
37 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
38 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
39 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
40 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
41 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
42 #define ICS_ARCIN_V6_IDESTEPPING 6
45 unsigned int dataoffset;
46 unsigned int ctrloffset;
47 unsigned int stepping;
50 static struct cardinfo icside_cardinfo_v5 = {
51 .dataoffset = ICS_ARCIN_V5_IDEOFFSET,
52 .ctrloffset = ICS_ARCIN_V5_IDEALTOFFSET,
53 .stepping = ICS_ARCIN_V5_IDESTEPPING,
56 static struct cardinfo icside_cardinfo_v6_1 = {
57 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_1,
58 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_1,
59 .stepping = ICS_ARCIN_V6_IDESTEPPING,
62 static struct cardinfo icside_cardinfo_v6_2 = {
63 .dataoffset = ICS_ARCIN_V6_IDEOFFSET_2,
64 .ctrloffset = ICS_ARCIN_V6_IDEALTOFFSET_2,
65 .stepping = ICS_ARCIN_V6_IDESTEPPING,
71 void __iomem *irq_port;
72 void __iomem *ioc_base;
74 /* parent device... until the IDE core gets one of its own */
79 #define ICS_TYPE_A3IN 0
80 #define ICS_TYPE_A3USER 1
82 #define ICS_TYPE_V5 15
83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
85 /* ---------------- Version 5 PCB Support Functions --------------------- */
86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
87 * Purpose : enable interrupts from card
89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
91 struct icside_state *state = ec->irq_data;
93 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
97 * Purpose : disable interrupts from card
99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
101 struct icside_state *state = ec->irq_data;
103 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
107 .irqenable = icside_irqenable_arcin_v5,
108 .irqdisable = icside_irqdisable_arcin_v5,
112 /* ---------------- Version 6 PCB Support Functions --------------------- */
113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
114 * Purpose : enable interrupts from card
116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
118 struct icside_state *state = ec->irq_data;
119 void __iomem *base = state->irq_port;
123 switch (state->channel) {
125 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
126 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
129 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
130 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
136 * Purpose : disable interrupts from card
138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
140 struct icside_state *state = ec->irq_data;
144 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
145 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
149 * Purpose : detect an active interrupt from card
151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
153 struct icside_state *state = ec->irq_data;
155 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
156 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
160 .irqenable = icside_irqenable_arcin_v6,
161 .irqdisable = icside_irqdisable_arcin_v6,
162 .irqpending = icside_irqpending_arcin_v6,
166 * Handle routing of interrupts. This is called before
167 * we write the command to the drive.
169 static void icside_maskproc(ide_drive_t *drive, int mask)
171 ide_hwif_t *hwif = HWIF(drive);
172 struct icside_state *state = hwif->hwif_data;
175 local_irq_save(flags);
177 state->channel = hwif->channel;
179 if (state->enabled && !mask) {
180 switch (hwif->channel) {
182 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
183 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
186 writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
187 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
191 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
192 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
195 local_irq_restore(flags);
198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
200 #ifndef CONFIG_IDEDMA_ICS_AUTO
201 #warning CONFIG_IDEDMA_ICS_AUTO=n support is obsolete, and will be removed soon.
207 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
208 * There is only one DMA controller per card, which means that only
209 * one drive can be accessed at one time. NOTE! We do not enforce that
210 * here, but we rely on the main IDE driver spotting that both
211 * interfaces use the same IRQ, which should guarantee this.
214 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
216 ide_hwif_t *hwif = drive->hwif;
217 struct icside_state *state = hwif->hwif_data;
218 struct scatterlist *sg = hwif->sg_table;
220 ide_map_sg(drive, rq);
222 if (rq_data_dir(rq) == READ)
223 hwif->sg_dma_direction = DMA_FROM_DEVICE;
225 hwif->sg_dma_direction = DMA_TO_DEVICE;
227 hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
228 hwif->sg_dma_direction);
232 * Configure the IOMD to give the appropriate timings for the transfer
233 * mode being requested. We take the advice of the ATA standards, and
234 * calculate the cycle time based on the transfer mode, and the EIDE
235 * MW DMA specs that the drive provides in the IDENTIFY command.
237 * We have the following IOMD DMA modes to choose from:
239 * Type Active Recovery Cycle
240 * A 250 (250) 312 (550) 562 (800)
242 * C 125 (125) 125 (375) 250 (500)
245 * (figures in brackets are actual measured timings)
247 * However, we also need to take care of the read/write active and
251 * Mode Active -- Recovery -- Cycle IOMD type
252 * MW0 215 50 215 480 A
256 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
258 int on = 0, cycle_time = 0, use_dma_info = 0;
261 * Limit the transfer speed to MW_DMA_2.
263 if (xfer_mode > XFER_MW_DMA_2)
264 xfer_mode = XFER_MW_DMA_2;
289 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
290 * take care to note the values in the ID...
292 if (use_dma_info && drive->id->eide_dma_time > cycle_time)
293 cycle_time = drive->id->eide_dma_time;
295 drive->drive_data = cycle_time;
297 if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
300 drive->drive_data = 480;
302 printk("%s: %s selected (peak %dMB/s)\n", drive->name,
303 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
305 drive->current_speed = xfer_mode;
310 static void icside_dma_host_off(ide_drive_t *drive)
314 static void icside_dma_off_quietly(ide_drive_t *drive)
316 drive->using_dma = 0;
319 static void icside_dma_host_on(ide_drive_t *drive)
323 static int icside_dma_on(ide_drive_t *drive)
325 drive->using_dma = 1;
330 static int icside_dma_check(ide_drive_t *drive)
332 struct hd_driveid *id = drive->id;
333 ide_hwif_t *hwif = HWIF(drive);
334 int xfer_mode = XFER_PIO_2;
337 if (!(id->capability & 1) || !hwif->autodma)
341 * Consult the list of known "bad" drives
343 if (__ide_dma_bad_drive(drive))
347 * Enable DMA on any drive that has multiword DMA
349 if (id->field_valid & 2) {
350 xfer_mode = ide_dma_speed(drive, 0);
355 * Consult the list of known "good" drives
357 if (__ide_dma_good_drive(drive)) {
358 if (id->eide_dma_time > 150)
360 xfer_mode = XFER_MW_DMA_1;
364 on = icside_set_speed(drive, xfer_mode);
369 static int icside_dma_end(ide_drive_t *drive)
371 ide_hwif_t *hwif = HWIF(drive);
372 struct icside_state *state = hwif->hwif_data;
374 drive->waiting_for_dma = 0;
376 disable_dma(hwif->hw.dma);
378 /* Teardown mappings after DMA has completed. */
379 dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
380 hwif->sg_dma_direction);
382 return get_dma_residue(hwif->hw.dma) != 0;
385 static void icside_dma_start(ide_drive_t *drive)
387 ide_hwif_t *hwif = HWIF(drive);
389 /* We can not enable DMA on both channels simultaneously. */
390 BUG_ON(dma_channel_active(hwif->hw.dma));
391 enable_dma(hwif->hw.dma);
394 static int icside_dma_setup(ide_drive_t *drive)
396 ide_hwif_t *hwif = HWIF(drive);
397 struct request *rq = hwif->hwgroup->rq;
398 unsigned int dma_mode;
401 dma_mode = DMA_MODE_WRITE;
403 dma_mode = DMA_MODE_READ;
406 * We can not enable DMA on both channels.
408 BUG_ON(dma_channel_active(hwif->hw.dma));
410 icside_build_sglist(drive, rq);
413 * Ensure that we have the right interrupt routed.
415 icside_maskproc(drive, 0);
418 * Route the DMA signals to the correct interface.
420 writeb(hwif->select_data, hwif->config_data);
423 * Select the correct timing for this drive.
425 set_dma_speed(hwif->hw.dma, drive->drive_data);
428 * Tell the DMA engine about the SG table and
431 set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
432 set_dma_mode(hwif->hw.dma, dma_mode);
434 drive->waiting_for_dma = 1;
439 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
441 /* issue cmd to drive */
442 ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
445 static int icside_dma_test_irq(ide_drive_t *drive)
447 ide_hwif_t *hwif = HWIF(drive);
448 struct icside_state *state = hwif->hwif_data;
450 return readb(state->irq_port +
452 ICS_ARCIN_V6_INTRSTAT_2 :
453 ICS_ARCIN_V6_INTRSTAT_1)) & 1;
456 static int icside_dma_timeout(ide_drive_t *drive)
458 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
460 if (icside_dma_test_irq(drive))
463 ide_dump_status(drive, "DMA timeout",
464 HWIF(drive)->INB(IDE_STATUS_REG));
466 return icside_dma_end(drive);
469 static int icside_dma_lostirq(ide_drive_t *drive)
471 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
475 static void icside_dma_init(ide_hwif_t *hwif)
479 #ifdef CONFIG_IDEDMA_ICS_AUTO
483 printk(" %s: SG-DMA", hwif->name);
486 hwif->mwdma_mask = 7; /* MW0..2 */
487 hwif->swdma_mask = 7; /* SW0..2 */
489 hwif->dmatable_cpu = NULL;
490 hwif->dmatable_dma = 0;
491 hwif->speedproc = icside_set_speed;
492 hwif->autodma = autodma;
494 hwif->ide_dma_check = icside_dma_check;
495 hwif->dma_host_off = icside_dma_host_off;
496 hwif->dma_off_quietly = icside_dma_off_quietly;
497 hwif->dma_host_on = icside_dma_host_on;
498 hwif->ide_dma_on = icside_dma_on;
499 hwif->dma_setup = icside_dma_setup;
500 hwif->dma_exec_cmd = icside_dma_exec_cmd;
501 hwif->dma_start = icside_dma_start;
502 hwif->ide_dma_end = icside_dma_end;
503 hwif->ide_dma_test_irq = icside_dma_test_irq;
504 hwif->ide_dma_timeout = icside_dma_timeout;
505 hwif->ide_dma_lostirq = icside_dma_lostirq;
507 hwif->drives[0].autodma = hwif->autodma;
508 hwif->drives[1].autodma = hwif->autodma;
510 printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
513 #define icside_dma_init(hwif) (0)
516 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
521 for (index = 0; index < MAX_HWIFS; ++index) {
522 hwif = &ide_hwifs[index];
523 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
527 for (index = 0; index < MAX_HWIFS; ++index) {
528 hwif = &ide_hwifs[index];
529 if (!hwif->io_ports[IDE_DATA_OFFSET])
539 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
541 unsigned long port = (unsigned long)base + info->dataoffset;
544 hwif = icside_find_hwif(port);
548 memset(&hwif->hw, 0, sizeof(hw_regs_t));
551 * Ensure we're using MMIO
553 default_hwif_mmiops(hwif);
556 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
557 hwif->hw.io_ports[i] = port;
558 hwif->io_ports[i] = port;
559 port += 1 << info->stepping;
561 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
562 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
563 hwif->hw.irq = ec->irq;
566 hwif->chipset = ide_acorn;
567 hwif->gendev.parent = &ec->dev;
574 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
579 base = ioremap(ecard_resource_start(ec, ECARD_RES_MEMC),
580 ecard_resource_len(ec, ECARD_RES_MEMC));
584 state->irq_port = base;
586 ec->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
588 ec->irq_data = state;
589 ec->ops = &icside_ops_arcin_v5;
592 * Be on the safe side - disable interrupts
594 icside_irqdisable_arcin_v5(ec, 0);
596 hwif = icside_setup(base, &icside_cardinfo_v5, ec);
602 state->hwif[0] = hwif;
604 probe_hwif_init(hwif);
605 create_proc_ide_interfaces();
611 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
613 ide_hwif_t *hwif, *mate;
614 void __iomem *ioc_base, *easi_base;
615 unsigned int sel = 0;
618 ioc_base = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
619 ecard_resource_len(ec, ECARD_RES_IOCFAST));
625 easi_base = ioc_base;
627 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
628 easi_base = ioremap(ecard_resource_start(ec, ECARD_RES_EASI),
629 ecard_resource_len(ec, ECARD_RES_EASI));
636 * Enable access to the EASI region.
641 writeb(sel, ioc_base);
643 ec->irq_data = state;
644 ec->ops = &icside_ops_arcin_v6;
646 state->irq_port = easi_base;
647 state->ioc_base = ioc_base;
650 * Be on the safe side - disable interrupts
652 icside_irqdisable_arcin_v6(ec, 0);
655 * Find and register the interfaces.
657 hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
658 mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
660 if (!hwif || !mate) {
665 state->hwif[0] = hwif;
666 state->hwif[1] = mate;
668 hwif->maskproc = icside_maskproc;
670 hwif->hwif_data = state;
672 hwif->serialized = 1;
673 hwif->config_data = (unsigned long)ioc_base;
674 hwif->select_data = sel;
675 hwif->hw.dma = ec->dma;
677 mate->maskproc = icside_maskproc;
679 mate->hwif_data = state;
681 mate->serialized = 1;
682 mate->config_data = (unsigned long)ioc_base;
683 mate->select_data = sel | 1;
684 mate->hw.dma = ec->dma;
686 if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
687 icside_dma_init(hwif);
688 icside_dma_init(mate);
691 probe_hwif_init(hwif);
692 probe_hwif_init(mate);
693 create_proc_ide_interfaces();
698 if (easi_base != ioc_base)
707 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
709 struct icside_state *state;
713 ret = ecard_request_resources(ec);
717 state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
723 memset(state, 0, sizeof(state));
724 state->type = ICS_TYPE_NOTYPE;
725 state->dev = &ec->dev;
727 idmem = ioremap(ecard_resource_start(ec, ECARD_RES_IOCFAST),
728 ecard_resource_len(ec, ECARD_RES_IOCFAST));
732 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
733 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
734 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
735 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
741 switch (state->type) {
743 dev_warn(&ec->dev, "A3IN unsupported\n");
747 case ICS_TYPE_A3USER:
748 dev_warn(&ec->dev, "A3USER unsupported\n");
753 ret = icside_register_v5(state, ec);
757 ret = icside_register_v6(state, ec);
761 dev_warn(&ec->dev, "unknown interface type\n");
767 ecard_set_drvdata(ec, state);
773 ecard_release_resources(ec);
778 static void __devexit icside_remove(struct expansion_card *ec)
780 struct icside_state *state = ecard_get_drvdata(ec);
782 switch (state->type) {
784 /* FIXME: tell IDE to stop using the interface */
786 /* Disable interrupts */
787 icside_irqdisable_arcin_v5(ec, 0);
791 /* FIXME: tell IDE to stop using the interface */
792 if (ec->dma != NO_DMA)
795 /* Disable interrupts */
796 icside_irqdisable_arcin_v6(ec, 0);
798 /* Reset the ROM pointer/EASI selection */
799 writeb(0, state->ioc_base);
803 ecard_set_drvdata(ec, NULL);
808 iounmap(state->ioc_base);
809 if (state->ioc_base != state->irq_port)
810 iounmap(state->irq_port);
813 ecard_release_resources(ec);
816 static void icside_shutdown(struct expansion_card *ec)
818 struct icside_state *state = ecard_get_drvdata(ec);
822 * Disable interrupts from this card. We need to do
823 * this before disabling EASI since we may be accessing
824 * this register via that region.
826 local_irq_save(flags);
827 ec->ops->irqdisable(ec, 0);
828 local_irq_restore(flags);
831 * Reset the ROM pointer so that we can read the ROM
832 * after a soft reboot. This also disables access to
833 * the IDE taskfile via the EASI region.
836 writeb(0, state->ioc_base);
839 static const struct ecard_id icside_ids[] = {
840 { MANU_ICS, PROD_ICS_IDE },
841 { MANU_ICS2, PROD_ICS2_IDE },
845 static struct ecard_driver icside_driver = {
846 .probe = icside_probe,
847 .remove = __devexit_p(icside_remove),
848 .shutdown = icside_shutdown,
849 .id_table = icside_ids,
855 static int __init icside_init(void)
857 return ecard_register_driver(&icside_driver);
860 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
861 MODULE_LICENSE("GPL");
862 MODULE_DESCRIPTION("ICS IDE driver");
864 module_init(icside_init);