git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/module.h>
  38 #include <linux/errno.h>
  39 #include <linux/signal.h>
  40 #include <linux/sched.h>
  41 #include <linux/timer.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/tty.h>
  45 #include <linux/tty_flip.h>
  46 #include <linux/serial.h>
  47 #include <linux/major.h>
  48 #include <linux/string.h>
  49 #include <linux/fcntl.h>
  50 #include <linux/ptrace.h>
  51 #include <linux/ioport.h>
  52 #include <linux/mm.h>
  53 #include <linux/slab.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/vmalloc.h>
  56 #include <linux/init.h>
  57 #include <linux/delay.h>
  58 #include <linux/ioctl.h>
  59
  60 #include <asm/system.h>
  61 #include <asm/io.h>
  62 #include <asm/irq.h>
  63 #include <asm/dma.h>
  64 #include <linux/bitops.h>
  65 #include <asm/types.h>
  66 #include <linux/termios.h>
  67 #include <linux/workqueue.h>
  68 #include <linux/hdlc.h>
  69 #include <linux/synclink.h>
  70
  71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
  72 #define SYNCLINK_GENERIC_HDLC 1
  73 #else
  74 #define SYNCLINK_GENERIC_HDLC 0
  75 #endif
  76
  77 #define GET_USER(error,value,addr) error = get_user(value,addr)
  78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  81
  82 #include <asm/uaccess.h>
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 struct  _input_signal_events {
 138         int     ri_up;
 139         int     ri_down;
 140         int     dsr_up;
 141         int     dsr_down;
 142         int     dcd_up;
 143         int     dcd_down;
 144         int     cts_up;
 145         int     cts_down;
 146 };
 147
 148 /*
 149  * Device instance data structure
 150  */
 151 typedef struct _synclinkmp_info {
 152         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 153         int                     magic;
 154         int                     flags;
 155         int                     count;          /* count of opens */
 156         int                     line;
 157         unsigned short          close_delay;
 158         unsigned short          closing_wait;   /* time to wait before closing */
 159
 160         struct mgsl_icount      icount;
 161
 162         struct tty_struct       *tty;
 163         int                     timeout;
 164         int                     x_char;         /* xon/xoff character */
 165         int                     blocked_open;   /* # of blocked opens */
 166         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 167         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 168         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 169         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           *tx_buf;
 171         int                     tx_put;
 172         int                     tx_get;
 173         int                     tx_count;
 174
 175         wait_queue_head_t       open_wait;
 176         wait_queue_head_t       close_wait;
 177
 178         wait_queue_head_t       status_event_wait_q;
 179         wait_queue_head_t       event_wait_q;
 180         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 181         struct _synclinkmp_info *next_device;   /* device list link */
 182         struct timer_list       status_timer;   /* input signal status check timer */
 183
 184         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 185         struct work_struct task;                        /* task structure for scheduling bh */
 186
 187         u32 max_frame_size;                     /* as set by device config */
 188
 189         u32 pending_bh;
 190
 191         bool bh_running;                                /* Protection from multiple */
 192         int isr_overflow;
 193         bool bh_requested;
 194
 195         int dcd_chkcount;                       /* check counts to prevent */
 196         int cts_chkcount;                       /* too many IRQs if a signal */
 197         int dsr_chkcount;                       /* is floating */
 198         int ri_chkcount;
 199
 200         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 201         unsigned long buffer_list_phys;
 202
 203         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 204         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 205         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 206         unsigned int current_rx_buf;
 207
 208         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 209         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 210         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 211         unsigned int last_tx_buf;
 212
 213         unsigned char *tmp_rx_buf;
 214         unsigned int tmp_rx_buf_count;
 215
 216         bool rx_enabled;
 217         bool rx_overflow;
 218
 219         bool tx_enabled;
 220         bool tx_active;
 221         u32 idle_mode;
 222
 223         unsigned char ie0_value;
 224         unsigned char ie1_value;
 225         unsigned char ie2_value;
 226         unsigned char ctrlreg_value;
 227         unsigned char old_signals;
 228
 229         char device_name[25];                   /* device instance name */
 230
 231         int port_count;
 232         int adapter_num;
 233         int port_num;
 234
 235         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 236
 237         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 238
 239         unsigned int irq_level;                 /* interrupt level */
 240         unsigned long irq_flags;
 241         bool irq_requested;                     /* true if IRQ requested */
 242
 243         MGSL_PARAMS params;                     /* communications parameters */
 244
 245         unsigned char serial_signals;           /* current serial signal states */
 246
 247         bool irq_occurred;                      /* for diagnostics use */
 248         unsigned int init_error;                /* Initialization startup error */
 249
 250         u32 last_mem_alloc;
 251         unsigned char* memory_base;             /* shared memory address (PCI only) */
 252         u32 phys_memory_base;
 253         int shared_mem_requested;
 254
 255         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 256         u32 phys_sca_base;
 257         u32 sca_offset;
 258         bool sca_base_requested;
 259
 260         unsigned char* lcr_base;                /* local config registers (PCI only) */
 261         u32 phys_lcr_base;
 262         u32 lcr_offset;
 263         int lcr_mem_requested;
 264
 265         unsigned char* statctrl_base;           /* status/control register memory */
 266         u32 phys_statctrl_base;
 267         u32 statctrl_offset;
 268         bool sca_statctrl_requested;
 269
 270         u32 misc_ctrl_value;
 271         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 272         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 273         bool drop_rts_on_tx_done;
 274
 275         struct  _input_signal_events    input_signal_events;
 276
 277         /* SPPP/Cisco HDLC device parts */
 278         int netcount;
 279         int dosyncppp;
 280         spinlock_t netlock;
 281
 282 #if SYNCLINK_GENERIC_HDLC
 283         struct net_device *netdev;
 284 #endif
 285
 286 } SLMP_INFO;
 287
 288 #define MGSL_MAGIC 0x5401
 289
 290 /*
 291  * define serial signal status change macros
 292  */
 293 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 294 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 295 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 296 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 297
 298 /* Common Register macros */
 299 #define LPR     0x00
 300 #define PABR0   0x02
 301 #define PABR1   0x03
 302 #define WCRL    0x04
 303 #define WCRM    0x05
 304 #define WCRH    0x06
 305 #define DPCR    0x08
 306 #define DMER    0x09
 307 #define ISR0    0x10
 308 #define ISR1    0x11
 309 #define ISR2    0x12
 310 #define IER0    0x14
 311 #define IER1    0x15
 312 #define IER2    0x16
 313 #define ITCR    0x18
 314 #define INTVR   0x1a
 315 #define IMVR    0x1c
 316
 317 /* MSCI Register macros */
 318 #define TRB     0x20
 319 #define TRBL    0x20
 320 #define TRBH    0x21
 321 #define SR0     0x22
 322 #define SR1     0x23
 323 #define SR2     0x24
 324 #define SR3     0x25
 325 #define FST     0x26
 326 #define IE0     0x28
 327 #define IE1     0x29
 328 #define IE2     0x2a
 329 #define FIE     0x2b
 330 #define CMD     0x2c
 331 #define MD0     0x2e
 332 #define MD1     0x2f
 333 #define MD2     0x30
 334 #define CTL     0x31
 335 #define SA0     0x32
 336 #define SA1     0x33
 337 #define IDL     0x34
 338 #define TMC     0x35
 339 #define RXS     0x36
 340 #define TXS     0x37
 341 #define TRC0    0x38
 342 #define TRC1    0x39
 343 #define RRC     0x3a
 344 #define CST0    0x3c
 345 #define CST1    0x3d
 346
 347 /* Timer Register Macros */
 348 #define TCNT    0x60
 349 #define TCNTL   0x60
 350 #define TCNTH   0x61
 351 #define TCONR   0x62
 352 #define TCONRL  0x62
 353 #define TCONRH  0x63
 354 #define TMCS    0x64
 355 #define TEPR    0x65
 356
 357 /* DMA Controller Register macros */
 358 #define DARL    0x80
 359 #define DARH    0x81
 360 #define DARB    0x82
 361 #define BAR     0x80
 362 #define BARL    0x80
 363 #define BARH    0x81
 364 #define BARB    0x82
 365 #define SAR     0x84
 366 #define SARL    0x84
 367 #define SARH    0x85
 368 #define SARB    0x86
 369 #define CPB     0x86
 370 #define CDA     0x88
 371 #define CDAL    0x88
 372 #define CDAH    0x89
 373 #define EDA     0x8a
 374 #define EDAL    0x8a
 375 #define EDAH    0x8b
 376 #define BFL     0x8c
 377 #define BFLL    0x8c
 378 #define BFLH    0x8d
 379 #define BCR     0x8e
 380 #define BCRL    0x8e
 381 #define BCRH    0x8f
 382 #define DSR     0x90
 383 #define DMR     0x91
 384 #define FCT     0x93
 385 #define DIR     0x94
 386 #define DCMD    0x95
 387
 388 /* combine with timer or DMA register address */
 389 #define TIMER0  0x00
 390 #define TIMER1  0x08
 391 #define TIMER2  0x10
 392 #define TIMER3  0x18
 393 #define RXDMA   0x00
 394 #define TXDMA   0x20
 395
 396 /* SCA Command Codes */
 397 #define NOOP            0x00
 398 #define TXRESET         0x01
 399 #define TXENABLE        0x02
 400 #define TXDISABLE       0x03
 401 #define TXCRCINIT       0x04
 402 #define TXCRCEXCL       0x05
 403 #define TXEOM           0x06
 404 #define TXABORT         0x07
 405 #define MPON            0x08
 406 #define TXBUFCLR        0x09
 407 #define RXRESET         0x11
 408 #define RXENABLE        0x12
 409 #define RXDISABLE       0x13
 410 #define RXCRCINIT       0x14
 411 #define RXREJECT        0x15
 412 #define SEARCHMP        0x16
 413 #define RXCRCEXCL       0x17
 414 #define RXCRCCALC       0x18
 415 #define CHRESET         0x21
 416 #define HUNT            0x31
 417
 418 /* DMA command codes */
 419 #define SWABORT         0x01
 420 #define FEICLEAR        0x02
 421
 422 /* IE0 */
 423 #define TXINTE          BIT7
 424 #define RXINTE          BIT6
 425 #define TXRDYE          BIT1
 426 #define RXRDYE          BIT0
 427
 428 /* IE1 & SR1 */
 429 #define UDRN    BIT7
 430 #define IDLE    BIT6
 431 #define SYNCD   BIT4
 432 #define FLGD    BIT4
 433 #define CCTS    BIT3
 434 #define CDCD    BIT2
 435 #define BRKD    BIT1
 436 #define ABTD    BIT1
 437 #define GAPD    BIT1
 438 #define BRKE    BIT0
 439 #define IDLD    BIT0
 440
 441 /* IE2 & SR2 */
 442 #define EOM     BIT7
 443 #define PMP     BIT6
 444 #define SHRT    BIT6
 445 #define PE      BIT5
 446 #define ABT     BIT5
 447 #define FRME    BIT4
 448 #define RBIT    BIT4
 449 #define OVRN    BIT3
 450 #define CRCE    BIT2
 451
 452
 453 /*
 454  * Global linked list of SyncLink devices
 455  */
 456 static SLMP_INFO *synclinkmp_device_list = NULL;
 457 static int synclinkmp_adapter_count = -1;
 458 static int synclinkmp_device_count = 0;
 459
 460 /*
 461  * Set this param to non-zero to load eax with the
 462  * .text section address and breakpoint on module load.
 463  * This is useful for use with gdb and add-symbol-file command.
 464  */
 465 static int break_on_load=0;
 466
 467 /*
 468  * Driver major number, defaults to zero to get auto
 469  * assigned major number. May be forced as module parameter.
 470  */
 471 static int ttymajor=0;
 472
 473 /*
 474  * Array of user specified options for ISA adapters.
 475  */
 476 static int debug_level = 0;
 477 static int maxframe[MAX_DEVICES] = {0,};
 478 static int dosyncppp[MAX_DEVICES] = {0,};
 479
 480 module_param(break_on_load, bool, 0);
 481 module_param(ttymajor, int, 0);
 482 module_param(debug_level, int, 0);
 483 module_param_array(maxframe, int, NULL, 0);
 484 module_param_array(dosyncppp, int, NULL, 0);
 485
 486 static char *driver_name = "SyncLink MultiPort driver";
 487 static char *driver_version = "$Revision: 4.38 $";
 488
 489 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 490 static void synclinkmp_remove_one(struct pci_dev *dev);
 491
 492 static struct pci_device_id synclinkmp_pci_tbl[] = {
 493         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 494         { 0, }, /* terminate list */
 495 };
 496 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 497
 498 MODULE_LICENSE("GPL");
 499
 500 static struct pci_driver synclinkmp_pci_driver = {
 501         .name           = "synclinkmp",
 502         .id_table       = synclinkmp_pci_tbl,
 503         .probe          = synclinkmp_init_one,
 504         .remove         = __devexit_p(synclinkmp_remove_one),
 505 };
 506
 507
 508 static struct tty_driver *serial_driver;
 509
 510 /* number of characters left in xmit buffer before we ask for more */
 511 #define WAKEUP_CHARS 256
 512
 513
 514 /* tty callbacks */
 515
 516 static int  open(struct tty_struct *tty, struct file * filp);
 517 static void close(struct tty_struct *tty, struct file * filp);
 518 static void hangup(struct tty_struct *tty);
 519 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 520
 521 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 522 static void put_char(struct tty_struct *tty, unsigned char ch);
 523 static void send_xchar(struct tty_struct *tty, char ch);
 524 static void wait_until_sent(struct tty_struct *tty, int timeout);
 525 static int  write_room(struct tty_struct *tty);
 526 static void flush_chars(struct tty_struct *tty);
 527 static void flush_buffer(struct tty_struct *tty);
 528 static void tx_hold(struct tty_struct *tty);
 529 static void tx_release(struct tty_struct *tty);
 530
 531 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 532 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 533 static int  chars_in_buffer(struct tty_struct *tty);
 534 static void throttle(struct tty_struct * tty);
 535 static void unthrottle(struct tty_struct * tty);
 536 static void set_break(struct tty_struct *tty, int break_state);
 537
 538 #if SYNCLINK_GENERIC_HDLC
 539 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 540 static void hdlcdev_tx_done(SLMP_INFO *info);
 541 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 542 static int  hdlcdev_init(SLMP_INFO *info);
 543 static void hdlcdev_exit(SLMP_INFO *info);
 544 #endif
 545
 546 /* ioctl handlers */
 547
 548 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 549 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 550 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 551 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 552 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 553 static int  tx_enable(SLMP_INFO *info, int enable);
 554 static int  tx_abort(SLMP_INFO *info);
 555 static int  rx_enable(SLMP_INFO *info, int enable);
 556 static int  modem_input_wait(SLMP_INFO *info,int arg);
 557 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 558 static int  tiocmget(struct tty_struct *tty, struct file *file);
 559 static int  tiocmset(struct tty_struct *tty, struct file *file,
 560                      unsigned int set, unsigned int clear);
 561 static void set_break(struct tty_struct *tty, int break_state);
 562
 563 static void add_device(SLMP_INFO *info);
 564 static void device_init(int adapter_num, struct pci_dev *pdev);
 565 static int  claim_resources(SLMP_INFO *info);
 566 static void release_resources(SLMP_INFO *info);
 567
 568 static int  startup(SLMP_INFO *info);
 569 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 570 static void shutdown(SLMP_INFO *info);
 571 static void program_hw(SLMP_INFO *info);
 572 static void change_params(SLMP_INFO *info);
 573
 574 static bool init_adapter(SLMP_INFO *info);
 575 static bool register_test(SLMP_INFO *info);
 576 static bool irq_test(SLMP_INFO *info);
 577 static bool loopback_test(SLMP_INFO *info);
 578 static int  adapter_test(SLMP_INFO *info);
 579 static bool memory_test(SLMP_INFO *info);
 580
 581 static void reset_adapter(SLMP_INFO *info);
 582 static void reset_port(SLMP_INFO *info);
 583 static void async_mode(SLMP_INFO *info);
 584 static void hdlc_mode(SLMP_INFO *info);
 585
 586 static void rx_stop(SLMP_INFO *info);
 587 static void rx_start(SLMP_INFO *info);
 588 static void rx_reset_buffers(SLMP_INFO *info);
 589 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 590 static bool rx_get_frame(SLMP_INFO *info);
 591
 592 static void tx_start(SLMP_INFO *info);
 593 static void tx_stop(SLMP_INFO *info);
 594 static void tx_load_fifo(SLMP_INFO *info);
 595 static void tx_set_idle(SLMP_INFO *info);
 596 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 597
 598 static void get_signals(SLMP_INFO *info);
 599 static void set_signals(SLMP_INFO *info);
 600 static void enable_loopback(SLMP_INFO *info, int enable);
 601 static void set_rate(SLMP_INFO *info, u32 data_rate);
 602
 603 static int  bh_action(SLMP_INFO *info);
 604 static void bh_handler(struct work_struct *work);
 605 static void bh_receive(SLMP_INFO *info);
 606 static void bh_transmit(SLMP_INFO *info);
 607 static void bh_status(SLMP_INFO *info);
 608 static void isr_timer(SLMP_INFO *info);
 609 static void isr_rxint(SLMP_INFO *info);
 610 static void isr_rxrdy(SLMP_INFO *info);
 611 static void isr_txint(SLMP_INFO *info);
 612 static void isr_txrdy(SLMP_INFO *info);
 613 static void isr_rxdmaok(SLMP_INFO *info);
 614 static void isr_rxdmaerror(SLMP_INFO *info);
 615 static void isr_txdmaok(SLMP_INFO *info);
 616 static void isr_txdmaerror(SLMP_INFO *info);
 617 static void isr_io_pin(SLMP_INFO *info, u16 status);
 618
 619 static int  alloc_dma_bufs(SLMP_INFO *info);
 620 static void free_dma_bufs(SLMP_INFO *info);
 621 static int  alloc_buf_list(SLMP_INFO *info);
 622 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 623 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 624 static void free_tmp_rx_buf(SLMP_INFO *info);
 625
 626 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 627 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 628 static void tx_timeout(unsigned long context);
 629 static void status_timeout(unsigned long context);
 630
 631 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 632 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 633 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 635 static unsigned char read_status_reg(SLMP_INFO * info);
 636 static void write_control_reg(SLMP_INFO * info);
 637
 638
 639 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 640 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 641 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 642
 643 static u32 misc_ctrl_value = 0x007e4040;
 644 static u32 lcr1_brdr_value = 0x00800028;
 645
 646 static u32 read_ahead_count = 8;
 647
 648 /* DPCR, DMA Priority Control
 649  *
 650  * 07..05  Not used, must be 0
 651  * 04      BRC, bus release condition: 0=all transfers complete
 652  *              1=release after 1 xfer on all channels
 653  * 03      CCC, channel change condition: 0=every cycle
 654  *              1=after each channel completes all xfers
 655  * 02..00  PR<2..0>, priority 100=round robin
 656  *
 657  * 00000100 = 0x00
 658  */
 659 static unsigned char dma_priority = 0x04;
 660
 661 // Number of bytes that can be written to shared RAM
 662 // in a single write operation
 663 static u32 sca_pci_load_interval = 64;
 664
 665 /*
 666  * 1st function defined in .text section. Calling this function in
 667  * init_module() followed by a breakpoint allows a remote debugger
 668  * (gdb) to get the .text address for the add-symbol-file command.
 669  * This allows remote debugging of dynamically loadable modules.
 670  */
 671 static void* synclinkmp_get_text_ptr(void);
 672 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 673
 674 static inline int sanity_check(SLMP_INFO *info,
 675                                char *name, const char *routine)
 676 {
 677 #ifdef SANITY_CHECK
 678         static const char *badmagic =
 679                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 680         static const char *badinfo =
 681                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 682
 683         if (!info) {
 684                 printk(badinfo, name, routine);
 685                 return 1;
 686         }
 687         if (info->magic != MGSL_MAGIC) {
 688                 printk(badmagic, name, routine);
 689                 return 1;
 690         }
 691 #else
 692         if (!info)
 693                 return 1;
 694 #endif
 695         return 0;
 696 }
 697
 698 /**
 699  * line discipline callback wrappers
 700  *
 701  * The wrappers maintain line discipline references
 702  * while calling into the line discipline.
 703  *
 704  * ldisc_receive_buf  - pass receive data to line discipline
 705  */
 706
 707 static void ldisc_receive_buf(struct tty_struct *tty,
 708                               const __u8 *data, char *flags, int count)
 709 {
 710         struct tty_ldisc *ld;
 711         if (!tty)
 712                 return;
 713         ld = tty_ldisc_ref(tty);
 714         if (ld) {
 715                 if (ld->receive_buf)
 716                         ld->receive_buf(tty, data, flags, count);
 717                 tty_ldisc_deref(ld);
 718         }
 719 }
 720
 721 /* tty callbacks */
 722
 723 /* Called when a port is opened.  Init and enable port.
 724  */
 725 static int open(struct tty_struct *tty, struct file *filp)
 726 {
 727         SLMP_INFO *info;
 728         int retval, line;
 729         unsigned long flags;
 730
 731         line = tty->index;
 732         if ((line < 0) || (line >= synclinkmp_device_count)) {
 733                 printk("%s(%d): open with invalid line #%d.\n",
 734                         __FILE__,__LINE__,line);
 735                 return -ENODEV;
 736         }
 737
 738         info = synclinkmp_device_list;
 739         while(info && info->line != line)
 740                 info = info->next_device;
 741         if (sanity_check(info, tty->name, "open"))
 742                 return -ENODEV;
 743         if ( info->init_error ) {
 744                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 745                         __FILE__,__LINE__,info->device_name,info->init_error);
 746                 return -ENODEV;
 747         }
 748
 749         tty->driver_data = info;
 750         info->tty = tty;
 751
 752         if (debug_level >= DEBUG_LEVEL_INFO)
 753                 printk("%s(%d):%s open(), old ref count = %d\n",
 754                          __FILE__,__LINE__,tty->driver->name, info->count);
 755
 756         /* If port is closing, signal caller to try again */
 757         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 758                 if (info->flags & ASYNC_CLOSING)
 759                         interruptible_sleep_on(&info->close_wait);
 760                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 761                         -EAGAIN : -ERESTARTSYS);
 762                 goto cleanup;
 763         }
 764
 765         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 766
 767         spin_lock_irqsave(&info->netlock, flags);
 768         if (info->netcount) {
 769                 retval = -EBUSY;
 770                 spin_unlock_irqrestore(&info->netlock, flags);
 771                 goto cleanup;
 772         }
 773         info->count++;
 774         spin_unlock_irqrestore(&info->netlock, flags);
 775
 776         if (info->count == 1) {
 777                 /* 1st open on this device, init hardware */
 778                 retval = startup(info);
 779                 if (retval < 0)
 780                         goto cleanup;
 781         }
 782
 783         retval = block_til_ready(tty, filp, info);
 784         if (retval) {
 785                 if (debug_level >= DEBUG_LEVEL_INFO)
 786                         printk("%s(%d):%s block_til_ready() returned %d\n",
 787                                  __FILE__,__LINE__, info->device_name, retval);
 788                 goto cleanup;
 789         }
 790
 791         if (debug_level >= DEBUG_LEVEL_INFO)
 792                 printk("%s(%d):%s open() success\n",
 793                          __FILE__,__LINE__, info->device_name);
 794         retval = 0;
 795
 796 cleanup:
 797         if (retval) {
 798                 if (tty->count == 1)
 799                         info->tty = NULL; /* tty layer will release tty struct */
 800                 if(info->count)
 801                         info->count--;
 802         }
 803
 804         return retval;
 805 }
 806
 807 /* Called when port is closed. Wait for remaining data to be
 808  * sent. Disable port and free resources.
 809  */
 810 static void close(struct tty_struct *tty, struct file *filp)
 811 {
 812         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 813
 814         if (sanity_check(info, tty->name, "close"))
 815                 return;
 816
 817         if (debug_level >= DEBUG_LEVEL_INFO)
 818                 printk("%s(%d):%s close() entry, count=%d\n",
 819                          __FILE__,__LINE__, info->device_name, info->count);
 820
 821         if (!info->count)
 822                 return;
 823
 824         if (tty_hung_up_p(filp))
 825                 goto cleanup;
 826
 827         if ((tty->count == 1) && (info->count != 1)) {
 828                 /*
 829                  * tty->count is 1 and the tty structure will be freed.
 830                  * info->count should be one in this case.
 831                  * if it's not, correct it so that the port is shutdown.
 832                  */
 833                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 834                        "info->count is %d\n",
 835                          __FILE__,__LINE__, info->device_name, info->count);
 836                 info->count = 1;
 837         }
 838
 839         info->count--;
 840
 841         /* if at least one open remaining, leave hardware active */
 842         if (info->count)
 843                 goto cleanup;
 844
 845         info->flags |= ASYNC_CLOSING;
 846
 847         /* set tty->closing to notify line discipline to
 848          * only process XON/XOFF characters. Only the N_TTY
 849          * discipline appears to use this (ppp does not).
 850          */
 851         tty->closing = 1;
 852
 853         /* wait for transmit data to clear all layers */
 854
 855         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 856                 if (debug_level >= DEBUG_LEVEL_INFO)
 857                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 858                                  __FILE__,__LINE__, info->device_name );
 859                 tty_wait_until_sent(tty, info->closing_wait);
 860         }
 861
 862         if (info->flags & ASYNC_INITIALIZED)
 863                 wait_until_sent(tty, info->timeout);
 864
 865         if (tty->driver->flush_buffer)
 866                 tty->driver->flush_buffer(tty);
 867
 868         tty_ldisc_flush(tty);
 869
 870         shutdown(info);
 871
 872         tty->closing = 0;
 873         info->tty = NULL;
 874
 875         if (info->blocked_open) {
 876                 if (info->close_delay) {
 877                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 878                 }
 879                 wake_up_interruptible(&info->open_wait);
 880         }
 881
 882         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 883
 884         wake_up_interruptible(&info->close_wait);
 885
 886 cleanup:
 887         if (debug_level >= DEBUG_LEVEL_INFO)
 888                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 889                         tty->driver->name, info->count);
 890 }
 891
 892 /* Called by tty_hangup() when a hangup is signaled.
 893  * This is the same as closing all open descriptors for the port.
 894  */
 895 static void hangup(struct tty_struct *tty)
 896 {
 897         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 898
 899         if (debug_level >= DEBUG_LEVEL_INFO)
 900                 printk("%s(%d):%s hangup()\n",
 901                          __FILE__,__LINE__, info->device_name );
 902
 903         if (sanity_check(info, tty->name, "hangup"))
 904                 return;
 905
 906         flush_buffer(tty);
 907         shutdown(info);
 908
 909         info->count = 0;
 910         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 911         info->tty = NULL;
 912
 913         wake_up_interruptible(&info->open_wait);
 914 }
 915
 916 /* Set new termios settings
 917  */
 918 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 919 {
 920         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 921         unsigned long flags;
 922
 923         if (debug_level >= DEBUG_LEVEL_INFO)
 924                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 925                         tty->driver->name );
 926
 927         change_params(info);
 928
 929         /* Handle transition to B0 status */
 930         if (old_termios->c_cflag & CBAUD &&
 931             !(tty->termios->c_cflag & CBAUD)) {
 932                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 933                 spin_lock_irqsave(&info->lock,flags);
 934                 set_signals(info);
 935                 spin_unlock_irqrestore(&info->lock,flags);
 936         }
 937
 938         /* Handle transition away from B0 status */
 939         if (!(old_termios->c_cflag & CBAUD) &&
 940             tty->termios->c_cflag & CBAUD) {
 941                 info->serial_signals |= SerialSignal_DTR;
 942                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 943                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 944                         info->serial_signals |= SerialSignal_RTS;
 945                 }
 946                 spin_lock_irqsave(&info->lock,flags);
 947                 set_signals(info);
 948                 spin_unlock_irqrestore(&info->lock,flags);
 949         }
 950
 951         /* Handle turning off CRTSCTS */
 952         if (old_termios->c_cflag & CRTSCTS &&
 953             !(tty->termios->c_cflag & CRTSCTS)) {
 954                 tty->hw_stopped = 0;
 955                 tx_release(tty);
 956         }
 957 }
 958
 959 /* Send a block of data
 960  *
 961  * Arguments:
 962  *
 963  *      tty             pointer to tty information structure
 964  *      buf             pointer to buffer containing send data
 965  *      count           size of send data in bytes
 966  *
 967  * Return Value:        number of characters written
 968  */
 969 static int write(struct tty_struct *tty,
 970                  const unsigned char *buf, int count)
 971 {
 972         int     c, ret = 0;
 973         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 974         unsigned long flags;
 975
 976         if (debug_level >= DEBUG_LEVEL_INFO)
 977                 printk("%s(%d):%s write() count=%d\n",
 978                        __FILE__,__LINE__,info->device_name,count);
 979
 980         if (sanity_check(info, tty->name, "write"))
 981                 goto cleanup;
 982
 983         if (!info->tx_buf)
 984                 goto cleanup;
 985
 986         if (info->params.mode == MGSL_MODE_HDLC) {
 987                 if (count > info->max_frame_size) {
 988                         ret = -EIO;
 989                         goto cleanup;
 990                 }
 991                 if (info->tx_active)
 992                         goto cleanup;
 993                 if (info->tx_count) {
 994                         /* send accumulated data from send_char() calls */
 995                         /* as frame and wait before accepting more data. */
 996                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
 997                         goto start;
 998                 }
 999                 ret = info->tx_count = count;
1000                 tx_load_dma_buffer(info, buf, count);
1001                 goto start;
1002         }
1003
1004         for (;;) {
1005                 c = min_t(int, count,
1006                         min(info->max_frame_size - info->tx_count - 1,
1007                             info->max_frame_size - info->tx_put));
1008                 if (c <= 0)
1009                         break;
1010
1011                 memcpy(info->tx_buf + info->tx_put, buf, c);
1012
1013                 spin_lock_irqsave(&info->lock,flags);
1014                 info->tx_put += c;
1015                 if (info->tx_put >= info->max_frame_size)
1016                         info->tx_put -= info->max_frame_size;
1017                 info->tx_count += c;
1018                 spin_unlock_irqrestore(&info->lock,flags);
1019
1020                 buf += c;
1021                 count -= c;
1022                 ret += c;
1023         }
1024
1025         if (info->params.mode == MGSL_MODE_HDLC) {
1026                 if (count) {
1027                         ret = info->tx_count = 0;
1028                         goto cleanup;
1029                 }
1030                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1031         }
1032 start:
1033         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1034                 spin_lock_irqsave(&info->lock,flags);
1035                 if (!info->tx_active)
1036                         tx_start(info);
1037                 spin_unlock_irqrestore(&info->lock,flags);
1038         }
1039
1040 cleanup:
1041         if (debug_level >= DEBUG_LEVEL_INFO)
1042                 printk( "%s(%d):%s write() returning=%d\n",
1043                         __FILE__,__LINE__,info->device_name,ret);
1044         return ret;
1045 }
1046
1047 /* Add a character to the transmit buffer.
1048  */
1049 static void put_char(struct tty_struct *tty, unsigned char ch)
1050 {
1051         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1052         unsigned long flags;
1053
1054         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1055                 printk( "%s(%d):%s put_char(%d)\n",
1056                         __FILE__,__LINE__,info->device_name,ch);
1057         }
1058
1059         if (sanity_check(info, tty->name, "put_char"))
1060                 return;
1061
1062         if (!info->tx_buf)
1063                 return;
1064
1065         spin_lock_irqsave(&info->lock,flags);
1066
1067         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1068              !info->tx_active ) {
1069
1070                 if (info->tx_count < info->max_frame_size - 1) {
1071                         info->tx_buf[info->tx_put++] = ch;
1072                         if (info->tx_put >= info->max_frame_size)
1073                                 info->tx_put -= info->max_frame_size;
1074                         info->tx_count++;
1075                 }
1076         }
1077
1078         spin_unlock_irqrestore(&info->lock,flags);
1079 }
1080
1081 /* Send a high-priority XON/XOFF character
1082  */
1083 static void send_xchar(struct tty_struct *tty, char ch)
1084 {
1085         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1086         unsigned long flags;
1087
1088         if (debug_level >= DEBUG_LEVEL_INFO)
1089                 printk("%s(%d):%s send_xchar(%d)\n",
1090                          __FILE__,__LINE__, info->device_name, ch );
1091
1092         if (sanity_check(info, tty->name, "send_xchar"))
1093                 return;
1094
1095         info->x_char = ch;
1096         if (ch) {
1097                 /* Make sure transmit interrupts are on */
1098                 spin_lock_irqsave(&info->lock,flags);
1099                 if (!info->tx_enabled)
1100                         tx_start(info);
1101                 spin_unlock_irqrestore(&info->lock,flags);
1102         }
1103 }
1104
1105 /* Wait until the transmitter is empty.
1106  */
1107 static void wait_until_sent(struct tty_struct *tty, int timeout)
1108 {
1109         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1110         unsigned long orig_jiffies, char_time;
1111
1112         if (!info )
1113                 return;
1114
1115         if (debug_level >= DEBUG_LEVEL_INFO)
1116                 printk("%s(%d):%s wait_until_sent() entry\n",
1117                          __FILE__,__LINE__, info->device_name );
1118
1119         if (sanity_check(info, tty->name, "wait_until_sent"))
1120                 return;
1121
1122         if (!(info->flags & ASYNC_INITIALIZED))
1123                 goto exit;
1124
1125         orig_jiffies = jiffies;
1126
1127         /* Set check interval to 1/5 of estimated time to
1128          * send a character, and make it at least 1. The check
1129          * interval should also be less than the timeout.
1130          * Note: use tight timings here to satisfy the NIST-PCTS.
1131          */
1132
1133         if ( info->params.data_rate ) {
1134                 char_time = info->timeout/(32 * 5);
1135                 if (!char_time)
1136                         char_time++;
1137         } else
1138                 char_time = 1;
1139
1140         if (timeout)
1141                 char_time = min_t(unsigned long, char_time, timeout);
1142
1143         if ( info->params.mode == MGSL_MODE_HDLC ) {
1144                 while (info->tx_active) {
1145                         msleep_interruptible(jiffies_to_msecs(char_time));
1146                         if (signal_pending(current))
1147                                 break;
1148                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1149                                 break;
1150                 }
1151         } else {
1152                 //TODO: determine if there is something similar to USC16C32
1153                 //      TXSTATUS_ALL_SENT status
1154                 while ( info->tx_active && info->tx_enabled) {
1155                         msleep_interruptible(jiffies_to_msecs(char_time));
1156                         if (signal_pending(current))
1157                                 break;
1158                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1159                                 break;
1160                 }
1161         }
1162
1163 exit:
1164         if (debug_level >= DEBUG_LEVEL_INFO)
1165                 printk("%s(%d):%s wait_until_sent() exit\n",
1166                          __FILE__,__LINE__, info->device_name );
1167 }
1168
1169 /* Return the count of free bytes in transmit buffer
1170  */
1171 static int write_room(struct tty_struct *tty)
1172 {
1173         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1174         int ret;
1175
1176         if (sanity_check(info, tty->name, "write_room"))
1177                 return 0;
1178
1179         if (info->params.mode == MGSL_MODE_HDLC) {
1180                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1181         } else {
1182                 ret = info->max_frame_size - info->tx_count - 1;
1183                 if (ret < 0)
1184                         ret = 0;
1185         }
1186
1187         if (debug_level >= DEBUG_LEVEL_INFO)
1188                 printk("%s(%d):%s write_room()=%d\n",
1189                        __FILE__, __LINE__, info->device_name, ret);
1190
1191         return ret;
1192 }
1193
1194 /* enable transmitter and send remaining buffered characters
1195  */
1196 static void flush_chars(struct tty_struct *tty)
1197 {
1198         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1199         unsigned long flags;
1200
1201         if ( debug_level >= DEBUG_LEVEL_INFO )
1202                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1203                         __FILE__,__LINE__,info->device_name,info->tx_count);
1204
1205         if (sanity_check(info, tty->name, "flush_chars"))
1206                 return;
1207
1208         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1209             !info->tx_buf)
1210                 return;
1211
1212         if ( debug_level >= DEBUG_LEVEL_INFO )
1213                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1214                         __FILE__,__LINE__,info->device_name );
1215
1216         spin_lock_irqsave(&info->lock,flags);
1217
1218         if (!info->tx_active) {
1219                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1220                         info->tx_count ) {
1221                         /* operating in synchronous (frame oriented) mode */
1222                         /* copy data from circular tx_buf to */
1223                         /* transmit DMA buffer. */
1224                         tx_load_dma_buffer(info,
1225                                  info->tx_buf,info->tx_count);
1226                 }
1227                 tx_start(info);
1228         }
1229
1230         spin_unlock_irqrestore(&info->lock,flags);
1231 }
1232
1233 /* Discard all data in the send buffer
1234  */
1235 static void flush_buffer(struct tty_struct *tty)
1236 {
1237         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1238         unsigned long flags;
1239
1240         if (debug_level >= DEBUG_LEVEL_INFO)
1241                 printk("%s(%d):%s flush_buffer() entry\n",
1242                          __FILE__,__LINE__, info->device_name );
1243
1244         if (sanity_check(info, tty->name, "flush_buffer"))
1245                 return;
1246
1247         spin_lock_irqsave(&info->lock,flags);
1248         info->tx_count = info->tx_put = info->tx_get = 0;
1249         del_timer(&info->tx_timer);
1250         spin_unlock_irqrestore(&info->lock,flags);
1251
1252         tty_wakeup(tty);
1253 }
1254
1255 /* throttle (stop) transmitter
1256  */
1257 static void tx_hold(struct tty_struct *tty)
1258 {
1259         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1260         unsigned long flags;
1261
1262         if (sanity_check(info, tty->name, "tx_hold"))
1263                 return;
1264
1265         if ( debug_level >= DEBUG_LEVEL_INFO )
1266                 printk("%s(%d):%s tx_hold()\n",
1267                         __FILE__,__LINE__,info->device_name);
1268
1269         spin_lock_irqsave(&info->lock,flags);
1270         if (info->tx_enabled)
1271                 tx_stop(info);
1272         spin_unlock_irqrestore(&info->lock,flags);
1273 }
1274
1275 /* release (start) transmitter
1276  */
1277 static void tx_release(struct tty_struct *tty)
1278 {
1279         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1280         unsigned long flags;
1281
1282         if (sanity_check(info, tty->name, "tx_release"))
1283                 return;
1284
1285         if ( debug_level >= DEBUG_LEVEL_INFO )
1286                 printk("%s(%d):%s tx_release()\n",
1287                         __FILE__,__LINE__,info->device_name);
1288
1289         spin_lock_irqsave(&info->lock,flags);
1290         if (!info->tx_enabled)
1291                 tx_start(info);
1292         spin_unlock_irqrestore(&info->lock,flags);
1293 }
1294
1295 /* Service an IOCTL request
1296  *
1297  * Arguments:
1298  *
1299  *      tty     pointer to tty instance data
1300  *      file    pointer to associated file object for device
1301  *      cmd     IOCTL command code
1302  *      arg     command argument/context
1303  *
1304  * Return Value:        0 if success, otherwise error code
1305  */
1306 static int ioctl(struct tty_struct *tty, struct file *file,
1307                  unsigned int cmd, unsigned long arg)
1308 {
1309         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1310         int error;
1311         struct mgsl_icount cnow;        /* kernel counter temps */
1312         struct serial_icounter_struct __user *p_cuser;  /* user space */
1313         unsigned long flags;
1314         void __user *argp = (void __user *)arg;
1315
1316         if (debug_level >= DEBUG_LEVEL_INFO)
1317                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1318                         info->device_name, cmd );
1319
1320         if (sanity_check(info, tty->name, "ioctl"))
1321                 return -ENODEV;
1322
1323         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1324             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1325                 if (tty->flags & (1 << TTY_IO_ERROR))
1326                     return -EIO;
1327         }
1328
1329         switch (cmd) {
1330         case MGSL_IOCGPARAMS:
1331                 return get_params(info, argp);
1332         case MGSL_IOCSPARAMS:
1333                 return set_params(info, argp);
1334         case MGSL_IOCGTXIDLE:
1335                 return get_txidle(info, argp);
1336         case MGSL_IOCSTXIDLE:
1337                 return set_txidle(info, (int)arg);
1338         case MGSL_IOCTXENABLE:
1339                 return tx_enable(info, (int)arg);
1340         case MGSL_IOCRXENABLE:
1341                 return rx_enable(info, (int)arg);
1342         case MGSL_IOCTXABORT:
1343                 return tx_abort(info);
1344         case MGSL_IOCGSTATS:
1345                 return get_stats(info, argp);
1346         case MGSL_IOCWAITEVENT:
1347                 return wait_mgsl_event(info, argp);
1348         case MGSL_IOCLOOPTXDONE:
1349                 return 0; // TODO: Not supported, need to document
1350                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1351                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1352                  */
1353         case TIOCMIWAIT:
1354                 return modem_input_wait(info,(int)arg);
1355
1356                 /*
1357                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1358                  * Return: write counters to the user passed counter struct
1359                  * NB: both 1->0 and 0->1 transitions are counted except for
1360                  *     RI where only 0->1 is counted.
1361                  */
1362         case TIOCGICOUNT:
1363                 spin_lock_irqsave(&info->lock,flags);
1364                 cnow = info->icount;
1365                 spin_unlock_irqrestore(&info->lock,flags);
1366                 p_cuser = argp;
1367                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1368                 if (error) return error;
1369                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1370                 if (error) return error;
1371                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1372                 if (error) return error;
1373                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1374                 if (error) return error;
1375                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1376                 if (error) return error;
1377                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1378                 if (error) return error;
1379                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1380                 if (error) return error;
1381                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1382                 if (error) return error;
1383                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1384                 if (error) return error;
1385                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1386                 if (error) return error;
1387                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1388                 if (error) return error;
1389                 return 0;
1390         default:
1391                 return -ENOIOCTLCMD;
1392         }
1393         return 0;
1394 }
1395
1396 /*
1397  * /proc fs routines....
1398  */
1399
1400 static inline int line_info(char *buf, SLMP_INFO *info)
1401 {
1402         char    stat_buf[30];
1403         int     ret;
1404         unsigned long flags;
1405
1406         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1407                        "\tIRQ=%d MaxFrameSize=%u\n",
1408                 info->device_name,
1409                 info->phys_sca_base,
1410                 info->phys_memory_base,
1411                 info->phys_statctrl_base,
1412                 info->phys_lcr_base,
1413                 info->irq_level,
1414                 info->max_frame_size );
1415
1416         /* output current serial signal states */
1417         spin_lock_irqsave(&info->lock,flags);
1418         get_signals(info);
1419         spin_unlock_irqrestore(&info->lock,flags);
1420
1421         stat_buf[0] = 0;
1422         stat_buf[1] = 0;
1423         if (info->serial_signals & SerialSignal_RTS)
1424                 strcat(stat_buf, "|RTS");
1425         if (info->serial_signals & SerialSignal_CTS)
1426                 strcat(stat_buf, "|CTS");
1427         if (info->serial_signals & SerialSignal_DTR)
1428                 strcat(stat_buf, "|DTR");
1429         if (info->serial_signals & SerialSignal_DSR)
1430                 strcat(stat_buf, "|DSR");
1431         if (info->serial_signals & SerialSignal_DCD)
1432                 strcat(stat_buf, "|CD");
1433         if (info->serial_signals & SerialSignal_RI)
1434                 strcat(stat_buf, "|RI");
1435
1436         if (info->params.mode == MGSL_MODE_HDLC) {
1437                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1438                               info->icount.txok, info->icount.rxok);
1439                 if (info->icount.txunder)
1440                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1441                 if (info->icount.txabort)
1442                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1443                 if (info->icount.rxshort)
1444                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1445                 if (info->icount.rxlong)
1446                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1447                 if (info->icount.rxover)
1448                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1449                 if (info->icount.rxcrc)
1450                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1451         } else {
1452                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1453                               info->icount.tx, info->icount.rx);
1454                 if (info->icount.frame)
1455                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1456                 if (info->icount.parity)
1457                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1458                 if (info->icount.brk)
1459                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1460                 if (info->icount.overrun)
1461                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1462         }
1463
1464         /* Append serial signal status to end */
1465         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1466
1467         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1468          info->tx_active,info->bh_requested,info->bh_running,
1469          info->pending_bh);
1470
1471         return ret;
1472 }
1473
1474 /* Called to print information about devices
1475  */
1476 static int read_proc(char *page, char **start, off_t off, int count,
1477               int *eof, void *data)
1478 {
1479         int len = 0, l;
1480         off_t   begin = 0;
1481         SLMP_INFO *info;
1482
1483         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1484
1485         info = synclinkmp_device_list;
1486         while( info ) {
1487                 l = line_info(page + len, info);
1488                 len += l;
1489                 if (len+begin > off+count)
1490                         goto done;
1491                 if (len+begin < off) {
1492                         begin += len;
1493                         len = 0;
1494                 }
1495                 info = info->next_device;
1496         }
1497
1498         *eof = 1;
1499 done:
1500         if (off >= len+begin)
1501                 return 0;
1502         *start = page + (off-begin);
1503         return ((count < begin+len-off) ? count : begin+len-off);
1504 }
1505
1506 /* Return the count of bytes in transmit buffer
1507  */
1508 static int chars_in_buffer(struct tty_struct *tty)
1509 {
1510         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1511
1512         if (sanity_check(info, tty->name, "chars_in_buffer"))
1513                 return 0;
1514
1515         if (debug_level >= DEBUG_LEVEL_INFO)
1516                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1517                        __FILE__, __LINE__, info->device_name, info->tx_count);
1518
1519         return info->tx_count;
1520 }
1521
1522 /* Signal remote device to throttle send data (our receive data)
1523  */
1524 static void throttle(struct tty_struct * tty)
1525 {
1526         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1527         unsigned long flags;
1528
1529         if (debug_level >= DEBUG_LEVEL_INFO)
1530                 printk("%s(%d):%s throttle() entry\n",
1531                          __FILE__,__LINE__, info->device_name );
1532
1533         if (sanity_check(info, tty->name, "throttle"))
1534                 return;
1535
1536         if (I_IXOFF(tty))
1537                 send_xchar(tty, STOP_CHAR(tty));
1538
1539         if (tty->termios->c_cflag & CRTSCTS) {
1540                 spin_lock_irqsave(&info->lock,flags);
1541                 info->serial_signals &= ~SerialSignal_RTS;
1542                 set_signals(info);
1543                 spin_unlock_irqrestore(&info->lock,flags);
1544         }
1545 }
1546
1547 /* Signal remote device to stop throttling send data (our receive data)
1548  */
1549 static void unthrottle(struct tty_struct * tty)
1550 {
1551         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1552         unsigned long flags;
1553
1554         if (debug_level >= DEBUG_LEVEL_INFO)
1555                 printk("%s(%d):%s unthrottle() entry\n",
1556                          __FILE__,__LINE__, info->device_name );
1557
1558         if (sanity_check(info, tty->name, "unthrottle"))
1559                 return;
1560
1561         if (I_IXOFF(tty)) {
1562                 if (info->x_char)
1563                         info->x_char = 0;
1564                 else
1565                         send_xchar(tty, START_CHAR(tty));
1566         }
1567
1568         if (tty->termios->c_cflag & CRTSCTS) {
1569                 spin_lock_irqsave(&info->lock,flags);
1570                 info->serial_signals |= SerialSignal_RTS;
1571                 set_signals(info);
1572                 spin_unlock_irqrestore(&info->lock,flags);
1573         }
1574 }
1575
1576 /* set or clear transmit break condition
1577  * break_state  -1=set break condition, 0=clear
1578  */
1579 static void set_break(struct tty_struct *tty, int break_state)
1580 {
1581         unsigned char RegValue;
1582         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1583         unsigned long flags;
1584
1585         if (debug_level >= DEBUG_LEVEL_INFO)
1586                 printk("%s(%d):%s set_break(%d)\n",
1587                          __FILE__,__LINE__, info->device_name, break_state);
1588
1589         if (sanity_check(info, tty->name, "set_break"))
1590                 return;
1591
1592         spin_lock_irqsave(&info->lock,flags);
1593         RegValue = read_reg(info, CTL);
1594         if (break_state == -1)
1595                 RegValue |= BIT3;
1596         else
1597                 RegValue &= ~BIT3;
1598         write_reg(info, CTL, RegValue);
1599         spin_unlock_irqrestore(&info->lock,flags);
1600 }
1601
1602 #if SYNCLINK_GENERIC_HDLC
1603
1604 /**
1605  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1606  * set encoding and frame check sequence (FCS) options
1607  *
1608  * dev       pointer to network device structure
1609  * encoding  serial encoding setting
1610  * parity    FCS setting
1611  *
1612  * returns 0 if success, otherwise error code
1613  */
1614 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1615                           unsigned short parity)
1616 {
1617         SLMP_INFO *info = dev_to_port(dev);
1618         unsigned char  new_encoding;
1619         unsigned short new_crctype;
1620
1621         /* return error if TTY interface open */
1622         if (info->count)
1623                 return -EBUSY;
1624
1625         switch (encoding)
1626         {
1627         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1628         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1629         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1630         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1631         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1632         default: return -EINVAL;
1633         }
1634
1635         switch (parity)
1636         {
1637         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1638         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1639         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1640         default: return -EINVAL;
1641         }
1642
1643         info->params.encoding = new_encoding;
1644         info->params.crc_type = new_crctype;
1645
1646         /* if network interface up, reprogram hardware */
1647         if (info->netcount)
1648                 program_hw(info);
1649
1650         return 0;
1651 }
1652
1653 /**
1654  * called by generic HDLC layer to send frame
1655  *
1656  * skb  socket buffer containing HDLC frame
1657  * dev  pointer to network device structure
1658  *
1659  * returns 0 if success, otherwise error code
1660  */
1661 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1662 {
1663         SLMP_INFO *info = dev_to_port(dev);
1664         struct net_device_stats *stats = hdlc_stats(dev);
1665         unsigned long flags;
1666
1667         if (debug_level >= DEBUG_LEVEL_INFO)
1668                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1669
1670         /* stop sending until this frame completes */
1671         netif_stop_queue(dev);
1672
1673         /* copy data to device buffers */
1674         info->tx_count = skb->len;
1675         tx_load_dma_buffer(info, skb->data, skb->len);
1676
1677         /* update network statistics */
1678         stats->tx_packets++;
1679         stats->tx_bytes += skb->len;
1680
1681         /* done with socket buffer, so free it */
1682         dev_kfree_skb(skb);
1683
1684         /* save start time for transmit timeout detection */
1685         dev->trans_start = jiffies;
1686
1687         /* start hardware transmitter if necessary */
1688         spin_lock_irqsave(&info->lock,flags);
1689         if (!info->tx_active)
1690                 tx_start(info);
1691         spin_unlock_irqrestore(&info->lock,flags);
1692
1693         return 0;
1694 }
1695
1696 /**
1697  * called by network layer when interface enabled
1698  * claim resources and initialize hardware
1699  *
1700  * dev  pointer to network device structure
1701  *
1702  * returns 0 if success, otherwise error code
1703  */
1704 static int hdlcdev_open(struct net_device *dev)
1705 {
1706         SLMP_INFO *info = dev_to_port(dev);
1707         int rc;
1708         unsigned long flags;
1709
1710         if (debug_level >= DEBUG_LEVEL_INFO)
1711                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1712
1713         /* generic HDLC layer open processing */
1714         if ((rc = hdlc_open(dev)))
1715                 return rc;
1716
1717         /* arbitrate between network and tty opens */
1718         spin_lock_irqsave(&info->netlock, flags);
1719         if (info->count != 0 || info->netcount != 0) {
1720                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1721                 spin_unlock_irqrestore(&info->netlock, flags);
1722                 return -EBUSY;
1723         }
1724         info->netcount=1;
1725         spin_unlock_irqrestore(&info->netlock, flags);
1726
1727         /* claim resources and init adapter */
1728         if ((rc = startup(info)) != 0) {
1729                 spin_lock_irqsave(&info->netlock, flags);
1730                 info->netcount=0;
1731                 spin_unlock_irqrestore(&info->netlock, flags);
1732                 return rc;
1733         }
1734
1735         /* assert DTR and RTS, apply hardware settings */
1736         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1737         program_hw(info);
1738
1739         /* enable network layer transmit */
1740         dev->trans_start = jiffies;
1741         netif_start_queue(dev);
1742
1743         /* inform generic HDLC layer of current DCD status */
1744         spin_lock_irqsave(&info->lock, flags);
1745         get_signals(info);
1746         spin_unlock_irqrestore(&info->lock, flags);
1747         if (info->serial_signals & SerialSignal_DCD)
1748                 netif_carrier_on(dev);
1749         else
1750                 netif_carrier_off(dev);
1751         return 0;
1752 }
1753
1754 /**
1755  * called by network layer when interface is disabled
1756  * shutdown hardware and release resources
1757  *
1758  * dev  pointer to network device structure
1759  *
1760  * returns 0 if success, otherwise error code
1761  */
1762 static int hdlcdev_close(struct net_device *dev)
1763 {
1764         SLMP_INFO *info = dev_to_port(dev);
1765         unsigned long flags;
1766
1767         if (debug_level >= DEBUG_LEVEL_INFO)
1768                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1769
1770         netif_stop_queue(dev);
1771
1772         /* shutdown adapter and release resources */
1773         shutdown(info);
1774
1775         hdlc_close(dev);
1776
1777         spin_lock_irqsave(&info->netlock, flags);
1778         info->netcount=0;
1779         spin_unlock_irqrestore(&info->netlock, flags);
1780
1781         return 0;
1782 }
1783
1784 /**
1785  * called by network layer to process IOCTL call to network device
1786  *
1787  * dev  pointer to network device structure
1788  * ifr  pointer to network interface request structure
1789  * cmd  IOCTL command code
1790  *
1791  * returns 0 if success, otherwise error code
1792  */
1793 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1794 {
1795         const size_t size = sizeof(sync_serial_settings);
1796         sync_serial_settings new_line;
1797         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1798         SLMP_INFO *info = dev_to_port(dev);
1799         unsigned int flags;
1800
1801         if (debug_level >= DEBUG_LEVEL_INFO)
1802                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1803
1804         /* return error if TTY interface open */
1805         if (info->count)
1806                 return -EBUSY;
1807
1808         if (cmd != SIOCWANDEV)
1809                 return hdlc_ioctl(dev, ifr, cmd);
1810
1811         switch(ifr->ifr_settings.type) {
1812         case IF_GET_IFACE: /* return current sync_serial_settings */
1813
1814                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1815                 if (ifr->ifr_settings.size < size) {
1816                         ifr->ifr_settings.size = size; /* data size wanted */
1817                         return -ENOBUFS;
1818                 }
1819
1820                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1821                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1822                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1823                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1824
1825                 switch (flags){
1826                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1827                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1828                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1829                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1830                 default: new_line.clock_type = CLOCK_DEFAULT;
1831                 }
1832
1833                 new_line.clock_rate = info->params.clock_speed;
1834                 new_line.loopback   = info->params.loopback ? 1:0;
1835
1836                 if (copy_to_user(line, &new_line, size))
1837                         return -EFAULT;
1838                 return 0;
1839
1840         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1841
1842                 if(!capable(CAP_NET_ADMIN))
1843                         return -EPERM;
1844                 if (copy_from_user(&new_line, line, size))
1845                         return -EFAULT;
1846
1847                 switch (new_line.clock_type)
1848                 {
1849                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1850                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1851                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1852                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1853                 case CLOCK_DEFAULT:  flags = info->params.flags &
1854                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1855                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1856                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1857                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1858                 default: return -EINVAL;
1859                 }
1860
1861                 if (new_line.loopback != 0 && new_line.loopback != 1)
1862                         return -EINVAL;
1863
1864                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1865                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1866                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1867                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1868                 info->params.flags |= flags;
1869
1870                 info->params.loopback = new_line.loopback;
1871
1872                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1873                         info->params.clock_speed = new_line.clock_rate;
1874                 else
1875                         info->params.clock_speed = 0;
1876
1877                 /* if network interface up, reprogram hardware */
1878                 if (info->netcount)
1879                         program_hw(info);
1880                 return 0;
1881
1882         default:
1883                 return hdlc_ioctl(dev, ifr, cmd);
1884         }
1885 }
1886
1887 /**
1888  * called by network layer when transmit timeout is detected
1889  *
1890  * dev  pointer to network device structure
1891  */
1892 static void hdlcdev_tx_timeout(struct net_device *dev)
1893 {
1894         SLMP_INFO *info = dev_to_port(dev);
1895         struct net_device_stats *stats = hdlc_stats(dev);
1896         unsigned long flags;
1897
1898         if (debug_level >= DEBUG_LEVEL_INFO)
1899                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1900
1901         stats->tx_errors++;
1902         stats->tx_aborted_errors++;
1903
1904         spin_lock_irqsave(&info->lock,flags);
1905         tx_stop(info);
1906         spin_unlock_irqrestore(&info->lock,flags);
1907
1908         netif_wake_queue(dev);
1909 }
1910
1911 /**
1912  * called by device driver when transmit completes
1913  * reenable network layer transmit if stopped
1914  *
1915  * info  pointer to device instance information
1916  */
1917 static void hdlcdev_tx_done(SLMP_INFO *info)
1918 {
1919         if (netif_queue_stopped(info->netdev))
1920                 netif_wake_queue(info->netdev);
1921 }
1922
1923 /**
1924  * called by device driver when frame received
1925  * pass frame to network layer
1926  *
1927  * info  pointer to device instance information
1928  * buf   pointer to buffer contianing frame data
1929  * size  count of data bytes in buf
1930  */
1931 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1932 {
1933         struct sk_buff *skb = dev_alloc_skb(size);
1934         struct net_device *dev = info->netdev;
1935         struct net_device_stats *stats = hdlc_stats(dev);
1936
1937         if (debug_level >= DEBUG_LEVEL_INFO)
1938                 printk("hdlcdev_rx(%s)\n",dev->name);
1939
1940         if (skb == NULL) {
1941                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1942                 stats->rx_dropped++;
1943                 return;
1944         }
1945
1946         memcpy(skb_put(skb, size),buf,size);
1947
1948         skb->protocol = hdlc_type_trans(skb, info->netdev);
1949
1950         stats->rx_packets++;
1951         stats->rx_bytes += size;
1952
1953         netif_rx(skb);
1954
1955         info->netdev->last_rx = jiffies;
1956 }
1957
1958 /**
1959  * called by device driver when adding device instance
1960  * do generic HDLC initialization
1961  *
1962  * info  pointer to device instance information
1963  *
1964  * returns 0 if success, otherwise error code
1965  */
1966 static int hdlcdev_init(SLMP_INFO *info)
1967 {
1968         int rc;
1969         struct net_device *dev;
1970         hdlc_device *hdlc;
1971
1972         /* allocate and initialize network and HDLC layer objects */
1973
1974         if (!(dev = alloc_hdlcdev(info))) {
1975                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1976                 return -ENOMEM;
1977         }
1978
1979         /* for network layer reporting purposes only */
1980         dev->mem_start = info->phys_sca_base;
1981         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1982         dev->irq       = info->irq_level;
1983
1984         /* network layer callbacks and settings */
1985         dev->do_ioctl       = hdlcdev_ioctl;
1986         dev->open           = hdlcdev_open;
1987         dev->stop           = hdlcdev_close;
1988         dev->tx_timeout     = hdlcdev_tx_timeout;
1989         dev->watchdog_timeo = 10*HZ;
1990         dev->tx_queue_len   = 50;
1991
1992         /* generic HDLC layer callbacks and settings */
1993         hdlc         = dev_to_hdlc(dev);
1994         hdlc->attach = hdlcdev_attach;
1995         hdlc->xmit   = hdlcdev_xmit;
1996
1997         /* register objects with HDLC layer */
1998         if ((rc = register_hdlc_device(dev))) {
1999                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2000                 free_netdev(dev);
2001                 return rc;
2002         }
2003
2004         info->netdev = dev;
2005         return 0;
2006 }
2007
2008 /**
2009  * called by device driver when removing device instance
2010  * do generic HDLC cleanup
2011  *
2012  * info  pointer to device instance information
2013  */
2014 static void hdlcdev_exit(SLMP_INFO *info)
2015 {
2016         unregister_hdlc_device(info->netdev);
2017         free_netdev(info->netdev);
2018         info->netdev = NULL;
2019 }
2020
2021 #endif /* CONFIG_HDLC */
2022
2023
2024 /* Return next bottom half action to perform.
2025  * Return Value:        BH action code or 0 if nothing to do.
2026  */
2027 static int bh_action(SLMP_INFO *info)
2028 {
2029         unsigned long flags;
2030         int rc = 0;
2031
2032         spin_lock_irqsave(&info->lock,flags);
2033
2034         if (info->pending_bh & BH_RECEIVE) {
2035                 info->pending_bh &= ~BH_RECEIVE;
2036                 rc = BH_RECEIVE;
2037         } else if (info->pending_bh & BH_TRANSMIT) {
2038                 info->pending_bh &= ~BH_TRANSMIT;
2039                 rc = BH_TRANSMIT;
2040         } else if (info->pending_bh & BH_STATUS) {
2041                 info->pending_bh &= ~BH_STATUS;
2042                 rc = BH_STATUS;
2043         }
2044
2045         if (!rc) {
2046                 /* Mark BH routine as complete */
2047                 info->bh_running = false;
2048                 info->bh_requested = false;
2049         }
2050
2051         spin_unlock_irqrestore(&info->lock,flags);
2052
2053         return rc;
2054 }
2055
2056 /* Perform bottom half processing of work items queued by ISR.
2057  */
2058 static void bh_handler(struct work_struct *work)
2059 {
2060         SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2061         int action;
2062
2063         if (!info)
2064                 return;
2065
2066         if ( debug_level >= DEBUG_LEVEL_BH )
2067                 printk( "%s(%d):%s bh_handler() entry\n",
2068                         __FILE__,__LINE__,info->device_name);
2069
2070         info->bh_running = true;
2071
2072         while((action = bh_action(info)) != 0) {
2073
2074                 /* Process work item */
2075                 if ( debug_level >= DEBUG_LEVEL_BH )
2076                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2077                                 __FILE__,__LINE__,info->device_name, action);
2078
2079                 switch (action) {
2080
2081                 case BH_RECEIVE:
2082                         bh_receive(info);
2083                         break;
2084                 case BH_TRANSMIT:
2085                         bh_transmit(info);
2086                         break;
2087                 case BH_STATUS:
2088                         bh_status(info);
2089                         break;
2090                 default:
2091                         /* unknown work item ID */
2092                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2093                                 __FILE__,__LINE__,info->device_name,action);
2094                         break;
2095                 }
2096         }
2097
2098         if ( debug_level >= DEBUG_LEVEL_BH )
2099                 printk( "%s(%d):%s bh_handler() exit\n",
2100                         __FILE__,__LINE__,info->device_name);
2101 }
2102
2103 static void bh_receive(SLMP_INFO *info)
2104 {
2105         if ( debug_level >= DEBUG_LEVEL_BH )
2106                 printk( "%s(%d):%s bh_receive()\n",
2107                         __FILE__,__LINE__,info->device_name);
2108
2109         while( rx_get_frame(info) );
2110 }
2111
2112 static void bh_transmit(SLMP_INFO *info)
2113 {
2114         struct tty_struct *tty = info->tty;
2115
2116         if ( debug_level >= DEBUG_LEVEL_BH )
2117                 printk( "%s(%d):%s bh_transmit() entry\n",
2118                         __FILE__,__LINE__,info->device_name);
2119
2120         if (tty)
2121                 tty_wakeup(tty);
2122 }
2123
2124 static void bh_status(SLMP_INFO *info)
2125 {
2126         if ( debug_level >= DEBUG_LEVEL_BH )
2127                 printk( "%s(%d):%s bh_status() entry\n",
2128                         __FILE__,__LINE__,info->device_name);
2129
2130         info->ri_chkcount = 0;
2131         info->dsr_chkcount = 0;
2132         info->dcd_chkcount = 0;
2133         info->cts_chkcount = 0;
2134 }
2135
2136 static void isr_timer(SLMP_INFO * info)
2137 {
2138         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2139
2140         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2141         write_reg(info, IER2, 0);
2142
2143         /* TMCS, Timer Control/Status Register
2144          *
2145          * 07      CMF, Compare match flag (read only) 1=match
2146          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2147          * 05      Reserved, must be 0
2148          * 04      TME, Timer Enable
2149          * 03..00  Reserved, must be 0
2150          *
2151          * 0000 0000
2152          */
2153         write_reg(info, (unsigned char)(timer + TMCS), 0);
2154
2155         info->irq_occurred = true;
2156
2157         if ( debug_level >= DEBUG_LEVEL_ISR )
2158                 printk("%s(%d):%s isr_timer()\n",
2159                         __FILE__,__LINE__,info->device_name);
2160 }
2161
2162 static void isr_rxint(SLMP_INFO * info)
2163 {
2164         struct tty_struct *tty = info->tty;
2165         struct  mgsl_icount *icount = &info->icount;
2166         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2167         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2168
2169         /* clear status bits */
2170         if (status)
2171                 write_reg(info, SR1, status);
2172
2173         if (status2)
2174                 write_reg(info, SR2, status2);
2175
2176         if ( debug_level >= DEBUG_LEVEL_ISR )
2177                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2178                         __FILE__,__LINE__,info->device_name,status,status2);
2179
2180         if (info->params.mode == MGSL_MODE_ASYNC) {
2181                 if (status & BRKD) {
2182                         icount->brk++;
2183
2184                         /* process break detection if tty control
2185                          * is not set to ignore it
2186                          */
2187                         if ( tty ) {
2188                                 if (!(status & info->ignore_status_mask1)) {
2189                                         if (info->read_status_mask1 & BRKD) {
2190                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2191                                                 if (info->flags & ASYNC_SAK)
2192                                                         do_SAK(tty);
2193                                         }
2194                                 }
2195                         }
2196                 }
2197         }
2198         else {
2199                 if (status & (FLGD|IDLD)) {
2200                         if (status & FLGD)
2201                                 info->icount.exithunt++;
2202                         else if (status & IDLD)
2203                                 info->icount.rxidle++;
2204                         wake_up_interruptible(&info->event_wait_q);
2205                 }
2206         }
2207
2208         if (status & CDCD) {
2209                 /* simulate a common modem status change interrupt
2210                  * for our handler
2211                  */
2212                 get_signals( info );
2213                 isr_io_pin(info,
2214                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2215         }
2216 }
2217
2218 /*
2219  * handle async rx data interrupts
2220  */
2221 static void isr_rxrdy(SLMP_INFO * info)
2222 {
2223         u16 status;
2224         unsigned char DataByte;
2225         struct tty_struct *tty = info->tty;
2226         struct  mgsl_icount *icount = &info->icount;
2227
2228         if ( debug_level >= DEBUG_LEVEL_ISR )
2229                 printk("%s(%d):%s isr_rxrdy\n",
2230                         __FILE__,__LINE__,info->device_name);
2231
2232         while((status = read_reg(info,CST0)) & BIT0)
2233         {
2234                 int flag = 0;
2235                 bool over = false;
2236                 DataByte = read_reg(info,TRB);
2237
2238                 icount->rx++;
2239
2240                 if ( status & (PE + FRME + OVRN) ) {
2241                         printk("%s(%d):%s rxerr=%04X\n",
2242                                 __FILE__,__LINE__,info->device_name,status);
2243
2244                         /* update error statistics */
2245                         if (status & PE)
2246                                 icount->parity++;
2247                         else if (status & FRME)
2248                                 icount->frame++;
2249                         else if (status & OVRN)
2250                                 icount->overrun++;
2251
2252                         /* discard char if tty control flags say so */
2253                         if (status & info->ignore_status_mask2)
2254                                 continue;
2255
2256                         status &= info->read_status_mask2;
2257
2258                         if ( tty ) {
2259                                 if (status & PE)
2260                                         flag = TTY_PARITY;
2261                                 else if (status & FRME)
2262                                         flag = TTY_FRAME;
2263                                 if (status & OVRN) {
2264                                         /* Overrun is special, since it's
2265                                          * reported immediately, and doesn't
2266                                          * affect the current character
2267                                          */
2268                                         over = true;
2269                                 }
2270                         }
2271                 }       /* end of if (error) */
2272
2273                 if ( tty ) {
2274                         tty_insert_flip_char(tty, DataByte, flag);
2275                         if (over)
2276                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2277                 }
2278         }
2279
2280         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2281                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2282                         __FILE__,__LINE__,info->device_name,
2283                         icount->rx,icount->brk,icount->parity,
2284                         icount->frame,icount->overrun);
2285         }
2286
2287         if ( tty )
2288                 tty_flip_buffer_push(tty);
2289 }
2290
2291 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2292 {
2293         if ( debug_level >= DEBUG_LEVEL_ISR )
2294                 printk("%s(%d):%s isr_txeom status=%02x\n",
2295                         __FILE__,__LINE__,info->device_name,status);
2296
2297         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2298         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2299         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2300
2301         if (status & UDRN) {
2302                 write_reg(info, CMD, TXRESET);
2303                 write_reg(info, CMD, TXENABLE);
2304         } else
2305                 write_reg(info, CMD, TXBUFCLR);
2306
2307         /* disable and clear tx interrupts */
2308         info->ie0_value &= ~TXRDYE;
2309         info->ie1_value &= ~(IDLE + UDRN);
2310         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2311         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2312
2313         if ( info->tx_active ) {
2314                 if (info->params.mode != MGSL_MODE_ASYNC) {
2315                         if (status & UDRN)
2316                                 info->icount.txunder++;
2317                         else if (status & IDLE)
2318                                 info->icount.txok++;
2319                 }
2320
2321                 info->tx_active = false;
2322                 info->tx_count = info->tx_put = info->tx_get = 0;
2323
2324                 del_timer(&info->tx_timer);
2325
2326                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2327                         info->serial_signals &= ~SerialSignal_RTS;
2328                         info->drop_rts_on_tx_done = false;
2329                         set_signals(info);
2330                 }
2331
2332 #if SYNCLINK_GENERIC_HDLC
2333                 if (info->netcount)
2334                         hdlcdev_tx_done(info);
2335                 else
2336 #endif
2337                 {
2338                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2339                                 tx_stop(info);
2340                                 return;
2341                         }
2342                         info->pending_bh |= BH_TRANSMIT;
2343                 }
2344         }
2345 }
2346
2347
2348 /*
2349  * handle tx status interrupts
2350  */
2351 static void isr_txint(SLMP_INFO * info)
2352 {
2353         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2354
2355         /* clear status bits */
2356         write_reg(info, SR1, status);
2357
2358         if ( debug_level >= DEBUG_LEVEL_ISR )
2359                 printk("%s(%d):%s isr_txint status=%02x\n",
2360                         __FILE__,__LINE__,info->device_name,status);
2361
2362         if (status & (UDRN + IDLE))
2363                 isr_txeom(info, status);
2364
2365         if (status & CCTS) {
2366                 /* simulate a common modem status change interrupt
2367                  * for our handler
2368                  */
2369                 get_signals( info );
2370                 isr_io_pin(info,
2371                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2372
2373         }
2374 }
2375
2376 /*
2377  * handle async tx data interrupts
2378  */
2379 static void isr_txrdy(SLMP_INFO * info)
2380 {
2381         if ( debug_level >= DEBUG_LEVEL_ISR )
2382                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2383                         __FILE__,__LINE__,info->device_name,info->tx_count);
2384
2385         if (info->params.mode != MGSL_MODE_ASYNC) {
2386                 /* disable TXRDY IRQ, enable IDLE IRQ */
2387                 info->ie0_value &= ~TXRDYE;
2388                 info->ie1_value |= IDLE;
2389                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2390                 return;
2391         }
2392
2393         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2394                 tx_stop(info);
2395                 return;
2396         }
2397
2398         if ( info->tx_count )
2399                 tx_load_fifo( info );
2400         else {
2401                 info->tx_active = false;
2402                 info->ie0_value &= ~TXRDYE;
2403                 write_reg(info, IE0, info->ie0_value);
2404         }
2405
2406         if (info->tx_count < WAKEUP_CHARS)
2407                 info->pending_bh |= BH_TRANSMIT;
2408 }
2409
2410 static void isr_rxdmaok(SLMP_INFO * info)
2411 {
2412         /* BIT7 = EOT (end of transfer)
2413          * BIT6 = EOM (end of message/frame)
2414          */
2415         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2416
2417         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2418         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2419
2420         if ( debug_level >= DEBUG_LEVEL_ISR )
2421                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2422                         __FILE__,__LINE__,info->device_name,status);
2423
2424         info->pending_bh |= BH_RECEIVE;
2425 }
2426
2427 static void isr_rxdmaerror(SLMP_INFO * info)
2428 {
2429         /* BIT5 = BOF (buffer overflow)
2430          * BIT4 = COF (counter overflow)
2431          */
2432         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2433
2434         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2435         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2436
2437         if ( debug_level >= DEBUG_LEVEL_ISR )
2438                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2439                         __FILE__,__LINE__,info->device_name,status);
2440
2441         info->rx_overflow = true;
2442         info->pending_bh |= BH_RECEIVE;
2443 }
2444
2445 static void isr_txdmaok(SLMP_INFO * info)
2446 {
2447         unsigned char status_reg1 = read_reg(info, SR1);
2448
2449         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2450         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2451         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2452
2453         if ( debug_level >= DEBUG_LEVEL_ISR )
2454                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2455                         __FILE__,__LINE__,info->device_name,status_reg1);
2456
2457         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2458         write_reg16(info, TRC0, 0);
2459         info->ie0_value |= TXRDYE;
2460         write_reg(info, IE0, info->ie0_value);
2461 }
2462
2463 static void isr_txdmaerror(SLMP_INFO * info)
2464 {
2465         /* BIT5 = BOF (buffer overflow)
2466          * BIT4 = COF (counter overflow)
2467          */
2468         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2469
2470         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2471         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2472
2473         if ( debug_level >= DEBUG_LEVEL_ISR )
2474                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2475                         __FILE__,__LINE__,info->device_name,status);
2476 }
2477
2478 /* handle input serial signal changes
2479  */
2480 static void isr_io_pin( SLMP_INFO *info, u16 status )
2481 {
2482         struct  mgsl_icount *icount;
2483
2484         if ( debug_level >= DEBUG_LEVEL_ISR )
2485                 printk("%s(%d):isr_io_pin status=%04X\n",
2486                         __FILE__,__LINE__,status);
2487
2488         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2489                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2490                 icount = &info->icount;
2491                 /* update input line counters */
2492                 if (status & MISCSTATUS_RI_LATCHED) {
2493                         icount->rng++;
2494                         if ( status & SerialSignal_RI )
2495                                 info->input_signal_events.ri_up++;
2496                         else
2497                                 info->input_signal_events.ri_down++;
2498                 }
2499                 if (status & MISCSTATUS_DSR_LATCHED) {
2500                         icount->dsr++;
2501                         if ( status & SerialSignal_DSR )
2502                                 info->input_signal_events.dsr_up++;
2503                         else
2504                                 info->input_signal_events.dsr_down++;
2505                 }
2506                 if (status & MISCSTATUS_DCD_LATCHED) {
2507                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2508                                 info->ie1_value &= ~CDCD;
2509                                 write_reg(info, IE1, info->ie1_value);
2510                         }
2511                         icount->dcd++;
2512                         if (status & SerialSignal_DCD) {
2513                                 info->input_signal_events.dcd_up++;
2514                         } else
2515                                 info->input_signal_events.dcd_down++;
2516 #if SYNCLINK_GENERIC_HDLC
2517                         if (info->netcount) {
2518                                 if (status & SerialSignal_DCD)
2519                                         netif_carrier_on(info->netdev);
2520                                 else
2521                                         netif_carrier_off(info->netdev);
2522                         }
2523 #endif
2524                 }
2525                 if (status & MISCSTATUS_CTS_LATCHED)
2526                 {
2527                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2528                                 info->ie1_value &= ~CCTS;
2529                                 write_reg(info, IE1, info->ie1_value);
2530                         }
2531                         icount->cts++;
2532                         if ( status & SerialSignal_CTS )
2533                                 info->input_signal_events.cts_up++;
2534                         else
2535                                 info->input_signal_events.cts_down++;
2536                 }
2537                 wake_up_interruptible(&info->status_event_wait_q);
2538                 wake_up_interruptible(&info->event_wait_q);
2539
2540                 if ( (info->flags & ASYNC_CHECK_CD) &&
2541                      (status & MISCSTATUS_DCD_LATCHED) ) {
2542                         if ( debug_level >= DEBUG_LEVEL_ISR )
2543                                 printk("%s CD now %s...", info->device_name,
2544                                        (status & SerialSignal_DCD) ? "on" : "off");
2545                         if (status & SerialSignal_DCD)
2546                                 wake_up_interruptible(&info->open_wait);
2547                         else {
2548                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2549                                         printk("doing serial hangup...");
2550                                 if (info->tty)
2551                                         tty_hangup(info->tty);
2552                         }
2553                 }
2554
2555                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2556                      (status & MISCSTATUS_CTS_LATCHED) ) {
2557                         if ( info->tty ) {
2558                                 if (info->tty->hw_stopped) {
2559                                         if (status & SerialSignal_CTS) {
2560                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2561                                                         printk("CTS tx start...");
2562                                                 info->tty->hw_stopped = 0;
2563                                                 tx_start(info);
2564                                                 info->pending_bh |= BH_TRANSMIT;
2565                                                 return;
2566                                         }
2567                                 } else {
2568                                         if (!(status & SerialSignal_CTS)) {
2569                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2570                                                         printk("CTS tx stop...");
2571                                                 info->tty->hw_stopped = 1;
2572                                                 tx_stop(info);
2573                                         }
2574                                 }
2575                         }
2576                 }
2577         }
2578
2579         info->pending_bh |= BH_STATUS;
2580 }
2581
2582 /* Interrupt service routine entry point.
2583  *
2584  * Arguments:
2585  *      irq             interrupt number that caused interrupt
2586  *      dev_id          device ID supplied during interrupt registration
2587  *      regs            interrupted processor context
2588  */
2589 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2590 {
2591         SLMP_INFO *info = dev_id;
2592         unsigned char status, status0, status1=0;
2593         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2594         unsigned char timerstatus0, timerstatus1=0;
2595         unsigned char shift;
2596         unsigned int i;
2597         unsigned short tmp;
2598
2599         if ( debug_level >= DEBUG_LEVEL_ISR )
2600                 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2601                         __FILE__, __LINE__, info->irq_level);
2602
2603         spin_lock(&info->lock);
2604
2605         for(;;) {
2606
2607                 /* get status for SCA0 (ports 0-1) */
2608                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2609                 status0 = (unsigned char)tmp;
2610                 dmastatus0 = (unsigned char)(tmp>>8);
2611                 timerstatus0 = read_reg(info, ISR2);
2612
2613                 if ( debug_level >= DEBUG_LEVEL_ISR )
2614                         printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2615                                 __FILE__, __LINE__, info->device_name,
2616                                 status0, dmastatus0, timerstatus0);
2617
2618                 if (info->port_count == 4) {
2619                         /* get status for SCA1 (ports 2-3) */
2620                         tmp = read_reg16(info->port_array[2], ISR0);
2621                         status1 = (unsigned char)tmp;
2622                         dmastatus1 = (unsigned char)(tmp>>8);
2623                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2624
2625                         if ( debug_level >= DEBUG_LEVEL_ISR )
2626                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2627                                         __FILE__,__LINE__,info->device_name,
2628                                         status1,dmastatus1,timerstatus1);
2629                 }
2630
2631                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2632                          !status1 && !dmastatus1 && !timerstatus1)
2633                         break;
2634
2635                 for(i=0; i < info->port_count ; i++) {
2636                         if (info->port_array[i] == NULL)
2637                                 continue;
2638                         if (i < 2) {
2639                                 status = status0;
2640                                 dmastatus = dmastatus0;
2641                         } else {
2642                                 status = status1;
2643                                 dmastatus = dmastatus1;
2644                         }
2645
2646                         shift = i & 1 ? 4 :0;
2647
2648                         if (status & BIT0 << shift)
2649                                 isr_rxrdy(info->port_array[i]);
2650                         if (status & BIT1 << shift)
2651                                 isr_txrdy(info->port_array[i]);
2652                         if (status & BIT2 << shift)
2653                                 isr_rxint(info->port_array[i]);
2654                         if (status & BIT3 << shift)
2655                                 isr_txint(info->port_array[i]);
2656
2657                         if (dmastatus & BIT0 << shift)
2658                                 isr_rxdmaerror(info->port_array[i]);
2659                         if (dmastatus & BIT1 << shift)
2660                                 isr_rxdmaok(info->port_array[i]);
2661                         if (dmastatus & BIT2 << shift)
2662                                 isr_txdmaerror(info->port_array[i]);
2663                         if (dmastatus & BIT3 << shift)
2664                                 isr_txdmaok(info->port_array[i]);
2665                 }
2666
2667                 if (timerstatus0 & (BIT5 | BIT4))
2668                         isr_timer(info->port_array[0]);
2669                 if (timerstatus0 & (BIT7 | BIT6))
2670                         isr_timer(info->port_array[1]);
2671                 if (timerstatus1 & (BIT5 | BIT4))
2672                         isr_timer(info->port_array[2]);
2673                 if (timerstatus1 & (BIT7 | BIT6))
2674                         isr_timer(info->port_array[3]);
2675         }
2676
2677         for(i=0; i < info->port_count ; i++) {
2678                 SLMP_INFO * port = info->port_array[i];
2679
2680                 /* Request bottom half processing if there's something
2681                  * for it to do and the bh is not already running.
2682                  *
2683                  * Note: startup adapter diags require interrupts.
2684                  * do not request bottom half processing if the
2685                  * device is not open in a normal mode.
2686                  */
2687                 if ( port && (port->count || port->netcount) &&
2688                      port->pending_bh && !port->bh_running &&
2689                      !port->bh_requested ) {
2690                         if ( debug_level >= DEBUG_LEVEL_ISR )
2691                                 printk("%s(%d):%s queueing bh task.\n",
2692                                         __FILE__,__LINE__,port->device_name);
2693                         schedule_work(&port->task);
2694                         port->bh_requested = true;
2695                 }
2696         }
2697
2698         spin_unlock(&info->lock);
2699
2700         if ( debug_level >= DEBUG_LEVEL_ISR )
2701                 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2702                         __FILE__, __LINE__, info->irq_level);
2703         return IRQ_HANDLED;
2704 }
2705
2706 /* Initialize and start device.
2707  */
2708 static int startup(SLMP_INFO * info)
2709 {
2710         if ( debug_level >= DEBUG_LEVEL_INFO )
2711                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2712
2713         if (info->flags & ASYNC_INITIALIZED)
2714                 return 0;
2715
2716         if (!info->tx_buf) {
2717                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2718                 if (!info->tx_buf) {
2719                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2720                                 __FILE__,__LINE__,info->device_name);
2721                         return -ENOMEM;
2722                 }
2723         }
2724
2725         info->pending_bh = 0;
2726
2727         memset(&info->icount, 0, sizeof(info->icount));
2728
2729         /* program hardware for current parameters */
2730         reset_port(info);
2731
2732         change_params(info);
2733
2734         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2735
2736         if (info->tty)
2737                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2738
2739         info->flags |= ASYNC_INITIALIZED;
2740
2741         return 0;
2742 }
2743
2744 /* Called by close() and hangup() to shutdown hardware
2745  */
2746 static void shutdown(SLMP_INFO * info)
2747 {
2748         unsigned long flags;
2749
2750         if (!(info->flags & ASYNC_INITIALIZED))
2751                 return;
2752
2753         if (debug_level >= DEBUG_LEVEL_INFO)
2754                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2755                          __FILE__,__LINE__, info->device_name );
2756
2757         /* clear status wait queue because status changes */
2758         /* can't happen after shutting down the hardware */
2759         wake_up_interruptible(&info->status_event_wait_q);
2760         wake_up_interruptible(&info->event_wait_q);
2761
2762         del_timer(&info->tx_timer);
2763         del_timer(&info->status_timer);
2764
2765         kfree(info->tx_buf);
2766         info->tx_buf = NULL;
2767
2768         spin_lock_irqsave(&info->lock,flags);
2769
2770         reset_port(info);
2771
2772         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2773                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2774                 set_signals(info);
2775         }
2776
2777         spin_unlock_irqrestore(&info->lock,flags);
2778
2779         if (info->tty)
2780                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2781
2782         info->flags &= ~ASYNC_INITIALIZED;
2783 }
2784
2785 static void program_hw(SLMP_INFO *info)
2786 {
2787         unsigned long flags;
2788
2789         spin_lock_irqsave(&info->lock,flags);
2790
2791         rx_stop(info);
2792         tx_stop(info);
2793
2794         info->tx_count = info->tx_put = info->tx_get = 0;
2795
2796         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2797                 hdlc_mode(info);
2798         else
2799                 async_mode(info);
2800
2801         set_signals(info);
2802
2803         info->dcd_chkcount = 0;
2804         info->cts_chkcount = 0;
2805         info->ri_chkcount = 0;
2806         info->dsr_chkcount = 0;
2807
2808         info->ie1_value |= (CDCD|CCTS);
2809         write_reg(info, IE1, info->ie1_value);
2810
2811         get_signals(info);
2812
2813         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2814                 rx_start(info);
2815
2816         spin_unlock_irqrestore(&info->lock,flags);
2817 }
2818
2819 /* Reconfigure adapter based on new parameters
2820  */
2821 static void change_params(SLMP_INFO *info)
2822 {
2823         unsigned cflag;
2824         int bits_per_char;
2825
2826         if (!info->tty || !info->tty->termios)
2827                 return;
2828
2829         if (debug_level >= DEBUG_LEVEL_INFO)
2830                 printk("%s(%d):%s change_params()\n",
2831                          __FILE__,__LINE__, info->device_name );
2832
2833         cflag = info->tty->termios->c_cflag;
2834
2835         /* if B0 rate (hangup) specified then negate DTR and RTS */
2836         /* otherwise assert DTR and RTS */
2837         if (cflag & CBAUD)
2838                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2839         else
2840                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2841
2842         /* byte size and parity */
2843
2844         switch (cflag & CSIZE) {
2845               case CS5: info->params.data_bits = 5; break;
2846               case CS6: info->params.data_bits = 6; break;
2847               case CS7: info->params.data_bits = 7; break;
2848               case CS8: info->params.data_bits = 8; break;
2849               /* Never happens, but GCC is too dumb to figure it out */
2850               default:  info->params.data_bits = 7; break;
2851               }
2852
2853         if (cflag & CSTOPB)
2854                 info->params.stop_bits = 2;
2855         else
2856                 info->params.stop_bits = 1;
2857
2858         info->params.parity = ASYNC_PARITY_NONE;
2859         if (cflag & PARENB) {
2860                 if (cflag & PARODD)
2861                         info->params.parity = ASYNC_PARITY_ODD;
2862                 else
2863                         info->params.parity = ASYNC_PARITY_EVEN;
2864 #ifdef CMSPAR
2865                 if (cflag & CMSPAR)
2866                         info->params.parity = ASYNC_PARITY_SPACE;
2867 #endif
2868         }
2869
2870         /* calculate number of jiffies to transmit a full
2871          * FIFO (32 bytes) at specified data rate
2872          */
2873         bits_per_char = info->params.data_bits +
2874                         info->params.stop_bits + 1;
2875
2876         /* if port data rate is set to 460800 or less then
2877          * allow tty settings to override, otherwise keep the
2878          * current data rate.
2879          */
2880         if (info->params.data_rate <= 460800) {
2881                 info->params.data_rate = tty_get_baud_rate(info->tty);
2882         }
2883
2884         if ( info->params.data_rate ) {
2885                 info->timeout = (32*HZ*bits_per_char) /
2886                                 info->params.data_rate;
2887         }
2888         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2889
2890         if (cflag & CRTSCTS)
2891                 info->flags |= ASYNC_CTS_FLOW;
2892         else
2893                 info->flags &= ~ASYNC_CTS_FLOW;
2894
2895         if (cflag & CLOCAL)
2896                 info->flags &= ~ASYNC_CHECK_CD;
2897         else
2898                 info->flags |= ASYNC_CHECK_CD;
2899
2900         /* process tty input control flags */
2901
2902         info->read_status_mask2 = OVRN;
2903         if (I_INPCK(info->tty))
2904                 info->read_status_mask2 |= PE | FRME;
2905         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2906                 info->read_status_mask1 |= BRKD;
2907         if (I_IGNPAR(info->tty))
2908                 info->ignore_status_mask2 |= PE | FRME;
2909         if (I_IGNBRK(info->tty)) {
2910                 info->ignore_status_mask1 |= BRKD;
2911                 /* If ignoring parity and break indicators, ignore
2912                  * overruns too.  (For real raw support).
2913                  */
2914                 if (I_IGNPAR(info->tty))
2915                         info->ignore_status_mask2 |= OVRN;
2916         }
2917
2918         program_hw(info);
2919 }
2920
2921 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2922 {
2923         int err;
2924
2925         if (debug_level >= DEBUG_LEVEL_INFO)
2926                 printk("%s(%d):%s get_params()\n",
2927                          __FILE__,__LINE__, info->device_name);
2928
2929         if (!user_icount) {
2930                 memset(&info->icount, 0, sizeof(info->icount));
2931         } else {
2932                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2933                 if (err)
2934                         return -EFAULT;
2935         }
2936
2937         return 0;
2938 }
2939
2940 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2941 {
2942         int err;
2943         if (debug_level >= DEBUG_LEVEL_INFO)
2944                 printk("%s(%d):%s get_params()\n",
2945                          __FILE__,__LINE__, info->device_name);
2946
2947         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2948         if (err) {
2949                 if ( debug_level >= DEBUG_LEVEL_INFO )
2950                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2951                                 __FILE__,__LINE__,info->device_name);
2952                 return -EFAULT;
2953         }
2954
2955         return 0;
2956 }
2957
2958 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2959 {
2960         unsigned long flags;
2961         MGSL_PARAMS tmp_params;
2962         int err;
2963
2964         if (debug_level >= DEBUG_LEVEL_INFO)
2965                 printk("%s(%d):%s set_params\n",
2966                         __FILE__,__LINE__,info->device_name );
2967         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2968         if (err) {
2969                 if ( debug_level >= DEBUG_LEVEL_INFO )
2970                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2971                                 __FILE__,__LINE__,info->device_name);
2972                 return -EFAULT;
2973         }
2974
2975         spin_lock_irqsave(&info->lock,flags);
2976         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2977         spin_unlock_irqrestore(&info->lock,flags);
2978
2979         change_params(info);
2980
2981         return 0;
2982 }
2983
2984 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2985 {
2986         int err;
2987
2988         if (debug_level >= DEBUG_LEVEL_INFO)
2989                 printk("%s(%d):%s get_txidle()=%d\n",
2990                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2991
2992         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2993         if (err) {
2994                 if ( debug_level >= DEBUG_LEVEL_INFO )
2995                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2996                                 __FILE__,__LINE__,info->device_name);
2997                 return -EFAULT;
2998         }
2999
3000         return 0;
3001 }
3002
3003 static int set_txidle(SLMP_INFO * info, int idle_mode)
3004 {
3005         unsigned long flags;
3006
3007         if (debug_level >= DEBUG_LEVEL_INFO)
3008                 printk("%s(%d):%s set_txidle(%d)\n",
3009                         __FILE__,__LINE__,info->device_name, idle_mode );
3010
3011         spin_lock_irqsave(&info->lock,flags);
3012         info->idle_mode = idle_mode;
3013         tx_set_idle( info );
3014         spin_unlock_irqrestore(&info->lock,flags);
3015         return 0;
3016 }
3017
3018 static int tx_enable(SLMP_INFO * info, int enable)
3019 {
3020         unsigned long flags;
3021
3022         if (debug_level >= DEBUG_LEVEL_INFO)
3023                 printk("%s(%d):%s tx_enable(%d)\n",
3024                         __FILE__,__LINE__,info->device_name, enable);
3025
3026         spin_lock_irqsave(&info->lock,flags);
3027         if ( enable ) {
3028                 if ( !info->tx_enabled ) {
3029                         tx_start(info);
3030                 }
3031         } else {
3032                 if ( info->tx_enabled )
3033                         tx_stop(info);
3034         }
3035         spin_unlock_irqrestore(&info->lock,flags);
3036         return 0;
3037 }
3038
3039 /* abort send HDLC frame
3040  */
3041 static int tx_abort(SLMP_INFO * info)
3042 {
3043         unsigned long flags;
3044
3045         if (debug_level >= DEBUG_LEVEL_INFO)
3046                 printk("%s(%d):%s tx_abort()\n",
3047                         __FILE__,__LINE__,info->device_name);
3048
3049         spin_lock_irqsave(&info->lock,flags);
3050         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3051                 info->ie1_value &= ~UDRN;
3052                 info->ie1_value |= IDLE;
3053                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3054                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3055
3056                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3057                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3058
3059                 write_reg(info, CMD, TXABORT);
3060         }
3061         spin_unlock_irqrestore(&info->lock,flags);
3062         return 0;
3063 }
3064
3065 static int rx_enable(SLMP_INFO * info, int enable)
3066 {
3067         unsigned long flags;
3068
3069         if (debug_level >= DEBUG_LEVEL_INFO)
3070                 printk("%s(%d):%s rx_enable(%d)\n",
3071                         __FILE__,__LINE__,info->device_name,enable);
3072
3073         spin_lock_irqsave(&info->lock,flags);
3074         if ( enable ) {
3075                 if ( !info->rx_enabled )
3076                         rx_start(info);
3077         } else {
3078                 if ( info->rx_enabled )
3079                         rx_stop(info);
3080         }
3081         spin_unlock_irqrestore(&info->lock,flags);
3082         return 0;
3083 }
3084
3085 /* wait for specified event to occur
3086  */
3087 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3088 {
3089         unsigned long flags;
3090         int s;
3091         int rc=0;
3092         struct mgsl_icount cprev, cnow;
3093         int events;
3094         int mask;
3095         struct  _input_signal_events oldsigs, newsigs;
3096         DECLARE_WAITQUEUE(wait, current);
3097
3098         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3099         if (rc) {
3100                 return  -EFAULT;
3101         }
3102
3103         if (debug_level >= DEBUG_LEVEL_INFO)
3104                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3105                         __FILE__,__LINE__,info->device_name,mask);
3106
3107         spin_lock_irqsave(&info->lock,flags);
3108
3109         /* return immediately if state matches requested events */
3110         get_signals(info);
3111         s = info->serial_signals;
3112
3113         events = mask &
3114                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3115                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3116                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3117                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3118         if (events) {
3119                 spin_unlock_irqrestore(&info->lock,flags);
3120                 goto exit;
3121         }
3122
3123         /* save current irq counts */
3124         cprev = info->icount;
3125         oldsigs = info->input_signal_events;
3126
3127         /* enable hunt and idle irqs if needed */
3128         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3129                 unsigned char oldval = info->ie1_value;
3130                 unsigned char newval = oldval +
3131                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3132                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3133                 if ( oldval != newval ) {
3134                         info->ie1_value = newval;
3135                         write_reg(info, IE1, info->ie1_value);
3136                 }
3137         }
3138
3139         set_current_state(TASK_INTERRUPTIBLE);
3140         add_wait_queue(&info->event_wait_q, &wait);
3141
3142         spin_unlock_irqrestore(&info->lock,flags);
3143
3144         for(;;) {
3145                 schedule();
3146                 if (signal_pending(current)) {
3147                         rc = -ERESTARTSYS;
3148                         break;
3149                 }
3150
3151                 /* get current irq counts */
3152                 spin_lock_irqsave(&info->lock,flags);
3153                 cnow = info->icount;
3154                 newsigs = info->input_signal_events;
3155                 set_current_state(TASK_INTERRUPTIBLE);
3156                 spin_unlock_irqrestore(&info->lock,flags);
3157
3158                 /* if no change, wait aborted for some reason */
3159                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3160                     newsigs.dsr_down == oldsigs.dsr_down &&
3161                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3162                     newsigs.dcd_down == oldsigs.dcd_down &&
3163                     newsigs.cts_up   == oldsigs.cts_up   &&
3164                     newsigs.cts_down == oldsigs.cts_down &&
3165                     newsigs.ri_up    == oldsigs.ri_up    &&
3166                     newsigs.ri_down  == oldsigs.ri_down  &&
3167                     cnow.exithunt    == cprev.exithunt   &&
3168                     cnow.rxidle      == cprev.rxidle) {
3169                         rc = -EIO;
3170                         break;
3171                 }
3172
3173                 events = mask &
3174                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3175                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3176                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3177                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3178                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3179                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3180                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3181                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3182                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3183                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3184                 if (events)
3185                         break;
3186
3187                 cprev = cnow;
3188                 oldsigs = newsigs;
3189         }
3190
3191         remove_wait_queue(&info->event_wait_q, &wait);
3192         set_current_state(TASK_RUNNING);
3193
3194
3195         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3196                 spin_lock_irqsave(&info->lock,flags);
3197                 if (!waitqueue_active(&info->event_wait_q)) {
3198                         /* disable enable exit hunt mode/idle rcvd IRQs */
3199                         info->ie1_value &= ~(FLGD|IDLD);
3200                         write_reg(info, IE1, info->ie1_value);
3201                 }
3202                 spin_unlock_irqrestore(&info->lock,flags);
3203         }
3204 exit:
3205         if ( rc == 0 )
3206                 PUT_USER(rc, events, mask_ptr);
3207
3208         return rc;
3209 }
3210
3211 static int modem_input_wait(SLMP_INFO *info,int arg)
3212 {
3213         unsigned long flags;
3214         int rc;
3215         struct mgsl_icount cprev, cnow;
3216         DECLARE_WAITQUEUE(wait, current);
3217
3218         /* save current irq counts */
3219         spin_lock_irqsave(&info->lock,flags);
3220         cprev = info->icount;
3221         add_wait_queue(&info->status_event_wait_q, &wait);
3222         set_current_state(TASK_INTERRUPTIBLE);
3223         spin_unlock_irqrestore(&info->lock,flags);
3224
3225         for(;;) {
3226                 schedule();
3227                 if (signal_pending(current)) {
3228                         rc = -ERESTARTSYS;
3229                         break;
3230                 }
3231
3232                 /* get new irq counts */
3233                 spin_lock_irqsave(&info->lock,flags);
3234                 cnow = info->icount;
3235                 set_current_state(TASK_INTERRUPTIBLE);
3236                 spin_unlock_irqrestore(&info->lock,flags);
3237
3238                 /* if no change, wait aborted for some reason */
3239                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3240                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3241                         rc = -EIO;
3242                         break;
3243                 }
3244
3245                 /* check for change in caller specified modem input */
3246                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3247                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3248                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3249                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3250                         rc = 0;
3251                         break;
3252                 }
3253
3254                 cprev = cnow;
3255         }
3256         remove_wait_queue(&info->status_event_wait_q, &wait);
3257         set_current_state(TASK_RUNNING);
3258         return rc;
3259 }
3260
3261 /* return the state of the serial control and status signals
3262  */
3263 static int tiocmget(struct tty_struct *tty, struct file *file)
3264 {
3265         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3266         unsigned int result;
3267         unsigned long flags;
3268
3269         spin_lock_irqsave(&info->lock,flags);
3270         get_signals(info);
3271         spin_unlock_irqrestore(&info->lock,flags);
3272
3273         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3274                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3275                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3276                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3277                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3278                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3279
3280         if (debug_level >= DEBUG_LEVEL_INFO)
3281                 printk("%s(%d):%s tiocmget() value=%08X\n",
3282                          __FILE__,__LINE__, info->device_name, result );
3283         return result;
3284 }
3285
3286 /* set modem control signals (DTR/RTS)
3287  */
3288 static int tiocmset(struct tty_struct *tty, struct file *file,
3289                     unsigned int set, unsigned int clear)
3290 {
3291         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3292         unsigned long flags;
3293
3294         if (debug_level >= DEBUG_LEVEL_INFO)
3295                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3296                         __FILE__,__LINE__,info->device_name, set, clear);
3297
3298         if (set & TIOCM_RTS)
3299                 info->serial_signals |= SerialSignal_RTS;
3300         if (set & TIOCM_DTR)
3301                 info->serial_signals |= SerialSignal_DTR;
3302         if (clear & TIOCM_RTS)
3303                 info->serial_signals &= ~SerialSignal_RTS;
3304         if (clear & TIOCM_DTR)
3305                 info->serial_signals &= ~SerialSignal_DTR;
3306
3307         spin_lock_irqsave(&info->lock,flags);
3308         set_signals(info);
3309         spin_unlock_irqrestore(&info->lock,flags);
3310
3311         return 0;
3312 }
3313
3314
3315
3316 /* Block the current process until the specified port is ready to open.
3317  */
3318 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3319                            SLMP_INFO *info)
3320 {
3321         DECLARE_WAITQUEUE(wait, current);
3322         int             retval;
3323         bool            do_clocal = false;
3324         bool            extra_count = false;
3325         unsigned long   flags;
3326
3327         if (debug_level >= DEBUG_LEVEL_INFO)
3328                 printk("%s(%d):%s block_til_ready()\n",
3329                          __FILE__,__LINE__, tty->driver->name );
3330
3331         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3332                 /* nonblock mode is set or port is not enabled */
3333                 /* just verify that callout device is not active */
3334                 info->flags |= ASYNC_NORMAL_ACTIVE;
3335                 return 0;
3336         }
3337
3338         if (tty->termios->c_cflag & CLOCAL)
3339                 do_clocal = true;
3340
3341         /* Wait for carrier detect and the line to become
3342          * free (i.e., not in use by the callout).  While we are in
3343          * this loop, info->count is dropped by one, so that
3344          * close() knows when to free things.  We restore it upon
3345          * exit, either normal or abnormal.
3346          */
3347
3348         retval = 0;
3349         add_wait_queue(&info->open_wait, &wait);
3350
3351         if (debug_level >= DEBUG_LEVEL_INFO)
3352                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3353                          __FILE__,__LINE__, tty->driver->name, info->count );
3354
3355         spin_lock_irqsave(&info->lock, flags);
3356         if (!tty_hung_up_p(filp)) {
3357                 extra_count = true;
3358                 info->count--;
3359         }
3360         spin_unlock_irqrestore(&info->lock, flags);
3361         info->blocked_open++;
3362
3363         while (1) {
3364                 if ((tty->termios->c_cflag & CBAUD)) {
3365                         spin_lock_irqsave(&info->lock,flags);
3366                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3367                         set_signals(info);
3368                         spin_unlock_irqrestore(&info->lock,flags);
3369                 }
3370
3371                 set_current_state(TASK_INTERRUPTIBLE);
3372
3373                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3374                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3375                                         -EAGAIN : -ERESTARTSYS;
3376                         break;
3377                 }
3378
3379                 spin_lock_irqsave(&info->lock,flags);
3380                 get_signals(info);
3381                 spin_unlock_irqrestore(&info->lock,flags);
3382
3383                 if (!(info->flags & ASYNC_CLOSING) &&
3384                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3385                         break;
3386                 }
3387
3388                 if (signal_pending(current)) {
3389                         retval = -ERESTARTSYS;
3390                         break;
3391                 }
3392
3393                 if (debug_level >= DEBUG_LEVEL_INFO)
3394                         printk("%s(%d):%s block_til_ready() count=%d\n",
3395                                  __FILE__,__LINE__, tty->driver->name, info->count );
3396
3397                 schedule();
3398         }
3399
3400         set_current_state(TASK_RUNNING);
3401         remove_wait_queue(&info->open_wait, &wait);
3402
3403         if (extra_count)
3404                 info->count++;
3405         info->blocked_open--;
3406
3407         if (debug_level >= DEBUG_LEVEL_INFO)
3408                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3409                          __FILE__,__LINE__, tty->driver->name, info->count );
3410
3411         if (!retval)
3412                 info->flags |= ASYNC_NORMAL_ACTIVE;
3413
3414         return retval;
3415 }
3416
3417 static int alloc_dma_bufs(SLMP_INFO *info)
3418 {
3419         unsigned short BuffersPerFrame;
3420         unsigned short BufferCount;
3421
3422         // Force allocation to start at 64K boundary for each port.
3423         // This is necessary because *all* buffer descriptors for a port
3424         // *must* be in the same 64K block. All descriptors on a port
3425         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3426         // into the CBP register.
3427         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3428
3429         /* Calculate the number of DMA buffers necessary to hold the */
3430         /* largest allowable frame size. Note: If the max frame size is */
3431         /* not an even multiple of the DMA buffer size then we need to */
3432         /* round the buffer count per frame up one. */
3433
3434         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3435         if ( info->max_frame_size % SCABUFSIZE )
3436                 BuffersPerFrame++;
3437
3438         /* calculate total number of data buffers (SCABUFSIZE) possible
3439          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3440          * for the descriptor list (BUFFERLISTSIZE).
3441          */
3442         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3443
3444         /* limit number of buffers to maximum amount of descriptors */
3445         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3446                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3447
3448         /* use enough buffers to transmit one max size frame */
3449         info->tx_buf_count = BuffersPerFrame + 1;
3450
3451         /* never use more than half the available buffers for transmit */
3452         if (info->tx_buf_count > (BufferCount/2))
3453                 info->tx_buf_count = BufferCount/2;
3454
3455         if (info->tx_buf_count > SCAMAXDESC)
3456                 info->tx_buf_count = SCAMAXDESC;
3457
3458         /* use remaining buffers for receive */
3459         info->rx_buf_count = BufferCount - info->tx_buf_count;
3460
3461         if (info->rx_buf_count > SCAMAXDESC)
3462                 info->rx_buf_count = SCAMAXDESC;
3463
3464         if ( debug_level >= DEBUG_LEVEL_INFO )
3465                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3466                         __FILE__,__LINE__, info->device_name,
3467                         info->tx_buf_count,info->rx_buf_count);
3468
3469         if ( alloc_buf_list( info ) < 0 ||
3470                 alloc_frame_bufs(info,
3471                                         info->rx_buf_list,
3472                                         info->rx_buf_list_ex,
3473                                         info->rx_buf_count) < 0 ||
3474                 alloc_frame_bufs(info,
3475                                         info->tx_buf_list,
3476                                         info->tx_buf_list_ex,
3477                                         info->tx_buf_count) < 0 ||
3478                 alloc_tmp_rx_buf(info) < 0 ) {
3479                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3480                         __FILE__,__LINE__, info->device_name);
3481                 return -ENOMEM;
3482         }
3483
3484         rx_reset_buffers( info );
3485
3486         return 0;
3487 }
3488
3489 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3490  */
3491 static int alloc_buf_list(SLMP_INFO *info)
3492 {
3493         unsigned int i;
3494
3495         /* build list in adapter shared memory */
3496         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3497         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3498         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3499
3500         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3501
3502         /* Save virtual address pointers to the receive and */
3503         /* transmit buffer lists. (Receive 1st). These pointers will */
3504         /* be used by the processor to access the lists. */
3505         info->rx_buf_list = (SCADESC *)info->buffer_list;
3506
3507         info->tx_buf_list = (SCADESC *)info->buffer_list;
3508         info->tx_buf_list += info->rx_buf_count;
3509
3510         /* Build links for circular buffer entry lists (tx and rx)
3511          *
3512          * Note: links are physical addresses read by the SCA device
3513          * to determine the next buffer entry to use.
3514          */
3515
3516         for ( i = 0; i < info->rx_buf_count; i++ ) {
3517                 /* calculate and store physical address of this buffer entry */
3518                 info->rx_buf_list_ex[i].phys_entry =
3519                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3520
3521                 /* calculate and store physical address of */
3522                 /* next entry in cirular list of entries */
3523                 info->rx_buf_list[i].next = info->buffer_list_phys;
3524                 if ( i < info->rx_buf_count - 1 )
3525                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3526
3527                 info->rx_buf_list[i].length = SCABUFSIZE;
3528         }
3529
3530         for ( i = 0; i < info->tx_buf_count; i++ ) {
3531                 /* calculate and store physical address of this buffer entry */
3532                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3533                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3534
3535                 /* calculate and store physical address of */
3536                 /* next entry in cirular list of entries */
3537
3538                 info->tx_buf_list[i].next = info->buffer_list_phys +
3539                         info->rx_buf_count * sizeof(SCADESC);
3540
3541                 if ( i < info->tx_buf_count - 1 )
3542                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3543         }
3544
3545         return 0;
3546 }
3547
3548 /* Allocate the frame DMA buffers used by the specified buffer list.
3549  */
3550 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3551 {
3552         int i;
3553         unsigned long phys_addr;
3554
3555         for ( i = 0; i < count; i++ ) {
3556                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3557                 phys_addr = info->port_array[0]->last_mem_alloc;
3558                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3559
3560                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3561                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3562         }
3563
3564         return 0;
3565 }
3566
3567 static void free_dma_bufs(SLMP_INFO *info)
3568 {
3569         info->buffer_list = NULL;
3570         info->rx_buf_list = NULL;
3571         info->tx_buf_list = NULL;
3572 }
3573
3574 /* allocate buffer large enough to hold max_frame_size.
3575  * This buffer is used to pass an assembled frame to the line discipline.
3576  */
3577 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3578 {
3579         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3580         if (info->tmp_rx_buf == NULL)
3581                 return -ENOMEM;
3582         return 0;
3583 }
3584
3585 static void free_tmp_rx_buf(SLMP_INFO *info)
3586 {
3587         kfree(info->tmp_rx_buf);
3588         info->tmp_rx_buf = NULL;
3589 }
3590
3591 static int claim_resources(SLMP_INFO *info)
3592 {
3593         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3594                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3595                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3596                 info->init_error = DiagStatus_AddressConflict;
3597                 goto errout;
3598         }
3599         else
3600                 info->shared_mem_requested = true;
3601
3602         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3603                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3604                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3605                 info->init_error = DiagStatus_AddressConflict;
3606                 goto errout;
3607         }
3608         else
3609                 info->lcr_mem_requested = true;
3610
3611         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3612                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3613                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3614                 info->init_error = DiagStatus_AddressConflict;
3615                 goto errout;
3616         }
3617         else
3618                 info->sca_base_requested = true;
3619
3620         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3621                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3622                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3623                 info->init_error = DiagStatus_AddressConflict;
3624                 goto errout;
3625         }
3626         else
3627                 info->sca_statctrl_requested = true;
3628
3629         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3630         if (!info->memory_base) {
3631                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3632                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3633                 info->init_error = DiagStatus_CantAssignPciResources;
3634                 goto errout;
3635         }
3636
3637         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3638         if (!info->lcr_base) {
3639                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3640                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3641                 info->init_error = DiagStatus_CantAssignPciResources;
3642                 goto errout;
3643         }
3644         info->lcr_base += info->lcr_offset;
3645
3646         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3647         if (!info->sca_base) {
3648                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3649                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3650                 info->init_error = DiagStatus_CantAssignPciResources;
3651                 goto errout;
3652         }
3653         info->sca_base += info->sca_offset;
3654
3655         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3656         if (!info->statctrl_base) {
3657                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3658                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3659                 info->init_error = DiagStatus_CantAssignPciResources;
3660                 goto errout;
3661         }
3662         info->statctrl_base += info->statctrl_offset;
3663
3664         if ( !memory_test(info) ) {
3665                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3666                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3667                 info->init_error = DiagStatus_MemoryError;
3668                 goto errout;
3669         }
3670
3671         return 0;
3672
3673 errout:
3674         release_resources( info );
3675         return -ENODEV;
3676 }
3677
3678 static void release_resources(SLMP_INFO *info)
3679 {
3680         if ( debug_level >= DEBUG_LEVEL_INFO )
3681                 printk( "%s(%d):%s release_resources() entry\n",
3682                         __FILE__,__LINE__,info->device_name );
3683
3684         if ( info->irq_requested ) {
3685                 free_irq(info->irq_level, info);
3686                 info->irq_requested = false;
3687         }
3688
3689         if ( info->shared_mem_requested ) {
3690                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3691                 info->shared_mem_requested = false;
3692         }
3693         if ( info->lcr_mem_requested ) {
3694                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3695                 info->lcr_mem_requested = false;
3696         }
3697         if ( info->sca_base_requested ) {
3698                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3699                 info->sca_base_requested = false;
3700         }
3701         if ( info->sca_statctrl_requested ) {
3702                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3703                 info->sca_statctrl_requested = false;
3704         }
3705
3706         if (info->memory_base){
3707                 iounmap(info->memory_base);
3708                 info->memory_base = NULL;
3709         }
3710
3711         if (info->sca_base) {
3712                 iounmap(info->sca_base - info->sca_offset);
3713                 info->sca_base=NULL;
3714         }
3715
3716         if (info->statctrl_base) {
3717                 iounmap(info->statctrl_base - info->statctrl_offset);
3718                 info->statctrl_base=NULL;
3719         }
3720
3721         if (info->lcr_base){
3722                 iounmap(info->lcr_base - info->lcr_offset);
3723                 info->lcr_base = NULL;
3724         }
3725
3726         if ( debug_level >= DEBUG_LEVEL_INFO )
3727                 printk( "%s(%d):%s release_resources() exit\n",
3728                         __FILE__,__LINE__,info->device_name );
3729 }
3730
3731 /* Add the specified device instance data structure to the
3732  * global linked list of devices and increment the device count.
3733  */
3734 static void add_device(SLMP_INFO *info)
3735 {
3736         info->next_device = NULL;
3737         info->line = synclinkmp_device_count;
3738         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3739
3740         if (info->line < MAX_DEVICES) {
3741                 if (maxframe[info->line])
3742                         info->max_frame_size = maxframe[info->line];
3743                 info->dosyncppp = dosyncppp[info->line];
3744         }
3745
3746         synclinkmp_device_count++;
3747
3748         if ( !synclinkmp_device_list )
3749                 synclinkmp_device_list = info;
3750         else {
3751                 SLMP_INFO *current_dev = synclinkmp_device_list;
3752                 while( current_dev->next_device )
3753                         current_dev = current_dev->next_device;
3754                 current_dev->next_device = info;
3755         }
3756
3757         if ( info->max_frame_size < 4096 )
3758                 info->max_frame_size = 4096;
3759         else if ( info->max_frame_size > 65535 )
3760                 info->max_frame_size = 65535;
3761
3762         printk( "SyncLink MultiPort %s: "
3763                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3764                 info->device_name,
3765                 info->phys_sca_base,
3766                 info->phys_memory_base,
3767                 info->phys_statctrl_base,
3768                 info->phys_lcr_base,
3769                 info->irq_level,
3770                 info->max_frame_size );
3771
3772 #if SYNCLINK_GENERIC_HDLC
3773         hdlcdev_init(info);
3774 #endif
3775 }
3776
3777 /* Allocate and initialize a device instance structure
3778  *
3779  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3780  */
3781 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3782 {
3783         SLMP_INFO *info;
3784
3785         info = kzalloc(sizeof(SLMP_INFO),
3786                  GFP_KERNEL);
3787
3788         if (!info) {
3789                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3790                         __FILE__,__LINE__, adapter_num, port_num);
3791         } else {
3792                 info->magic = MGSL_MAGIC;
3793                 INIT_WORK(&info->task, bh_handler);
3794                 info->max_frame_size = 4096;
3795                 info->close_delay = 5*HZ/10;
3796                 info->closing_wait = 30*HZ;
3797                 init_waitqueue_head(&info->open_wait);
3798                 init_waitqueue_head(&info->close_wait);
3799                 init_waitqueue_head(&info->status_event_wait_q);
3800                 init_waitqueue_head(&info->event_wait_q);
3801                 spin_lock_init(&info->netlock);
3802                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3803                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3804                 info->adapter_num = adapter_num;
3805                 info->port_num = port_num;
3806
3807                 /* Copy configuration info to device instance data */
3808                 info->irq_level = pdev->irq;
3809                 info->phys_lcr_base = pci_resource_start(pdev,0);
3810                 info->phys_sca_base = pci_resource_start(pdev,2);
3811                 info->phys_memory_base = pci_resource_start(pdev,3);
3812                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3813
3814                 /* Because veremap only works on page boundaries we must map
3815                  * a larger area than is actually implemented for the LCR
3816                  * memory range. We map a full page starting at the page boundary.
3817                  */
3818                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3819                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3820
3821                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3822                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3823
3824                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3825                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3826
3827                 info->bus_type = MGSL_BUS_TYPE_PCI;
3828                 info->irq_flags = IRQF_SHARED;
3829
3830                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3831                 setup_timer(&info->status_timer, status_timeout,
3832                                 (unsigned long)info);
3833
3834                 /* Store the PCI9050 misc control register value because a flaw
3835                  * in the PCI9050 prevents LCR registers from being read if
3836                  * BIOS assigns an LCR base address with bit 7 set.
3837                  *
3838                  * Only the misc control register is accessed for which only
3839                  * write access is needed, so set an initial value and change
3840                  * bits to the device instance data as we write the value
3841                  * to the actual misc control register.
3842                  */
3843                 info->misc_ctrl_value = 0x087e4546;
3844
3845                 /* initial port state is unknown - if startup errors
3846                  * occur, init_error will be set to indicate the
3847                  * problem. Once the port is fully initialized,
3848                  * this value will be set to 0 to indicate the
3849                  * port is available.
3850                  */
3851                 info->init_error = -1;
3852         }
3853
3854         return info;
3855 }
3856
3857 static void device_init(int adapter_num, struct pci_dev *pdev)
3858 {
3859         SLMP_INFO *port_array[SCA_MAX_PORTS];
3860         int port;
3861
3862         /* allocate device instances for up to SCA_MAX_PORTS devices */
3863         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3864                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3865                 if( port_array[port] == NULL ) {
3866                         for ( --port; port >= 0; --port )
3867                                 kfree(port_array[port]);
3868                         return;
3869                 }
3870         }
3871
3872         /* give copy of port_array to all ports and add to device list  */
3873         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3874                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3875                 add_device( port_array[port] );
3876                 spin_lock_init(&port_array[port]->lock);
3877         }
3878
3879         /* Allocate and claim adapter resources */
3880         if ( !claim_resources(port_array[0]) ) {
3881
3882                 alloc_dma_bufs(port_array[0]);
3883
3884                 /* copy resource information from first port to others */
3885                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3886                         port_array[port]->lock  = port_array[0]->lock;
3887                         port_array[port]->irq_level     = port_array[0]->irq_level;
3888                         port_array[port]->memory_base   = port_array[0]->memory_base;
3889                         port_array[port]->sca_base      = port_array[0]->sca_base;
3890                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3891                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3892                         alloc_dma_bufs(port_array[port]);
3893                 }
3894
3895                 if ( request_irq(port_array[0]->irq_level,
3896                                         synclinkmp_interrupt,
3897                                         port_array[0]->irq_flags,
3898                                         port_array[0]->device_name,
3899                                         port_array[0]) < 0 ) {
3900                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3901                                 __FILE__,__LINE__,
3902                                 port_array[0]->device_name,
3903                                 port_array[0]->irq_level );
3904                 }
3905                 else {
3906                         port_array[0]->irq_requested = true;
3907                         adapter_test(port_array[0]);
3908                 }
3909         }
3910 }
3911
3912 static const struct tty_operations ops = {
3913         .open = open,
3914         .close = close,
3915         .write = write,
3916         .put_char = put_char,
3917         .flush_chars = flush_chars,
3918         .write_room = write_room,
3919         .chars_in_buffer = chars_in_buffer,
3920         .flush_buffer = flush_buffer,
3921         .ioctl = ioctl,
3922         .throttle = throttle,
3923         .unthrottle = unthrottle,
3924         .send_xchar = send_xchar,
3925         .break_ctl = set_break,
3926         .wait_until_sent = wait_until_sent,
3927         .read_proc = read_proc,
3928         .set_termios = set_termios,
3929         .stop = tx_hold,
3930         .start = tx_release,
3931         .hangup = hangup,
3932         .tiocmget = tiocmget,
3933         .tiocmset = tiocmset,
3934 };
3935
3936 static void synclinkmp_cleanup(void)
3937 {
3938         int rc;
3939         SLMP_INFO *info;
3940         SLMP_INFO *tmp;
3941
3942         printk("Unloading %s %s\n", driver_name, driver_version);
3943
3944         if (serial_driver) {
3945                 if ((rc = tty_unregister_driver(serial_driver)))
3946                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3947                                __FILE__,__LINE__,rc);
3948                 put_tty_driver(serial_driver);
3949         }
3950
3951         /* reset devices */
3952         info = synclinkmp_device_list;
3953         while(info) {
3954                 reset_port(info);
3955                 info = info->next_device;
3956         }
3957
3958         /* release devices */
3959         info = synclinkmp_device_list;
3960         while(info) {
3961 #if SYNCLINK_GENERIC_HDLC
3962                 hdlcdev_exit(info);
3963 #endif
3964                 free_dma_bufs(info);
3965                 free_tmp_rx_buf(info);
3966                 if ( info->port_num == 0 ) {
3967                         if (info->sca_base)
3968                                 write_reg(info, LPR, 1); /* set low power mode */
3969                         release_resources(info);
3970                 }
3971                 tmp = info;
3972                 info = info->next_device;
3973                 kfree(tmp);
3974         }
3975
3976         pci_unregister_driver(&synclinkmp_pci_driver);
3977 }
3978
3979 /* Driver initialization entry point.
3980  */
3981
3982 static int __init synclinkmp_init(void)
3983 {
3984         int rc;
3985
3986         if (break_on_load) {
3987                 synclinkmp_get_text_ptr();
3988                 BREAKPOINT();
3989         }
3990
3991         printk("%s %s\n", driver_name, driver_version);
3992
3993         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3994                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3995                 return rc;
3996         }
3997
3998         serial_driver = alloc_tty_driver(128);
3999         if (!serial_driver) {
4000                 rc = -ENOMEM;
4001                 goto error;
4002         }
4003
4004         /* Initialize the tty_driver structure */
4005
4006         serial_driver->owner = THIS_MODULE;
4007         serial_driver->driver_name = "synclinkmp";
4008         serial_driver->name = "ttySLM";
4009         serial_driver->major = ttymajor;
4010         serial_driver->minor_start = 64;
4011         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4012         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4013         serial_driver->init_termios = tty_std_termios;
4014         serial_driver->init_termios.c_cflag =
4015                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4016         serial_driver->init_termios.c_ispeed = 9600;
4017         serial_driver->init_termios.c_ospeed = 9600;
4018         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4019         tty_set_operations(serial_driver, &ops);
4020         if ((rc = tty_register_driver(serial_driver)) < 0) {
4021                 printk("%s(%d):Couldn't register serial driver\n",
4022                         __FILE__,__LINE__);
4023                 put_tty_driver(serial_driver);
4024                 serial_driver = NULL;
4025                 goto error;
4026         }
4027
4028         printk("%s %s, tty major#%d\n",
4029                 driver_name, driver_version,
4030                 serial_driver->major);
4031
4032         return 0;
4033
4034 error:
4035         synclinkmp_cleanup();
4036         return rc;
4037 }
4038
4039 static void __exit synclinkmp_exit(void)
4040 {
4041         synclinkmp_cleanup();
4042 }
4043
4044 module_init(synclinkmp_init);
4045 module_exit(synclinkmp_exit);
4046
4047 /* Set the port for internal loopback mode.
4048  * The TxCLK and RxCLK signals are generated from the BRG and
4049  * the TxD is looped back to the RxD internally.
4050  */
4051 static void enable_loopback(SLMP_INFO *info, int enable)
4052 {
4053         if (enable) {
4054                 /* MD2 (Mode Register 2)
4055                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4056                  */
4057                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4058
4059                 /* degate external TxC clock source */
4060                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4061                 write_control_reg(info);
4062
4063                 /* RXS/TXS (Rx/Tx clock source)
4064                  * 07      Reserved, must be 0
4065                  * 06..04  Clock Source, 100=BRG
4066                  * 03..00  Clock Divisor, 0000=1
4067                  */
4068                 write_reg(info, RXS, 0x40);
4069                 write_reg(info, TXS, 0x40);
4070
4071         } else {
4072                 /* MD2 (Mode Register 2)
4073                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4074                  */
4075                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4076
4077                 /* RXS/TXS (Rx/Tx clock source)
4078                  * 07      Reserved, must be 0
4079                  * 06..04  Clock Source, 000=RxC/TxC Pin
4080                  * 03..00  Clock Divisor, 0000=1
4081                  */
4082                 write_reg(info, RXS, 0x00);
4083                 write_reg(info, TXS, 0x00);
4084         }
4085
4086         /* set LinkSpeed if available, otherwise default to 2Mbps */
4087         if (info->params.clock_speed)
4088                 set_rate(info, info->params.clock_speed);
4089         else
4090                 set_rate(info, 3686400);
4091 }
4092
4093 /* Set the baud rate register to the desired speed
4094  *
4095  *      data_rate       data rate of clock in bits per second
4096  *                      A data rate of 0 disables the AUX clock.
4097  */
4098 static void set_rate( SLMP_INFO *info, u32 data_rate )
4099 {
4100         u32 TMCValue;
4101         unsigned char BRValue;
4102         u32 Divisor=0;
4103
4104         /* fBRG = fCLK/(TMC * 2^BR)
4105          */
4106         if (data_rate != 0) {
4107                 Divisor = 14745600/data_rate;
4108                 if (!Divisor)
4109                         Divisor = 1;
4110
4111                 TMCValue = Divisor;
4112
4113                 BRValue = 0;
4114                 if (TMCValue != 1 && TMCValue != 2) {
4115                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4116                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4117                          * 50/50 duty cycle.
4118                          */
4119                         BRValue = 1;
4120                         TMCValue >>= 1;
4121                 }
4122
4123                 /* while TMCValue is too big for TMC register, divide
4124                  * by 2 and increment BR exponent.
4125                  */
4126                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4127                         TMCValue >>= 1;
4128
4129                 write_reg(info, TXS,
4130                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4131                 write_reg(info, RXS,
4132                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4133                 write_reg(info, TMC, (unsigned char)TMCValue);
4134         }
4135         else {
4136                 write_reg(info, TXS,0);
4137                 write_reg(info, RXS,0);
4138                 write_reg(info, TMC, 0);
4139         }
4140 }
4141
4142 /* Disable receiver
4143  */
4144 static void rx_stop(SLMP_INFO *info)
4145 {
4146         if (debug_level >= DEBUG_LEVEL_ISR)
4147                 printk("%s(%d):%s rx_stop()\n",
4148                          __FILE__,__LINE__, info->device_name );
4149
4150         write_reg(info, CMD, RXRESET);
4151
4152         info->ie0_value &= ~RXRDYE;
4153         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4154
4155         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4156         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4157         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4158
4159         info->rx_enabled = false;
4160         info->rx_overflow = false;
4161 }
4162
4163 /* enable the receiver
4164  */
4165 static void rx_start(SLMP_INFO *info)
4166 {
4167         int i;
4168
4169         if (debug_level >= DEBUG_LEVEL_ISR)
4170                 printk("%s(%d):%s rx_start()\n",
4171                          __FILE__,__LINE__, info->device_name );
4172
4173         write_reg(info, CMD, RXRESET);
4174
4175         if ( info->params.mode == MGSL_MODE_HDLC ) {
4176                 /* HDLC, disabe IRQ on rxdata */
4177                 info->ie0_value &= ~RXRDYE;
4178                 write_reg(info, IE0, info->ie0_value);
4179
4180                 /* Reset all Rx DMA buffers and program rx dma */
4181                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4182                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4183
4184                 for (i = 0; i < info->rx_buf_count; i++) {
4185                         info->rx_buf_list[i].status = 0xff;
4186
4187                         // throttle to 4 shared memory writes at a time to prevent
4188                         // hogging local bus (keep latency time for DMA requests low).
4189                         if (!(i % 4))
4190                                 read_status_reg(info);
4191                 }
4192                 info->current_rx_buf = 0;
4193
4194                 /* set current/1st descriptor address */
4195                 write_reg16(info, RXDMA + CDA,
4196                         info->rx_buf_list_ex[0].phys_entry);
4197
4198                 /* set new last rx descriptor address */
4199                 write_reg16(info, RXDMA + EDA,
4200                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4201
4202                 /* set buffer length (shared by all rx dma data buffers) */
4203                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4204
4205                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4206                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4207         } else {
4208                 /* async, enable IRQ on rxdata */
4209                 info->ie0_value |= RXRDYE;
4210                 write_reg(info, IE0, info->ie0_value);
4211         }
4212
4213         write_reg(info, CMD, RXENABLE);
4214
4215         info->rx_overflow = false;
4216         info->rx_enabled = true;
4217 }
4218
4219 /* Enable the transmitter and send a transmit frame if
4220  * one is loaded in the DMA buffers.
4221  */
4222 static void tx_start(SLMP_INFO *info)
4223 {
4224         if (debug_level >= DEBUG_LEVEL_ISR)
4225                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4226                          __FILE__,__LINE__, info->device_name,info->tx_count );
4227
4228         if (!info->tx_enabled ) {
4229                 write_reg(info, CMD, TXRESET);
4230                 write_reg(info, CMD, TXENABLE);
4231                 info->tx_enabled = true;
4232         }
4233
4234         if ( info->tx_count ) {
4235
4236                 /* If auto RTS enabled and RTS is inactive, then assert */
4237                 /* RTS and set a flag indicating that the driver should */
4238                 /* negate RTS when the transmission completes. */
4239
4240                 info->drop_rts_on_tx_done = false;
4241
4242                 if (info->params.mode != MGSL_MODE_ASYNC) {
4243
4244                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4245                                 get_signals( info );
4246                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4247                                         info->serial_signals |= SerialSignal_RTS;
4248                                         set_signals( info );
4249                                         info->drop_rts_on_tx_done = true;
4250                                 }
4251                         }
4252
4253                         write_reg16(info, TRC0,
4254                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4255
4256                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4257                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4258
4259                         /* set TX CDA (current descriptor address) */
4260                         write_reg16(info, TXDMA + CDA,
4261                                 info->tx_buf_list_ex[0].phys_entry);
4262
4263                         /* set TX EDA (last descriptor address) */
4264                         write_reg16(info, TXDMA + EDA,
4265                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4266
4267                         /* enable underrun IRQ */
4268                         info->ie1_value &= ~IDLE;
4269                         info->ie1_value |= UDRN;
4270                         write_reg(info, IE1, info->ie1_value);
4271                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4272
4273                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4274                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4275
4276                         mod_timer(&info->tx_timer, jiffies +
4277                                         msecs_to_jiffies(5000));
4278                 }
4279                 else {
4280                         tx_load_fifo(info);
4281                         /* async, enable IRQ on txdata */
4282                         info->ie0_value |= TXRDYE;
4283                         write_reg(info, IE0, info->ie0_value);
4284                 }
4285
4286                 info->tx_active = true;
4287         }
4288 }
4289
4290 /* stop the transmitter and DMA
4291  */
4292 static void tx_stop( SLMP_INFO *info )
4293 {
4294         if (debug_level >= DEBUG_LEVEL_ISR)
4295                 printk("%s(%d):%s tx_stop()\n",
4296                          __FILE__,__LINE__, info->device_name );
4297
4298         del_timer(&info->tx_timer);
4299
4300         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4301         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4302
4303         write_reg(info, CMD, TXRESET);
4304
4305         info->ie1_value &= ~(UDRN + IDLE);
4306         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4307         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4308
4309         info->ie0_value &= ~TXRDYE;
4310         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4311
4312         info->tx_enabled = false;
4313         info->tx_active = false;
4314 }
4315
4316 /* Fill the transmit FIFO until the FIFO is full or
4317  * there is no more data to load.
4318  */
4319 static void tx_load_fifo(SLMP_INFO *info)
4320 {
4321         u8 TwoBytes[2];
4322
4323         /* do nothing is now tx data available and no XON/XOFF pending */
4324
4325         if ( !info->tx_count && !info->x_char )
4326                 return;
4327
4328         /* load the Transmit FIFO until FIFOs full or all data sent */
4329
4330         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4331
4332                 /* there is more space in the transmit FIFO and */
4333                 /* there is more data in transmit buffer */
4334
4335                 if ( (info->tx_count > 1) && !info->x_char ) {
4336                         /* write 16-bits */
4337                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4338                         if (info->tx_get >= info->max_frame_size)
4339                                 info->tx_get -= info->max_frame_size;
4340                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4341                         if (info->tx_get >= info->max_frame_size)
4342                                 info->tx_get -= info->max_frame_size;
4343
4344                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4345
4346                         info->tx_count -= 2;
4347                         info->icount.tx += 2;
4348                 } else {
4349                         /* only 1 byte left to transmit or 1 FIFO slot left */
4350
4351                         if (info->x_char) {
4352                                 /* transmit pending high priority char */
4353                                 write_reg(info, TRB, info->x_char);
4354                                 info->x_char = 0;
4355                         } else {
4356                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4357                                 if (info->tx_get >= info->max_frame_size)
4358                                         info->tx_get -= info->max_frame_size;
4359                                 info->tx_count--;
4360                         }
4361                         info->icount.tx++;
4362                 }
4363         }
4364 }
4365
4366 /* Reset a port to a known state
4367  */
4368 static void reset_port(SLMP_INFO *info)
4369 {
4370         if (info->sca_base) {
4371
4372                 tx_stop(info);
4373                 rx_stop(info);
4374
4375                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4376                 set_signals(info);
4377
4378                 /* disable all port interrupts */
4379                 info->ie0_value = 0;
4380                 info->ie1_value = 0;
4381                 info->ie2_value = 0;
4382                 write_reg(info, IE0, info->ie0_value);
4383                 write_reg(info, IE1, info->ie1_value);
4384                 write_reg(info, IE2, info->ie2_value);
4385
4386                 write_reg(info, CMD, CHRESET);
4387         }
4388 }
4389
4390 /* Reset all the ports to a known state.
4391  */
4392 static void reset_adapter(SLMP_INFO *info)
4393 {
4394         int i;
4395
4396         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4397                 if (info->port_array[i])
4398                         reset_port(info->port_array[i]);
4399         }
4400 }
4401
4402 /* Program port for asynchronous communications.
4403  */
4404 static void async_mode(SLMP_INFO *info)
4405 {
4406
4407         unsigned char RegValue;
4408
4409         tx_stop(info);
4410         rx_stop(info);
4411
4412         /* MD0, Mode Register 0
4413          *
4414          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4415          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4416          * 03      Reserved, must be 0
4417          * 02      CRCCC, CRC Calculation, 0=disabled
4418          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4419          *
4420          * 0000 0000
4421          */
4422         RegValue = 0x00;
4423         if (info->params.stop_bits != 1)
4424                 RegValue |= BIT1;
4425         write_reg(info, MD0, RegValue);
4426
4427         /* MD1, Mode Register 1
4428          *
4429          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4430          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4431          * 03..02  RXCHR<1..0>, rx char size
4432          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4433          *
4434          * 0100 0000
4435          */
4436         RegValue = 0x40;
4437         switch (info->params.data_bits) {
4438         case 7: RegValue |= BIT4 + BIT2; break;
4439         case 6: RegValue |= BIT5 + BIT3; break;
4440         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4441         }
4442         if (info->params.parity != ASYNC_PARITY_NONE) {
4443                 RegValue |= BIT1;
4444                 if (info->params.parity == ASYNC_PARITY_ODD)
4445                         RegValue |= BIT0;
4446         }
4447         write_reg(info, MD1, RegValue);
4448
4449         /* MD2, Mode Register 2
4450          *
4451          * 07..02  Reserved, must be 0
4452          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4453          *
4454          * 0000 0000
4455          */
4456         RegValue = 0x00;
4457         if (info->params.loopback)
4458                 RegValue |= (BIT1 + BIT0);
4459         write_reg(info, MD2, RegValue);
4460
4461         /* RXS, Receive clock source
4462          *
4463          * 07      Reserved, must be 0
4464          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4465          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4466          */
4467         RegValue=BIT6;
4468         write_reg(info, RXS, RegValue);
4469
4470         /* TXS, Transmit clock source
4471          *
4472          * 07      Reserved, must be 0
4473          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4474          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4475          */
4476         RegValue=BIT6;
4477         write_reg(info, TXS, RegValue);
4478
4479         /* Control Register
4480          *
4481          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4482          */
4483         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4484         write_control_reg(info);
4485
4486         tx_set_idle(info);
4487
4488         /* RRC Receive Ready Control 0
4489          *
4490          * 07..05  Reserved, must be 0
4491          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4492          */
4493         write_reg(info, RRC, 0x00);
4494
4495         /* TRC0 Transmit Ready Control 0
4496          *
4497          * 07..05  Reserved, must be 0
4498          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4499          */
4500         write_reg(info, TRC0, 0x10);
4501
4502         /* TRC1 Transmit Ready Control 1
4503          *
4504          * 07..05  Reserved, must be 0
4505          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4506          */
4507         write_reg(info, TRC1, 0x1e);
4508
4509         /* CTL, MSCI control register
4510          *
4511          * 07..06  Reserved, set to 0
4512          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4513          * 04      IDLC, idle control, 0=mark 1=idle register
4514          * 03      BRK, break, 0=off 1 =on (async)
4515          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4516          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4517          * 00      RTS, RTS output control, 0=active 1=inactive
4518          *
4519          * 0001 0001
4520          */
4521         RegValue = 0x10;
4522         if (!(info->serial_signals & SerialSignal_RTS))
4523                 RegValue |= 0x01;
4524         write_reg(info, CTL, RegValue);
4525
4526         /* enable status interrupts */
4527         info->ie0_value |= TXINTE + RXINTE;
4528         write_reg(info, IE0, info->ie0_value);
4529
4530         /* enable break detect interrupt */
4531         info->ie1_value = BRKD;
4532         write_reg(info, IE1, info->ie1_value);
4533
4534         /* enable rx overrun interrupt */
4535         info->ie2_value = OVRN;
4536         write_reg(info, IE2, info->ie2_value);
4537
4538         set_rate( info, info->params.data_rate * 16 );
4539 }
4540
4541 /* Program the SCA for HDLC communications.
4542  */
4543 static void hdlc_mode(SLMP_INFO *info)
4544 {
4545         unsigned char RegValue;
4546         u32 DpllDivisor;
4547
4548         // Can't use DPLL because SCA outputs recovered clock on RxC when
4549         // DPLL mode selected. This causes output contention with RxC receiver.
4550         // Use of DPLL would require external hardware to disable RxC receiver
4551         // when DPLL mode selected.
4552         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4553
4554         /* disable DMA interrupts */
4555         write_reg(info, TXDMA + DIR, 0);
4556         write_reg(info, RXDMA + DIR, 0);
4557
4558         /* MD0, Mode Register 0
4559          *
4560          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4561          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4562          * 03      Reserved, must be 0
4563          * 02      CRCCC, CRC Calculation, 1=enabled
4564          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4565          * 00      CRC0, CRC initial value, 1 = all 1s
4566          *
4567          * 1000 0001
4568          */
4569         RegValue = 0x81;
4570         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4571                 RegValue |= BIT4;
4572         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4573                 RegValue |= BIT4;
4574         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4575                 RegValue |= BIT2 + BIT1;
4576         write_reg(info, MD0, RegValue);
4577
4578         /* MD1, Mode Register 1
4579          *
4580          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4581          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4582          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4583          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4584          *
4585          * 0000 0000
4586          */
4587         RegValue = 0x00;
4588         write_reg(info, MD1, RegValue);
4589
4590         /* MD2, Mode Register 2
4591          *
4592          * 07      NRZFM, 0=NRZ, 1=FM
4593          * 06..05  CODE<1..0> Encoding, 00=NRZ
4594          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4595          * 02      Reserved, must be 0
4596          * 01..00  CNCT<1..0> Channel connection, 0=normal
4597          *
4598          * 0000 0000
4599          */
4600         RegValue = 0x00;
4601         switch(info->params.encoding) {
4602         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4603         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4604         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4605         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4606 #if 0
4607         case HDLC_ENCODING_NRZB:                                        /* not supported */
4608         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4609         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4610 #endif
4611         }
4612         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4613                 DpllDivisor = 16;
4614                 RegValue |= BIT3;
4615         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4616                 DpllDivisor = 8;
4617         } else {
4618                 DpllDivisor = 32;
4619                 RegValue |= BIT4;
4620         }
4621         write_reg(info, MD2, RegValue);
4622
4623
4624         /* RXS, Receive clock source
4625          *
4626          * 07      Reserved, must be 0
4627          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4628          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4629          */
4630         RegValue=0;
4631         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4632                 RegValue |= BIT6;
4633         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4634                 RegValue |= BIT6 + BIT5;
4635         write_reg(info, RXS, RegValue);
4636
4637         /* TXS, Transmit clock source
4638          *
4639          * 07      Reserved, must be 0
4640          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4641          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4642          */
4643         RegValue=0;
4644         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4645                 RegValue |= BIT6;
4646         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4647                 RegValue |= BIT6 + BIT5;
4648         write_reg(info, TXS, RegValue);
4649
4650         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4651                 set_rate(info, info->params.clock_speed * DpllDivisor);
4652         else
4653                 set_rate(info, info->params.clock_speed);
4654
4655         /* GPDATA (General Purpose I/O Data Register)
4656          *
4657          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4658          */
4659         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4660                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4661         else
4662                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4663         write_control_reg(info);
4664
4665         /* RRC Receive Ready Control 0
4666          *
4667          * 07..05  Reserved, must be 0
4668          * 04..00  RRC<4..0> Rx FIFO trigger active
4669          */
4670         write_reg(info, RRC, rx_active_fifo_level);
4671
4672         /* TRC0 Transmit Ready Control 0
4673          *
4674          * 07..05  Reserved, must be 0
4675          * 04..00  TRC<4..0> Tx FIFO trigger active
4676          */
4677         write_reg(info, TRC0, tx_active_fifo_level);
4678
4679         /* TRC1 Transmit Ready Control 1
4680          *
4681          * 07..05  Reserved, must be 0
4682          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4683          */
4684         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4685
4686         /* DMR, DMA Mode Register
4687          *
4688          * 07..05  Reserved, must be 0
4689          * 04      TMOD, Transfer Mode: 1=chained-block
4690          * 03      Reserved, must be 0
4691          * 02      NF, Number of Frames: 1=multi-frame
4692          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4693          * 00      Reserved, must be 0
4694          *
4695          * 0001 0100
4696          */
4697         write_reg(info, TXDMA + DMR, 0x14);
4698         write_reg(info, RXDMA + DMR, 0x14);
4699
4700         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4701         write_reg(info, RXDMA + CPB,
4702                 (unsigned char)(info->buffer_list_phys >> 16));
4703
4704         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4705         write_reg(info, TXDMA + CPB,
4706                 (unsigned char)(info->buffer_list_phys >> 16));
4707
4708         /* enable status interrupts. other code enables/disables
4709          * the individual sources for these two interrupt classes.
4710          */
4711         info->ie0_value |= TXINTE + RXINTE;
4712         write_reg(info, IE0, info->ie0_value);
4713
4714         /* CTL, MSCI control register
4715          *
4716          * 07..06  Reserved, set to 0
4717          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4718          * 04      IDLC, idle control, 0=mark 1=idle register
4719          * 03      BRK, break, 0=off 1 =on (async)
4720          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4721          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4722          * 00      RTS, RTS output control, 0=active 1=inactive
4723          *
4724          * 0001 0001
4725          */
4726         RegValue = 0x10;
4727         if (!(info->serial_signals & SerialSignal_RTS))
4728                 RegValue |= 0x01;
4729         write_reg(info, CTL, RegValue);
4730
4731         /* preamble not supported ! */
4732
4733         tx_set_idle(info);
4734         tx_stop(info);
4735         rx_stop(info);
4736
4737         set_rate(info, info->params.clock_speed);
4738
4739         if (info->params.loopback)
4740                 enable_loopback(info,1);
4741 }
4742
4743 /* Set the transmit HDLC idle mode
4744  */
4745 static void tx_set_idle(SLMP_INFO *info)
4746 {
4747         unsigned char RegValue = 0xff;
4748
4749         /* Map API idle mode to SCA register bits */
4750         switch(info->idle_mode) {
4751         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4752         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4753         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4754         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4755         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4756         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4757         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4758         }
4759
4760         write_reg(info, IDL, RegValue);
4761 }
4762
4763 /* Query the adapter for the state of the V24 status (input) signals.
4764  */
4765 static void get_signals(SLMP_INFO *info)
4766 {
4767         u16 status = read_reg(info, SR3);
4768         u16 gpstatus = read_status_reg(info);
4769         u16 testbit;
4770
4771         /* clear all serial signals except DTR and RTS */
4772         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4773
4774         /* set serial signal bits to reflect MISR */
4775
4776         if (!(status & BIT3))
4777                 info->serial_signals |= SerialSignal_CTS;
4778
4779         if ( !(status & BIT2))
4780                 info->serial_signals |= SerialSignal_DCD;
4781
4782         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4783         if (!(gpstatus & testbit))
4784                 info->serial_signals |= SerialSignal_RI;
4785
4786         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4787         if (!(gpstatus & testbit))
4788                 info->serial_signals |= SerialSignal_DSR;
4789 }
4790
4791 /* Set the state of DTR and RTS based on contents of
4792  * serial_signals member of device context.
4793  */
4794 static void set_signals(SLMP_INFO *info)
4795 {
4796         unsigned char RegValue;
4797         u16 EnableBit;
4798
4799         RegValue = read_reg(info, CTL);
4800         if (info->serial_signals & SerialSignal_RTS)
4801                 RegValue &= ~BIT0;
4802         else
4803                 RegValue |= BIT0;
4804         write_reg(info, CTL, RegValue);
4805
4806         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4807         EnableBit = BIT1 << (info->port_num*2);
4808         if (info->serial_signals & SerialSignal_DTR)
4809                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4810         else
4811                 info->port_array[0]->ctrlreg_value |= EnableBit;
4812         write_control_reg(info);
4813 }
4814
4815 /*******************/
4816 /* DMA Buffer Code */
4817 /*******************/
4818
4819 /* Set the count for all receive buffers to SCABUFSIZE
4820  * and set the current buffer to the first buffer. This effectively
4821  * makes all buffers free and discards any data in buffers.
4822  */
4823 static void rx_reset_buffers(SLMP_INFO *info)
4824 {
4825         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4826 }
4827
4828 /* Free the buffers used by a received frame
4829  *
4830  * info   pointer to device instance data
4831  * first  index of 1st receive buffer of frame
4832  * last   index of last receive buffer of frame
4833  */
4834 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4835 {
4836         bool done = false;
4837
4838         while(!done) {
4839                 /* reset current buffer for reuse */
4840                 info->rx_buf_list[first].status = 0xff;
4841
4842                 if (first == last) {
4843                         done = true;
4844                         /* set new last rx descriptor address */
4845                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4846                 }
4847
4848                 first++;
4849                 if (first == info->rx_buf_count)
4850                         first = 0;
4851         }
4852
4853         /* set current buffer to next buffer after last buffer of frame */
4854         info->current_rx_buf = first;
4855 }
4856
4857 /* Return a received frame from the receive DMA buffers.
4858  * Only frames received without errors are returned.
4859  *
4860  * Return Value:        true if frame returned, otherwise false
4861  */
4862 static bool rx_get_frame(SLMP_INFO *info)
4863 {
4864         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4865         unsigned short status;
4866         unsigned int framesize = 0;
4867         bool ReturnCode = false;
4868         unsigned long flags;
4869         struct tty_struct *tty = info->tty;
4870         unsigned char addr_field = 0xff;
4871         SCADESC *desc;
4872         SCADESC_EX *desc_ex;
4873
4874 CheckAgain:
4875         /* assume no frame returned, set zero length */
4876         framesize = 0;
4877         addr_field = 0xff;
4878
4879         /*
4880          * current_rx_buf points to the 1st buffer of the next available
4881          * receive frame. To find the last buffer of the frame look for
4882          * a non-zero status field in the buffer entries. (The status
4883          * field is set by the 16C32 after completing a receive frame.
4884          */
4885         StartIndex = EndIndex = info->current_rx_buf;
4886
4887         for ( ;; ) {
4888                 desc = &info->rx_buf_list[EndIndex];
4889                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4890
4891                 if (desc->status == 0xff)
4892                         goto Cleanup;   /* current desc still in use, no frames available */
4893
4894                 if (framesize == 0 && info->params.addr_filter != 0xff)
4895                         addr_field = desc_ex->virt_addr[0];
4896
4897                 framesize += desc->length;
4898
4899                 /* Status != 0 means last buffer of frame */
4900                 if (desc->status)
4901                         break;
4902
4903                 EndIndex++;
4904                 if (EndIndex == info->rx_buf_count)
4905                         EndIndex = 0;
4906
4907                 if (EndIndex == info->current_rx_buf) {
4908                         /* all buffers have been 'used' but none mark      */
4909                         /* the end of a frame. Reset buffers and receiver. */
4910                         if ( info->rx_enabled ){
4911                                 spin_lock_irqsave(&info->lock,flags);
4912                                 rx_start(info);
4913                                 spin_unlock_irqrestore(&info->lock,flags);
4914                         }
4915                         goto Cleanup;
4916                 }
4917
4918         }
4919
4920         /* check status of receive frame */
4921
4922         /* frame status is byte stored after frame data
4923          *
4924          * 7 EOM (end of msg), 1 = last buffer of frame
4925          * 6 Short Frame, 1 = short frame
4926          * 5 Abort, 1 = frame aborted
4927          * 4 Residue, 1 = last byte is partial
4928          * 3 Overrun, 1 = overrun occurred during frame reception
4929          * 2 CRC,     1 = CRC error detected
4930          *
4931          */
4932         status = desc->status;
4933
4934         /* ignore CRC bit if not using CRC (bit is undefined) */
4935         /* Note:CRC is not save to data buffer */
4936         if (info->params.crc_type == HDLC_CRC_NONE)
4937                 status &= ~BIT2;
4938
4939         if (framesize == 0 ||
4940                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4941                 /* discard 0 byte frames, this seems to occur sometime
4942                  * when remote is idling flags.
4943                  */
4944                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4945                 goto CheckAgain;
4946         }
4947
4948         if (framesize < 2)
4949                 status |= BIT6;
4950
4951         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4952                 /* received frame has errors,
4953                  * update counts and mark frame size as 0
4954                  */
4955                 if (status & BIT6)
4956                         info->icount.rxshort++;
4957                 else if (status & BIT5)
4958                         info->icount.rxabort++;
4959                 else if (status & BIT3)
4960                         info->icount.rxover++;
4961                 else
4962                         info->icount.rxcrc++;
4963
4964                 framesize = 0;
4965 #if SYNCLINK_GENERIC_HDLC
4966                 {
4967                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4968                         stats->rx_errors++;
4969                         stats->rx_frame_errors++;
4970                 }
4971 #endif
4972         }
4973
4974         if ( debug_level >= DEBUG_LEVEL_BH )
4975                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4976                         __FILE__,__LINE__,info->device_name,status,framesize);
4977
4978         if ( debug_level >= DEBUG_LEVEL_DATA )
4979                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4980                         min_t(int, framesize,SCABUFSIZE),0);
4981
4982         if (framesize) {
4983                 if (framesize > info->max_frame_size)
4984                         info->icount.rxlong++;
4985                 else {
4986                         /* copy dma buffer(s) to contiguous intermediate buffer */
4987                         int copy_count = framesize;
4988                         int index = StartIndex;
4989                         unsigned char *ptmp = info->tmp_rx_buf;
4990                         info->tmp_rx_buf_count = framesize;
4991
4992                         info->icount.rxok++;
4993
4994                         while(copy_count) {
4995                                 int partial_count = min(copy_count,SCABUFSIZE);
4996                                 memcpy( ptmp,
4997                                         info->rx_buf_list_ex[index].virt_addr,
4998                                         partial_count );
4999                                 ptmp += partial_count;
5000                                 copy_count -= partial_count;
5001
5002                                 if ( ++index == info->rx_buf_count )
5003                                         index = 0;
5004                         }
5005
5006 #if SYNCLINK_GENERIC_HDLC
5007                         if (info->netcount)
5008                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5009                         else
5010 #endif
5011                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5012                                                   info->flag_buf, framesize);
5013                 }
5014         }
5015         /* Free the buffers used by this frame. */
5016         rx_free_frame_buffers( info, StartIndex, EndIndex );
5017
5018         ReturnCode = true;
5019
5020 Cleanup:
5021         if ( info->rx_enabled && info->rx_overflow ) {
5022                 /* Receiver is enabled, but needs to restarted due to
5023                  * rx buffer overflow. If buffers are empty, restart receiver.
5024                  */
5025                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5026                         spin_lock_irqsave(&info->lock,flags);
5027                         rx_start(info);
5028                         spin_unlock_irqrestore(&info->lock,flags);
5029                 }
5030         }
5031
5032         return ReturnCode;
5033 }
5034
5035 /* load the transmit DMA buffer with data
5036  */
5037 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5038 {
5039         unsigned short copy_count;
5040         unsigned int i = 0;
5041         SCADESC *desc;
5042         SCADESC_EX *desc_ex;
5043
5044         if ( debug_level >= DEBUG_LEVEL_DATA )
5045                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5046
5047         /* Copy source buffer to one or more DMA buffers, starting with
5048          * the first transmit dma buffer.
5049          */
5050         for(i=0;;)
5051         {
5052                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5053
5054                 desc = &info->tx_buf_list[i];
5055                 desc_ex = &info->tx_buf_list_ex[i];
5056
5057                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5058
5059                 desc->length = copy_count;
5060                 desc->status = 0;
5061
5062                 buf += copy_count;
5063                 count -= copy_count;
5064
5065                 if (!count)
5066                         break;
5067
5068                 i++;
5069                 if (i >= info->tx_buf_count)
5070                         i = 0;
5071         }
5072
5073         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5074         info->last_tx_buf = ++i;
5075 }
5076
5077 static bool register_test(SLMP_INFO *info)
5078 {
5079         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5080         static unsigned int count = ARRAY_SIZE(testval);
5081         unsigned int i;
5082         bool rc = true;
5083         unsigned long flags;
5084
5085         spin_lock_irqsave(&info->lock,flags);
5086         reset_port(info);
5087
5088         /* assume failure */
5089         info->init_error = DiagStatus_AddressFailure;
5090
5091         /* Write bit patterns to various registers but do it out of */
5092         /* sync, then read back and verify values. */
5093
5094         for (i = 0 ; i < count ; i++) {
5095                 write_reg(info, TMC, testval[i]);
5096                 write_reg(info, IDL, testval[(i+1)%count]);
5097                 write_reg(info, SA0, testval[(i+2)%count]);
5098                 write_reg(info, SA1, testval[(i+3)%count]);
5099
5100                 if ( (read_reg(info, TMC) != testval[i]) ||
5101                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5102                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5103                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5104                 {
5105                         rc = false;
5106                         break;
5107                 }
5108         }
5109
5110         reset_port(info);
5111         spin_unlock_irqrestore(&info->lock,flags);
5112
5113         return rc;
5114 }
5115
5116 static bool irq_test(SLMP_INFO *info)
5117 {
5118         unsigned long timeout;
5119         unsigned long flags;
5120
5121         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5122
5123         spin_lock_irqsave(&info->lock,flags);
5124         reset_port(info);
5125
5126         /* assume failure */
5127         info->init_error = DiagStatus_IrqFailure;
5128         info->irq_occurred = false;
5129
5130         /* setup timer0 on SCA0 to interrupt */
5131
5132         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5133         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5134
5135         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5136         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5137
5138
5139         /* TMCS, Timer Control/Status Register
5140          *
5141          * 07      CMF, Compare match flag (read only) 1=match
5142          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5143          * 05      Reserved, must be 0
5144          * 04      TME, Timer Enable
5145          * 03..00  Reserved, must be 0
5146          *
5147          * 0101 0000
5148          */
5149         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5150
5151         spin_unlock_irqrestore(&info->lock,flags);
5152
5153         timeout=100;
5154         while( timeout-- && !info->irq_occurred ) {
5155                 msleep_interruptible(10);
5156         }
5157
5158         spin_lock_irqsave(&info->lock,flags);
5159         reset_port(info);
5160         spin_unlock_irqrestore(&info->lock,flags);
5161
5162         return info->irq_occurred;
5163 }
5164
5165 /* initialize individual SCA device (2 ports)
5166  */
5167 static bool sca_init(SLMP_INFO *info)
5168 {
5169         /* set wait controller to single mem partition (low), no wait states */
5170         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5171         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5172         write_reg(info, WCRL, 0);       /* wait controller low range */
5173         write_reg(info, WCRM, 0);       /* wait controller mid range */
5174         write_reg(info, WCRH, 0);       /* wait controller high range */
5175
5176         /* DPCR, DMA Priority Control
5177          *
5178          * 07..05  Not used, must be 0
5179          * 04      BRC, bus release condition: 0=all transfers complete
5180          * 03      CCC, channel change condition: 0=every cycle
5181          * 02..00  PR<2..0>, priority 100=round robin
5182          *
5183          * 00000100 = 0x04
5184          */
5185         write_reg(info, DPCR, dma_priority);
5186
5187         /* DMA Master Enable, BIT7: 1=enable all channels */
5188         write_reg(info, DMER, 0x80);
5189
5190         /* enable all interrupt classes */
5191         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5192         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5193         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5194
5195         /* ITCR, interrupt control register
5196          * 07      IPC, interrupt priority, 0=MSCI->DMA
5197          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5198          * 04      VOS, Vector Output, 0=unmodified vector
5199          * 03..00  Reserved, must be 0
5200          */
5201         write_reg(info, ITCR, 0);
5202
5203         return true;
5204 }
5205
5206 /* initialize adapter hardware
5207  */
5208 static bool init_adapter(SLMP_INFO *info)
5209 {
5210         int i;
5211
5212         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5213         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5214         u32 readval;
5215
5216         info->misc_ctrl_value |= BIT30;
5217         *MiscCtrl = info->misc_ctrl_value;
5218
5219         /*
5220          * Force at least 170ns delay before clearing
5221          * reset bit. Each read from LCR takes at least
5222          * 30ns so 10 times for 300ns to be safe.
5223          */
5224         for(i=0;i<10;i++)
5225                 readval = *MiscCtrl;
5226
5227         info->misc_ctrl_value &= ~BIT30;
5228         *MiscCtrl = info->misc_ctrl_value;
5229
5230         /* init control reg (all DTRs off, all clksel=input) */
5231         info->ctrlreg_value = 0xaa;
5232         write_control_reg(info);
5233
5234         {
5235                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5236                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5237
5238                 switch(read_ahead_count)
5239                 {
5240                 case 16:
5241                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5242                         break;
5243                 case 8:
5244                         lcr1_brdr_value |= BIT5 + BIT4;
5245                         break;
5246                 case 4:
5247                         lcr1_brdr_value |= BIT5 + BIT3;
5248                         break;
5249                 case 0:
5250                         lcr1_brdr_value |= BIT5;
5251                         break;
5252                 }
5253
5254                 *LCR1BRDR = lcr1_brdr_value;
5255                 *MiscCtrl = misc_ctrl_value;
5256         }
5257
5258         sca_init(info->port_array[0]);
5259         sca_init(info->port_array[2]);
5260
5261         return true;
5262 }
5263
5264 /* Loopback an HDLC frame to test the hardware
5265  * interrupt and DMA functions.
5266  */
5267 static bool loopback_test(SLMP_INFO *info)
5268 {
5269 #define TESTFRAMESIZE 20
5270
5271         unsigned long timeout;
5272         u16 count = TESTFRAMESIZE;
5273         unsigned char buf[TESTFRAMESIZE];
5274         bool rc = false;
5275         unsigned long flags;
5276
5277         struct tty_struct *oldtty = info->tty;
5278         u32 speed = info->params.clock_speed;
5279
5280         info->params.clock_speed = 3686400;
5281         info->tty = NULL;
5282
5283         /* assume failure */
5284         info->init_error = DiagStatus_DmaFailure;
5285
5286         /* build and send transmit frame */
5287         for (count = 0; count < TESTFRAMESIZE;++count)
5288                 buf[count] = (unsigned char)count;
5289
5290         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5291
5292         /* program hardware for HDLC and enabled receiver */
5293         spin_lock_irqsave(&info->lock,flags);
5294         hdlc_mode(info);
5295         enable_loopback(info,1);
5296         rx_start(info);
5297         info->tx_count = count;
5298         tx_load_dma_buffer(info,buf,count);
5299         tx_start(info);
5300         spin_unlock_irqrestore(&info->lock,flags);
5301
5302         /* wait for receive complete */
5303         /* Set a timeout for waiting for interrupt. */
5304         for ( timeout = 100; timeout; --timeout ) {
5305                 msleep_interruptible(10);
5306
5307                 if (rx_get_frame(info)) {
5308                         rc = true;
5309                         break;
5310                 }
5311         }
5312
5313         /* verify received frame length and contents */
5314         if (rc &&
5315             ( info->tmp_rx_buf_count != count ||
5316               memcmp(buf, info->tmp_rx_buf,count))) {
5317                 rc = false;
5318         }
5319
5320         spin_lock_irqsave(&info->lock,flags);
5321         reset_adapter(info);
5322         spin_unlock_irqrestore(&info->lock,flags);
5323
5324         info->params.clock_speed = speed;
5325         info->tty = oldtty;
5326
5327         return rc;
5328 }
5329
5330 /* Perform diagnostics on hardware
5331  */
5332 static int adapter_test( SLMP_INFO *info )
5333 {
5334         unsigned long flags;
5335         if ( debug_level >= DEBUG_LEVEL_INFO )
5336                 printk( "%s(%d):Testing device %s\n",
5337                         __FILE__,__LINE__,info->device_name );
5338
5339         spin_lock_irqsave(&info->lock,flags);
5340         init_adapter(info);
5341         spin_unlock_irqrestore(&info->lock,flags);
5342
5343         info->port_array[0]->port_count = 0;
5344
5345         if ( register_test(info->port_array[0]) &&
5346                 register_test(info->port_array[1])) {
5347
5348                 info->port_array[0]->port_count = 2;
5349
5350                 if ( register_test(info->port_array[2]) &&
5351                         register_test(info->port_array[3]) )
5352                         info->port_array[0]->port_count += 2;
5353         }
5354         else {
5355                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5356                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5357                 return -ENODEV;
5358         }
5359
5360         if ( !irq_test(info->port_array[0]) ||
5361                 !irq_test(info->port_array[1]) ||
5362                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5363                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5364                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5365                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5366                 return -ENODEV;
5367         }
5368
5369         if (!loopback_test(info->port_array[0]) ||
5370                 !loopback_test(info->port_array[1]) ||
5371                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5372                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5373                 printk( "%s(%d):DMA test failure for device %s\n",
5374                         __FILE__,__LINE__,info->device_name);
5375                 return -ENODEV;
5376         }
5377
5378         if ( debug_level >= DEBUG_LEVEL_INFO )
5379                 printk( "%s(%d):device %s passed diagnostics\n",
5380                         __FILE__,__LINE__,info->device_name );
5381
5382         info->port_array[0]->init_error = 0;
5383         info->port_array[1]->init_error = 0;
5384         if ( info->port_count > 2 ) {
5385                 info->port_array[2]->init_error = 0;
5386                 info->port_array[3]->init_error = 0;
5387         }
5388
5389         return 0;
5390 }
5391
5392 /* Test the shared memory on a PCI adapter.
5393  */
5394 static bool memory_test(SLMP_INFO *info)
5395 {
5396         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5397                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5398         unsigned long count = ARRAY_SIZE(testval);
5399         unsigned long i;
5400         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5401         unsigned long * addr = (unsigned long *)info->memory_base;
5402
5403         /* Test data lines with test pattern at one location. */
5404
5405         for ( i = 0 ; i < count ; i++ ) {
5406                 *addr = testval[i];
5407                 if ( *addr != testval[i] )
5408                         return false;
5409         }
5410
5411         /* Test address lines with incrementing pattern over */
5412         /* entire address range. */
5413
5414         for ( i = 0 ; i < limit ; i++ ) {
5415                 *addr = i * 4;
5416                 addr++;
5417         }
5418
5419         addr = (unsigned long *)info->memory_base;
5420
5421         for ( i = 0 ; i < limit ; i++ ) {
5422                 if ( *addr != i * 4 )
5423                         return false;
5424                 addr++;
5425         }
5426
5427         memset( info->memory_base, 0, SCA_MEM_SIZE );
5428         return true;
5429 }
5430
5431 /* Load data into PCI adapter shared memory.
5432  *
5433  * The PCI9050 releases control of the local bus
5434  * after completing the current read or write operation.
5435  *
5436  * While the PCI9050 write FIFO not empty, the
5437  * PCI9050 treats all of the writes as a single transaction
5438  * and does not release the bus. This causes DMA latency problems
5439  * at high speeds when copying large data blocks to the shared memory.
5440  *
5441  * This function breaks a write into multiple transations by
5442  * interleaving a read which flushes the write FIFO and 'completes'
5443  * the write transation. This allows any pending DMA request to gain control
5444  * of the local bus in a timely fasion.
5445  */
5446 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5447 {
5448         /* A load interval of 16 allows for 4 32-bit writes at */
5449         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5450
5451         unsigned short interval = count / sca_pci_load_interval;
5452         unsigned short i;
5453
5454         for ( i = 0 ; i < interval ; i++ )
5455         {
5456                 memcpy(dest, src, sca_pci_load_interval);
5457                 read_status_reg(info);
5458                 dest += sca_pci_load_interval;
5459                 src += sca_pci_load_interval;
5460         }
5461
5462         memcpy(dest, src, count % sca_pci_load_interval);
5463 }
5464
5465 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5466 {
5467         int i;
5468         int linecount;
5469         if (xmit)
5470                 printk("%s tx data:\n",info->device_name);
5471         else
5472                 printk("%s rx data:\n",info->device_name);
5473
5474         while(count) {
5475                 if (count > 16)
5476                         linecount = 16;
5477                 else
5478                         linecount = count;
5479
5480                 for(i=0;i<linecount;i++)
5481                         printk("%02X ",(unsigned char)data[i]);
5482                 for(;i<17;i++)
5483                         printk("   ");
5484                 for(i=0;i<linecount;i++) {
5485                         if (data[i]>=040 && data[i]<=0176)
5486                                 printk("%c",data[i]);
5487                         else
5488                                 printk(".");
5489                 }
5490                 printk("\n");
5491
5492                 data  += linecount;
5493                 count -= linecount;
5494         }
5495 }       /* end of trace_block() */
5496
5497 /* called when HDLC frame times out
5498  * update stats and do tx completion processing
5499  */
5500 static void tx_timeout(unsigned long context)
5501 {
5502         SLMP_INFO *info = (SLMP_INFO*)context;
5503         unsigned long flags;
5504
5505         if ( debug_level >= DEBUG_LEVEL_INFO )
5506                 printk( "%s(%d):%s tx_timeout()\n",
5507                         __FILE__,__LINE__,info->device_name);
5508         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5509                 info->icount.txtimeout++;
5510         }
5511         spin_lock_irqsave(&info->lock,flags);
5512         info->tx_active = false;
5513         info->tx_count = info->tx_put = info->tx_get = 0;
5514
5515         spin_unlock_irqrestore(&info->lock,flags);
5516
5517 #if SYNCLINK_GENERIC_HDLC
5518         if (info->netcount)
5519                 hdlcdev_tx_done(info);
5520         else
5521 #endif
5522                 bh_transmit(info);
5523 }
5524
5525 /* called to periodically check the DSR/RI modem signal input status
5526  */
5527 static void status_timeout(unsigned long context)
5528 {
5529         u16 status = 0;
5530         SLMP_INFO *info = (SLMP_INFO*)context;
5531         unsigned long flags;
5532         unsigned char delta;
5533
5534
5535         spin_lock_irqsave(&info->lock,flags);
5536         get_signals(info);
5537         spin_unlock_irqrestore(&info->lock,flags);
5538
5539         /* check for DSR/RI state change */
5540
5541         delta = info->old_signals ^ info->serial_signals;
5542         info->old_signals = info->serial_signals;
5543
5544         if (delta & SerialSignal_DSR)
5545                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5546
5547         if (delta & SerialSignal_RI)
5548                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5549
5550         if (delta & SerialSignal_DCD)
5551                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5552
5553         if (delta & SerialSignal_CTS)
5554                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5555
5556         if (status)
5557                 isr_io_pin(info,status);
5558
5559         mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5560 }
5561
5562
5563 /* Register Access Routines -
5564  * All registers are memory mapped
5565  */
5566 #define CALC_REGADDR() \
5567         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5568         if (info->port_num > 1) \
5569                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5570         if ( info->port_num & 1) { \
5571                 if (Addr > 0x7f) \
5572                         RegAddr += 0x40;        /* DMA access */ \
5573                 else if (Addr > 0x1f && Addr < 0x60) \
5574                         RegAddr += 0x20;        /* MSCI access */ \
5575         }
5576
5577
5578 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5579 {
5580         CALC_REGADDR();
5581         return *RegAddr;
5582 }
5583 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5584 {
5585         CALC_REGADDR();
5586         *RegAddr = Value;
5587 }
5588
5589 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5590 {
5591         CALC_REGADDR();
5592         return *((u16 *)RegAddr);
5593 }
5594
5595 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5596 {
5597         CALC_REGADDR();
5598         *((u16 *)RegAddr) = Value;
5599 }
5600
5601 static unsigned char read_status_reg(SLMP_INFO * info)
5602 {
5603         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5604         return *RegAddr;
5605 }
5606
5607 static void write_control_reg(SLMP_INFO * info)
5608 {
5609         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5610         *RegAddr = info->port_array[0]->ctrlreg_value;
5611 }
5612
5613
5614 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5615                                           const struct pci_device_id *ent)
5616 {
5617         if (pci_enable_device(dev)) {
5618                 printk("error enabling pci device %p\n", dev);
5619                 return -EIO;
5620         }
5621         device_init( ++synclinkmp_adapter_count, dev );
5622         return 0;
5623 }
5624
5625 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5626 {
5627 }