2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
67 #define __apicdebuginit(type) static type __init
70 * Is the SiS APIC rmw bug present ?
71 * -1 = don't know, 0 = no, 1 = yes
73 int sis_apic_bug = -1;
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
79 * # of IRQ routing registers
81 int nr_ioapic_registers[MAX_IO_APICS];
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90 /* # of MP IRQ source entries */
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99 int skip_ioapic_setup;
101 void arch_disable_smp_support(void)
105 noioapicreroute = -1;
107 skip_ioapic_setup = 1;
110 static int __init parse_noapic(char *str)
112 /* disable IO-APIC */
113 arch_disable_smp_support();
116 early_param("noapic", parse_noapic);
121 * This is performance-critical, we want to do it O(1)
123 * the indexing order of this array favors 1:1 mappings
124 * between pins and IRQs.
127 struct irq_pin_list {
129 struct irq_pin_list *next;
132 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 struct irq_pin_list *pin;
136 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
142 struct irq_pin_list *irq_2_pin;
143 cpumask_var_t domain;
144 cpumask_var_t old_domain;
145 unsigned move_cleanup_count;
147 u8 move_in_progress : 1;
150 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
151 #ifdef CONFIG_SPARSE_IRQ
152 static struct irq_cfg irq_cfgx[] = {
154 static struct irq_cfg irq_cfgx[NR_IRQS] = {
156 [0] = { .vector = IRQ0_VECTOR, },
157 [1] = { .vector = IRQ1_VECTOR, },
158 [2] = { .vector = IRQ2_VECTOR, },
159 [3] = { .vector = IRQ3_VECTOR, },
160 [4] = { .vector = IRQ4_VECTOR, },
161 [5] = { .vector = IRQ5_VECTOR, },
162 [6] = { .vector = IRQ6_VECTOR, },
163 [7] = { .vector = IRQ7_VECTOR, },
164 [8] = { .vector = IRQ8_VECTOR, },
165 [9] = { .vector = IRQ9_VECTOR, },
166 [10] = { .vector = IRQ10_VECTOR, },
167 [11] = { .vector = IRQ11_VECTOR, },
168 [12] = { .vector = IRQ12_VECTOR, },
169 [13] = { .vector = IRQ13_VECTOR, },
170 [14] = { .vector = IRQ14_VECTOR, },
171 [15] = { .vector = IRQ15_VECTOR, },
174 int __init arch_early_irq_init(void)
177 struct irq_desc *desc;
182 count = ARRAY_SIZE(irq_cfgx);
184 for (i = 0; i < count; i++) {
185 desc = irq_to_desc(i);
186 desc->chip_data = &cfg[i];
187 alloc_bootmem_cpumask_var(&cfg[i].domain);
188 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
189 if (i < NR_IRQS_LEGACY)
190 cpumask_setall(cfg[i].domain);
196 #ifdef CONFIG_SPARSE_IRQ
197 static struct irq_cfg *irq_cfg(unsigned int irq)
199 struct irq_cfg *cfg = NULL;
200 struct irq_desc *desc;
202 desc = irq_to_desc(irq);
204 cfg = desc->chip_data;
209 static struct irq_cfg *get_one_free_irq_cfg(int node)
213 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
215 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
218 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
220 free_cpumask_var(cfg->domain);
224 cpumask_clear(cfg->domain);
225 cpumask_clear(cfg->old_domain);
232 int arch_init_chip_data(struct irq_desc *desc, int node)
236 cfg = desc->chip_data;
238 desc->chip_data = get_one_free_irq_cfg(node);
239 if (!desc->chip_data) {
240 printk(KERN_ERR "can not alloc irq_cfg\n");
248 /* for move_irq_desc */
250 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
252 struct irq_pin_list *old_entry, *head, *tail, *entry;
254 cfg->irq_2_pin = NULL;
255 old_entry = old_cfg->irq_2_pin;
259 entry = get_one_free_irq_2_pin(node);
263 entry->apic = old_entry->apic;
264 entry->pin = old_entry->pin;
267 old_entry = old_entry->next;
269 entry = get_one_free_irq_2_pin(node);
277 /* still use the old one */
280 entry->apic = old_entry->apic;
281 entry->pin = old_entry->pin;
284 old_entry = old_entry->next;
288 cfg->irq_2_pin = head;
291 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
293 struct irq_pin_list *entry, *next;
295 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
298 entry = old_cfg->irq_2_pin;
305 old_cfg->irq_2_pin = NULL;
308 void arch_init_copy_chip_data(struct irq_desc *old_desc,
309 struct irq_desc *desc, int node)
312 struct irq_cfg *old_cfg;
314 cfg = get_one_free_irq_cfg(node);
319 desc->chip_data = cfg;
321 old_cfg = old_desc->chip_data;
323 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
325 init_copy_irq_2_pin(old_cfg, cfg, node);
328 static void free_irq_cfg(struct irq_cfg *old_cfg)
333 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
335 struct irq_cfg *old_cfg, *cfg;
337 old_cfg = old_desc->chip_data;
338 cfg = desc->chip_data;
344 free_irq_2_pin(old_cfg, cfg);
345 free_irq_cfg(old_cfg);
346 old_desc->chip_data = NULL;
349 /* end for move_irq_desc */
352 static struct irq_cfg *irq_cfg(unsigned int irq)
354 return irq < nr_irqs ? irq_cfgx + irq : NULL;
361 unsigned int unused[3];
363 unsigned int unused2[11];
367 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
369 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
370 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
373 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
375 struct io_apic __iomem *io_apic = io_apic_base(apic);
376 writel(vector, &io_apic->eoi);
379 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
381 struct io_apic __iomem *io_apic = io_apic_base(apic);
382 writel(reg, &io_apic->index);
383 return readl(&io_apic->data);
386 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
388 struct io_apic __iomem *io_apic = io_apic_base(apic);
389 writel(reg, &io_apic->index);
390 writel(value, &io_apic->data);
394 * Re-write a value: to be used for read-modify-write
395 * cycles where the read already set up the index register.
397 * Older SiS APIC requires we rewrite the index register
399 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
401 struct io_apic __iomem *io_apic = io_apic_base(apic);
404 writel(reg, &io_apic->index);
405 writel(value, &io_apic->data);
408 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
410 struct irq_pin_list *entry;
413 spin_lock_irqsave(&ioapic_lock, flags);
414 entry = cfg->irq_2_pin;
422 reg = io_apic_read(entry->apic, 0x10 + pin*2);
423 /* Is the remote IRR bit set? */
424 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
425 spin_unlock_irqrestore(&ioapic_lock, flags);
432 spin_unlock_irqrestore(&ioapic_lock, flags);
438 struct { u32 w1, w2; };
439 struct IO_APIC_route_entry entry;
442 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
444 union entry_union eu;
446 spin_lock_irqsave(&ioapic_lock, flags);
447 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
448 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
449 spin_unlock_irqrestore(&ioapic_lock, flags);
454 * When we write a new IO APIC routing entry, we need to write the high
455 * word first! If the mask bit in the low word is clear, we will enable
456 * the interrupt, and we need to make sure the entry is fully populated
457 * before that happens.
460 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 union entry_union eu;
464 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
465 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
468 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
471 spin_lock_irqsave(&ioapic_lock, flags);
472 __ioapic_write_entry(apic, pin, e);
473 spin_unlock_irqrestore(&ioapic_lock, flags);
477 * When we mask an IO APIC routing entry, we need to write the low
478 * word first, in order to set the mask bit before we change the
481 static void ioapic_mask_entry(int apic, int pin)
484 union entry_union eu = { .entry.mask = 1 };
486 spin_lock_irqsave(&ioapic_lock, flags);
487 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
488 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
489 spin_unlock_irqrestore(&ioapic_lock, flags);
493 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
494 * shared ISA-space IRQs, so we have to support them. We are super
495 * fast in the common case, and fast for shared ISA-space IRQs.
497 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
499 struct irq_pin_list *entry;
501 entry = cfg->irq_2_pin;
503 entry = get_one_free_irq_2_pin(node);
505 printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
509 cfg->irq_2_pin = entry;
515 while (entry->next) {
516 /* not again, please */
517 if (entry->apic == apic && entry->pin == pin)
523 entry->next = get_one_free_irq_2_pin(node);
530 * Reroute an IRQ to a different pin.
532 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
533 int oldapic, int oldpin,
534 int newapic, int newpin)
536 struct irq_pin_list *entry = cfg->irq_2_pin;
540 if (entry->apic == oldapic && entry->pin == oldpin) {
541 entry->apic = newapic;
544 /* every one is different, right? */
550 /* why? call replace before add? */
552 add_pin_to_irq_node(cfg, node, newapic, newpin);
555 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
556 int mask_and, int mask_or,
557 void (*final)(struct irq_pin_list *entry))
560 struct irq_pin_list *entry;
562 for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
565 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
568 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
574 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
576 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
580 static void io_apic_sync(struct irq_pin_list *entry)
583 * Synchronize the IO-APIC and the CPU by doing
584 * a dummy read from the IO-APIC
586 struct io_apic __iomem *io_apic;
587 io_apic = io_apic_base(entry->apic);
588 readl(&io_apic->data);
591 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
593 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
595 #else /* CONFIG_X86_32 */
596 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
598 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
601 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
603 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
604 IO_APIC_REDIR_MASKED, NULL);
607 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
609 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
610 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
612 #endif /* CONFIG_X86_32 */
614 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
616 struct irq_cfg *cfg = desc->chip_data;
621 spin_lock_irqsave(&ioapic_lock, flags);
622 __mask_IO_APIC_irq(cfg);
623 spin_unlock_irqrestore(&ioapic_lock, flags);
626 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
628 struct irq_cfg *cfg = desc->chip_data;
631 spin_lock_irqsave(&ioapic_lock, flags);
632 __unmask_IO_APIC_irq(cfg);
633 spin_unlock_irqrestore(&ioapic_lock, flags);
636 static void mask_IO_APIC_irq(unsigned int irq)
638 struct irq_desc *desc = irq_to_desc(irq);
640 mask_IO_APIC_irq_desc(desc);
642 static void unmask_IO_APIC_irq(unsigned int irq)
644 struct irq_desc *desc = irq_to_desc(irq);
646 unmask_IO_APIC_irq_desc(desc);
649 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
651 struct IO_APIC_route_entry entry;
653 /* Check delivery_mode to be sure we're not clearing an SMI pin */
654 entry = ioapic_read_entry(apic, pin);
655 if (entry.delivery_mode == dest_SMI)
658 * Disable it in the IO-APIC irq-routing table:
660 ioapic_mask_entry(apic, pin);
663 static void clear_IO_APIC (void)
667 for (apic = 0; apic < nr_ioapics; apic++)
668 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
669 clear_IO_APIC_pin(apic, pin);
674 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
675 * specific CPU-side IRQs.
679 static int pirq_entries[MAX_PIRQS] = {
680 [0 ... MAX_PIRQS - 1] = -1
683 static int __init ioapic_pirq_setup(char *str)
686 int ints[MAX_PIRQS+1];
688 get_options(str, ARRAY_SIZE(ints), ints);
690 apic_printk(APIC_VERBOSE, KERN_INFO
691 "PIRQ redirection, working around broken MP-BIOS.\n");
693 if (ints[0] < MAX_PIRQS)
696 for (i = 0; i < max; i++) {
697 apic_printk(APIC_VERBOSE, KERN_DEBUG
698 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
700 * PIRQs are mapped upside down, usually.
702 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
707 __setup("pirq=", ioapic_pirq_setup);
708 #endif /* CONFIG_X86_32 */
710 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
713 struct IO_APIC_route_entry **ioapic_entries;
715 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
720 for (apic = 0; apic < nr_ioapics; apic++) {
721 ioapic_entries[apic] =
722 kzalloc(sizeof(struct IO_APIC_route_entry) *
723 nr_ioapic_registers[apic], GFP_ATOMIC);
724 if (!ioapic_entries[apic])
728 return ioapic_entries;
732 kfree(ioapic_entries[apic]);
733 kfree(ioapic_entries);
739 * Saves all the IO-APIC RTE's
741 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
748 for (apic = 0; apic < nr_ioapics; apic++) {
749 if (!ioapic_entries[apic])
752 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
753 ioapic_entries[apic][pin] =
754 ioapic_read_entry(apic, pin);
761 * Mask all IO APIC entries.
763 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
770 for (apic = 0; apic < nr_ioapics; apic++) {
771 if (!ioapic_entries[apic])
774 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
775 struct IO_APIC_route_entry entry;
777 entry = ioapic_entries[apic][pin];
780 ioapic_write_entry(apic, pin, entry);
787 * Restore IO APIC entries which was saved in ioapic_entries.
789 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
796 for (apic = 0; apic < nr_ioapics; apic++) {
797 if (!ioapic_entries[apic])
800 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
801 ioapic_write_entry(apic, pin,
802 ioapic_entries[apic][pin]);
807 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
811 for (apic = 0; apic < nr_ioapics; apic++)
812 kfree(ioapic_entries[apic]);
814 kfree(ioapic_entries);
818 * Find the IRQ entry number of a certain pin.
820 static int find_irq_entry(int apic, int pin, int type)
824 for (i = 0; i < mp_irq_entries; i++)
825 if (mp_irqs[i].irqtype == type &&
826 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
827 mp_irqs[i].dstapic == MP_APIC_ALL) &&
828 mp_irqs[i].dstirq == pin)
835 * Find the pin to which IRQ[irq] (ISA) is connected
837 static int __init find_isa_irq_pin(int irq, int type)
841 for (i = 0; i < mp_irq_entries; i++) {
842 int lbus = mp_irqs[i].srcbus;
844 if (test_bit(lbus, mp_bus_not_pci) &&
845 (mp_irqs[i].irqtype == type) &&
846 (mp_irqs[i].srcbusirq == irq))
848 return mp_irqs[i].dstirq;
853 static int __init find_isa_irq_apic(int irq, int type)
857 for (i = 0; i < mp_irq_entries; i++) {
858 int lbus = mp_irqs[i].srcbus;
860 if (test_bit(lbus, mp_bus_not_pci) &&
861 (mp_irqs[i].irqtype == type) &&
862 (mp_irqs[i].srcbusirq == irq))
865 if (i < mp_irq_entries) {
867 for(apic = 0; apic < nr_ioapics; apic++) {
868 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
877 * Find a specific PCI IRQ entry.
878 * Not an __init, possibly needed by modules
880 static int pin_2_irq(int idx, int apic, int pin);
882 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
884 int apic, i, best_guess = -1;
886 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
888 if (test_bit(bus, mp_bus_not_pci)) {
889 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
892 for (i = 0; i < mp_irq_entries; i++) {
893 int lbus = mp_irqs[i].srcbus;
895 for (apic = 0; apic < nr_ioapics; apic++)
896 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
897 mp_irqs[i].dstapic == MP_APIC_ALL)
900 if (!test_bit(lbus, mp_bus_not_pci) &&
901 !mp_irqs[i].irqtype &&
903 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
904 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
906 if (!(apic || IO_APIC_IRQ(irq)))
909 if (pin == (mp_irqs[i].srcbusirq & 3))
912 * Use the first all-but-pin matching entry as a
913 * best-guess fuzzy result for broken mptables.
922 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
924 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
926 * EISA Edge/Level control register, ELCR
928 static int EISA_ELCR(unsigned int irq)
930 if (irq < NR_IRQS_LEGACY) {
931 unsigned int port = 0x4d0 + (irq >> 3);
932 return (inb(port) >> (irq & 7)) & 1;
934 apic_printk(APIC_VERBOSE, KERN_INFO
935 "Broken MPtable reports ISA irq %d\n", irq);
941 /* ISA interrupts are always polarity zero edge triggered,
942 * when listed as conforming in the MP table. */
944 #define default_ISA_trigger(idx) (0)
945 #define default_ISA_polarity(idx) (0)
947 /* EISA interrupts are always polarity zero and can be edge or level
948 * trigger depending on the ELCR value. If an interrupt is listed as
949 * EISA conforming in the MP table, that means its trigger type must
950 * be read in from the ELCR */
952 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
953 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
955 /* PCI interrupts are always polarity one level triggered,
956 * when listed as conforming in the MP table. */
958 #define default_PCI_trigger(idx) (1)
959 #define default_PCI_polarity(idx) (1)
961 /* MCA interrupts are always polarity zero level triggered,
962 * when listed as conforming in the MP table. */
964 #define default_MCA_trigger(idx) (1)
965 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
967 static int MPBIOS_polarity(int idx)
969 int bus = mp_irqs[idx].srcbus;
973 * Determine IRQ line polarity (high active or low active):
975 switch (mp_irqs[idx].irqflag & 3)
977 case 0: /* conforms, ie. bus-type dependent polarity */
978 if (test_bit(bus, mp_bus_not_pci))
979 polarity = default_ISA_polarity(idx);
981 polarity = default_PCI_polarity(idx);
983 case 1: /* high active */
988 case 2: /* reserved */
990 printk(KERN_WARNING "broken BIOS!!\n");
994 case 3: /* low active */
999 default: /* invalid */
1001 printk(KERN_WARNING "broken BIOS!!\n");
1009 static int MPBIOS_trigger(int idx)
1011 int bus = mp_irqs[idx].srcbus;
1015 * Determine IRQ trigger mode (edge or level sensitive):
1017 switch ((mp_irqs[idx].irqflag>>2) & 3)
1019 case 0: /* conforms, ie. bus-type dependent */
1020 if (test_bit(bus, mp_bus_not_pci))
1021 trigger = default_ISA_trigger(idx);
1023 trigger = default_PCI_trigger(idx);
1024 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1025 switch (mp_bus_id_to_type[bus]) {
1026 case MP_BUS_ISA: /* ISA pin */
1028 /* set before the switch */
1031 case MP_BUS_EISA: /* EISA pin */
1033 trigger = default_EISA_trigger(idx);
1036 case MP_BUS_PCI: /* PCI pin */
1038 /* set before the switch */
1041 case MP_BUS_MCA: /* MCA pin */
1043 trigger = default_MCA_trigger(idx);
1048 printk(KERN_WARNING "broken BIOS!!\n");
1060 case 2: /* reserved */
1062 printk(KERN_WARNING "broken BIOS!!\n");
1071 default: /* invalid */
1073 printk(KERN_WARNING "broken BIOS!!\n");
1081 static inline int irq_polarity(int idx)
1083 return MPBIOS_polarity(idx);
1086 static inline int irq_trigger(int idx)
1088 return MPBIOS_trigger(idx);
1091 int (*ioapic_renumber_irq)(int ioapic, int irq);
1092 static int pin_2_irq(int idx, int apic, int pin)
1095 int bus = mp_irqs[idx].srcbus;
1098 * Debugging check, we are in big trouble if this message pops up!
1100 if (mp_irqs[idx].dstirq != pin)
1101 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1103 if (test_bit(bus, mp_bus_not_pci)) {
1104 irq = mp_irqs[idx].srcbusirq;
1107 * PCI IRQs are mapped in order
1111 irq += nr_ioapic_registers[i++];
1114 * For MPS mode, so far only needed by ES7000 platform
1116 if (ioapic_renumber_irq)
1117 irq = ioapic_renumber_irq(apic, irq);
1120 #ifdef CONFIG_X86_32
1122 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1124 if ((pin >= 16) && (pin <= 23)) {
1125 if (pirq_entries[pin-16] != -1) {
1126 if (!pirq_entries[pin-16]) {
1127 apic_printk(APIC_VERBOSE, KERN_DEBUG
1128 "disabling PIRQ%d\n", pin-16);
1130 irq = pirq_entries[pin-16];
1131 apic_printk(APIC_VERBOSE, KERN_DEBUG
1132 "using PIRQ%d -> IRQ %d\n",
1142 void lock_vector_lock(void)
1144 /* Used to the online set of cpus does not change
1145 * during assign_irq_vector.
1147 spin_lock(&vector_lock);
1150 void unlock_vector_lock(void)
1152 spin_unlock(&vector_lock);
1156 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1159 * NOTE! The local APIC isn't very good at handling
1160 * multiple interrupts at the same interrupt level.
1161 * As the interrupt level is determined by taking the
1162 * vector number and shifting that right by 4, we
1163 * want to spread these out a bit so that they don't
1164 * all fall in the same interrupt level.
1166 * Also, we've got to be careful not to trash gate
1167 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1169 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1170 unsigned int old_vector;
1172 cpumask_var_t tmp_mask;
1174 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1177 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1180 old_vector = cfg->vector;
1182 cpumask_and(tmp_mask, mask, cpu_online_mask);
1183 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1184 if (!cpumask_empty(tmp_mask)) {
1185 free_cpumask_var(tmp_mask);
1190 /* Only try and allocate irqs on cpus that are present */
1192 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1196 apic->vector_allocation_domain(cpu, tmp_mask);
1198 vector = current_vector;
1199 offset = current_offset;
1202 if (vector >= first_system_vector) {
1203 /* If out of vectors on large boxen, must share them. */
1204 offset = (offset + 1) % 8;
1205 vector = FIRST_DEVICE_VECTOR + offset;
1207 if (unlikely(current_vector == vector))
1210 if (test_bit(vector, used_vectors))
1213 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1214 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1217 current_vector = vector;
1218 current_offset = offset;
1220 cfg->move_in_progress = 1;
1221 cpumask_copy(cfg->old_domain, cfg->domain);
1223 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1224 per_cpu(vector_irq, new_cpu)[vector] = irq;
1225 cfg->vector = vector;
1226 cpumask_copy(cfg->domain, tmp_mask);
1230 free_cpumask_var(tmp_mask);
1235 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1238 unsigned long flags;
1240 spin_lock_irqsave(&vector_lock, flags);
1241 err = __assign_irq_vector(irq, cfg, mask);
1242 spin_unlock_irqrestore(&vector_lock, flags);
1246 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1250 BUG_ON(!cfg->vector);
1252 vector = cfg->vector;
1253 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1254 per_cpu(vector_irq, cpu)[vector] = -1;
1257 cpumask_clear(cfg->domain);
1259 if (likely(!cfg->move_in_progress))
1261 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1262 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1264 if (per_cpu(vector_irq, cpu)[vector] != irq)
1266 per_cpu(vector_irq, cpu)[vector] = -1;
1270 cfg->move_in_progress = 0;
1273 void __setup_vector_irq(int cpu)
1275 /* Initialize vector_irq on a new cpu */
1276 /* This function must be called with vector_lock held */
1278 struct irq_cfg *cfg;
1279 struct irq_desc *desc;
1281 /* Mark the inuse vectors */
1282 for_each_irq_desc(irq, desc) {
1283 cfg = desc->chip_data;
1284 if (!cpumask_test_cpu(cpu, cfg->domain))
1286 vector = cfg->vector;
1287 per_cpu(vector_irq, cpu)[vector] = irq;
1289 /* Mark the free vectors */
1290 for (vector = 0; vector < NR_VECTORS; ++vector) {
1291 irq = per_cpu(vector_irq, cpu)[vector];
1296 if (!cpumask_test_cpu(cpu, cfg->domain))
1297 per_cpu(vector_irq, cpu)[vector] = -1;
1301 static struct irq_chip ioapic_chip;
1302 static struct irq_chip ir_ioapic_chip;
1304 #define IOAPIC_AUTO -1
1305 #define IOAPIC_EDGE 0
1306 #define IOAPIC_LEVEL 1
1308 #ifdef CONFIG_X86_32
1309 static inline int IO_APIC_irq_trigger(int irq)
1313 for (apic = 0; apic < nr_ioapics; apic++) {
1314 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1315 idx = find_irq_entry(apic, pin, mp_INT);
1316 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1317 return irq_trigger(idx);
1321 * nonexistent IRQs are edge default
1326 static inline int IO_APIC_irq_trigger(int irq)
1332 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1335 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1336 trigger == IOAPIC_LEVEL)
1337 desc->status |= IRQ_LEVEL;
1339 desc->status &= ~IRQ_LEVEL;
1341 if (irq_remapped(irq)) {
1342 desc->status |= IRQ_MOVE_PCNTXT;
1344 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1348 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1349 handle_edge_irq, "edge");
1353 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1354 trigger == IOAPIC_LEVEL)
1355 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1359 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1360 handle_edge_irq, "edge");
1363 int setup_ioapic_entry(int apic_id, int irq,
1364 struct IO_APIC_route_entry *entry,
1365 unsigned int destination, int trigger,
1366 int polarity, int vector, int pin)
1369 * add it to the IO-APIC irq-routing table:
1371 memset(entry,0,sizeof(*entry));
1373 if (intr_remapping_enabled) {
1374 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1376 struct IR_IO_APIC_route_entry *ir_entry =
1377 (struct IR_IO_APIC_route_entry *) entry;
1381 panic("No mapping iommu for ioapic %d\n", apic_id);
1383 index = alloc_irte(iommu, irq, 1);
1385 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1387 memset(&irte, 0, sizeof(irte));
1390 irte.dst_mode = apic->irq_dest_mode;
1392 * Trigger mode in the IRTE will always be edge, and the
1393 * actual level or edge trigger will be setup in the IO-APIC
1394 * RTE. This will help simplify level triggered irq migration.
1395 * For more details, see the comments above explainig IO-APIC
1396 * irq migration in the presence of interrupt-remapping.
1398 irte.trigger_mode = 0;
1399 irte.dlvry_mode = apic->irq_delivery_mode;
1400 irte.vector = vector;
1401 irte.dest_id = IRTE_DEST(destination);
1403 modify_irte(irq, &irte);
1405 ir_entry->index2 = (index >> 15) & 0x1;
1407 ir_entry->format = 1;
1408 ir_entry->index = (index & 0x7fff);
1410 * IO-APIC RTE will be configured with virtual vector.
1411 * irq handler will do the explicit EOI to the io-apic.
1413 ir_entry->vector = pin;
1415 entry->delivery_mode = apic->irq_delivery_mode;
1416 entry->dest_mode = apic->irq_dest_mode;
1417 entry->dest = destination;
1418 entry->vector = vector;
1421 entry->mask = 0; /* enable IRQ */
1422 entry->trigger = trigger;
1423 entry->polarity = polarity;
1425 /* Mask level triggered irqs.
1426 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1433 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1434 int trigger, int polarity)
1436 struct irq_cfg *cfg;
1437 struct IO_APIC_route_entry entry;
1440 if (!IO_APIC_IRQ(irq))
1443 cfg = desc->chip_data;
1445 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1448 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1450 apic_printk(APIC_VERBOSE,KERN_DEBUG
1451 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1452 "IRQ %d Mode:%i Active:%i)\n",
1453 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1454 irq, trigger, polarity);
1457 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1458 dest, trigger, polarity, cfg->vector, pin)) {
1459 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1460 mp_ioapics[apic_id].apicid, pin);
1461 __clear_irq_vector(irq, cfg);
1465 ioapic_register_intr(irq, desc, trigger);
1466 if (irq < NR_IRQS_LEGACY)
1467 disable_8259A_irq(irq);
1469 ioapic_write_entry(apic_id, pin, entry);
1472 static void __init setup_IO_APIC_irqs(void)
1474 int apic_id, pin, idx, irq;
1476 struct irq_desc *desc;
1477 struct irq_cfg *cfg;
1478 int node = cpu_to_node(boot_cpu_id);
1480 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1482 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1483 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1485 idx = find_irq_entry(apic_id, pin, mp_INT);
1489 apic_printk(APIC_VERBOSE,
1490 KERN_DEBUG " %d-%d",
1491 mp_ioapics[apic_id].apicid, pin);
1493 apic_printk(APIC_VERBOSE, " %d-%d",
1494 mp_ioapics[apic_id].apicid, pin);
1498 apic_printk(APIC_VERBOSE,
1499 " (apicid-pin) not connected\n");
1503 irq = pin_2_irq(idx, apic_id, pin);
1506 * Skip the timer IRQ if there's a quirk handler
1507 * installed and if it returns 1:
1509 if (apic->multi_timer_check &&
1510 apic->multi_timer_check(apic_id, irq))
1513 desc = irq_to_desc_alloc_node(irq, node);
1515 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1518 cfg = desc->chip_data;
1519 add_pin_to_irq_node(cfg, node, apic_id, pin);
1521 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1522 irq_trigger(idx), irq_polarity(idx));
1527 apic_printk(APIC_VERBOSE,
1528 " (apicid-pin) not connected\n");
1532 * Set up the timer pin, possibly with the 8259A-master behind.
1534 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1537 struct IO_APIC_route_entry entry;
1539 if (intr_remapping_enabled)
1542 memset(&entry, 0, sizeof(entry));
1545 * We use logical delivery to get the timer IRQ
1548 entry.dest_mode = apic->irq_dest_mode;
1549 entry.mask = 0; /* don't mask IRQ for edge */
1550 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1551 entry.delivery_mode = apic->irq_delivery_mode;
1554 entry.vector = vector;
1557 * The timer IRQ doesn't have to know that behind the
1558 * scene we may have a 8259A-master in AEOI mode ...
1560 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1563 * Add it to the IO-APIC irq-routing table:
1565 ioapic_write_entry(apic_id, pin, entry);
1569 __apicdebuginit(void) print_IO_APIC(void)
1572 union IO_APIC_reg_00 reg_00;
1573 union IO_APIC_reg_01 reg_01;
1574 union IO_APIC_reg_02 reg_02;
1575 union IO_APIC_reg_03 reg_03;
1576 unsigned long flags;
1577 struct irq_cfg *cfg;
1578 struct irq_desc *desc;
1581 if (apic_verbosity == APIC_QUIET)
1584 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1585 for (i = 0; i < nr_ioapics; i++)
1586 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1587 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1590 * We are a bit conservative about what we expect. We have to
1591 * know about every hardware change ASAP.
1593 printk(KERN_INFO "testing the IO APIC.......................\n");
1595 for (apic = 0; apic < nr_ioapics; apic++) {
1597 spin_lock_irqsave(&ioapic_lock, flags);
1598 reg_00.raw = io_apic_read(apic, 0);
1599 reg_01.raw = io_apic_read(apic, 1);
1600 if (reg_01.bits.version >= 0x10)
1601 reg_02.raw = io_apic_read(apic, 2);
1602 if (reg_01.bits.version >= 0x20)
1603 reg_03.raw = io_apic_read(apic, 3);
1604 spin_unlock_irqrestore(&ioapic_lock, flags);
1607 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1608 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1609 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1610 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1611 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1613 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1614 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1616 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1617 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1620 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1621 * but the value of reg_02 is read as the previous read register
1622 * value, so ignore it if reg_02 == reg_01.
1624 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1625 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1626 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1630 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1631 * or reg_03, but the value of reg_0[23] is read as the previous read
1632 * register value, so ignore it if reg_03 == reg_0[12].
1634 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1635 reg_03.raw != reg_01.raw) {
1636 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1637 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1640 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1642 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1643 " Stat Dmod Deli Vect: \n");
1645 for (i = 0; i <= reg_01.bits.entries; i++) {
1646 struct IO_APIC_route_entry entry;
1648 entry = ioapic_read_entry(apic, i);
1650 printk(KERN_DEBUG " %02x %03X ",
1655 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1660 entry.delivery_status,
1662 entry.delivery_mode,
1667 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1668 for_each_irq_desc(irq, desc) {
1669 struct irq_pin_list *entry;
1671 cfg = desc->chip_data;
1672 entry = cfg->irq_2_pin;
1675 printk(KERN_DEBUG "IRQ%d ", irq);
1677 printk("-> %d:%d", entry->apic, entry->pin);
1680 entry = entry->next;
1685 printk(KERN_INFO ".................................... done.\n");
1690 __apicdebuginit(void) print_APIC_bitfield(int base)
1695 if (apic_verbosity == APIC_QUIET)
1698 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1699 for (i = 0; i < 8; i++) {
1700 v = apic_read(base + i*0x10);
1701 for (j = 0; j < 32; j++) {
1711 __apicdebuginit(void) print_local_APIC(void *dummy)
1713 unsigned int v, ver, maxlvt;
1716 if (apic_verbosity == APIC_QUIET)
1719 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1720 smp_processor_id(), hard_smp_processor_id());
1721 v = apic_read(APIC_ID);
1722 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1723 v = apic_read(APIC_LVR);
1724 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1725 ver = GET_APIC_VERSION(v);
1726 maxlvt = lapic_get_maxlvt();
1728 v = apic_read(APIC_TASKPRI);
1729 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1731 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1732 if (!APIC_XAPIC(ver)) {
1733 v = apic_read(APIC_ARBPRI);
1734 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1735 v & APIC_ARBPRI_MASK);
1737 v = apic_read(APIC_PROCPRI);
1738 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1742 * Remote read supported only in the 82489DX and local APIC for
1743 * Pentium processors.
1745 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1746 v = apic_read(APIC_RRR);
1747 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1750 v = apic_read(APIC_LDR);
1751 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1752 if (!x2apic_enabled()) {
1753 v = apic_read(APIC_DFR);
1754 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1756 v = apic_read(APIC_SPIV);
1757 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1759 printk(KERN_DEBUG "... APIC ISR field:\n");
1760 print_APIC_bitfield(APIC_ISR);
1761 printk(KERN_DEBUG "... APIC TMR field:\n");
1762 print_APIC_bitfield(APIC_TMR);
1763 printk(KERN_DEBUG "... APIC IRR field:\n");
1764 print_APIC_bitfield(APIC_IRR);
1766 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1767 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1768 apic_write(APIC_ESR, 0);
1770 v = apic_read(APIC_ESR);
1771 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1774 icr = apic_icr_read();
1775 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1776 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1778 v = apic_read(APIC_LVTT);
1779 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1781 if (maxlvt > 3) { /* PC is LVT#4. */
1782 v = apic_read(APIC_LVTPC);
1783 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1785 v = apic_read(APIC_LVT0);
1786 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1787 v = apic_read(APIC_LVT1);
1788 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1790 if (maxlvt > 2) { /* ERR is LVT#3. */
1791 v = apic_read(APIC_LVTERR);
1792 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1795 v = apic_read(APIC_TMICT);
1796 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1797 v = apic_read(APIC_TMCCT);
1798 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1799 v = apic_read(APIC_TDCR);
1800 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1804 __apicdebuginit(void) print_all_local_APICs(void)
1809 for_each_online_cpu(cpu)
1810 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1814 __apicdebuginit(void) print_PIC(void)
1817 unsigned long flags;
1819 if (apic_verbosity == APIC_QUIET)
1822 printk(KERN_DEBUG "\nprinting PIC contents\n");
1824 spin_lock_irqsave(&i8259A_lock, flags);
1826 v = inb(0xa1) << 8 | inb(0x21);
1827 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1829 v = inb(0xa0) << 8 | inb(0x20);
1830 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1834 v = inb(0xa0) << 8 | inb(0x20);
1838 spin_unlock_irqrestore(&i8259A_lock, flags);
1840 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1842 v = inb(0x4d1) << 8 | inb(0x4d0);
1843 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1846 __apicdebuginit(int) print_all_ICs(void)
1849 print_all_local_APICs();
1855 fs_initcall(print_all_ICs);
1858 /* Where if anywhere is the i8259 connect in external int mode */
1859 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1861 void __init enable_IO_APIC(void)
1863 union IO_APIC_reg_01 reg_01;
1864 int i8259_apic, i8259_pin;
1866 unsigned long flags;
1869 * The number of IO-APIC IRQ registers (== #pins):
1871 for (apic = 0; apic < nr_ioapics; apic++) {
1872 spin_lock_irqsave(&ioapic_lock, flags);
1873 reg_01.raw = io_apic_read(apic, 1);
1874 spin_unlock_irqrestore(&ioapic_lock, flags);
1875 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1877 for(apic = 0; apic < nr_ioapics; apic++) {
1879 /* See if any of the pins is in ExtINT mode */
1880 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1881 struct IO_APIC_route_entry entry;
1882 entry = ioapic_read_entry(apic, pin);
1884 /* If the interrupt line is enabled and in ExtInt mode
1885 * I have found the pin where the i8259 is connected.
1887 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1888 ioapic_i8259.apic = apic;
1889 ioapic_i8259.pin = pin;
1895 /* Look to see what if the MP table has reported the ExtINT */
1896 /* If we could not find the appropriate pin by looking at the ioapic
1897 * the i8259 probably is not connected the ioapic but give the
1898 * mptable a chance anyway.
1900 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1901 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1902 /* Trust the MP table if nothing is setup in the hardware */
1903 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1904 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1905 ioapic_i8259.pin = i8259_pin;
1906 ioapic_i8259.apic = i8259_apic;
1908 /* Complain if the MP table and the hardware disagree */
1909 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1910 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1912 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1916 * Do not trust the IO-APIC being empty at bootup
1922 * Not an __init, needed by the reboot code
1924 void disable_IO_APIC(void)
1927 * Clear the IO-APIC before rebooting:
1932 * If the i8259 is routed through an IOAPIC
1933 * Put that IOAPIC in virtual wire mode
1934 * so legacy interrupts can be delivered.
1936 * With interrupt-remapping, for now we will use virtual wire A mode,
1937 * as virtual wire B is little complex (need to configure both
1938 * IOAPIC RTE aswell as interrupt-remapping table entry).
1939 * As this gets called during crash dump, keep this simple for now.
1941 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1942 struct IO_APIC_route_entry entry;
1944 memset(&entry, 0, sizeof(entry));
1945 entry.mask = 0; /* Enabled */
1946 entry.trigger = 0; /* Edge */
1948 entry.polarity = 0; /* High */
1949 entry.delivery_status = 0;
1950 entry.dest_mode = 0; /* Physical */
1951 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1953 entry.dest = read_apic_id();
1956 * Add it to the IO-APIC irq-routing table:
1958 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1962 * Use virtual wire A mode when interrupt remapping is enabled.
1964 disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
1967 #ifdef CONFIG_X86_32
1969 * function to set the IO-APIC physical IDs based on the
1970 * values stored in the MPC table.
1972 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1975 static void __init setup_ioapic_ids_from_mpc(void)
1977 union IO_APIC_reg_00 reg_00;
1978 physid_mask_t phys_id_present_map;
1981 unsigned char old_id;
1982 unsigned long flags;
1984 if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
1988 * Don't check I/O APIC IDs for xAPIC systems. They have
1989 * no meaning without the serial APIC bus.
1991 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1992 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1995 * This is broken; anything with a real cpu count has to
1996 * circumvent this idiocy regardless.
1998 phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2001 * Set the IOAPIC ID to the value stored in the MPC table.
2003 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2005 /* Read the register 0 value */
2006 spin_lock_irqsave(&ioapic_lock, flags);
2007 reg_00.raw = io_apic_read(apic_id, 0);
2008 spin_unlock_irqrestore(&ioapic_lock, flags);
2010 old_id = mp_ioapics[apic_id].apicid;
2012 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2013 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2014 apic_id, mp_ioapics[apic_id].apicid);
2015 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2017 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2021 * Sanity check, is the ID really free? Every APIC in a
2022 * system must have a unique ID or we get lots of nice
2023 * 'stuck on smp_invalidate_needed IPI wait' messages.
2025 if (apic->check_apicid_used(phys_id_present_map,
2026 mp_ioapics[apic_id].apicid)) {
2027 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2028 apic_id, mp_ioapics[apic_id].apicid);
2029 for (i = 0; i < get_physical_broadcast(); i++)
2030 if (!physid_isset(i, phys_id_present_map))
2032 if (i >= get_physical_broadcast())
2033 panic("Max APIC ID exceeded!\n");
2034 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2036 physid_set(i, phys_id_present_map);
2037 mp_ioapics[apic_id].apicid = i;
2040 tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2041 apic_printk(APIC_VERBOSE, "Setting %d in the "
2042 "phys_id_present_map\n",
2043 mp_ioapics[apic_id].apicid);
2044 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2049 * We need to adjust the IRQ routing table
2050 * if the ID changed.
2052 if (old_id != mp_ioapics[apic_id].apicid)
2053 for (i = 0; i < mp_irq_entries; i++)
2054 if (mp_irqs[i].dstapic == old_id)
2056 = mp_ioapics[apic_id].apicid;
2059 * Read the right value from the MPC table and
2060 * write it into the ID register.
2062 apic_printk(APIC_VERBOSE, KERN_INFO
2063 "...changing IO-APIC physical APIC ID to %d ...",
2064 mp_ioapics[apic_id].apicid);
2066 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2067 spin_lock_irqsave(&ioapic_lock, flags);
2068 io_apic_write(apic_id, 0, reg_00.raw);
2069 spin_unlock_irqrestore(&ioapic_lock, flags);
2074 spin_lock_irqsave(&ioapic_lock, flags);
2075 reg_00.raw = io_apic_read(apic_id, 0);
2076 spin_unlock_irqrestore(&ioapic_lock, flags);
2077 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2078 printk("could not set ID!\n");
2080 apic_printk(APIC_VERBOSE, " ok.\n");
2085 int no_timer_check __initdata;
2087 static int __init notimercheck(char *s)
2092 __setup("no_timer_check", notimercheck);
2095 * There is a nasty bug in some older SMP boards, their mptable lies
2096 * about the timer IRQ. We do the following to work around the situation:
2098 * - timer IRQ defaults to IO-APIC IRQ
2099 * - if this function detects that timer IRQs are defunct, then we fall
2100 * back to ISA timer IRQs
2102 static int __init timer_irq_works(void)
2104 unsigned long t1 = jiffies;
2105 unsigned long flags;
2110 local_save_flags(flags);
2112 /* Let ten ticks pass... */
2113 mdelay((10 * 1000) / HZ);
2114 local_irq_restore(flags);
2117 * Expect a few ticks at least, to be sure some possible
2118 * glue logic does not lock up after one or two first
2119 * ticks in a non-ExtINT mode. Also the local APIC
2120 * might have cached one ExtINT interrupt. Finally, at
2121 * least one tick may be lost due to delays.
2125 if (time_after(jiffies, t1 + 4))
2131 * In the SMP+IOAPIC case it might happen that there are an unspecified
2132 * number of pending IRQ events unhandled. These cases are very rare,
2133 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2134 * better to do it this way as thus we do not have to be aware of
2135 * 'pending' interrupts in the IRQ path, except at this point.
2138 * Edge triggered needs to resend any interrupt
2139 * that was delayed but this is now handled in the device
2144 * Starting up a edge-triggered IO-APIC interrupt is
2145 * nasty - we need to make sure that we get the edge.
2146 * If it is already asserted for some reason, we need
2147 * return 1 to indicate that is was pending.
2149 * This is not complete - we should be able to fake
2150 * an edge even if it isn't on the 8259A...
2153 static unsigned int startup_ioapic_irq(unsigned int irq)
2155 int was_pending = 0;
2156 unsigned long flags;
2157 struct irq_cfg *cfg;
2159 spin_lock_irqsave(&ioapic_lock, flags);
2160 if (irq < NR_IRQS_LEGACY) {
2161 disable_8259A_irq(irq);
2162 if (i8259A_irq_pending(irq))
2166 __unmask_IO_APIC_irq(cfg);
2167 spin_unlock_irqrestore(&ioapic_lock, flags);
2172 #ifdef CONFIG_X86_64
2173 static int ioapic_retrigger_irq(unsigned int irq)
2176 struct irq_cfg *cfg = irq_cfg(irq);
2177 unsigned long flags;
2179 spin_lock_irqsave(&vector_lock, flags);
2180 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2181 spin_unlock_irqrestore(&vector_lock, flags);
2186 static int ioapic_retrigger_irq(unsigned int irq)
2188 apic->send_IPI_self(irq_cfg(irq)->vector);
2195 * Level and edge triggered IO-APIC interrupts need different handling,
2196 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2197 * handled with the level-triggered descriptor, but that one has slightly
2198 * more overhead. Level-triggered interrupts cannot be handled with the
2199 * edge-triggered handler, without risking IRQ storms and other ugly
2204 static void send_cleanup_vector(struct irq_cfg *cfg)
2206 cpumask_var_t cleanup_mask;
2208 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2210 cfg->move_cleanup_count = 0;
2211 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2212 cfg->move_cleanup_count++;
2213 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2214 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2216 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2217 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2218 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2219 free_cpumask_var(cleanup_mask);
2221 cfg->move_in_progress = 0;
2224 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2227 struct irq_pin_list *entry;
2228 u8 vector = cfg->vector;
2230 entry = cfg->irq_2_pin;
2240 * With interrupt-remapping, destination information comes
2241 * from interrupt-remapping table entry.
2243 if (!irq_remapped(irq))
2244 io_apic_write(apic, 0x11 + pin*2, dest);
2245 reg = io_apic_read(apic, 0x10 + pin*2);
2246 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2248 io_apic_modify(apic, 0x10 + pin*2, reg);
2251 entry = entry->next;
2256 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2259 * Either sets desc->affinity to a valid value, and returns
2260 * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2261 * leaves desc->affinity untouched.
2264 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2266 struct irq_cfg *cfg;
2269 if (!cpumask_intersects(mask, cpu_online_mask))
2273 cfg = desc->chip_data;
2274 if (assign_irq_vector(irq, cfg, mask))
2277 cpumask_copy(desc->affinity, mask);
2279 return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2283 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2285 struct irq_cfg *cfg;
2286 unsigned long flags;
2292 cfg = desc->chip_data;
2294 spin_lock_irqsave(&ioapic_lock, flags);
2295 dest = set_desc_affinity(desc, mask);
2296 if (dest != BAD_APICID) {
2297 /* Only the high 8 bits are valid. */
2298 dest = SET_APIC_LOGICAL_ID(dest);
2299 __target_IO_APIC_irq(irq, dest, cfg);
2302 spin_unlock_irqrestore(&ioapic_lock, flags);
2308 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2310 struct irq_desc *desc;
2312 desc = irq_to_desc(irq);
2314 return set_ioapic_affinity_irq_desc(desc, mask);
2317 #ifdef CONFIG_INTR_REMAP
2320 * Migrate the IO-APIC irq in the presence of intr-remapping.
2322 * For both level and edge triggered, irq migration is a simple atomic
2323 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2325 * For level triggered, we eliminate the io-apic RTE modification (with the
2326 * updated vector information), by using a virtual vector (io-apic pin number).
2327 * Real vector that is used for interrupting cpu will be coming from
2328 * the interrupt-remapping table entry.
2331 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2333 struct irq_cfg *cfg;
2339 if (!cpumask_intersects(mask, cpu_online_mask))
2343 if (get_irte(irq, &irte))
2346 cfg = desc->chip_data;
2347 if (assign_irq_vector(irq, cfg, mask))
2350 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2352 irte.vector = cfg->vector;
2353 irte.dest_id = IRTE_DEST(dest);
2356 * Modified the IRTE and flushes the Interrupt entry cache.
2358 modify_irte(irq, &irte);
2360 if (cfg->move_in_progress)
2361 send_cleanup_vector(cfg);
2363 cpumask_copy(desc->affinity, mask);
2369 * Migrates the IRQ destination in the process context.
2371 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2372 const struct cpumask *mask)
2374 return migrate_ioapic_irq_desc(desc, mask);
2376 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2377 const struct cpumask *mask)
2379 struct irq_desc *desc = irq_to_desc(irq);
2381 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2384 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2385 const struct cpumask *mask)
2391 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2393 unsigned vector, me;
2399 me = smp_processor_id();
2400 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2403 struct irq_desc *desc;
2404 struct irq_cfg *cfg;
2405 irq = __get_cpu_var(vector_irq)[vector];
2410 desc = irq_to_desc(irq);
2415 spin_lock(&desc->lock);
2416 if (!cfg->move_cleanup_count)
2419 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2422 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2424 * Check if the vector that needs to be cleanedup is
2425 * registered at the cpu's IRR. If so, then this is not
2426 * the best time to clean it up. Lets clean it up in the
2427 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2430 if (irr & (1 << (vector % 32))) {
2431 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2434 __get_cpu_var(vector_irq)[vector] = -1;
2435 cfg->move_cleanup_count--;
2437 spin_unlock(&desc->lock);
2443 static void irq_complete_move(struct irq_desc **descp)
2445 struct irq_desc *desc = *descp;
2446 struct irq_cfg *cfg = desc->chip_data;
2447 unsigned vector, me;
2449 if (likely(!cfg->move_in_progress))
2452 vector = ~get_irq_regs()->orig_ax;
2453 me = smp_processor_id();
2455 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2456 send_cleanup_vector(cfg);
2459 static inline void irq_complete_move(struct irq_desc **descp) {}
2462 static void ack_apic_edge(unsigned int irq)
2464 struct irq_desc *desc = irq_to_desc(irq);
2466 irq_complete_move(&desc);
2467 move_native_irq(irq);
2471 atomic_t irq_mis_count;
2473 static void ack_apic_level(unsigned int irq)
2475 struct irq_desc *desc = irq_to_desc(irq);
2477 #ifdef CONFIG_X86_32
2481 struct irq_cfg *cfg;
2482 int do_unmask_irq = 0;
2484 irq_complete_move(&desc);
2485 #ifdef CONFIG_GENERIC_PENDING_IRQ
2486 /* If we are moving the irq we need to mask it */
2487 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2489 mask_IO_APIC_irq_desc(desc);
2493 #ifdef CONFIG_X86_32
2495 * It appears there is an erratum which affects at least version 0x11
2496 * of I/O APIC (that's the 82093AA and cores integrated into various
2497 * chipsets). Under certain conditions a level-triggered interrupt is
2498 * erroneously delivered as edge-triggered one but the respective IRR
2499 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2500 * message but it will never arrive and further interrupts are blocked
2501 * from the source. The exact reason is so far unknown, but the
2502 * phenomenon was observed when two consecutive interrupt requests
2503 * from a given source get delivered to the same CPU and the source is
2504 * temporarily disabled in between.
2506 * A workaround is to simulate an EOI message manually. We achieve it
2507 * by setting the trigger mode to edge and then to level when the edge
2508 * trigger mode gets detected in the TMR of a local APIC for a
2509 * level-triggered interrupt. We mask the source for the time of the
2510 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2511 * The idea is from Manfred Spraul. --macro
2513 cfg = desc->chip_data;
2516 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2520 * We must acknowledge the irq before we move it or the acknowledge will
2521 * not propagate properly.
2525 /* Now we can move and renable the irq */
2526 if (unlikely(do_unmask_irq)) {
2527 /* Only migrate the irq if the ack has been received.
2529 * On rare occasions the broadcast level triggered ack gets
2530 * delayed going to ioapics, and if we reprogram the
2531 * vector while Remote IRR is still set the irq will never
2534 * To prevent this scenario we read the Remote IRR bit
2535 * of the ioapic. This has two effects.
2536 * - On any sane system the read of the ioapic will
2537 * flush writes (and acks) going to the ioapic from
2539 * - We get to see if the ACK has actually been delivered.
2541 * Based on failed experiments of reprogramming the
2542 * ioapic entry from outside of irq context starting
2543 * with masking the ioapic entry and then polling until
2544 * Remote IRR was clear before reprogramming the
2545 * ioapic I don't trust the Remote IRR bit to be
2546 * completey accurate.
2548 * However there appears to be no other way to plug
2549 * this race, so if the Remote IRR bit is not
2550 * accurate and is causing problems then it is a hardware bug
2551 * and you can go talk to the chipset vendor about it.
2553 cfg = desc->chip_data;
2554 if (!io_apic_level_ack_pending(cfg))
2555 move_masked_irq(irq);
2556 unmask_IO_APIC_irq_desc(desc);
2559 #ifdef CONFIG_X86_32
2560 if (!(v & (1 << (i & 0x1f)))) {
2561 atomic_inc(&irq_mis_count);
2562 spin_lock(&ioapic_lock);
2563 __mask_and_edge_IO_APIC_irq(cfg);
2564 __unmask_and_level_IO_APIC_irq(cfg);
2565 spin_unlock(&ioapic_lock);
2570 #ifdef CONFIG_INTR_REMAP
2571 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2574 struct irq_pin_list *entry;
2576 entry = cfg->irq_2_pin;
2584 io_apic_eoi(apic, pin);
2585 entry = entry->next;
2590 eoi_ioapic_irq(struct irq_desc *desc)
2592 struct irq_cfg *cfg;
2593 unsigned long flags;
2597 cfg = desc->chip_data;
2599 spin_lock_irqsave(&ioapic_lock, flags);
2600 __eoi_ioapic_irq(irq, cfg);
2601 spin_unlock_irqrestore(&ioapic_lock, flags);
2604 static void ir_ack_apic_edge(unsigned int irq)
2609 static void ir_ack_apic_level(unsigned int irq)
2611 struct irq_desc *desc = irq_to_desc(irq);
2614 eoi_ioapic_irq(desc);
2616 #endif /* CONFIG_INTR_REMAP */
2618 static struct irq_chip ioapic_chip __read_mostly = {
2620 .startup = startup_ioapic_irq,
2621 .mask = mask_IO_APIC_irq,
2622 .unmask = unmask_IO_APIC_irq,
2623 .ack = ack_apic_edge,
2624 .eoi = ack_apic_level,
2626 .set_affinity = set_ioapic_affinity_irq,
2628 .retrigger = ioapic_retrigger_irq,
2631 static struct irq_chip ir_ioapic_chip __read_mostly = {
2632 .name = "IR-IO-APIC",
2633 .startup = startup_ioapic_irq,
2634 .mask = mask_IO_APIC_irq,
2635 .unmask = unmask_IO_APIC_irq,
2636 #ifdef CONFIG_INTR_REMAP
2637 .ack = ir_ack_apic_edge,
2638 .eoi = ir_ack_apic_level,
2640 .set_affinity = set_ir_ioapic_affinity_irq,
2643 .retrigger = ioapic_retrigger_irq,
2646 static inline void init_IO_APIC_traps(void)
2649 struct irq_desc *desc;
2650 struct irq_cfg *cfg;
2653 * NOTE! The local APIC isn't very good at handling
2654 * multiple interrupts at the same interrupt level.
2655 * As the interrupt level is determined by taking the
2656 * vector number and shifting that right by 4, we
2657 * want to spread these out a bit so that they don't
2658 * all fall in the same interrupt level.
2660 * Also, we've got to be careful not to trash gate
2661 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2663 for_each_irq_desc(irq, desc) {
2664 cfg = desc->chip_data;
2665 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2667 * Hmm.. We don't have an entry for this,
2668 * so default to an old-fashioned 8259
2669 * interrupt if we can..
2671 if (irq < NR_IRQS_LEGACY)
2672 make_8259A_irq(irq);
2674 /* Strange. Oh, well.. */
2675 desc->chip = &no_irq_chip;
2681 * The local APIC irq-chip implementation:
2684 static void mask_lapic_irq(unsigned int irq)
2688 v = apic_read(APIC_LVT0);
2689 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2692 static void unmask_lapic_irq(unsigned int irq)
2696 v = apic_read(APIC_LVT0);
2697 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2700 static void ack_lapic_irq(unsigned int irq)
2705 static struct irq_chip lapic_chip __read_mostly = {
2706 .name = "local-APIC",
2707 .mask = mask_lapic_irq,
2708 .unmask = unmask_lapic_irq,
2709 .ack = ack_lapic_irq,
2712 static void lapic_register_intr(int irq, struct irq_desc *desc)
2714 desc->status &= ~IRQ_LEVEL;
2715 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2719 static void __init setup_nmi(void)
2722 * Dirty trick to enable the NMI watchdog ...
2723 * We put the 8259A master into AEOI mode and
2724 * unmask on all local APICs LVT0 as NMI.
2726 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2727 * is from Maciej W. Rozycki - so we do not have to EOI from
2728 * the NMI handler or the timer interrupt.
2730 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2732 enable_NMI_through_LVT0();
2734 apic_printk(APIC_VERBOSE, " done.\n");
2738 * This looks a bit hackish but it's about the only one way of sending
2739 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2740 * not support the ExtINT mode, unfortunately. We need to send these
2741 * cycles as some i82489DX-based boards have glue logic that keeps the
2742 * 8259A interrupt line asserted until INTA. --macro
2744 static inline void __init unlock_ExtINT_logic(void)
2747 struct IO_APIC_route_entry entry0, entry1;
2748 unsigned char save_control, save_freq_select;
2750 pin = find_isa_irq_pin(8, mp_INT);
2755 apic = find_isa_irq_apic(8, mp_INT);
2761 entry0 = ioapic_read_entry(apic, pin);
2762 clear_IO_APIC_pin(apic, pin);
2764 memset(&entry1, 0, sizeof(entry1));
2766 entry1.dest_mode = 0; /* physical delivery */
2767 entry1.mask = 0; /* unmask IRQ now */
2768 entry1.dest = hard_smp_processor_id();
2769 entry1.delivery_mode = dest_ExtINT;
2770 entry1.polarity = entry0.polarity;
2774 ioapic_write_entry(apic, pin, entry1);
2776 save_control = CMOS_READ(RTC_CONTROL);
2777 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2778 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2780 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2785 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2789 CMOS_WRITE(save_control, RTC_CONTROL);
2790 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2791 clear_IO_APIC_pin(apic, pin);
2793 ioapic_write_entry(apic, pin, entry0);
2796 static int disable_timer_pin_1 __initdata;
2797 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2798 static int __init disable_timer_pin_setup(char *arg)
2800 disable_timer_pin_1 = 1;
2803 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2805 int timer_through_8259 __initdata;
2808 * This code may look a bit paranoid, but it's supposed to cooperate with
2809 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2810 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2811 * fanatically on his truly buggy board.
2813 * FIXME: really need to revamp this for all platforms.
2815 static inline void __init check_timer(void)
2817 struct irq_desc *desc = irq_to_desc(0);
2818 struct irq_cfg *cfg = desc->chip_data;
2819 int node = cpu_to_node(boot_cpu_id);
2820 int apic1, pin1, apic2, pin2;
2821 unsigned long flags;
2824 local_irq_save(flags);
2827 * get/set the timer IRQ vector:
2829 disable_8259A_irq(0);
2830 assign_irq_vector(0, cfg, apic->target_cpus());
2833 * As IRQ0 is to be enabled in the 8259A, the virtual
2834 * wire has to be disabled in the local APIC. Also
2835 * timer interrupts need to be acknowledged manually in
2836 * the 8259A for the i82489DX when using the NMI
2837 * watchdog as that APIC treats NMIs as level-triggered.
2838 * The AEOI mode will finish them in the 8259A
2841 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2843 #ifdef CONFIG_X86_32
2847 ver = apic_read(APIC_LVR);
2848 ver = GET_APIC_VERSION(ver);
2849 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2853 pin1 = find_isa_irq_pin(0, mp_INT);
2854 apic1 = find_isa_irq_apic(0, mp_INT);
2855 pin2 = ioapic_i8259.pin;
2856 apic2 = ioapic_i8259.apic;
2858 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2859 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2860 cfg->vector, apic1, pin1, apic2, pin2);
2863 * Some BIOS writers are clueless and report the ExtINTA
2864 * I/O APIC input from the cascaded 8259A as the timer
2865 * interrupt input. So just in case, if only one pin
2866 * was found above, try it both directly and through the
2870 if (intr_remapping_enabled)
2871 panic("BIOS bug: timer not connected to IO-APIC");
2875 } else if (pin2 == -1) {
2882 * Ok, does IRQ0 through the IOAPIC work?
2885 add_pin_to_irq_node(cfg, node, apic1, pin1);
2886 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2888 /* for edge trigger, setup_IO_APIC_irq already
2889 * leave it unmasked.
2890 * so only need to unmask if it is level-trigger
2891 * do we really have level trigger timer?
2894 idx = find_irq_entry(apic1, pin1, mp_INT);
2895 if (idx != -1 && irq_trigger(idx))
2896 unmask_IO_APIC_irq_desc(desc);
2898 if (timer_irq_works()) {
2899 if (nmi_watchdog == NMI_IO_APIC) {
2901 enable_8259A_irq(0);
2903 if (disable_timer_pin_1 > 0)
2904 clear_IO_APIC_pin(0, pin1);
2907 if (intr_remapping_enabled)
2908 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2909 local_irq_disable();
2910 clear_IO_APIC_pin(apic1, pin1);
2912 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2913 "8254 timer not connected to IO-APIC\n");
2915 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2916 "(IRQ0) through the 8259A ...\n");
2917 apic_printk(APIC_QUIET, KERN_INFO
2918 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2920 * legacy devices should be connected to IO APIC #0
2922 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2923 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2924 enable_8259A_irq(0);
2925 if (timer_irq_works()) {
2926 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2927 timer_through_8259 = 1;
2928 if (nmi_watchdog == NMI_IO_APIC) {
2929 disable_8259A_irq(0);
2931 enable_8259A_irq(0);
2936 * Cleanup, just in case ...
2938 local_irq_disable();
2939 disable_8259A_irq(0);
2940 clear_IO_APIC_pin(apic2, pin2);
2941 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2944 if (nmi_watchdog == NMI_IO_APIC) {
2945 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2946 "through the IO-APIC - disabling NMI Watchdog!\n");
2947 nmi_watchdog = NMI_NONE;
2949 #ifdef CONFIG_X86_32
2953 apic_printk(APIC_QUIET, KERN_INFO
2954 "...trying to set up timer as Virtual Wire IRQ...\n");
2956 lapic_register_intr(0, desc);
2957 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2958 enable_8259A_irq(0);
2960 if (timer_irq_works()) {
2961 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2964 local_irq_disable();
2965 disable_8259A_irq(0);
2966 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2967 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2969 apic_printk(APIC_QUIET, KERN_INFO
2970 "...trying to set up timer as ExtINT IRQ...\n");
2974 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2976 unlock_ExtINT_logic();
2978 if (timer_irq_works()) {
2979 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2982 local_irq_disable();
2983 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2984 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2985 "report. Then try booting with the 'noapic' option.\n");
2987 local_irq_restore(flags);
2991 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2992 * to devices. However there may be an I/O APIC pin available for
2993 * this interrupt regardless. The pin may be left unconnected, but
2994 * typically it will be reused as an ExtINT cascade interrupt for
2995 * the master 8259A. In the MPS case such a pin will normally be
2996 * reported as an ExtINT interrupt in the MP table. With ACPI
2997 * there is no provision for ExtINT interrupts, and in the absence
2998 * of an override it would be treated as an ordinary ISA I/O APIC
2999 * interrupt, that is edge-triggered and unmasked by default. We
3000 * used to do this, but it caused problems on some systems because
3001 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3002 * the same ExtINT cascade interrupt to drive the local APIC of the
3003 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3004 * the I/O APIC in all cases now. No actual device should request
3005 * it anyway. --macro
3007 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3009 void __init setup_IO_APIC(void)
3013 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3016 io_apic_irqs = ~PIC_IRQS;
3018 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3020 * Set up IO-APIC IRQ routing.
3022 #ifdef CONFIG_X86_32
3024 setup_ioapic_ids_from_mpc();
3027 setup_IO_APIC_irqs();
3028 init_IO_APIC_traps();
3033 * Called after all the initialization is done. If we didnt find any
3034 * APIC bugs then we can allow the modify fast path
3037 static int __init io_apic_bug_finalize(void)
3039 if (sis_apic_bug == -1)
3044 late_initcall(io_apic_bug_finalize);
3046 struct sysfs_ioapic_data {
3047 struct sys_device dev;
3048 struct IO_APIC_route_entry entry[0];
3050 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3052 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3054 struct IO_APIC_route_entry *entry;
3055 struct sysfs_ioapic_data *data;
3058 data = container_of(dev, struct sysfs_ioapic_data, dev);
3059 entry = data->entry;
3060 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3061 *entry = ioapic_read_entry(dev->id, i);
3066 static int ioapic_resume(struct sys_device *dev)
3068 struct IO_APIC_route_entry *entry;
3069 struct sysfs_ioapic_data *data;
3070 unsigned long flags;
3071 union IO_APIC_reg_00 reg_00;
3074 data = container_of(dev, struct sysfs_ioapic_data, dev);
3075 entry = data->entry;
3077 spin_lock_irqsave(&ioapic_lock, flags);
3078 reg_00.raw = io_apic_read(dev->id, 0);
3079 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3080 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3081 io_apic_write(dev->id, 0, reg_00.raw);
3083 spin_unlock_irqrestore(&ioapic_lock, flags);
3084 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3085 ioapic_write_entry(dev->id, i, entry[i]);
3090 static struct sysdev_class ioapic_sysdev_class = {
3092 .suspend = ioapic_suspend,
3093 .resume = ioapic_resume,
3096 static int __init ioapic_init_sysfs(void)
3098 struct sys_device * dev;
3101 error = sysdev_class_register(&ioapic_sysdev_class);
3105 for (i = 0; i < nr_ioapics; i++ ) {
3106 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3107 * sizeof(struct IO_APIC_route_entry);
3108 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3109 if (!mp_ioapic_data[i]) {
3110 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3113 dev = &mp_ioapic_data[i]->dev;
3115 dev->cls = &ioapic_sysdev_class;
3116 error = sysdev_register(dev);
3118 kfree(mp_ioapic_data[i]);
3119 mp_ioapic_data[i] = NULL;
3120 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3128 device_initcall(ioapic_init_sysfs);
3130 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3132 * Dynamic irq allocate and deallocation
3134 unsigned int create_irq_nr(unsigned int irq_want, int node)
3136 /* Allocate an unused irq */
3139 unsigned long flags;
3140 struct irq_cfg *cfg_new = NULL;
3141 struct irq_desc *desc_new = NULL;
3144 if (irq_want < nr_irqs_gsi)
3145 irq_want = nr_irqs_gsi;
3147 spin_lock_irqsave(&vector_lock, flags);
3148 for (new = irq_want; new < nr_irqs; new++) {
3149 desc_new = irq_to_desc_alloc_node(new, node);
3151 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3154 cfg_new = desc_new->chip_data;
3156 if (cfg_new->vector != 0)
3159 desc_new = move_irq_desc(desc_new, node);
3161 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3165 spin_unlock_irqrestore(&vector_lock, flags);
3168 dynamic_irq_init(irq);
3169 /* restore it, in case dynamic_irq_init clear it */
3171 desc_new->chip_data = cfg_new;
3176 int create_irq(void)
3178 int node = cpu_to_node(boot_cpu_id);
3179 unsigned int irq_want;
3182 irq_want = nr_irqs_gsi;
3183 irq = create_irq_nr(irq_want, node);
3191 void destroy_irq(unsigned int irq)
3193 unsigned long flags;
3194 struct irq_cfg *cfg;
3195 struct irq_desc *desc;
3197 /* store it, in case dynamic_irq_cleanup clear it */
3198 desc = irq_to_desc(irq);
3199 cfg = desc->chip_data;
3200 dynamic_irq_cleanup(irq);
3201 /* connect back irq_cfg */
3203 desc->chip_data = cfg;
3206 spin_lock_irqsave(&vector_lock, flags);
3207 __clear_irq_vector(irq, cfg);
3208 spin_unlock_irqrestore(&vector_lock, flags);
3212 * MSI message composition
3214 #ifdef CONFIG_PCI_MSI
3215 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3217 struct irq_cfg *cfg;
3225 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3229 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3231 if (irq_remapped(irq)) {
3236 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3237 BUG_ON(ir_index == -1);
3239 memset (&irte, 0, sizeof(irte));
3242 irte.dst_mode = apic->irq_dest_mode;
3243 irte.trigger_mode = 0; /* edge */
3244 irte.dlvry_mode = apic->irq_delivery_mode;
3245 irte.vector = cfg->vector;
3246 irte.dest_id = IRTE_DEST(dest);
3248 modify_irte(irq, &irte);
3250 msg->address_hi = MSI_ADDR_BASE_HI;
3251 msg->data = sub_handle;
3252 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3254 MSI_ADDR_IR_INDEX1(ir_index) |
3255 MSI_ADDR_IR_INDEX2(ir_index);
3257 if (x2apic_enabled())
3258 msg->address_hi = MSI_ADDR_BASE_HI |
3259 MSI_ADDR_EXT_DEST_ID(dest);
3261 msg->address_hi = MSI_ADDR_BASE_HI;
3265 ((apic->irq_dest_mode == 0) ?
3266 MSI_ADDR_DEST_MODE_PHYSICAL:
3267 MSI_ADDR_DEST_MODE_LOGICAL) |
3268 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3269 MSI_ADDR_REDIRECTION_CPU:
3270 MSI_ADDR_REDIRECTION_LOWPRI) |
3271 MSI_ADDR_DEST_ID(dest);
3274 MSI_DATA_TRIGGER_EDGE |
3275 MSI_DATA_LEVEL_ASSERT |
3276 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3277 MSI_DATA_DELIVERY_FIXED:
3278 MSI_DATA_DELIVERY_LOWPRI) |
3279 MSI_DATA_VECTOR(cfg->vector);
3285 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3287 struct irq_desc *desc = irq_to_desc(irq);
3288 struct irq_cfg *cfg;
3292 dest = set_desc_affinity(desc, mask);
3293 if (dest == BAD_APICID)
3296 cfg = desc->chip_data;
3298 read_msi_msg_desc(desc, &msg);
3300 msg.data &= ~MSI_DATA_VECTOR_MASK;
3301 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3302 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3303 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3305 write_msi_msg_desc(desc, &msg);
3309 #ifdef CONFIG_INTR_REMAP
3311 * Migrate the MSI irq to another cpumask. This migration is
3312 * done in the process context using interrupt-remapping hardware.
3315 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3317 struct irq_desc *desc = irq_to_desc(irq);
3318 struct irq_cfg *cfg = desc->chip_data;
3322 if (get_irte(irq, &irte))
3325 dest = set_desc_affinity(desc, mask);
3326 if (dest == BAD_APICID)
3329 irte.vector = cfg->vector;
3330 irte.dest_id = IRTE_DEST(dest);
3333 * atomically update the IRTE with the new destination and vector.
3335 modify_irte(irq, &irte);
3338 * After this point, all the interrupts will start arriving
3339 * at the new destination. So, time to cleanup the previous
3340 * vector allocation.
3342 if (cfg->move_in_progress)
3343 send_cleanup_vector(cfg);
3349 #endif /* CONFIG_SMP */
3352 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3353 * which implement the MSI or MSI-X Capability Structure.
3355 static struct irq_chip msi_chip = {
3357 .unmask = unmask_msi_irq,
3358 .mask = mask_msi_irq,
3359 .ack = ack_apic_edge,
3361 .set_affinity = set_msi_irq_affinity,
3363 .retrigger = ioapic_retrigger_irq,
3366 static struct irq_chip msi_ir_chip = {
3367 .name = "IR-PCI-MSI",
3368 .unmask = unmask_msi_irq,
3369 .mask = mask_msi_irq,
3370 #ifdef CONFIG_INTR_REMAP
3371 .ack = ir_ack_apic_edge,
3373 .set_affinity = ir_set_msi_irq_affinity,
3376 .retrigger = ioapic_retrigger_irq,
3380 * Map the PCI dev to the corresponding remapping hardware unit
3381 * and allocate 'nvec' consecutive interrupt-remapping table entries
3384 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3386 struct intel_iommu *iommu;
3389 iommu = map_dev_to_ir(dev);
3392 "Unable to map PCI %s to iommu\n", pci_name(dev));
3396 index = alloc_irte(iommu, irq, nvec);
3399 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3406 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3411 ret = msi_compose_msg(dev, irq, &msg);
3415 set_irq_msi(irq, msidesc);
3416 write_msi_msg(irq, &msg);
3418 if (irq_remapped(irq)) {
3419 struct irq_desc *desc = irq_to_desc(irq);
3421 * irq migration in process context
3423 desc->status |= IRQ_MOVE_PCNTXT;
3424 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3426 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3428 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3433 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3436 int ret, sub_handle;
3437 struct msi_desc *msidesc;
3438 unsigned int irq_want;
3439 struct intel_iommu *iommu = NULL;
3443 /* x86 doesn't support multiple MSI yet */
3444 if (type == PCI_CAP_ID_MSI && nvec > 1)
3447 node = dev_to_node(&dev->dev);
3448 irq_want = nr_irqs_gsi;
3450 list_for_each_entry(msidesc, &dev->msi_list, list) {
3451 irq = create_irq_nr(irq_want, node);
3455 if (!intr_remapping_enabled)
3460 * allocate the consecutive block of IRTE's
3463 index = msi_alloc_irte(dev, irq, nvec);
3469 iommu = map_dev_to_ir(dev);
3475 * setup the mapping between the irq and the IRTE
3476 * base index, the sub_handle pointing to the
3477 * appropriate interrupt remap table entry.
3479 set_irte_irq(irq, iommu, index, sub_handle);
3482 ret = setup_msi_irq(dev, msidesc, irq);
3494 void arch_teardown_msi_irq(unsigned int irq)
3499 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3501 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3503 struct irq_desc *desc = irq_to_desc(irq);
3504 struct irq_cfg *cfg;
3508 dest = set_desc_affinity(desc, mask);
3509 if (dest == BAD_APICID)
3512 cfg = desc->chip_data;
3514 dmar_msi_read(irq, &msg);
3516 msg.data &= ~MSI_DATA_VECTOR_MASK;
3517 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3518 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3519 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3521 dmar_msi_write(irq, &msg);
3526 #endif /* CONFIG_SMP */
3528 struct irq_chip dmar_msi_type = {
3530 .unmask = dmar_msi_unmask,
3531 .mask = dmar_msi_mask,
3532 .ack = ack_apic_edge,
3534 .set_affinity = dmar_msi_set_affinity,
3536 .retrigger = ioapic_retrigger_irq,
3539 int arch_setup_dmar_msi(unsigned int irq)
3544 ret = msi_compose_msg(NULL, irq, &msg);
3547 dmar_msi_write(irq, &msg);
3548 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3554 #ifdef CONFIG_HPET_TIMER
3557 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3559 struct irq_desc *desc = irq_to_desc(irq);
3560 struct irq_cfg *cfg;
3564 dest = set_desc_affinity(desc, mask);
3565 if (dest == BAD_APICID)
3568 cfg = desc->chip_data;
3570 hpet_msi_read(irq, &msg);
3572 msg.data &= ~MSI_DATA_VECTOR_MASK;
3573 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3574 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3575 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3577 hpet_msi_write(irq, &msg);
3582 #endif /* CONFIG_SMP */
3584 static struct irq_chip hpet_msi_type = {
3586 .unmask = hpet_msi_unmask,
3587 .mask = hpet_msi_mask,
3588 .ack = ack_apic_edge,
3590 .set_affinity = hpet_msi_set_affinity,
3592 .retrigger = ioapic_retrigger_irq,
3595 int arch_setup_hpet_msi(unsigned int irq)
3599 struct irq_desc *desc = irq_to_desc(irq);
3601 ret = msi_compose_msg(NULL, irq, &msg);
3605 hpet_msi_write(irq, &msg);
3606 desc->status |= IRQ_MOVE_PCNTXT;
3607 set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3614 #endif /* CONFIG_PCI_MSI */
3616 * Hypertransport interrupt support
3618 #ifdef CONFIG_HT_IRQ
3622 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3624 struct ht_irq_msg msg;
3625 fetch_ht_irq_msg(irq, &msg);
3627 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3628 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3630 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3631 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3633 write_ht_irq_msg(irq, &msg);
3636 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3638 struct irq_desc *desc = irq_to_desc(irq);
3639 struct irq_cfg *cfg;
3642 dest = set_desc_affinity(desc, mask);
3643 if (dest == BAD_APICID)
3646 cfg = desc->chip_data;
3648 target_ht_irq(irq, dest, cfg->vector);
3655 static struct irq_chip ht_irq_chip = {
3657 .mask = mask_ht_irq,
3658 .unmask = unmask_ht_irq,
3659 .ack = ack_apic_edge,
3661 .set_affinity = set_ht_irq_affinity,
3663 .retrigger = ioapic_retrigger_irq,
3666 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3668 struct irq_cfg *cfg;
3675 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3677 struct ht_irq_msg msg;
3680 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3681 apic->target_cpus());
3683 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3687 HT_IRQ_LOW_DEST_ID(dest) |
3688 HT_IRQ_LOW_VECTOR(cfg->vector) |
3689 ((apic->irq_dest_mode == 0) ?
3690 HT_IRQ_LOW_DM_PHYSICAL :
3691 HT_IRQ_LOW_DM_LOGICAL) |
3692 HT_IRQ_LOW_RQEOI_EDGE |
3693 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3694 HT_IRQ_LOW_MT_FIXED :
3695 HT_IRQ_LOW_MT_ARBITRATED) |
3696 HT_IRQ_LOW_IRQ_MASKED;
3698 write_ht_irq_msg(irq, &msg);
3700 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3701 handle_edge_irq, "edge");
3703 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3707 #endif /* CONFIG_HT_IRQ */
3709 #ifdef CONFIG_X86_UV
3711 * Re-target the irq to the specified CPU and enable the specified MMR located
3712 * on the specified blade to allow the sending of MSIs to the specified CPU.
3714 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3715 unsigned long mmr_offset)
3717 const struct cpumask *eligible_cpu = cpumask_of(cpu);
3718 struct irq_cfg *cfg;
3720 unsigned long mmr_value;
3721 struct uv_IO_APIC_route_entry *entry;
3722 unsigned long flags;
3727 err = assign_irq_vector(irq, cfg, eligible_cpu);
3731 spin_lock_irqsave(&vector_lock, flags);
3732 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3734 spin_unlock_irqrestore(&vector_lock, flags);
3737 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3738 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3740 entry->vector = cfg->vector;
3741 entry->delivery_mode = apic->irq_delivery_mode;
3742 entry->dest_mode = apic->irq_dest_mode;
3743 entry->polarity = 0;
3746 entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3748 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3749 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3755 * Disable the specified MMR located on the specified blade so that MSIs are
3756 * longer allowed to be sent.
3758 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3760 unsigned long mmr_value;
3761 struct uv_IO_APIC_route_entry *entry;
3765 entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3766 BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3770 mmr_pnode = uv_blade_to_pnode(mmr_blade);
3771 uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3773 #endif /* CONFIG_X86_64 */
3775 int __init io_apic_get_redir_entries (int ioapic)
3777 union IO_APIC_reg_01 reg_01;
3778 unsigned long flags;
3780 spin_lock_irqsave(&ioapic_lock, flags);
3781 reg_01.raw = io_apic_read(ioapic, 1);
3782 spin_unlock_irqrestore(&ioapic_lock, flags);
3784 return reg_01.bits.entries;
3787 void __init probe_nr_irqs_gsi(void)
3791 nr = acpi_probe_gsi();
3792 if (nr > nr_irqs_gsi) {
3795 /* for acpi=off or acpi is not compiled in */
3799 for (idx = 0; idx < nr_ioapics; idx++)
3800 nr += io_apic_get_redir_entries(idx) + 1;
3802 if (nr > nr_irqs_gsi)
3806 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3809 #ifdef CONFIG_SPARSE_IRQ
3810 int __init arch_probe_nr_irqs(void)
3814 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3815 nr_irqs = NR_VECTORS * nr_cpu_ids;
3817 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3818 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3820 * for MSI and HT dyn irq
3822 nr += nr_irqs_gsi * 16;
3831 /* --------------------------------------------------------------------------
3832 ACPI-based IOAPIC Configuration
3833 -------------------------------------------------------------------------- */
3837 #ifdef CONFIG_X86_32
3838 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3840 union IO_APIC_reg_00 reg_00;
3841 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3843 unsigned long flags;
3847 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3848 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3849 * supports up to 16 on one shared APIC bus.
3851 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3852 * advantage of new APIC bus architecture.
3855 if (physids_empty(apic_id_map))
3856 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3858 spin_lock_irqsave(&ioapic_lock, flags);
3859 reg_00.raw = io_apic_read(ioapic, 0);
3860 spin_unlock_irqrestore(&ioapic_lock, flags);
3862 if (apic_id >= get_physical_broadcast()) {
3863 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3864 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3865 apic_id = reg_00.bits.ID;
3869 * Every APIC in a system must have a unique ID or we get lots of nice
3870 * 'stuck on smp_invalidate_needed IPI wait' messages.
3872 if (apic->check_apicid_used(apic_id_map, apic_id)) {
3874 for (i = 0; i < get_physical_broadcast(); i++) {
3875 if (!apic->check_apicid_used(apic_id_map, i))
3879 if (i == get_physical_broadcast())
3880 panic("Max apic_id exceeded!\n");
3882 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3883 "trying %d\n", ioapic, apic_id, i);
3888 tmp = apic->apicid_to_cpu_present(apic_id);
3889 physids_or(apic_id_map, apic_id_map, tmp);
3891 if (reg_00.bits.ID != apic_id) {
3892 reg_00.bits.ID = apic_id;
3894 spin_lock_irqsave(&ioapic_lock, flags);
3895 io_apic_write(ioapic, 0, reg_00.raw);
3896 reg_00.raw = io_apic_read(ioapic, 0);
3897 spin_unlock_irqrestore(&ioapic_lock, flags);
3900 if (reg_00.bits.ID != apic_id) {
3901 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3906 apic_printk(APIC_VERBOSE, KERN_INFO
3907 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3912 int __init io_apic_get_version(int ioapic)
3914 union IO_APIC_reg_01 reg_01;
3915 unsigned long flags;
3917 spin_lock_irqsave(&ioapic_lock, flags);
3918 reg_01.raw = io_apic_read(ioapic, 1);
3919 spin_unlock_irqrestore(&ioapic_lock, flags);
3921 return reg_01.bits.version;
3925 int io_apic_set_pci_routing(struct device *dev, int ioapic, int pin, int irq,
3926 int triggering, int polarity)
3928 struct irq_desc *desc;
3929 struct irq_cfg *cfg;
3932 if (!IO_APIC_IRQ(irq)) {
3933 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3939 node = dev_to_node(dev);
3941 node = cpu_to_node(boot_cpu_id);
3943 desc = irq_to_desc_alloc_node(irq, node);
3945 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3950 * IRQs < 16 are already in the irq_2_pin[] map
3952 if (irq >= NR_IRQS_LEGACY) {
3953 cfg = desc->chip_data;
3954 add_pin_to_irq_node(cfg, node, ioapic, pin);
3957 setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3963 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3967 if (skip_ioapic_setup)
3970 for (i = 0; i < mp_irq_entries; i++)
3971 if (mp_irqs[i].irqtype == mp_INT &&
3972 mp_irqs[i].srcbusirq == bus_irq)
3974 if (i >= mp_irq_entries)
3977 *trigger = irq_trigger(i);
3978 *polarity = irq_polarity(i);
3982 #endif /* CONFIG_ACPI */
3985 * This function currently is only a helper for the i386 smp boot process where
3986 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3987 * so mask in all cases should simply be apic->target_cpus()
3990 void __init setup_ioapic_dest(void)
3992 int pin, ioapic, irq, irq_entry;
3993 struct irq_desc *desc;
3994 struct irq_cfg *cfg;
3995 const struct cpumask *mask;
3997 if (skip_ioapic_setup == 1)
4000 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4001 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4002 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4003 if (irq_entry == -1)
4005 irq = pin_2_irq(irq_entry, ioapic, pin);
4007 /* setup_IO_APIC_irqs could fail to get vector for some device
4008 * when you have too many devices, because at that time only boot
4011 desc = irq_to_desc(irq);
4012 cfg = desc->chip_data;
4014 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4015 irq_trigger(irq_entry),
4016 irq_polarity(irq_entry));
4022 * Honour affinities which have been set in early boot
4025 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4026 mask = desc->affinity;
4028 mask = apic->target_cpus();
4030 if (intr_remapping_enabled)
4031 set_ir_ioapic_affinity_irq_desc(desc, mask);
4033 set_ioapic_affinity_irq_desc(desc, mask);
4040 #define IOAPIC_RESOURCE_NAME_SIZE 11
4042 static struct resource *ioapic_resources;
4044 static struct resource * __init ioapic_setup_resources(void)
4047 struct resource *res;
4051 if (nr_ioapics <= 0)
4054 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4057 mem = alloc_bootmem(n);
4061 mem += sizeof(struct resource) * nr_ioapics;
4063 for (i = 0; i < nr_ioapics; i++) {
4065 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4066 sprintf(mem, "IOAPIC %u", i);
4067 mem += IOAPIC_RESOURCE_NAME_SIZE;
4071 ioapic_resources = res;
4076 void __init ioapic_init_mappings(void)
4078 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4079 struct resource *ioapic_res;
4082 ioapic_res = ioapic_setup_resources();
4083 for (i = 0; i < nr_ioapics; i++) {
4084 if (smp_found_config) {
4085 ioapic_phys = mp_ioapics[i].apicaddr;
4086 #ifdef CONFIG_X86_32
4089 "WARNING: bogus zero IO-APIC "
4090 "address found in MPTABLE, "
4091 "disabling IO/APIC support!\n");
4092 smp_found_config = 0;
4093 skip_ioapic_setup = 1;
4094 goto fake_ioapic_page;
4098 #ifdef CONFIG_X86_32
4101 ioapic_phys = (unsigned long)
4102 alloc_bootmem_pages(PAGE_SIZE);
4103 ioapic_phys = __pa(ioapic_phys);
4105 set_fixmap_nocache(idx, ioapic_phys);
4106 apic_printk(APIC_VERBOSE,
4107 "mapped IOAPIC to %08lx (%08lx)\n",
4108 __fix_to_virt(idx), ioapic_phys);
4111 if (ioapic_res != NULL) {
4112 ioapic_res->start = ioapic_phys;
4113 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4119 static int __init ioapic_insert_resources(void)
4122 struct resource *r = ioapic_resources;
4125 if (nr_ioapics > 0) {
4127 "IO APIC resources couldn't be allocated.\n");
4133 for (i = 0; i < nr_ioapics; i++) {
4134 insert_resource(&iomem_resource, r);
4141 /* Insert the IO APIC resources after PCI initialization has occured to handle
4142 * IO APICS that are mapped in on a BAR in PCI space. */
4143 late_initcall(ioapic_insert_resources);