git.oblomov.eu Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/smp_lock.h>
  29 #include <linux/pci.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #include <linux/msi.h>
  34 #include <linux/htirq.h>
  35 #ifdef CONFIG_ACPI
  36 #include <acpi/acpi_bus.h>
  37 #endif
  38
  39 #include <asm/io.h>
  40 #include <asm/smp.h>
  41 #include <asm/desc.h>
  42 #include <asm/proto.h>
  43 #include <asm/mach_apic.h>
  44 #include <asm/acpi.h>
  45 #include <asm/dma.h>
  46 #include <asm/nmi.h>
  47 #include <asm/msidef.h>
  48 #include <asm/hypertransport.h>
  49
  50 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result);
  51
  52 #define __apicdebuginit  __init
  53
  54 int sis_apic_bug; /* not actually supported, dummy for compile */
  55
  56 static int no_timer_check;
  57
  58 static int disable_timer_pin_1 __initdata;
  59
  60 int timer_over_8254 __initdata = 1;
  61
  62 /* Where if anywhere is the i8259 connect in external int mode */
  63 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  64
  65 static DEFINE_SPINLOCK(ioapic_lock);
  66 DEFINE_SPINLOCK(vector_lock);
  67
  68 /*
  69  * # of IRQ routing registers
  70  */
  71 int nr_ioapic_registers[MAX_IO_APICS];
  72
  73 /*
  74  * Rough estimation of how many shared IRQs there are, can
  75  * be changed anytime.
  76  */
  77 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  78 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  79
  80 /*
  81  * This is performance-critical, we want to do it O(1)
  82  *
  83  * the indexing order of this array favors 1:1 mappings
  84  * between pins and IRQs.
  85  */
  86
  87 static struct irq_pin_list {
  88         short apic, pin, next;
  89 } irq_2_pin[PIN_MAP_SIZE];
  90
  91 struct io_apic {
  92         unsigned int index;
  93         unsigned int unused[3];
  94         unsigned int data;
  95 };
  96
  97 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
  98 {
  99         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 100                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
 101 }
 102
 103 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 104 {
 105         struct io_apic __iomem *io_apic = io_apic_base(apic);
 106         writel(reg, &io_apic->index);
 107         return readl(&io_apic->data);
 108 }
 109
 110 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 111 {
 112         struct io_apic __iomem *io_apic = io_apic_base(apic);
 113         writel(reg, &io_apic->index);
 114         writel(value, &io_apic->data);
 115 }
 116
 117 /*
 118  * Re-write a value: to be used for read-modify-write
 119  * cycles where the read already set up the index register.
 120  */
 121 static inline void io_apic_modify(unsigned int apic, unsigned int value)
 122 {
 123         struct io_apic __iomem *io_apic = io_apic_base(apic);
 124         writel(value, &io_apic->data);
 125 }
 126
 127 /*
 128  * Synchronize the IO-APIC and the CPU by doing
 129  * a dummy read from the IO-APIC
 130  */
 131 static inline void io_apic_sync(unsigned int apic)
 132 {
 133         struct io_apic __iomem *io_apic = io_apic_base(apic);
 134         readl(&io_apic->data);
 135 }
 136
 137 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 138                                                                         \
 139 {                                                                       \
 140         int pin;                                                        \
 141         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 142                                                                         \
 143         BUG_ON(irq >= NR_IRQS);                                         \
 144         for (;;) {                                                      \
 145                 unsigned int reg;                                       \
 146                 pin = entry->pin;                                       \
 147                 if (pin == -1)                                          \
 148                         break;                                          \
 149                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 150                 reg ACTION;                                             \
 151                 io_apic_modify(entry->apic, reg);                       \
 152                 if (!entry->next)                                       \
 153                         break;                                          \
 154                 entry = irq_2_pin + entry->next;                        \
 155         }                                                               \
 156         FINAL;                                                          \
 157 }
 158
 159 union entry_union {
 160         struct { u32 w1, w2; };
 161         struct IO_APIC_route_entry entry;
 162 };
 163
 164 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 165 {
 166         union entry_union eu;
 167         unsigned long flags;
 168         spin_lock_irqsave(&ioapic_lock, flags);
 169         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 170         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 171         spin_unlock_irqrestore(&ioapic_lock, flags);
 172         return eu.entry;
 173 }
 174
 175 /*
 176  * When we write a new IO APIC routing entry, we need to write the high
 177  * word first! If the mask bit in the low word is clear, we will enable
 178  * the interrupt, and we need to make sure the entry is fully populated
 179  * before that happens.
 180  */
 181 static void
 182 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 183 {
 184         union entry_union eu;
 185         eu.entry = e;
 186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 187         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 188 }
 189
 190 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 191 {
 192         unsigned long flags;
 193         spin_lock_irqsave(&ioapic_lock, flags);
 194         __ioapic_write_entry(apic, pin, e);
 195         spin_unlock_irqrestore(&ioapic_lock, flags);
 196 }
 197
 198 /*
 199  * When we mask an IO APIC routing entry, we need to write the low
 200  * word first, in order to set the mask bit before we change the
 201  * high bits!
 202  */
 203 static void ioapic_mask_entry(int apic, int pin)
 204 {
 205         unsigned long flags;
 206         union entry_union eu = { .entry.mask = 1 };
 207
 208         spin_lock_irqsave(&ioapic_lock, flags);
 209         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 210         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 211         spin_unlock_irqrestore(&ioapic_lock, flags);
 212 }
 213
 214 #ifdef CONFIG_SMP
 215 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
 216 {
 217         int apic, pin;
 218         struct irq_pin_list *entry = irq_2_pin + irq;
 219
 220         BUG_ON(irq >= NR_IRQS);
 221         for (;;) {
 222                 unsigned int reg;
 223                 apic = entry->apic;
 224                 pin = entry->pin;
 225                 if (pin == -1)
 226                         break;
 227                 io_apic_write(apic, 0x11 + pin*2, dest);
 228                 reg = io_apic_read(apic, 0x10 + pin*2);
 229                 reg &= ~0x000000ff;
 230                 reg |= vector;
 231                 io_apic_modify(apic, reg);
 232                 if (!entry->next)
 233                         break;
 234                 entry = irq_2_pin + entry->next;
 235         }
 236 }
 237
 238 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 239 {
 240         unsigned long flags;
 241         unsigned int dest;
 242         cpumask_t tmp;
 243         int vector;
 244
 245         cpus_and(tmp, mask, cpu_online_map);
 246         if (cpus_empty(tmp))
 247                 tmp = TARGET_CPUS;
 248
 249         cpus_and(mask, tmp, CPU_MASK_ALL);
 250
 251         vector = assign_irq_vector(irq, mask, &tmp);
 252         if (vector < 0)
 253                 return;
 254
 255         dest = cpu_mask_to_apicid(tmp);
 256
 257         /*
 258          * Only the high 8 bits are valid.
 259          */
 260         dest = SET_APIC_LOGICAL_ID(dest);
 261
 262         spin_lock_irqsave(&ioapic_lock, flags);
 263         __target_IO_APIC_irq(irq, dest, vector);
 264         set_native_irq_info(irq, mask);
 265         spin_unlock_irqrestore(&ioapic_lock, flags);
 266 }
 267 #endif
 268
 269 /*
 270  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 271  * shared ISA-space IRQs, so we have to support them. We are super
 272  * fast in the common case, and fast for shared ISA-space IRQs.
 273  */
 274 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 275 {
 276         static int first_free_entry = NR_IRQS;
 277         struct irq_pin_list *entry = irq_2_pin + irq;
 278
 279         BUG_ON(irq >= NR_IRQS);
 280         while (entry->next)
 281                 entry = irq_2_pin + entry->next;
 282
 283         if (entry->pin != -1) {
 284                 entry->next = first_free_entry;
 285                 entry = irq_2_pin + entry->next;
 286                 if (++first_free_entry >= PIN_MAP_SIZE)
 287                         panic("io_apic.c: ran out of irq_2_pin entries!");
 288         }
 289         entry->apic = apic;
 290         entry->pin = pin;
 291 }
 292
 293
 294 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 295                                                                         \
 296         static void name##_IO_APIC_irq (unsigned int irq)               \
 297         __DO_ACTION(R, ACTION, FINAL)
 298
 299 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 300                                                 /* mask = 1 */
 301 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 302                                                 /* mask = 0 */
 303
 304 static void mask_IO_APIC_irq (unsigned int irq)
 305 {
 306         unsigned long flags;
 307
 308         spin_lock_irqsave(&ioapic_lock, flags);
 309         __mask_IO_APIC_irq(irq);
 310         spin_unlock_irqrestore(&ioapic_lock, flags);
 311 }
 312
 313 static void unmask_IO_APIC_irq (unsigned int irq)
 314 {
 315         unsigned long flags;
 316
 317         spin_lock_irqsave(&ioapic_lock, flags);
 318         __unmask_IO_APIC_irq(irq);
 319         spin_unlock_irqrestore(&ioapic_lock, flags);
 320 }
 321
 322 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 323 {
 324         struct IO_APIC_route_entry entry;
 325
 326         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 327         entry = ioapic_read_entry(apic, pin);
 328         if (entry.delivery_mode == dest_SMI)
 329                 return;
 330         /*
 331          * Disable it in the IO-APIC irq-routing table:
 332          */
 333         ioapic_mask_entry(apic, pin);
 334 }
 335
 336 static void clear_IO_APIC (void)
 337 {
 338         int apic, pin;
 339
 340         for (apic = 0; apic < nr_ioapics; apic++)
 341                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 342                         clear_IO_APIC_pin(apic, pin);
 343 }
 344
 345 int skip_ioapic_setup;
 346 int ioapic_force;
 347
 348 /* dummy parsing: see setup.c */
 349
 350 static int __init disable_ioapic_setup(char *str)
 351 {
 352         skip_ioapic_setup = 1;
 353         return 0;
 354 }
 355 early_param("noapic", disable_ioapic_setup);
 356
 357 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
 358 static int __init disable_timer_pin_setup(char *arg)
 359 {
 360         disable_timer_pin_1 = 1;
 361         return 1;
 362 }
 363 __setup("disable_timer_pin_1", disable_timer_pin_setup);
 364
 365 static int __init setup_disable_8254_timer(char *s)
 366 {
 367         timer_over_8254 = -1;
 368         return 1;
 369 }
 370 static int __init setup_enable_8254_timer(char *s)
 371 {
 372         timer_over_8254 = 2;
 373         return 1;
 374 }
 375
 376 __setup("disable_8254_timer", setup_disable_8254_timer);
 377 __setup("enable_8254_timer", setup_enable_8254_timer);
 378
 379
 380 /*
 381  * Find the IRQ entry number of a certain pin.
 382  */
 383 static int find_irq_entry(int apic, int pin, int type)
 384 {
 385         int i;
 386
 387         for (i = 0; i < mp_irq_entries; i++)
 388                 if (mp_irqs[i].mpc_irqtype == type &&
 389                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 390                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 391                     mp_irqs[i].mpc_dstirq == pin)
 392                         return i;
 393
 394         return -1;
 395 }
 396
 397 /*
 398  * Find the pin to which IRQ[irq] (ISA) is connected
 399  */
 400 static int __init find_isa_irq_pin(int irq, int type)
 401 {
 402         int i;
 403
 404         for (i = 0; i < mp_irq_entries; i++) {
 405                 int lbus = mp_irqs[i].mpc_srcbus;
 406
 407                 if (test_bit(lbus, mp_bus_not_pci) &&
 408                     (mp_irqs[i].mpc_irqtype == type) &&
 409                     (mp_irqs[i].mpc_srcbusirq == irq))
 410
 411                         return mp_irqs[i].mpc_dstirq;
 412         }
 413         return -1;
 414 }
 415
 416 static int __init find_isa_irq_apic(int irq, int type)
 417 {
 418         int i;
 419
 420         for (i = 0; i < mp_irq_entries; i++) {
 421                 int lbus = mp_irqs[i].mpc_srcbus;
 422
 423                 if (test_bit(lbus, mp_bus_not_pci) &&
 424                     (mp_irqs[i].mpc_irqtype == type) &&
 425                     (mp_irqs[i].mpc_srcbusirq == irq))
 426                         break;
 427         }
 428         if (i < mp_irq_entries) {
 429                 int apic;
 430                 for(apic = 0; apic < nr_ioapics; apic++) {
 431                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 432                                 return apic;
 433                 }
 434         }
 435
 436         return -1;
 437 }
 438
 439 /*
 440  * Find a specific PCI IRQ entry.
 441  * Not an __init, possibly needed by modules
 442  */
 443 static int pin_2_irq(int idx, int apic, int pin);
 444
 445 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 446 {
 447         int apic, i, best_guess = -1;
 448
 449         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 450                 bus, slot, pin);
 451         if (mp_bus_id_to_pci_bus[bus] == -1) {
 452                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 453                 return -1;
 454         }
 455         for (i = 0; i < mp_irq_entries; i++) {
 456                 int lbus = mp_irqs[i].mpc_srcbus;
 457
 458                 for (apic = 0; apic < nr_ioapics; apic++)
 459                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 460                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 461                                 break;
 462
 463                 if (!test_bit(lbus, mp_bus_not_pci) &&
 464                     !mp_irqs[i].mpc_irqtype &&
 465                     (bus == lbus) &&
 466                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 467                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 468
 469                         if (!(apic || IO_APIC_IRQ(irq)))
 470                                 continue;
 471
 472                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 473                                 return irq;
 474                         /*
 475                          * Use the first all-but-pin matching entry as a
 476                          * best-guess fuzzy result for broken mptables.
 477                          */
 478                         if (best_guess < 0)
 479                                 best_guess = irq;
 480                 }
 481         }
 482         BUG_ON(best_guess >= NR_IRQS);
 483         return best_guess;
 484 }
 485
 486 /* ISA interrupts are always polarity zero edge triggered,
 487  * when listed as conforming in the MP table. */
 488
 489 #define default_ISA_trigger(idx)        (0)
 490 #define default_ISA_polarity(idx)       (0)
 491
 492 /* PCI interrupts are always polarity one level triggered,
 493  * when listed as conforming in the MP table. */
 494
 495 #define default_PCI_trigger(idx)        (1)
 496 #define default_PCI_polarity(idx)       (1)
 497
 498 static int __init MPBIOS_polarity(int idx)
 499 {
 500         int bus = mp_irqs[idx].mpc_srcbus;
 501         int polarity;
 502
 503         /*
 504          * Determine IRQ line polarity (high active or low active):
 505          */
 506         switch (mp_irqs[idx].mpc_irqflag & 3)
 507         {
 508                 case 0: /* conforms, ie. bus-type dependent polarity */
 509                         if (test_bit(bus, mp_bus_not_pci))
 510                                 polarity = default_ISA_polarity(idx);
 511                         else
 512                                 polarity = default_PCI_polarity(idx);
 513                         break;
 514                 case 1: /* high active */
 515                 {
 516                         polarity = 0;
 517                         break;
 518                 }
 519                 case 2: /* reserved */
 520                 {
 521                         printk(KERN_WARNING "broken BIOS!!\n");
 522                         polarity = 1;
 523                         break;
 524                 }
 525                 case 3: /* low active */
 526                 {
 527                         polarity = 1;
 528                         break;
 529                 }
 530                 default: /* invalid */
 531                 {
 532                         printk(KERN_WARNING "broken BIOS!!\n");
 533                         polarity = 1;
 534                         break;
 535                 }
 536         }
 537         return polarity;
 538 }
 539
 540 static int MPBIOS_trigger(int idx)
 541 {
 542         int bus = mp_irqs[idx].mpc_srcbus;
 543         int trigger;
 544
 545         /*
 546          * Determine IRQ trigger mode (edge or level sensitive):
 547          */
 548         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 549         {
 550                 case 0: /* conforms, ie. bus-type dependent */
 551                         if (test_bit(bus, mp_bus_not_pci))
 552                                 trigger = default_ISA_trigger(idx);
 553                         else
 554                                 trigger = default_PCI_trigger(idx);
 555                         break;
 556                 case 1: /* edge */
 557                 {
 558                         trigger = 0;
 559                         break;
 560                 }
 561                 case 2: /* reserved */
 562                 {
 563                         printk(KERN_WARNING "broken BIOS!!\n");
 564                         trigger = 1;
 565                         break;
 566                 }
 567                 case 3: /* level */
 568                 {
 569                         trigger = 1;
 570                         break;
 571                 }
 572                 default: /* invalid */
 573                 {
 574                         printk(KERN_WARNING "broken BIOS!!\n");
 575                         trigger = 0;
 576                         break;
 577                 }
 578         }
 579         return trigger;
 580 }
 581
 582 static inline int irq_polarity(int idx)
 583 {
 584         return MPBIOS_polarity(idx);
 585 }
 586
 587 static inline int irq_trigger(int idx)
 588 {
 589         return MPBIOS_trigger(idx);
 590 }
 591
 592 static int pin_2_irq(int idx, int apic, int pin)
 593 {
 594         int irq, i;
 595         int bus = mp_irqs[idx].mpc_srcbus;
 596
 597         /*
 598          * Debugging check, we are in big trouble if this message pops up!
 599          */
 600         if (mp_irqs[idx].mpc_dstirq != pin)
 601                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 602
 603         if (test_bit(bus, mp_bus_not_pci)) {
 604                 irq = mp_irqs[idx].mpc_srcbusirq;
 605         } else {
 606                 /*
 607                  * PCI IRQs are mapped in order
 608                  */
 609                 i = irq = 0;
 610                 while (i < apic)
 611                         irq += nr_ioapic_registers[i++];
 612                 irq += pin;
 613         }
 614         BUG_ON(irq >= NR_IRQS);
 615         return irq;
 616 }
 617
 618 static inline int IO_APIC_irq_trigger(int irq)
 619 {
 620         int apic, idx, pin;
 621
 622         for (apic = 0; apic < nr_ioapics; apic++) {
 623                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 624                         idx = find_irq_entry(apic,pin,mp_INT);
 625                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 626                                 return irq_trigger(idx);
 627                 }
 628         }
 629         /*
 630          * nonexistent IRQs are edge default
 631          */
 632         return 0;
 633 }
 634
 635 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 636 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = {
 637         [0] = FIRST_EXTERNAL_VECTOR + 0,
 638         [1] = FIRST_EXTERNAL_VECTOR + 1,
 639         [2] = FIRST_EXTERNAL_VECTOR + 2,
 640         [3] = FIRST_EXTERNAL_VECTOR + 3,
 641         [4] = FIRST_EXTERNAL_VECTOR + 4,
 642         [5] = FIRST_EXTERNAL_VECTOR + 5,
 643         [6] = FIRST_EXTERNAL_VECTOR + 6,
 644         [7] = FIRST_EXTERNAL_VECTOR + 7,
 645         [8] = FIRST_EXTERNAL_VECTOR + 8,
 646         [9] = FIRST_EXTERNAL_VECTOR + 9,
 647         [10] = FIRST_EXTERNAL_VECTOR + 10,
 648         [11] = FIRST_EXTERNAL_VECTOR + 11,
 649         [12] = FIRST_EXTERNAL_VECTOR + 12,
 650         [13] = FIRST_EXTERNAL_VECTOR + 13,
 651         [14] = FIRST_EXTERNAL_VECTOR + 14,
 652         [15] = FIRST_EXTERNAL_VECTOR + 15,
 653 };
 654
 655 static cpumask_t irq_domain[NR_IRQ_VECTORS] __read_mostly = {
 656         [0] = CPU_MASK_ALL,
 657         [1] = CPU_MASK_ALL,
 658         [2] = CPU_MASK_ALL,
 659         [3] = CPU_MASK_ALL,
 660         [4] = CPU_MASK_ALL,
 661         [5] = CPU_MASK_ALL,
 662         [6] = CPU_MASK_ALL,
 663         [7] = CPU_MASK_ALL,
 664         [8] = CPU_MASK_ALL,
 665         [9] = CPU_MASK_ALL,
 666         [10] = CPU_MASK_ALL,
 667         [11] = CPU_MASK_ALL,
 668         [12] = CPU_MASK_ALL,
 669         [13] = CPU_MASK_ALL,
 670         [14] = CPU_MASK_ALL,
 671         [15] = CPU_MASK_ALL,
 672 };
 673
 674 static int __assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 675 {
 676         /*
 677          * NOTE! The local APIC isn't very good at handling
 678          * multiple interrupts at the same interrupt level.
 679          * As the interrupt level is determined by taking the
 680          * vector number and shifting that right by 4, we
 681          * want to spread these out a bit so that they don't
 682          * all fall in the same interrupt level.
 683          *
 684          * Also, we've got to be careful not to trash gate
 685          * 0x80, because int 0x80 is hm, kind of importantish. ;)
 686          */
 687         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
 688         int old_vector = -1;
 689         int cpu;
 690
 691         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
 692
 693         /* Only try and allocate irqs on cpus that are present */
 694         cpus_and(mask, mask, cpu_online_map);
 695
 696         if (irq_vector[irq] > 0)
 697                 old_vector = irq_vector[irq];
 698         if (old_vector > 0) {
 699                 cpus_and(*result, irq_domain[irq], mask);
 700                 if (!cpus_empty(*result))
 701                         return old_vector;
 702         }
 703
 704         for_each_cpu_mask(cpu, mask) {
 705                 cpumask_t domain, new_mask;
 706                 int new_cpu;
 707                 int vector, offset;
 708
 709                 domain = vector_allocation_domain(cpu);
 710                 cpus_and(new_mask, domain, cpu_online_map);
 711
 712                 vector = current_vector;
 713                 offset = current_offset;
 714 next:
 715                 vector += 8;
 716                 if (vector >= FIRST_SYSTEM_VECTOR) {
 717                         /* If we run out of vectors on large boxen, must share them. */
 718                         offset = (offset + 1) % 8;
 719                         vector = FIRST_DEVICE_VECTOR + offset;
 720                 }
 721                 if (unlikely(current_vector == vector))
 722                         continue;
 723                 if (vector == IA32_SYSCALL_VECTOR)
 724                         goto next;
 725                 for_each_cpu_mask(new_cpu, new_mask)
 726                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
 727                                 goto next;
 728                 /* Found one! */
 729                 current_vector = vector;
 730                 current_offset = offset;
 731                 if (old_vector >= 0) {
 732                         cpumask_t old_mask;
 733                         int old_cpu;
 734                         cpus_and(old_mask, irq_domain[irq], cpu_online_map);
 735                         for_each_cpu_mask(old_cpu, old_mask)
 736                                 per_cpu(vector_irq, old_cpu)[old_vector] = -1;
 737                 }
 738                 for_each_cpu_mask(new_cpu, new_mask)
 739                         per_cpu(vector_irq, new_cpu)[vector] = irq;
 740                 irq_vector[irq] = vector;
 741                 irq_domain[irq] = domain;
 742                 cpus_and(*result, domain, mask);
 743                 return vector;
 744         }
 745         return -ENOSPC;
 746 }
 747
 748 static int assign_irq_vector(int irq, cpumask_t mask, cpumask_t *result)
 749 {
 750         int vector;
 751         unsigned long flags;
 752
 753         spin_lock_irqsave(&vector_lock, flags);
 754         vector = __assign_irq_vector(irq, mask, result);
 755         spin_unlock_irqrestore(&vector_lock, flags);
 756         return vector;
 757 }
 758
 759 static void __clear_irq_vector(int irq)
 760 {
 761         cpumask_t mask;
 762         int cpu, vector;
 763
 764         BUG_ON(!irq_vector[irq]);
 765
 766         vector = irq_vector[irq];
 767         cpus_and(mask, irq_domain[irq], cpu_online_map);
 768         for_each_cpu_mask(cpu, mask)
 769                 per_cpu(vector_irq, cpu)[vector] = -1;
 770
 771         irq_vector[irq] = 0;
 772         irq_domain[irq] = CPU_MASK_NONE;
 773 }
 774
 775 void __setup_vector_irq(int cpu)
 776 {
 777         /* Initialize vector_irq on a new cpu */
 778         /* This function must be called with vector_lock held */
 779         int irq, vector;
 780
 781         /* Mark the inuse vectors */
 782         for (irq = 0; irq < NR_IRQ_VECTORS; ++irq) {
 783                 if (!cpu_isset(cpu, irq_domain[irq]))
 784                         continue;
 785                 vector = irq_vector[irq];
 786                 per_cpu(vector_irq, cpu)[vector] = irq;
 787         }
 788         /* Mark the free vectors */
 789         for (vector = 0; vector < NR_VECTORS; ++vector) {
 790                 irq = per_cpu(vector_irq, cpu)[vector];
 791                 if (irq < 0)
 792                         continue;
 793                 if (!cpu_isset(cpu, irq_domain[irq]))
 794                         per_cpu(vector_irq, cpu)[vector] = -1;
 795         }
 796 }
 797
 798
 799 extern void (*interrupt[NR_IRQS])(void);
 800
 801 static struct irq_chip ioapic_chip;
 802
 803 #define IOAPIC_AUTO     -1
 804 #define IOAPIC_EDGE     0
 805 #define IOAPIC_LEVEL    1
 806
 807 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 808 {
 809         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 810                         trigger == IOAPIC_LEVEL)
 811                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 812                                               handle_fasteoi_irq, "fasteoi");
 813         else {
 814                 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
 815                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
 816                                               handle_edge_irq, "edge");
 817         }
 818 }
 819 static void __init setup_IO_APIC_irq(int apic, int pin, int idx, int irq)
 820 {
 821         struct IO_APIC_route_entry entry;
 822         int vector;
 823         unsigned long flags;
 824
 825
 826         /*
 827          * add it to the IO-APIC irq-routing table:
 828          */
 829         memset(&entry,0,sizeof(entry));
 830
 831         entry.delivery_mode = INT_DELIVERY_MODE;
 832         entry.dest_mode = INT_DEST_MODE;
 833         entry.mask = 0;                         /* enable IRQ */
 834         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 835
 836         entry.trigger = irq_trigger(idx);
 837         entry.polarity = irq_polarity(idx);
 838
 839         if (irq_trigger(idx)) {
 840                 entry.trigger = 1;
 841                 entry.mask = 1;
 842                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 843         }
 844
 845         if (!apic && !IO_APIC_IRQ(irq))
 846                 return;
 847
 848         if (IO_APIC_IRQ(irq)) {
 849                 cpumask_t mask;
 850                 vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
 851                 if (vector < 0)
 852                         return;
 853
 854                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
 855                 entry.vector = vector;
 856
 857                 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 858                 if (!apic && (irq < 16))
 859                         disable_8259A_irq(irq);
 860         }
 861
 862         ioapic_write_entry(apic, pin, entry);
 863
 864         spin_lock_irqsave(&ioapic_lock, flags);
 865         set_native_irq_info(irq, TARGET_CPUS);
 866         spin_unlock_irqrestore(&ioapic_lock, flags);
 867
 868 }
 869
 870 static void __init setup_IO_APIC_irqs(void)
 871 {
 872         int apic, pin, idx, irq, first_notcon = 1;
 873
 874         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 875
 876         for (apic = 0; apic < nr_ioapics; apic++) {
 877         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 878
 879                 idx = find_irq_entry(apic,pin,mp_INT);
 880                 if (idx == -1) {
 881                         if (first_notcon) {
 882                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 883                                 first_notcon = 0;
 884                         } else
 885                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 886                         continue;
 887                 }
 888
 889                 irq = pin_2_irq(idx, apic, pin);
 890                 add_pin_to_irq(irq, apic, pin);
 891
 892                 setup_IO_APIC_irq(apic, pin, idx, irq);
 893
 894         }
 895         }
 896
 897         if (!first_notcon)
 898                 apic_printk(APIC_VERBOSE," not connected.\n");
 899 }
 900
 901 /*
 902  * Set up the 8259A-master output pin as broadcast to all
 903  * CPUs.
 904  */
 905 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 906 {
 907         struct IO_APIC_route_entry entry;
 908         unsigned long flags;
 909
 910         memset(&entry,0,sizeof(entry));
 911
 912         disable_8259A_irq(0);
 913
 914         /* mask LVT0 */
 915         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 916
 917         /*
 918          * We use logical delivery to get the timer IRQ
 919          * to the first CPU.
 920          */
 921         entry.dest_mode = INT_DEST_MODE;
 922         entry.mask = 0;                                 /* unmask IRQ now */
 923         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 924         entry.delivery_mode = INT_DELIVERY_MODE;
 925         entry.polarity = 0;
 926         entry.trigger = 0;
 927         entry.vector = vector;
 928
 929         /*
 930          * The timer IRQ doesn't have to know that behind the
 931          * scene we have a 8259A-master in AEOI mode ...
 932          */
 933         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
 934
 935         /*
 936          * Add it to the IO-APIC irq-routing table:
 937          */
 938         spin_lock_irqsave(&ioapic_lock, flags);
 939         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 940         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 941         spin_unlock_irqrestore(&ioapic_lock, flags);
 942
 943         enable_8259A_irq(0);
 944 }
 945
 946 void __init UNEXPECTED_IO_APIC(void)
 947 {
 948 }
 949
 950 void __apicdebuginit print_IO_APIC(void)
 951 {
 952         int apic, i;
 953         union IO_APIC_reg_00 reg_00;
 954         union IO_APIC_reg_01 reg_01;
 955         union IO_APIC_reg_02 reg_02;
 956         unsigned long flags;
 957
 958         if (apic_verbosity == APIC_QUIET)
 959                 return;
 960
 961         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 962         for (i = 0; i < nr_ioapics; i++)
 963                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 964                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 965
 966         /*
 967          * We are a bit conservative about what we expect.  We have to
 968          * know about every hardware change ASAP.
 969          */
 970         printk(KERN_INFO "testing the IO APIC.......................\n");
 971
 972         for (apic = 0; apic < nr_ioapics; apic++) {
 973
 974         spin_lock_irqsave(&ioapic_lock, flags);
 975         reg_00.raw = io_apic_read(apic, 0);
 976         reg_01.raw = io_apic_read(apic, 1);
 977         if (reg_01.bits.version >= 0x10)
 978                 reg_02.raw = io_apic_read(apic, 2);
 979         spin_unlock_irqrestore(&ioapic_lock, flags);
 980
 981         printk("\n");
 982         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 983         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 984         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 985         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 986                 UNEXPECTED_IO_APIC();
 987
 988         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 989         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 990         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 991                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 992                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 993                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 994                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 995                 (reg_01.bits.entries != 0x2E) &&
 996                 (reg_01.bits.entries != 0x3F) &&
 997                 (reg_01.bits.entries != 0x03)
 998         )
 999                 UNEXPECTED_IO_APIC();
1000
1001         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1002         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1003         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1004                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1005                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1006                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1007                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1008                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1009         )
1010                 UNEXPECTED_IO_APIC();
1011         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1012                 UNEXPECTED_IO_APIC();
1013
1014         if (reg_01.bits.version >= 0x10) {
1015                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1016                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1017                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1018                         UNEXPECTED_IO_APIC();
1019         }
1020
1021         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1022
1023         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1024                           " Stat Dest Deli Vect:   \n");
1025
1026         for (i = 0; i <= reg_01.bits.entries; i++) {
1027                 struct IO_APIC_route_entry entry;
1028
1029                 entry = ioapic_read_entry(apic, i);
1030
1031                 printk(KERN_DEBUG " %02x %03X %02X  ",
1032                         i,
1033                         entry.dest.logical.logical_dest,
1034                         entry.dest.physical.physical_dest
1035                 );
1036
1037                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1038                         entry.mask,
1039                         entry.trigger,
1040                         entry.irr,
1041                         entry.polarity,
1042                         entry.delivery_status,
1043                         entry.dest_mode,
1044                         entry.delivery_mode,
1045                         entry.vector
1046                 );
1047         }
1048         }
1049         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1050         for (i = 0; i < NR_IRQS; i++) {
1051                 struct irq_pin_list *entry = irq_2_pin + i;
1052                 if (entry->pin < 0)
1053                         continue;
1054                 printk(KERN_DEBUG "IRQ%d ", i);
1055                 for (;;) {
1056                         printk("-> %d:%d", entry->apic, entry->pin);
1057                         if (!entry->next)
1058                                 break;
1059                         entry = irq_2_pin + entry->next;
1060                 }
1061                 printk("\n");
1062         }
1063
1064         printk(KERN_INFO ".................................... done.\n");
1065
1066         return;
1067 }
1068
1069 #if 0
1070
1071 static __apicdebuginit void print_APIC_bitfield (int base)
1072 {
1073         unsigned int v;
1074         int i, j;
1075
1076         if (apic_verbosity == APIC_QUIET)
1077                 return;
1078
1079         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1080         for (i = 0; i < 8; i++) {
1081                 v = apic_read(base + i*0x10);
1082                 for (j = 0; j < 32; j++) {
1083                         if (v & (1<<j))
1084                                 printk("1");
1085                         else
1086                                 printk("0");
1087                 }
1088                 printk("\n");
1089         }
1090 }
1091
1092 void __apicdebuginit print_local_APIC(void * dummy)
1093 {
1094         unsigned int v, ver, maxlvt;
1095
1096         if (apic_verbosity == APIC_QUIET)
1097                 return;
1098
1099         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1100                 smp_processor_id(), hard_smp_processor_id());
1101         v = apic_read(APIC_ID);
1102         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1103         v = apic_read(APIC_LVR);
1104         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1105         ver = GET_APIC_VERSION(v);
1106         maxlvt = get_maxlvt();
1107
1108         v = apic_read(APIC_TASKPRI);
1109         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1110
1111         v = apic_read(APIC_ARBPRI);
1112         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1113                 v & APIC_ARBPRI_MASK);
1114         v = apic_read(APIC_PROCPRI);
1115         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1116
1117         v = apic_read(APIC_EOI);
1118         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1119         v = apic_read(APIC_RRR);
1120         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1121         v = apic_read(APIC_LDR);
1122         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1123         v = apic_read(APIC_DFR);
1124         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1125         v = apic_read(APIC_SPIV);
1126         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1127
1128         printk(KERN_DEBUG "... APIC ISR field:\n");
1129         print_APIC_bitfield(APIC_ISR);
1130         printk(KERN_DEBUG "... APIC TMR field:\n");
1131         print_APIC_bitfield(APIC_TMR);
1132         printk(KERN_DEBUG "... APIC IRR field:\n");
1133         print_APIC_bitfield(APIC_IRR);
1134
1135         v = apic_read(APIC_ESR);
1136         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1137
1138         v = apic_read(APIC_ICR);
1139         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1140         v = apic_read(APIC_ICR2);
1141         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1142
1143         v = apic_read(APIC_LVTT);
1144         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1145
1146         if (maxlvt > 3) {                       /* PC is LVT#4. */
1147                 v = apic_read(APIC_LVTPC);
1148                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1149         }
1150         v = apic_read(APIC_LVT0);
1151         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1152         v = apic_read(APIC_LVT1);
1153         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1154
1155         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1156                 v = apic_read(APIC_LVTERR);
1157                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1158         }
1159
1160         v = apic_read(APIC_TMICT);
1161         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1162         v = apic_read(APIC_TMCCT);
1163         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1164         v = apic_read(APIC_TDCR);
1165         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1166         printk("\n");
1167 }
1168
1169 void print_all_local_APICs (void)
1170 {
1171         on_each_cpu(print_local_APIC, NULL, 1, 1);
1172 }
1173
1174 void __apicdebuginit print_PIC(void)
1175 {
1176         unsigned int v;
1177         unsigned long flags;
1178
1179         if (apic_verbosity == APIC_QUIET)
1180                 return;
1181
1182         printk(KERN_DEBUG "\nprinting PIC contents\n");
1183
1184         spin_lock_irqsave(&i8259A_lock, flags);
1185
1186         v = inb(0xa1) << 8 | inb(0x21);
1187         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1188
1189         v = inb(0xa0) << 8 | inb(0x20);
1190         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1191
1192         outb(0x0b,0xa0);
1193         outb(0x0b,0x20);
1194         v = inb(0xa0) << 8 | inb(0x20);
1195         outb(0x0a,0xa0);
1196         outb(0x0a,0x20);
1197
1198         spin_unlock_irqrestore(&i8259A_lock, flags);
1199
1200         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1201
1202         v = inb(0x4d1) << 8 | inb(0x4d0);
1203         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1204 }
1205
1206 #endif  /*  0  */
1207
1208 static void __init enable_IO_APIC(void)
1209 {
1210         union IO_APIC_reg_01 reg_01;
1211         int i8259_apic, i8259_pin;
1212         int i, apic;
1213         unsigned long flags;
1214
1215         for (i = 0; i < PIN_MAP_SIZE; i++) {
1216                 irq_2_pin[i].pin = -1;
1217                 irq_2_pin[i].next = 0;
1218         }
1219
1220         /*
1221          * The number of IO-APIC IRQ registers (== #pins):
1222          */
1223         for (apic = 0; apic < nr_ioapics; apic++) {
1224                 spin_lock_irqsave(&ioapic_lock, flags);
1225                 reg_01.raw = io_apic_read(apic, 1);
1226                 spin_unlock_irqrestore(&ioapic_lock, flags);
1227                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1228         }
1229         for(apic = 0; apic < nr_ioapics; apic++) {
1230                 int pin;
1231                 /* See if any of the pins is in ExtINT mode */
1232                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1233                         struct IO_APIC_route_entry entry;
1234                         entry = ioapic_read_entry(apic, pin);
1235
1236                         /* If the interrupt line is enabled and in ExtInt mode
1237                          * I have found the pin where the i8259 is connected.
1238                          */
1239                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1240                                 ioapic_i8259.apic = apic;
1241                                 ioapic_i8259.pin  = pin;
1242                                 goto found_i8259;
1243                         }
1244                 }
1245         }
1246  found_i8259:
1247         /* Look to see what if the MP table has reported the ExtINT */
1248         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1249         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1250         /* Trust the MP table if nothing is setup in the hardware */
1251         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1252                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1253                 ioapic_i8259.pin  = i8259_pin;
1254                 ioapic_i8259.apic = i8259_apic;
1255         }
1256         /* Complain if the MP table and the hardware disagree */
1257         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1258                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1259         {
1260                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1261         }
1262
1263         /*
1264          * Do not trust the IO-APIC being empty at bootup
1265          */
1266         clear_IO_APIC();
1267 }
1268
1269 /*
1270  * Not an __init, needed by the reboot code
1271  */
1272 void disable_IO_APIC(void)
1273 {
1274         /*
1275          * Clear the IO-APIC before rebooting:
1276          */
1277         clear_IO_APIC();
1278
1279         /*
1280          * If the i8259 is routed through an IOAPIC
1281          * Put that IOAPIC in virtual wire mode
1282          * so legacy interrupts can be delivered.
1283          */
1284         if (ioapic_i8259.pin != -1) {
1285                 struct IO_APIC_route_entry entry;
1286
1287                 memset(&entry, 0, sizeof(entry));
1288                 entry.mask            = 0; /* Enabled */
1289                 entry.trigger         = 0; /* Edge */
1290                 entry.irr             = 0;
1291                 entry.polarity        = 0; /* High */
1292                 entry.delivery_status = 0;
1293                 entry.dest_mode       = 0; /* Physical */
1294                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1295                 entry.vector          = 0;
1296                 entry.dest.physical.physical_dest =
1297                                         GET_APIC_ID(apic_read(APIC_ID));
1298
1299                 /*
1300                  * Add it to the IO-APIC irq-routing table:
1301                  */
1302                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1303         }
1304
1305         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1306 }
1307
1308 /*
1309  * There is a nasty bug in some older SMP boards, their mptable lies
1310  * about the timer IRQ. We do the following to work around the situation:
1311  *
1312  *      - timer IRQ defaults to IO-APIC IRQ
1313  *      - if this function detects that timer IRQs are defunct, then we fall
1314  *        back to ISA timer IRQs
1315  */
1316 static int __init timer_irq_works(void)
1317 {
1318         unsigned long t1 = jiffies;
1319
1320         local_irq_enable();
1321         /* Let ten ticks pass... */
1322         mdelay((10 * 1000) / HZ);
1323
1324         /*
1325          * Expect a few ticks at least, to be sure some possible
1326          * glue logic does not lock up after one or two first
1327          * ticks in a non-ExtINT mode.  Also the local APIC
1328          * might have cached one ExtINT interrupt.  Finally, at
1329          * least one tick may be lost due to delays.
1330          */
1331
1332         /* jiffies wrap? */
1333         if (jiffies - t1 > 4)
1334                 return 1;
1335         return 0;
1336 }
1337
1338 /*
1339  * In the SMP+IOAPIC case it might happen that there are an unspecified
1340  * number of pending IRQ events unhandled. These cases are very rare,
1341  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1342  * better to do it this way as thus we do not have to be aware of
1343  * 'pending' interrupts in the IRQ path, except at this point.
1344  */
1345 /*
1346  * Edge triggered needs to resend any interrupt
1347  * that was delayed but this is now handled in the device
1348  * independent code.
1349  */
1350
1351 /*
1352  * Starting up a edge-triggered IO-APIC interrupt is
1353  * nasty - we need to make sure that we get the edge.
1354  * If it is already asserted for some reason, we need
1355  * return 1 to indicate that is was pending.
1356  *
1357  * This is not complete - we should be able to fake
1358  * an edge even if it isn't on the 8259A...
1359  */
1360
1361 static unsigned int startup_ioapic_irq(unsigned int irq)
1362 {
1363         int was_pending = 0;
1364         unsigned long flags;
1365
1366         spin_lock_irqsave(&ioapic_lock, flags);
1367         if (irq < 16) {
1368                 disable_8259A_irq(irq);
1369                 if (i8259A_irq_pending(irq))
1370                         was_pending = 1;
1371         }
1372         __unmask_IO_APIC_irq(irq);
1373         spin_unlock_irqrestore(&ioapic_lock, flags);
1374
1375         return was_pending;
1376 }
1377
1378 static int ioapic_retrigger_irq(unsigned int irq)
1379 {
1380         cpumask_t mask;
1381         unsigned vector;
1382         unsigned long flags;
1383
1384         spin_lock_irqsave(&vector_lock, flags);
1385         vector = irq_vector[irq];
1386         cpus_clear(mask);
1387         cpu_set(first_cpu(irq_domain[irq]), mask);
1388
1389         send_IPI_mask(mask, vector);
1390         spin_unlock_irqrestore(&vector_lock, flags);
1391
1392         return 1;
1393 }
1394
1395 /*
1396  * Level and edge triggered IO-APIC interrupts need different handling,
1397  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1398  * handled with the level-triggered descriptor, but that one has slightly
1399  * more overhead. Level-triggered interrupts cannot be handled with the
1400  * edge-triggered handler, without risking IRQ storms and other ugly
1401  * races.
1402  */
1403
1404 static void ack_apic_edge(unsigned int irq)
1405 {
1406         move_native_irq(irq);
1407         ack_APIC_irq();
1408 }
1409
1410 static void ack_apic_level(unsigned int irq)
1411 {
1412         int do_unmask_irq = 0;
1413
1414 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1415         /* If we are moving the irq we need to mask it */
1416         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1417                 do_unmask_irq = 1;
1418                 mask_IO_APIC_irq(irq);
1419         }
1420 #endif
1421
1422         /*
1423          * We must acknowledge the irq before we move it or the acknowledge will
1424          * not propogate properly.
1425          */
1426         ack_APIC_irq();
1427
1428         /* Now we can move and renable the irq */
1429         move_masked_irq(irq);
1430         if (unlikely(do_unmask_irq))
1431                 unmask_IO_APIC_irq(irq);
1432 }
1433
1434 static struct irq_chip ioapic_chip __read_mostly = {
1435         .name           = "IO-APIC",
1436         .startup        = startup_ioapic_irq,
1437         .mask           = mask_IO_APIC_irq,
1438         .unmask         = unmask_IO_APIC_irq,
1439         .ack            = ack_apic_edge,
1440         .eoi            = ack_apic_level,
1441 #ifdef CONFIG_SMP
1442         .set_affinity   = set_ioapic_affinity_irq,
1443 #endif
1444         .retrigger      = ioapic_retrigger_irq,
1445 };
1446
1447 static inline void init_IO_APIC_traps(void)
1448 {
1449         int irq;
1450
1451         /*
1452          * NOTE! The local APIC isn't very good at handling
1453          * multiple interrupts at the same interrupt level.
1454          * As the interrupt level is determined by taking the
1455          * vector number and shifting that right by 4, we
1456          * want to spread these out a bit so that they don't
1457          * all fall in the same interrupt level.
1458          *
1459          * Also, we've got to be careful not to trash gate
1460          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1461          */
1462         for (irq = 0; irq < NR_IRQS ; irq++) {
1463                 int tmp = irq;
1464                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
1465                         /*
1466                          * Hmm.. We don't have an entry for this,
1467                          * so default to an old-fashioned 8259
1468                          * interrupt if we can..
1469                          */
1470                         if (irq < 16)
1471                                 make_8259A_irq(irq);
1472                         else
1473                                 /* Strange. Oh, well.. */
1474                                 irq_desc[irq].chip = &no_irq_chip;
1475                 }
1476         }
1477 }
1478
1479 static void enable_lapic_irq (unsigned int irq)
1480 {
1481         unsigned long v;
1482
1483         v = apic_read(APIC_LVT0);
1484         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1485 }
1486
1487 static void disable_lapic_irq (unsigned int irq)
1488 {
1489         unsigned long v;
1490
1491         v = apic_read(APIC_LVT0);
1492         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1493 }
1494
1495 static void ack_lapic_irq (unsigned int irq)
1496 {
1497         ack_APIC_irq();
1498 }
1499
1500 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1501
1502 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1503         .typename = "local-APIC-edge",
1504         .startup = NULL, /* startup_irq() not used for IRQ0 */
1505         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1506         .enable = enable_lapic_irq,
1507         .disable = disable_lapic_irq,
1508         .ack = ack_lapic_irq,
1509         .end = end_lapic_irq,
1510 };
1511
1512 static void setup_nmi (void)
1513 {
1514         /*
1515          * Dirty trick to enable the NMI watchdog ...
1516          * We put the 8259A master into AEOI mode and
1517          * unmask on all local APICs LVT0 as NMI.
1518          *
1519          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1520          * is from Maciej W. Rozycki - so we do not have to EOI from
1521          * the NMI handler or the timer interrupt.
1522          */
1523         printk(KERN_INFO "activating NMI Watchdog ...");
1524
1525         enable_NMI_through_LVT0(NULL);
1526
1527         printk(" done.\n");
1528 }
1529
1530 /*
1531  * This looks a bit hackish but it's about the only one way of sending
1532  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1533  * not support the ExtINT mode, unfortunately.  We need to send these
1534  * cycles as some i82489DX-based boards have glue logic that keeps the
1535  * 8259A interrupt line asserted until INTA.  --macro
1536  */
1537 static inline void unlock_ExtINT_logic(void)
1538 {
1539         int apic, pin, i;
1540         struct IO_APIC_route_entry entry0, entry1;
1541         unsigned char save_control, save_freq_select;
1542         unsigned long flags;
1543
1544         pin  = find_isa_irq_pin(8, mp_INT);
1545         apic = find_isa_irq_apic(8, mp_INT);
1546         if (pin == -1)
1547                 return;
1548
1549         spin_lock_irqsave(&ioapic_lock, flags);
1550         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1551         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1552         spin_unlock_irqrestore(&ioapic_lock, flags);
1553         clear_IO_APIC_pin(apic, pin);
1554
1555         memset(&entry1, 0, sizeof(entry1));
1556
1557         entry1.dest_mode = 0;                   /* physical delivery */
1558         entry1.mask = 0;                        /* unmask IRQ now */
1559         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1560         entry1.delivery_mode = dest_ExtINT;
1561         entry1.polarity = entry0.polarity;
1562         entry1.trigger = 0;
1563         entry1.vector = 0;
1564
1565         spin_lock_irqsave(&ioapic_lock, flags);
1566         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1567         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1568         spin_unlock_irqrestore(&ioapic_lock, flags);
1569
1570         save_control = CMOS_READ(RTC_CONTROL);
1571         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1572         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1573                    RTC_FREQ_SELECT);
1574         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1575
1576         i = 100;
1577         while (i-- > 0) {
1578                 mdelay(10);
1579                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1580                         i -= 10;
1581         }
1582
1583         CMOS_WRITE(save_control, RTC_CONTROL);
1584         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1585         clear_IO_APIC_pin(apic, pin);
1586
1587         spin_lock_irqsave(&ioapic_lock, flags);
1588         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1589         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1590         spin_unlock_irqrestore(&ioapic_lock, flags);
1591 }
1592
1593 /*
1594  * This code may look a bit paranoid, but it's supposed to cooperate with
1595  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1596  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1597  * fanatically on his truly buggy board.
1598  *
1599  * FIXME: really need to revamp this for modern platforms only.
1600  */
1601 static inline void check_timer(void)
1602 {
1603         int apic1, pin1, apic2, pin2;
1604         int vector;
1605         cpumask_t mask;
1606
1607         /*
1608          * get/set the timer IRQ vector:
1609          */
1610         disable_8259A_irq(0);
1611         vector = assign_irq_vector(0, TARGET_CPUS, &mask);
1612
1613         /*
1614          * Subtle, code in do_timer_interrupt() expects an AEOI
1615          * mode for the 8259A whenever interrupts are routed
1616          * through I/O APICs.  Also IRQ0 has to be enabled in
1617          * the 8259A which implies the virtual wire has to be
1618          * disabled in the local APIC.
1619          */
1620         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1621         init_8259A(1);
1622         if (timer_over_8254 > 0)
1623                 enable_8259A_irq(0);
1624
1625         pin1  = find_isa_irq_pin(0, mp_INT);
1626         apic1 = find_isa_irq_apic(0, mp_INT);
1627         pin2  = ioapic_i8259.pin;
1628         apic2 = ioapic_i8259.apic;
1629
1630         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1631                 vector, apic1, pin1, apic2, pin2);
1632
1633         if (pin1 != -1) {
1634                 /*
1635                  * Ok, does IRQ0 through the IOAPIC work?
1636                  */
1637                 unmask_IO_APIC_irq(0);
1638                 if (!no_timer_check && timer_irq_works()) {
1639                         nmi_watchdog_default();
1640                         if (nmi_watchdog == NMI_IO_APIC) {
1641                                 disable_8259A_irq(0);
1642                                 setup_nmi();
1643                                 enable_8259A_irq(0);
1644                         }
1645                         if (disable_timer_pin_1 > 0)
1646                                 clear_IO_APIC_pin(0, pin1);
1647                         return;
1648                 }
1649                 clear_IO_APIC_pin(apic1, pin1);
1650                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1651                                 "connected to IO-APIC\n");
1652         }
1653
1654         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1655                                 "through the 8259A ... ");
1656         if (pin2 != -1) {
1657                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1658                         apic2, pin2);
1659                 /*
1660                  * legacy devices should be connected to IO APIC #0
1661                  */
1662                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1663                 if (timer_irq_works()) {
1664                         apic_printk(APIC_VERBOSE," works.\n");
1665                         nmi_watchdog_default();
1666                         if (nmi_watchdog == NMI_IO_APIC) {
1667                                 setup_nmi();
1668                         }
1669                         return;
1670                 }
1671                 /*
1672                  * Cleanup, just in case ...
1673                  */
1674                 clear_IO_APIC_pin(apic2, pin2);
1675         }
1676         apic_printk(APIC_VERBOSE," failed.\n");
1677
1678         if (nmi_watchdog == NMI_IO_APIC) {
1679                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1680                 nmi_watchdog = 0;
1681         }
1682
1683         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1684
1685         disable_8259A_irq(0);
1686         irq_desc[0].chip = &lapic_irq_type;
1687         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1688         enable_8259A_irq(0);
1689
1690         if (timer_irq_works()) {
1691                 apic_printk(APIC_VERBOSE," works.\n");
1692                 return;
1693         }
1694         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1695         apic_printk(APIC_VERBOSE," failed.\n");
1696
1697         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1698
1699         init_8259A(0);
1700         make_8259A_irq(0);
1701         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1702
1703         unlock_ExtINT_logic();
1704
1705         if (timer_irq_works()) {
1706                 apic_printk(APIC_VERBOSE," works.\n");
1707                 return;
1708         }
1709         apic_printk(APIC_VERBOSE," failed :(.\n");
1710         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1711 }
1712
1713 static int __init notimercheck(char *s)
1714 {
1715         no_timer_check = 1;
1716         return 1;
1717 }
1718 __setup("no_timer_check", notimercheck);
1719
1720 /*
1721  *
1722  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1723  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1724  *   Linux doesn't really care, as it's not actually used
1725  *   for any interrupt handling anyway.
1726  */
1727 #define PIC_IRQS        (1<<2)
1728
1729 void __init setup_IO_APIC(void)
1730 {
1731         enable_IO_APIC();
1732
1733         if (acpi_ioapic)
1734                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1735         else
1736                 io_apic_irqs = ~PIC_IRQS;
1737
1738         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1739
1740         sync_Arb_IDs();
1741         setup_IO_APIC_irqs();
1742         init_IO_APIC_traps();
1743         check_timer();
1744         if (!acpi_ioapic)
1745                 print_IO_APIC();
1746 }
1747
1748 struct sysfs_ioapic_data {
1749         struct sys_device dev;
1750         struct IO_APIC_route_entry entry[0];
1751 };
1752 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1753
1754 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1755 {
1756         struct IO_APIC_route_entry *entry;
1757         struct sysfs_ioapic_data *data;
1758         int i;
1759
1760         data = container_of(dev, struct sysfs_ioapic_data, dev);
1761         entry = data->entry;
1762         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1763                 *entry = ioapic_read_entry(dev->id, i);
1764
1765         return 0;
1766 }
1767
1768 static int ioapic_resume(struct sys_device *dev)
1769 {
1770         struct IO_APIC_route_entry *entry;
1771         struct sysfs_ioapic_data *data;
1772         unsigned long flags;
1773         union IO_APIC_reg_00 reg_00;
1774         int i;
1775
1776         data = container_of(dev, struct sysfs_ioapic_data, dev);
1777         entry = data->entry;
1778
1779         spin_lock_irqsave(&ioapic_lock, flags);
1780         reg_00.raw = io_apic_read(dev->id, 0);
1781         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1782                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1783                 io_apic_write(dev->id, 0, reg_00.raw);
1784         }
1785         spin_unlock_irqrestore(&ioapic_lock, flags);
1786         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1787                 ioapic_write_entry(dev->id, i, entry[i]);
1788
1789         return 0;
1790 }
1791
1792 static struct sysdev_class ioapic_sysdev_class = {
1793         set_kset_name("ioapic"),
1794         .suspend = ioapic_suspend,
1795         .resume = ioapic_resume,
1796 };
1797
1798 static int __init ioapic_init_sysfs(void)
1799 {
1800         struct sys_device * dev;
1801         int i, size, error = 0;
1802
1803         error = sysdev_class_register(&ioapic_sysdev_class);
1804         if (error)
1805                 return error;
1806
1807         for (i = 0; i < nr_ioapics; i++ ) {
1808                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1809                         * sizeof(struct IO_APIC_route_entry);
1810                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1811                 if (!mp_ioapic_data[i]) {
1812                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1813                         continue;
1814                 }
1815                 memset(mp_ioapic_data[i], 0, size);
1816                 dev = &mp_ioapic_data[i]->dev;
1817                 dev->id = i;
1818                 dev->cls = &ioapic_sysdev_class;
1819                 error = sysdev_register(dev);
1820                 if (error) {
1821                         kfree(mp_ioapic_data[i]);
1822                         mp_ioapic_data[i] = NULL;
1823                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1824                         continue;
1825                 }
1826         }
1827
1828         return 0;
1829 }
1830
1831 device_initcall(ioapic_init_sysfs);
1832
1833 /*
1834  * Dynamic irq allocate and deallocation
1835  */
1836 int create_irq(void)
1837 {
1838         /* Allocate an unused irq */
1839         int irq;
1840         int new;
1841         int vector = 0;
1842         unsigned long flags;
1843         cpumask_t mask;
1844
1845         irq = -ENOSPC;
1846         spin_lock_irqsave(&vector_lock, flags);
1847         for (new = (NR_IRQS - 1); new >= 0; new--) {
1848                 if (platform_legacy_irq(new))
1849                         continue;
1850                 if (irq_vector[new] != 0)
1851                         continue;
1852                 vector = __assign_irq_vector(new, TARGET_CPUS, &mask);
1853                 if (likely(vector > 0))
1854                         irq = new;
1855                 break;
1856         }
1857         spin_unlock_irqrestore(&vector_lock, flags);
1858
1859         if (irq >= 0) {
1860                 dynamic_irq_init(irq);
1861         }
1862         return irq;
1863 }
1864
1865 void destroy_irq(unsigned int irq)
1866 {
1867         unsigned long flags;
1868
1869         dynamic_irq_cleanup(irq);
1870
1871         spin_lock_irqsave(&vector_lock, flags);
1872         __clear_irq_vector(irq);
1873         spin_unlock_irqrestore(&vector_lock, flags);
1874 }
1875
1876 /*
1877  * MSI mesage composition
1878  */
1879 #ifdef CONFIG_PCI_MSI
1880 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1881 {
1882         int vector;
1883         unsigned dest;
1884         cpumask_t tmp;
1885
1886         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
1887         if (vector >= 0) {
1888                 dest = cpu_mask_to_apicid(tmp);
1889
1890                 msg->address_hi = MSI_ADDR_BASE_HI;
1891                 msg->address_lo =
1892                         MSI_ADDR_BASE_LO |
1893                         ((INT_DEST_MODE == 0) ?
1894                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1895                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1896                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1897                                 MSI_ADDR_REDIRECTION_CPU:
1898                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1899                         MSI_ADDR_DEST_ID(dest);
1900
1901                 msg->data =
1902                         MSI_DATA_TRIGGER_EDGE |
1903                         MSI_DATA_LEVEL_ASSERT |
1904                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1905                                 MSI_DATA_DELIVERY_FIXED:
1906                                 MSI_DATA_DELIVERY_LOWPRI) |
1907                         MSI_DATA_VECTOR(vector);
1908         }
1909         return vector;
1910 }
1911
1912 #ifdef CONFIG_SMP
1913 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
1914 {
1915         struct msi_msg msg;
1916         unsigned int dest;
1917         cpumask_t tmp;
1918         int vector;
1919
1920         cpus_and(tmp, mask, cpu_online_map);
1921         if (cpus_empty(tmp))
1922                 tmp = TARGET_CPUS;
1923
1924         cpus_and(mask, tmp, CPU_MASK_ALL);
1925
1926         vector = assign_irq_vector(irq, mask, &tmp);
1927         if (vector < 0)
1928                 return;
1929
1930         dest = cpu_mask_to_apicid(tmp);
1931
1932         read_msi_msg(irq, &msg);
1933
1934         msg.data &= ~MSI_DATA_VECTOR_MASK;
1935         msg.data |= MSI_DATA_VECTOR(vector);
1936         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1937         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
1938
1939         write_msi_msg(irq, &msg);
1940         set_native_irq_info(irq, mask);
1941 }
1942 #endif /* CONFIG_SMP */
1943
1944 /*
1945  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1946  * which implement the MSI or MSI-X Capability Structure.
1947  */
1948 static struct irq_chip msi_chip = {
1949         .name           = "PCI-MSI",
1950         .unmask         = unmask_msi_irq,
1951         .mask           = mask_msi_irq,
1952         .ack            = ack_apic_edge,
1953 #ifdef CONFIG_SMP
1954         .set_affinity   = set_msi_irq_affinity,
1955 #endif
1956         .retrigger      = ioapic_retrigger_irq,
1957 };
1958
1959 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
1960 {
1961         struct msi_msg msg;
1962         int irq, ret;
1963         irq = create_irq();
1964         if (irq < 0)
1965                 return irq;
1966
1967         set_irq_msi(irq, desc);
1968         ret = msi_compose_msg(dev, irq, &msg);
1969         if (ret < 0) {
1970                 destroy_irq(irq);
1971                 return ret;
1972         }
1973
1974         write_msi_msg(irq, &msg);
1975
1976         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
1977
1978         return irq;
1979 }
1980
1981 void arch_teardown_msi_irq(unsigned int irq)
1982 {
1983         destroy_irq(irq);
1984 }
1985
1986 #endif /* CONFIG_PCI_MSI */
1987
1988 /*
1989  * Hypertransport interrupt support
1990  */
1991 #ifdef CONFIG_HT_IRQ
1992
1993 #ifdef CONFIG_SMP
1994
1995 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1996 {
1997         struct ht_irq_msg msg;
1998         fetch_ht_irq_msg(irq, &msg);
1999
2000         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2001         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2002
2003         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2004         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2005
2006         write_ht_irq_msg(irq, &msg);
2007 }
2008
2009 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2010 {
2011         unsigned int dest;
2012         cpumask_t tmp;
2013         int vector;
2014
2015         cpus_and(tmp, mask, cpu_online_map);
2016         if (cpus_empty(tmp))
2017                 tmp = TARGET_CPUS;
2018
2019         cpus_and(mask, tmp, CPU_MASK_ALL);
2020
2021         vector = assign_irq_vector(irq, mask, &tmp);
2022         if (vector < 0)
2023                 return;
2024
2025         dest = cpu_mask_to_apicid(tmp);
2026
2027         target_ht_irq(irq, dest, vector);
2028         set_native_irq_info(irq, mask);
2029 }
2030 #endif
2031
2032 static struct irq_chip ht_irq_chip = {
2033         .name           = "PCI-HT",
2034         .mask           = mask_ht_irq,
2035         .unmask         = unmask_ht_irq,
2036         .ack            = ack_apic_edge,
2037 #ifdef CONFIG_SMP
2038         .set_affinity   = set_ht_irq_affinity,
2039 #endif
2040         .retrigger      = ioapic_retrigger_irq,
2041 };
2042
2043 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2044 {
2045         int vector;
2046         cpumask_t tmp;
2047
2048         vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2049         if (vector >= 0) {
2050                 struct ht_irq_msg msg;
2051                 unsigned dest;
2052
2053                 dest = cpu_mask_to_apicid(tmp);
2054
2055                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2056
2057                 msg.address_lo =
2058                         HT_IRQ_LOW_BASE |
2059                         HT_IRQ_LOW_DEST_ID(dest) |
2060                         HT_IRQ_LOW_VECTOR(vector) |
2061                         ((INT_DEST_MODE == 0) ?
2062                                 HT_IRQ_LOW_DM_PHYSICAL :
2063                                 HT_IRQ_LOW_DM_LOGICAL) |
2064                         HT_IRQ_LOW_RQEOI_EDGE |
2065                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2066                                 HT_IRQ_LOW_MT_FIXED :
2067                                 HT_IRQ_LOW_MT_ARBITRATED) |
2068                         HT_IRQ_LOW_IRQ_MASKED;
2069
2070                 write_ht_irq_msg(irq, &msg);
2071
2072                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2073                                               handle_edge_irq, "edge");
2074         }
2075         return vector;
2076 }
2077 #endif /* CONFIG_HT_IRQ */
2078
2079 /* --------------------------------------------------------------------------
2080                           ACPI-based IOAPIC Configuration
2081    -------------------------------------------------------------------------- */
2082
2083 #ifdef CONFIG_ACPI
2084
2085 #define IO_APIC_MAX_ID          0xFE
2086
2087 int __init io_apic_get_redir_entries (int ioapic)
2088 {
2089         union IO_APIC_reg_01    reg_01;
2090         unsigned long flags;
2091
2092         spin_lock_irqsave(&ioapic_lock, flags);
2093         reg_01.raw = io_apic_read(ioapic, 1);
2094         spin_unlock_irqrestore(&ioapic_lock, flags);
2095
2096         return reg_01.bits.entries;
2097 }
2098
2099
2100 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2101 {
2102         struct IO_APIC_route_entry entry;
2103         unsigned long flags;
2104         int vector;
2105         cpumask_t mask;
2106
2107         if (!IO_APIC_IRQ(irq)) {
2108                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2109                         ioapic);
2110                 return -EINVAL;
2111         }
2112
2113         /*
2114          * IRQs < 16 are already in the irq_2_pin[] map
2115          */
2116         if (irq >= 16)
2117                 add_pin_to_irq(irq, ioapic, pin);
2118
2119
2120         vector = assign_irq_vector(irq, TARGET_CPUS, &mask);
2121         if (vector < 0)
2122                 return vector;
2123
2124         /*
2125          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2126          * Note that we mask (disable) IRQs now -- these get enabled when the
2127          * corresponding device driver registers for this IRQ.
2128          */
2129
2130         memset(&entry,0,sizeof(entry));
2131
2132         entry.delivery_mode = INT_DELIVERY_MODE;
2133         entry.dest_mode = INT_DEST_MODE;
2134         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
2135         entry.trigger = triggering;
2136         entry.polarity = polarity;
2137         entry.mask = 1;                                  /* Disabled (masked) */
2138         entry.vector = vector & 0xff;
2139
2140         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2141                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2142                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2143                triggering, polarity);
2144
2145         ioapic_register_intr(irq, entry.vector, triggering);
2146
2147         if (!ioapic && (irq < 16))
2148                 disable_8259A_irq(irq);
2149
2150         ioapic_write_entry(ioapic, pin, entry);
2151
2152         spin_lock_irqsave(&ioapic_lock, flags);
2153         set_native_irq_info(irq, TARGET_CPUS);
2154         spin_unlock_irqrestore(&ioapic_lock, flags);
2155
2156         return 0;
2157 }
2158
2159 #endif /* CONFIG_ACPI */
2160
2161
2162 /*
2163  * This function currently is only a helper for the i386 smp boot process where
2164  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2165  * so mask in all cases should simply be TARGET_CPUS
2166  */
2167 #ifdef CONFIG_SMP
2168 void __init setup_ioapic_dest(void)
2169 {
2170         int pin, ioapic, irq, irq_entry;
2171
2172         if (skip_ioapic_setup == 1)
2173                 return;
2174
2175         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2176                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2177                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2178                         if (irq_entry == -1)
2179                                 continue;
2180                         irq = pin_2_irq(irq_entry, ioapic, pin);
2181
2182                         /* setup_IO_APIC_irqs could fail to get vector for some device
2183                          * when you have too many devices, because at that time only boot
2184                          * cpu is online.
2185                          */
2186                         if(!irq_vector[irq])
2187                                 setup_IO_APIC_irq(ioapic, pin, irq_entry, irq);
2188                         else
2189                                 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2190                 }
2191
2192         }
2193 }
2194 #endif