1 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
5 * OMAP3430 Clock Management register bits
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 /* Bits shared between registers */
21 /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
22 #define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
23 #define OMAP3430ES2_EN_MMC3_SHIFT 30
24 #define OMAP3430_EN_MSPRO (1 << 23)
25 #define OMAP3430_EN_MSPRO_SHIFT 23
26 #define OMAP3430_EN_HDQ (1 << 22)
27 #define OMAP3430_EN_HDQ_SHIFT 22
28 #define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
29 #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
30 #define OMAP3430ES1_EN_D2D (1 << 3)
31 #define OMAP3430ES1_EN_D2D_SHIFT 3
32 #define OMAP3430_EN_SSI (1 << 0)
33 #define OMAP3430_EN_SSI_SHIFT 0
35 /* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
36 #define OMAP3430ES2_EN_USBTLL_SHIFT 2
37 #define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
39 /* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
40 #define OMAP3430_EN_WDT2 (1 << 5)
41 #define OMAP3430_EN_WDT2_SHIFT 5
43 /* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
44 #define OMAP3430_EN_CAM (1 << 0)
45 #define OMAP3430_EN_CAM_SHIFT 0
47 /* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
48 #define OMAP3430_EN_WDT3 (1 << 12)
49 #define OMAP3430_EN_WDT3_SHIFT 12
51 /* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
52 #define OMAP3430_OVERRIDE_ENABLE (1 << 19)
55 /* Bits specific to each register */
58 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
59 #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
61 /* CM_CLKEN_PLL_IVA2 */
62 #define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
63 #define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
64 #define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
65 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
66 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
67 #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
68 #define OMAP3430_EN_IVA2_DPLL_SHIFT 0
69 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
72 #define OMAP3430_ST_IVA2 (1 << 0)
74 /* CM_IDLEST_PLL_IVA2 */
75 #define OMAP3430_ST_IVA2_CLK_SHIFT 0
76 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
78 /* CM_AUTOIDLE_PLL_IVA2 */
79 #define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
80 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
82 /* CM_CLKSEL1_PLL_IVA2 */
83 #define OMAP3430_IVA2_CLK_SRC_SHIFT 19
84 #define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
85 #define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
86 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
87 #define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
88 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
90 /* CM_CLKSEL2_PLL_IVA2 */
91 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
92 #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
94 /* CM_CLKSTCTRL_IVA2 */
95 #define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
96 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
99 #define OMAP3430_CLKACTIVITY_IVA2 (1 << 0)
101 /* CM_REVISION specific bits */
103 /* CM_SYSCONFIG specific bits */
105 /* CM_CLKEN_PLL_MPU */
106 #define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
107 #define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
108 #define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
109 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
110 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
111 #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
112 #define OMAP3430_EN_MPU_DPLL_SHIFT 0
113 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
116 #define OMAP3430_ST_MPU (1 << 0)
118 /* CM_IDLEST_PLL_MPU */
119 #define OMAP3430_ST_MPU_CLK_SHIFT 0
120 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
122 /* CM_AUTOIDLE_PLL_MPU */
123 #define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
124 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
126 /* CM_CLKSEL1_PLL_MPU */
127 #define OMAP3430_MPU_CLK_SRC_SHIFT 19
128 #define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
129 #define OMAP3430_MPU_DPLL_MULT_SHIFT 8
130 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
131 #define OMAP3430_MPU_DPLL_DIV_SHIFT 0
132 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
134 /* CM_CLKSEL2_PLL_MPU */
135 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
136 #define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
138 /* CM_CLKSTCTRL_MPU */
139 #define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
140 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
143 #define OMAP3430_CLKACTIVITY_MPU (1 << 0)
145 /* CM_FCLKEN1_CORE specific bits */
147 /* CM_ICLKEN1_CORE specific bits */
148 #define OMAP3430_EN_ICR (1 << 29)
149 #define OMAP3430_EN_ICR_SHIFT 29
150 #define OMAP3430_EN_AES2 (1 << 28)
151 #define OMAP3430_EN_AES2_SHIFT 28
152 #define OMAP3430_EN_SHA12 (1 << 27)
153 #define OMAP3430_EN_SHA12_SHIFT 27
154 #define OMAP3430_EN_DES2 (1 << 26)
155 #define OMAP3430_EN_DES2_SHIFT 26
156 #define OMAP3430ES1_EN_FAC (1 << 8)
157 #define OMAP3430ES1_EN_FAC_SHIFT 8
158 #define OMAP3430_EN_MAILBOXES (1 << 7)
159 #define OMAP3430_EN_MAILBOXES_SHIFT 7
160 #define OMAP3430_EN_OMAPCTRL (1 << 6)
161 #define OMAP3430_EN_OMAPCTRL_SHIFT 6
162 #define OMAP3430_EN_SDRC (1 << 1)
163 #define OMAP3430_EN_SDRC_SHIFT 1
165 /* CM_ICLKEN2_CORE */
166 #define OMAP3430_EN_PKA (1 << 4)
167 #define OMAP3430_EN_PKA_SHIFT 4
168 #define OMAP3430_EN_AES1 (1 << 3)
169 #define OMAP3430_EN_AES1_SHIFT 3
170 #define OMAP3430_EN_RNG (1 << 2)
171 #define OMAP3430_EN_RNG_SHIFT 2
172 #define OMAP3430_EN_SHA11 (1 << 1)
173 #define OMAP3430_EN_SHA11_SHIFT 1
174 #define OMAP3430_EN_DES1 (1 << 0)
175 #define OMAP3430_EN_DES1_SHIFT 0
177 /* CM_FCLKEN3_CORE specific bits */
178 #define OMAP3430ES2_EN_TS_SHIFT 1
179 #define OMAP3430ES2_EN_TS_MASK (1 << 1)
180 #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
181 #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
183 /* CM_IDLEST1_CORE specific bits */
184 #define OMAP3430_ST_ICR (1 << 29)
185 #define OMAP3430_ST_AES2 (1 << 28)
186 #define OMAP3430_ST_SHA12 (1 << 27)
187 #define OMAP3430_ST_DES2 (1 << 26)
188 #define OMAP3430_ST_MSPRO (1 << 23)
189 #define OMAP3430_ST_HDQ (1 << 22)
190 #define OMAP3430ES1_ST_FAC (1 << 8)
191 #define OMAP3430ES1_ST_MAILBOXES (1 << 7)
192 #define OMAP3430_ST_OMAPCTRL (1 << 6)
193 #define OMAP3430_ST_SDMA (1 << 2)
194 #define OMAP3430_ST_SDRC (1 << 1)
195 #define OMAP3430_ST_SSI (1 << 0)
197 /* CM_IDLEST2_CORE */
198 #define OMAP3430_ST_PKA (1 << 4)
199 #define OMAP3430_ST_AES1 (1 << 3)
200 #define OMAP3430_ST_RNG (1 << 2)
201 #define OMAP3430_ST_SHA11 (1 << 1)
202 #define OMAP3430_ST_DES1 (1 << 0)
204 /* CM_IDLEST3_CORE */
205 #define OMAP3430ES2_ST_USBTLL_SHIFT 2
206 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
208 /* CM_AUTOIDLE1_CORE */
209 #define OMAP3430_AUTO_AES2 (1 << 28)
210 #define OMAP3430_AUTO_AES2_SHIFT 28
211 #define OMAP3430_AUTO_SHA12 (1 << 27)
212 #define OMAP3430_AUTO_SHA12_SHIFT 27
213 #define OMAP3430_AUTO_DES2 (1 << 26)
214 #define OMAP3430_AUTO_DES2_SHIFT 26
215 #define OMAP3430_AUTO_MMC2 (1 << 25)
216 #define OMAP3430_AUTO_MMC2_SHIFT 25
217 #define OMAP3430_AUTO_MMC1 (1 << 24)
218 #define OMAP3430_AUTO_MMC1_SHIFT 24
219 #define OMAP3430_AUTO_MSPRO (1 << 23)
220 #define OMAP3430_AUTO_MSPRO_SHIFT 23
221 #define OMAP3430_AUTO_HDQ (1 << 22)
222 #define OMAP3430_AUTO_HDQ_SHIFT 22
223 #define OMAP3430_AUTO_MCSPI4 (1 << 21)
224 #define OMAP3430_AUTO_MCSPI4_SHIFT 21
225 #define OMAP3430_AUTO_MCSPI3 (1 << 20)
226 #define OMAP3430_AUTO_MCSPI3_SHIFT 20
227 #define OMAP3430_AUTO_MCSPI2 (1 << 19)
228 #define OMAP3430_AUTO_MCSPI2_SHIFT 19
229 #define OMAP3430_AUTO_MCSPI1 (1 << 18)
230 #define OMAP3430_AUTO_MCSPI1_SHIFT 18
231 #define OMAP3430_AUTO_I2C3 (1 << 17)
232 #define OMAP3430_AUTO_I2C3_SHIFT 17
233 #define OMAP3430_AUTO_I2C2 (1 << 16)
234 #define OMAP3430_AUTO_I2C2_SHIFT 16
235 #define OMAP3430_AUTO_I2C1 (1 << 15)
236 #define OMAP3430_AUTO_I2C1_SHIFT 15
237 #define OMAP3430_AUTO_UART2 (1 << 14)
238 #define OMAP3430_AUTO_UART2_SHIFT 14
239 #define OMAP3430_AUTO_UART1 (1 << 13)
240 #define OMAP3430_AUTO_UART1_SHIFT 13
241 #define OMAP3430_AUTO_GPT11 (1 << 12)
242 #define OMAP3430_AUTO_GPT11_SHIFT 12
243 #define OMAP3430_AUTO_GPT10 (1 << 11)
244 #define OMAP3430_AUTO_GPT10_SHIFT 11
245 #define OMAP3430_AUTO_MCBSP5 (1 << 10)
246 #define OMAP3430_AUTO_MCBSP5_SHIFT 10
247 #define OMAP3430_AUTO_MCBSP1 (1 << 9)
248 #define OMAP3430_AUTO_MCBSP1_SHIFT 9
249 #define OMAP3430ES1_AUTO_FAC (1 << 8)
250 #define OMAP3430ES1_AUTO_FAC_SHIFT 8
251 #define OMAP3430_AUTO_MAILBOXES (1 << 7)
252 #define OMAP3430_AUTO_MAILBOXES_SHIFT 7
253 #define OMAP3430_AUTO_OMAPCTRL (1 << 6)
254 #define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
255 #define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
256 #define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
257 #define OMAP3430_AUTO_HSOTGUSB (1 << 4)
258 #define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
259 #define OMAP3430ES1_AUTO_D2D (1 << 3)
260 #define OMAP3430ES1_AUTO_D2D_SHIFT 3
261 #define OMAP3430_AUTO_SSI (1 << 0)
262 #define OMAP3430_AUTO_SSI_SHIFT 0
264 /* CM_AUTOIDLE2_CORE */
265 #define OMAP3430_AUTO_PKA (1 << 4)
266 #define OMAP3430_AUTO_PKA_SHIFT 4
267 #define OMAP3430_AUTO_AES1 (1 << 3)
268 #define OMAP3430_AUTO_AES1_SHIFT 3
269 #define OMAP3430_AUTO_RNG (1 << 2)
270 #define OMAP3430_AUTO_RNG_SHIFT 2
271 #define OMAP3430_AUTO_SHA11 (1 << 1)
272 #define OMAP3430_AUTO_SHA11_SHIFT 1
273 #define OMAP3430_AUTO_DES1 (1 << 0)
274 #define OMAP3430_AUTO_DES1_SHIFT 0
276 /* CM_AUTOIDLE3_CORE */
277 #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
278 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
281 #define OMAP3430_CLKSEL_SSI_SHIFT 8
282 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
283 #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
284 #define OMAP3430_CLKSEL_GPT11_SHIFT 7
285 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
286 #define OMAP3430_CLKSEL_GPT10_SHIFT 6
287 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
288 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
289 #define OMAP3430_CLKSEL_L4_SHIFT 2
290 #define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
291 #define OMAP3430_CLKSEL_L3_SHIFT 0
292 #define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
294 /* CM_CLKSTCTRL_CORE */
295 #define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
296 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
297 #define OMAP3430_CLKTRCTRL_L4_SHIFT 2
298 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
299 #define OMAP3430_CLKTRCTRL_L3_SHIFT 0
300 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
302 /* CM_CLKSTST_CORE */
303 #define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
304 #define OMAP3430_CLKACTIVITY_L4 (1 << 1)
305 #define OMAP3430_CLKACTIVITY_L3 (1 << 0)
308 #define OMAP3430ES1_EN_3D (1 << 2)
309 #define OMAP3430ES1_EN_3D_SHIFT 2
310 #define OMAP3430ES1_EN_2D (1 << 1)
311 #define OMAP3430ES1_EN_2D_SHIFT 1
313 /* CM_ICLKEN_GFX specific bits */
315 /* CM_IDLEST_GFX specific bits */
317 /* CM_CLKSEL_GFX specific bits */
319 /* CM_SLEEPDEP_GFX specific bits */
321 /* CM_CLKSTCTRL_GFX */
322 #define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
323 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
326 #define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0)
329 #define OMAP3430ES2_EN_SGX_SHIFT 1
330 #define OMAP3430ES2_EN_SGX_MASK (1 << 1)
333 #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
334 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
336 /* CM_FCLKEN_WKUP specific bits */
337 #define OMAP3430ES2_EN_USIMOCP_SHIFT 9
339 /* CM_ICLKEN_WKUP specific bits */
340 #define OMAP3430_EN_WDT1 (1 << 4)
341 #define OMAP3430_EN_WDT1_SHIFT 4
342 #define OMAP3430_EN_32KSYNC (1 << 2)
343 #define OMAP3430_EN_32KSYNC_SHIFT 2
345 /* CM_IDLEST_WKUP specific bits */
346 #define OMAP3430_ST_WDT2 (1 << 5)
347 #define OMAP3430_ST_WDT1 (1 << 4)
348 #define OMAP3430_ST_32KSYNC (1 << 2)
350 /* CM_AUTOIDLE_WKUP */
351 #define OMAP3430_AUTO_WDT2 (1 << 5)
352 #define OMAP3430_AUTO_WDT2_SHIFT 5
353 #define OMAP3430_AUTO_WDT1 (1 << 4)
354 #define OMAP3430_AUTO_WDT1_SHIFT 4
355 #define OMAP3430_AUTO_GPIO1 (1 << 3)
356 #define OMAP3430_AUTO_GPIO1_SHIFT 3
357 #define OMAP3430_AUTO_32KSYNC (1 << 2)
358 #define OMAP3430_AUTO_32KSYNC_SHIFT 2
359 #define OMAP3430_AUTO_GPT12 (1 << 1)
360 #define OMAP3430_AUTO_GPT12_SHIFT 1
361 #define OMAP3430_AUTO_GPT1 (1 << 0)
362 #define OMAP3430_AUTO_GPT1_SHIFT 0
365 #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
366 #define OMAP3430_CLKSEL_RM_SHIFT 1
367 #define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
368 #define OMAP3430_CLKSEL_GPT1_SHIFT 0
369 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
372 #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
373 #define OMAP3430_PWRDN_CAM_SHIFT 30
374 #define OMAP3430_PWRDN_DSS1_SHIFT 29
375 #define OMAP3430_PWRDN_TV_SHIFT 28
376 #define OMAP3430_PWRDN_96M_SHIFT 27
377 #define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
378 #define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
379 #define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
380 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
381 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
382 #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
383 #define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
384 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
385 #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
386 #define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
387 #define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
388 #define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
389 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
390 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
391 #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
392 #define OMAP3430_EN_CORE_DPLL_SHIFT 0
393 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
396 #define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
397 #define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
398 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
399 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
400 #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
401 #define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
402 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
404 /* CM_IDLEST_CKGEN */
405 #define OMAP3430_ST_54M_CLK (1 << 5)
406 #define OMAP3430_ST_12M_CLK (1 << 4)
407 #define OMAP3430_ST_48M_CLK (1 << 3)
408 #define OMAP3430_ST_96M_CLK (1 << 2)
409 #define OMAP3430_ST_PERIPH_CLK_SHIFT 1
410 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
411 #define OMAP3430_ST_CORE_CLK_SHIFT 0
412 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
414 /* CM_IDLEST2_CKGEN */
415 #define OMAP3430ES2_ST_120M_CLK_SHIFT 1
416 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
417 #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
418 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
420 /* CM_AUTOIDLE_PLL */
421 #define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
422 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
423 #define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
424 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
426 /* CM_AUTOIDLE2_PLL */
427 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
428 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
431 /* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
432 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
433 #define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
434 #define OMAP3430_CORE_DPLL_MULT_SHIFT 16
435 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
436 #define OMAP3430_CORE_DPLL_DIV_SHIFT 8
437 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
438 #define OMAP3430_SOURCE_54M (1 << 5)
439 #define OMAP3430_SOURCE_48M (1 << 3)
442 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
443 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
444 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
445 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
448 #define OMAP3430_DIV_96M_SHIFT 0
449 #define OMAP3430_DIV_96M_MASK (0x1f << 0)
452 #define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
453 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
454 #define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
455 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
458 #define OMAP3430ES2_DIV_120M_SHIFT 0
459 #define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
462 #define OMAP3430_CLKOUT2_EN_SHIFT 7
463 #define OMAP3430_CLKOUT2_EN (1 << 7)
464 #define OMAP3430_CLKOUT2_DIV_SHIFT 3
465 #define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
466 #define OMAP3430_CLKOUT2SOURCE_SHIFT 0
467 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
470 #define OMAP3430_EN_TV (1 << 2)
471 #define OMAP3430_EN_TV_SHIFT 2
472 #define OMAP3430_EN_DSS2 (1 << 1)
473 #define OMAP3430_EN_DSS2_SHIFT 1
474 #define OMAP3430_EN_DSS1 (1 << 0)
475 #define OMAP3430_EN_DSS1_SHIFT 0
478 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS (1 << 0)
479 #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
482 #define OMAP3430_ST_DSS (1 << 0)
484 /* CM_AUTOIDLE_DSS */
485 #define OMAP3430_AUTO_DSS (1 << 0)
486 #define OMAP3430_AUTO_DSS_SHIFT 0
489 #define OMAP3430_CLKSEL_TV_SHIFT 8
490 #define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
491 #define OMAP3430_CLKSEL_DSS1_SHIFT 0
492 #define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
494 /* CM_SLEEPDEP_DSS specific bits */
496 /* CM_CLKSTCTRL_DSS */
497 #define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
498 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
501 #define OMAP3430_CLKACTIVITY_DSS (1 << 0)
503 /* CM_FCLKEN_CAM specific bits */
505 /* CM_ICLKEN_CAM specific bits */
508 #define OMAP3430_ST_CAM (1 << 0)
510 /* CM_AUTOIDLE_CAM */
511 #define OMAP3430_AUTO_CAM (1 << 0)
512 #define OMAP3430_AUTO_CAM_SHIFT 0
515 #define OMAP3430_CLKSEL_CAM_SHIFT 0
516 #define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
518 /* CM_SLEEPDEP_CAM specific bits */
520 /* CM_CLKSTCTRL_CAM */
521 #define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
522 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
525 #define OMAP3430_CLKACTIVITY_CAM (1 << 0)
527 /* CM_FCLKEN_PER specific bits */
529 /* CM_ICLKEN_PER specific bits */
532 #define OMAP3430_ST_WDT3 (1 << 12)
533 #define OMAP3430_ST_MCBSP4 (1 << 2)
534 #define OMAP3430_ST_MCBSP3 (1 << 1)
535 #define OMAP3430_ST_MCBSP2 (1 << 0)
537 /* CM_AUTOIDLE_PER */
538 #define OMAP3430_AUTO_GPIO6 (1 << 17)
539 #define OMAP3430_AUTO_GPIO6_SHIFT 17
540 #define OMAP3430_AUTO_GPIO5 (1 << 16)
541 #define OMAP3430_AUTO_GPIO5_SHIFT 16
542 #define OMAP3430_AUTO_GPIO4 (1 << 15)
543 #define OMAP3430_AUTO_GPIO4_SHIFT 15
544 #define OMAP3430_AUTO_GPIO3 (1 << 14)
545 #define OMAP3430_AUTO_GPIO3_SHIFT 14
546 #define OMAP3430_AUTO_GPIO2 (1 << 13)
547 #define OMAP3430_AUTO_GPIO2_SHIFT 13
548 #define OMAP3430_AUTO_WDT3 (1 << 12)
549 #define OMAP3430_AUTO_WDT3_SHIFT 12
550 #define OMAP3430_AUTO_UART3 (1 << 11)
551 #define OMAP3430_AUTO_UART3_SHIFT 11
552 #define OMAP3430_AUTO_GPT9 (1 << 10)
553 #define OMAP3430_AUTO_GPT9_SHIFT 10
554 #define OMAP3430_AUTO_GPT8 (1 << 9)
555 #define OMAP3430_AUTO_GPT8_SHIFT 9
556 #define OMAP3430_AUTO_GPT7 (1 << 8)
557 #define OMAP3430_AUTO_GPT7_SHIFT 8
558 #define OMAP3430_AUTO_GPT6 (1 << 7)
559 #define OMAP3430_AUTO_GPT6_SHIFT 7
560 #define OMAP3430_AUTO_GPT5 (1 << 6)
561 #define OMAP3430_AUTO_GPT5_SHIFT 6
562 #define OMAP3430_AUTO_GPT4 (1 << 5)
563 #define OMAP3430_AUTO_GPT4_SHIFT 5
564 #define OMAP3430_AUTO_GPT3 (1 << 4)
565 #define OMAP3430_AUTO_GPT3_SHIFT 4
566 #define OMAP3430_AUTO_GPT2 (1 << 3)
567 #define OMAP3430_AUTO_GPT2_SHIFT 3
568 #define OMAP3430_AUTO_MCBSP4 (1 << 2)
569 #define OMAP3430_AUTO_MCBSP4_SHIFT 2
570 #define OMAP3430_AUTO_MCBSP3 (1 << 1)
571 #define OMAP3430_AUTO_MCBSP3_SHIFT 1
572 #define OMAP3430_AUTO_MCBSP2 (1 << 0)
573 #define OMAP3430_AUTO_MCBSP2_SHIFT 0
576 #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
577 #define OMAP3430_CLKSEL_GPT9_SHIFT 7
578 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
579 #define OMAP3430_CLKSEL_GPT8_SHIFT 6
580 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
581 #define OMAP3430_CLKSEL_GPT7_SHIFT 5
582 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
583 #define OMAP3430_CLKSEL_GPT6_SHIFT 4
584 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
585 #define OMAP3430_CLKSEL_GPT5_SHIFT 3
586 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
587 #define OMAP3430_CLKSEL_GPT4_SHIFT 2
588 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
589 #define OMAP3430_CLKSEL_GPT3_SHIFT 1
590 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
591 #define OMAP3430_CLKSEL_GPT2_SHIFT 0
593 /* CM_SLEEPDEP_PER specific bits */
594 #define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2 (1 << 2)
596 /* CM_CLKSTCTRL_PER */
597 #define OMAP3430_CLKTRCTRL_PER_SHIFT 0
598 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
601 #define OMAP3430_CLKACTIVITY_PER (1 << 0)
604 #define OMAP3430_DIV_DPLL4_SHIFT 24
605 #define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
606 #define OMAP3430_DIV_DPLL3_SHIFT 16
607 #define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
608 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
609 #define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
610 #define OMAP3430_CLKSEL_PCLK_SHIFT 8
611 #define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
612 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
613 #define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
614 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4
615 #define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
616 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
617 #define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
618 #define OMAP3430_MUX_CTRL_SHIFT 0
619 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
621 /* CM_CLKSTCTRL_EMU */
622 #define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
623 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
626 #define OMAP3430_CLKACTIVITY_EMU (1 << 0)
628 /* CM_CLKSEL2_EMU specific bits */
629 #define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
630 #define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
631 #define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
632 #define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
634 /* CM_CLKSEL3_EMU specific bits */
635 #define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
636 #define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
637 #define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
638 #define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
641 #define OMAP3430_CLKOUT2_POL (1 << 0)
644 #define OMAP3430_ST_NEON (1 << 0)
646 /* CM_CLKSTCTRL_NEON */
647 #define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
648 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
650 /* CM_FCLKEN_USBHOST */
651 #define OMAP3430ES2_EN_USBHOST2_SHIFT 1
652 #define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
653 #define OMAP3430ES2_EN_USBHOST1_SHIFT 0
654 #define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
656 /* CM_ICLKEN_USBHOST */
657 #define OMAP3430ES2_EN_USBHOST_SHIFT 0
658 #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
660 /* CM_IDLEST_USBHOST */
662 /* CM_AUTOIDLE_USBHOST */
663 #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
664 #define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
666 /* CM_SLEEPDEP_USBHOST */
667 #define OMAP3430ES2_EN_MPU_SHIFT 1
668 #define OMAP3430ES2_EN_MPU_MASK (1 << 1)
669 #define OMAP3430ES2_EN_IVA2_SHIFT 2
670 #define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
672 /* CM_CLKSTCTRL_USBHOST */
673 #define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
674 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
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