1 /* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2440 Clock support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/device.h>
31 #include <linux/sysdev.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
36 #include <asm/hardware.h>
37 #include <asm/atomic.h>
41 #include <asm/hardware/clock.h>
42 #include <asm/arch/regs-clock.h>
47 /* S3C2440 extended clock support */
49 static struct clk s3c2440_clk_upll = {
54 static struct clk s3c2440_clk_cam = {
57 .enable = s3c24xx_clkcon_enable,
58 .ctrlbit = S3C2440_CLKCON_CAMERA,
61 static struct clk s3c2440_clk_ac97 = {
64 .enable = s3c24xx_clkcon_enable,
65 .ctrlbit = S3C2440_CLKCON_CAMERA,
68 static int s3c2440_clk_add(struct sys_device *sysdev)
70 unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
71 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
76 clk_xtal = clk_get(NULL, "xtal");
77 if (IS_ERR(clk_xtal)) {
78 printk(KERN_ERR "S3C2440: Failed to get clk_xtal\n");
82 s3c2440_clk_upll.rate = s3c2410_get_pll(upllcon, clk_xtal->rate);
84 printk("S3C2440: Clock Support, UPLL %ld.%03ld MHz, DVS %s\n",
85 print_mhz(s3c2440_clk_upll.rate),
86 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
88 clk_p = clk_get(NULL, "pclk");
89 clk_h = clk_get(NULL, "hclk");
91 if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
92 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
96 s3c2440_clk_cam.parent = clk_h;
97 s3c2440_clk_ac97.parent = clk_p;
99 s3c24xx_register_clock(&s3c2440_clk_ac97);
100 s3c24xx_register_clock(&s3c2440_clk_cam);
101 s3c24xx_register_clock(&s3c2440_clk_upll);
103 clk_disable(&s3c2440_clk_ac97);
104 clk_disable(&s3c2440_clk_cam);
109 static struct sysdev_driver s3c2440_clk_driver = {
110 .add = s3c2440_clk_add,
113 static __init int s3c24xx_clk_driver(void)
115 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
118 arch_initcall(s3c24xx_clk_driver);