2 * Performance counter support for POWER7 processors.
4 * Copyright 2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/perf_counter.h>
16 * Bits in event code for POWER7
18 #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
19 #define PM_PMC_MSK 0xf
20 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
21 #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
22 #define PM_UNIT_MSK 0xf
23 #define PM_COMBINE_SH 11 /* Combined event bit */
24 #define PM_COMBINE_MSK 1
25 #define PM_COMBINE_MSKS 0x800
26 #define PM_L2SEL_SH 8 /* L2 event select */
27 #define PM_L2SEL_MSK 7
28 #define PM_PMCSEL_MSK 0xff
31 * Bits in MMCR1 for POWER7
33 #define MMCR1_TTM0SEL_SH 60
34 #define MMCR1_TTM1SEL_SH 56
35 #define MMCR1_TTM2SEL_SH 52
36 #define MMCR1_TTM3SEL_SH 48
37 #define MMCR1_TTMSEL_MSK 0xf
38 #define MMCR1_L2SEL_SH 45
39 #define MMCR1_L2SEL_MSK 7
40 #define MMCR1_PMC1_COMBINE_SH 35
41 #define MMCR1_PMC2_COMBINE_SH 34
42 #define MMCR1_PMC3_COMBINE_SH 33
43 #define MMCR1_PMC4_COMBINE_SH 32
44 #define MMCR1_PMC1SEL_SH 24
45 #define MMCR1_PMC2SEL_SH 16
46 #define MMCR1_PMC3SEL_SH 8
47 #define MMCR1_PMC4SEL_SH 0
48 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
49 #define MMCR1_PMCSEL_MSK 0xff
56 * Layout of constraint bits:
57 * 6666555555555544444444443333333333222222222211111111110000000000
58 * 3210987654321098765432109876543210987654321098765432109876543210
62 * NC - number of counters
64 * 12-14: number of events needing PMC1-4 0x7000
68 * 10-11: Count of events needing PMC6
71 * 0-9: Count of events needing PMC1..PMC5
74 static int power7_get_constraint(u64 event, unsigned long *maskp,
78 unsigned long mask = 0, value = 0;
80 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
87 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
91 /* need a counter from PMC1-4 set */
100 #define MAX_ALT 2 /* at most 2 alternatives for any event */
102 static const unsigned int event_alternatives[][MAX_ALT] = {
103 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */
104 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
105 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
109 * Scan the alternatives table for a match and return the
110 * index into the alternatives table if found, else -1.
112 static int find_alternative(u64 event)
116 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
117 if (event < event_alternatives[i][0])
119 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
120 if (event == event_alternatives[i][j])
126 static s64 find_alternative_decode(u64 event)
130 /* this only handles the 4x decode events */
131 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
132 psel = event & PM_PMCSEL_MSK;
133 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
134 return event - (1 << PM_PMC_SH) + 8;
135 if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
136 return event + (1 << PM_PMC_SH) - 8;
140 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
147 i = find_alternative(event);
149 for (j = 0; j < MAX_ALT; ++j) {
150 ae = event_alternatives[i][j];
151 if (ae && ae != event)
155 ae = find_alternative_decode(event);
160 if (flags & PPMU_ONLY_COUNT_RUN) {
162 * We're only counting in RUN state,
163 * so PM_CYC is equivalent to PM_RUN_CYC
164 * and PM_INST_CMPL === PM_RUN_INST_CMPL.
165 * This doesn't include alternatives that don't provide
166 * any extra flexibility in assigning PMCs.
169 for (i = 0; i < nalt; ++i) {
171 case 0x1e: /* PM_CYC */
172 alt[j++] = 0x600f4; /* PM_RUN_CYC */
174 case 0x600f4: /* PM_RUN_CYC */
177 case 0x2: /* PM_PPC_CMPL */
178 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
180 case 0x500fa: /* PM_RUN_INST_CMPL */
181 alt[j++] = 0x2; /* PM_PPC_CMPL */
192 * Returns 1 if event counts things relating to marked instructions
193 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
195 static int power7_marked_instr_event(u64 event)
200 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
201 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
202 psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
208 return pmc == 2 || pmc == 4;
227 static int power7_compute_mmcr(u64 event[], int n_ev,
228 unsigned int hwc[], unsigned long mmcr[])
230 unsigned long mmcr1 = 0;
231 unsigned long mmcra = 0;
232 unsigned int pmc, unit, combine, l2sel, psel;
233 unsigned int pmc_inuse = 0;
236 /* First pass to count resource use */
237 for (i = 0; i < n_ev; ++i) {
238 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
242 if (pmc_inuse & (1 << (pmc - 1)))
244 pmc_inuse |= 1 << (pmc - 1);
248 /* Second pass: assign PMCs, set all MMCR1 fields */
249 for (i = 0; i < n_ev; ++i) {
250 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
251 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
252 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
253 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
254 psel = event[i] & PM_PMCSEL_MSK;
256 /* Bus event or any-PMC direct event */
257 for (pmc = 0; pmc < 4; ++pmc) {
258 if (!(pmc_inuse & (1 << pmc)))
263 pmc_inuse |= 1 << pmc;
265 /* Direct or decoded event */
269 mmcr1 |= (unsigned long) unit
270 << (MMCR1_TTM0SEL_SH - 4 * pmc);
271 mmcr1 |= (unsigned long) combine
272 << (MMCR1_PMC1_COMBINE_SH - pmc);
273 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
274 if (unit == 6) /* L2 events */
275 mmcr1 |= (unsigned long) l2sel
278 if (power7_marked_instr_event(event[i]))
279 mmcra |= MMCRA_SAMPLE_ENABLE;
283 /* Return MMCRx values */
286 mmcr[0] = MMCR0_PMC1CE;
287 if (pmc_inuse & 0x3e)
288 mmcr[0] |= MMCR0_PMCjCE;
294 static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
297 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
300 static int power7_generic_events[] = {
301 [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
302 [PERF_COUNT_HW_INSTRUCTIONS] = 2,
303 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/
304 [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */
305 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */
306 [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */
309 #define C(x) PERF_COUNT_HW_CACHE_##x
312 * Table of generalized cache-related events.
313 * 0 means not supported, -1 means nonsensical, other values
316 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
317 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
318 [C(OP_READ)] = { 0x400f0, 0xc880 },
319 [C(OP_WRITE)] = { 0, 0x300f0 },
320 [C(OP_PREFETCH)] = { 0xd8b8, 0 },
322 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
323 [C(OP_READ)] = { 0, 0x200fc },
324 [C(OP_WRITE)] = { -1, -1 },
325 [C(OP_PREFETCH)] = { 0x408a, 0 },
327 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
328 [C(OP_READ)] = { 0x6080, 0x6084 },
329 [C(OP_WRITE)] = { 0x6082, 0x6086 },
330 [C(OP_PREFETCH)] = { 0, 0 },
332 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
333 [C(OP_READ)] = { 0, 0x300fc },
334 [C(OP_WRITE)] = { -1, -1 },
335 [C(OP_PREFETCH)] = { -1, -1 },
337 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
338 [C(OP_READ)] = { 0, 0x400fc },
339 [C(OP_WRITE)] = { -1, -1 },
340 [C(OP_PREFETCH)] = { -1, -1 },
342 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
343 [C(OP_READ)] = { 0x10068, 0x400f6 },
344 [C(OP_WRITE)] = { -1, -1 },
345 [C(OP_PREFETCH)] = { -1, -1 },
349 struct power_pmu power7_pmu = {
351 .max_alternatives = MAX_ALT + 1,
352 .add_fields = 0x1555ul,
353 .test_adder = 0x3000ul,
354 .compute_mmcr = power7_compute_mmcr,
355 .get_constraint = power7_get_constraint,
356 .get_alternatives = power7_get_alternatives,
357 .disable_pmc = power7_disable_pmc,
358 .n_generic = ARRAY_SIZE(power7_generic_events),
359 .generic_events = power7_generic_events,
360 .cache_events = &power7_cache_events,