perf_counter: powerpc: Use unsigned long for register and constraint values
[linux-2.6] / arch / powerpc / kernel / power7-pmu.c
1 /*
2  * Performance counter support for POWER7 processors.
3  *
4  * Copyright 2009 Paul Mackerras, IBM Corporation.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 #include <linux/kernel.h>
12 #include <linux/perf_counter.h>
13 #include <asm/reg.h>
14
15 /*
16  * Bits in event code for POWER7
17  */
18 #define PM_PMC_SH       16      /* PMC number (1-based) for direct events */
19 #define PM_PMC_MSK      0xf
20 #define PM_PMC_MSKS     (PM_PMC_MSK << PM_PMC_SH)
21 #define PM_UNIT_SH      12      /* TTMMUX number and setting - unit select */
22 #define PM_UNIT_MSK     0xf
23 #define PM_COMBINE_SH   11      /* Combined event bit */
24 #define PM_COMBINE_MSK  1
25 #define PM_COMBINE_MSKS 0x800
26 #define PM_L2SEL_SH     8       /* L2 event select */
27 #define PM_L2SEL_MSK    7
28 #define PM_PMCSEL_MSK   0xff
29
30 /*
31  * Bits in MMCR1 for POWER7
32  */
33 #define MMCR1_TTM0SEL_SH        60
34 #define MMCR1_TTM1SEL_SH        56
35 #define MMCR1_TTM2SEL_SH        52
36 #define MMCR1_TTM3SEL_SH        48
37 #define MMCR1_TTMSEL_MSK        0xf
38 #define MMCR1_L2SEL_SH          45
39 #define MMCR1_L2SEL_MSK         7
40 #define MMCR1_PMC1_COMBINE_SH   35
41 #define MMCR1_PMC2_COMBINE_SH   34
42 #define MMCR1_PMC3_COMBINE_SH   33
43 #define MMCR1_PMC4_COMBINE_SH   32
44 #define MMCR1_PMC1SEL_SH        24
45 #define MMCR1_PMC2SEL_SH        16
46 #define MMCR1_PMC3SEL_SH        8
47 #define MMCR1_PMC4SEL_SH        0
48 #define MMCR1_PMCSEL_SH(n)      (MMCR1_PMC1SEL_SH - (n) * 8)
49 #define MMCR1_PMCSEL_MSK        0xff
50
51 /*
52  * Bits in MMCRA
53  */
54
55 /*
56  * Layout of constraint bits:
57  * 6666555555555544444444443333333333222222222211111111110000000000
58  * 3210987654321098765432109876543210987654321098765432109876543210
59  *                                                 [  ><><><><><><>
60  *                                                  NC P6P5P4P3P2P1
61  *
62  * NC - number of counters
63  *     15: NC error 0x8000
64  *     12-14: number of events needing PMC1-4 0x7000
65  *
66  * P6
67  *     11: P6 error 0x800
68  *     10-11: Count of events needing PMC6
69  *
70  * P1..P5
71  *     0-9: Count of events needing PMC1..PMC5
72  */
73
74 static int power7_get_constraint(u64 event, unsigned long *maskp,
75                                  unsigned long *valp)
76 {
77         int pmc, sh;
78         unsigned long mask = 0, value = 0;
79
80         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
81         if (pmc) {
82                 if (pmc > 6)
83                         return -1;
84                 sh = (pmc - 1) * 2;
85                 mask |= 2 << sh;
86                 value |= 1 << sh;
87                 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
88                         return -1;
89         }
90         if (pmc < 5) {
91                 /* need a counter from PMC1-4 set */
92                 mask  |= 0x8000;
93                 value |= 0x1000;
94         }
95         *maskp = mask;
96         *valp = value;
97         return 0;
98 }
99
100 #define MAX_ALT 2       /* at most 2 alternatives for any event */
101
102 static const unsigned int event_alternatives[][MAX_ALT] = {
103         { 0x200f2, 0x300f2 },           /* PM_INST_DISP */
104         { 0x200f4, 0x600f4 },           /* PM_RUN_CYC */
105         { 0x400fa, 0x500fa },           /* PM_RUN_INST_CMPL */
106 };
107
108 /*
109  * Scan the alternatives table for a match and return the
110  * index into the alternatives table if found, else -1.
111  */
112 static int find_alternative(u64 event)
113 {
114         int i, j;
115
116         for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
117                 if (event < event_alternatives[i][0])
118                         break;
119                 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
120                         if (event == event_alternatives[i][j])
121                                 return i;
122         }
123         return -1;
124 }
125
126 static s64 find_alternative_decode(u64 event)
127 {
128         int pmc, psel;
129
130         /* this only handles the 4x decode events */
131         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
132         psel = event & PM_PMCSEL_MSK;
133         if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
134                 return event - (1 << PM_PMC_SH) + 8;
135         if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
136                 return event + (1 << PM_PMC_SH) - 8;
137         return -1;
138 }
139
140 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
141 {
142         int i, j, nalt = 1;
143         s64 ae;
144
145         alt[0] = event;
146         nalt = 1;
147         i = find_alternative(event);
148         if (i >= 0) {
149                 for (j = 0; j < MAX_ALT; ++j) {
150                         ae = event_alternatives[i][j];
151                         if (ae && ae != event)
152                                 alt[nalt++] = ae;
153                 }
154         } else {
155                 ae = find_alternative_decode(event);
156                 if (ae > 0)
157                         alt[nalt++] = ae;
158         }
159
160         if (flags & PPMU_ONLY_COUNT_RUN) {
161                 /*
162                  * We're only counting in RUN state,
163                  * so PM_CYC is equivalent to PM_RUN_CYC
164                  * and PM_INST_CMPL === PM_RUN_INST_CMPL.
165                  * This doesn't include alternatives that don't provide
166                  * any extra flexibility in assigning PMCs.
167                  */
168                 j = nalt;
169                 for (i = 0; i < nalt; ++i) {
170                         switch (alt[i]) {
171                         case 0x1e:      /* PM_CYC */
172                                 alt[j++] = 0x600f4;     /* PM_RUN_CYC */
173                                 break;
174                         case 0x600f4:   /* PM_RUN_CYC */
175                                 alt[j++] = 0x1e;
176                                 break;
177                         case 0x2:       /* PM_PPC_CMPL */
178                                 alt[j++] = 0x500fa;     /* PM_RUN_INST_CMPL */
179                                 break;
180                         case 0x500fa:   /* PM_RUN_INST_CMPL */
181                                 alt[j++] = 0x2; /* PM_PPC_CMPL */
182                                 break;
183                         }
184                 }
185                 nalt = j;
186         }
187
188         return nalt;
189 }
190
191 /*
192  * Returns 1 if event counts things relating to marked instructions
193  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
194  */
195 static int power7_marked_instr_event(u64 event)
196 {
197         int pmc, psel;
198         int unit;
199
200         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
201         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
202         psel = event & PM_PMCSEL_MSK & ~1;      /* trim off edge/level bit */
203         if (pmc >= 5)
204                 return 0;
205
206         switch (psel >> 4) {
207         case 2:
208                 return pmc == 2 || pmc == 4;
209         case 3:
210                 if (psel == 0x3c)
211                         return pmc == 1;
212                 if (psel == 0x3e)
213                         return pmc != 2;
214                 return 1;
215         case 4:
216         case 5:
217                 return unit == 0xd;
218         case 6:
219                 if (psel == 0x64)
220                         return pmc >= 3;
221         case 8:
222                 return unit == 0xd;
223         }
224         return 0;
225 }
226
227 static int power7_compute_mmcr(u64 event[], int n_ev,
228                                unsigned int hwc[], unsigned long mmcr[])
229 {
230         unsigned long mmcr1 = 0;
231         unsigned long mmcra = 0;
232         unsigned int pmc, unit, combine, l2sel, psel;
233         unsigned int pmc_inuse = 0;
234         int i;
235
236         /* First pass to count resource use */
237         for (i = 0; i < n_ev; ++i) {
238                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
239                 if (pmc) {
240                         if (pmc > 6)
241                                 return -1;
242                         if (pmc_inuse & (1 << (pmc - 1)))
243                                 return -1;
244                         pmc_inuse |= 1 << (pmc - 1);
245                 }
246         }
247
248         /* Second pass: assign PMCs, set all MMCR1 fields */
249         for (i = 0; i < n_ev; ++i) {
250                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
251                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
252                 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
253                 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
254                 psel = event[i] & PM_PMCSEL_MSK;
255                 if (!pmc) {
256                         /* Bus event or any-PMC direct event */
257                         for (pmc = 0; pmc < 4; ++pmc) {
258                                 if (!(pmc_inuse & (1 << pmc)))
259                                         break;
260                         }
261                         if (pmc >= 4)
262                                 return -1;
263                         pmc_inuse |= 1 << pmc;
264                 } else {
265                         /* Direct or decoded event */
266                         --pmc;
267                 }
268                 if (pmc <= 3) {
269                         mmcr1 |= (unsigned long) unit
270                                 << (MMCR1_TTM0SEL_SH - 4 * pmc);
271                         mmcr1 |= (unsigned long) combine
272                                 << (MMCR1_PMC1_COMBINE_SH - pmc);
273                         mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
274                         if (unit == 6)  /* L2 events */
275                                 mmcr1 |= (unsigned long) l2sel
276                                         << MMCR1_L2SEL_SH;
277                 }
278                 if (power7_marked_instr_event(event[i]))
279                         mmcra |= MMCRA_SAMPLE_ENABLE;
280                 hwc[i] = pmc;
281         }
282
283         /* Return MMCRx values */
284         mmcr[0] = 0;
285         if (pmc_inuse & 1)
286                 mmcr[0] = MMCR0_PMC1CE;
287         if (pmc_inuse & 0x3e)
288                 mmcr[0] |= MMCR0_PMCjCE;
289         mmcr[1] = mmcr1;
290         mmcr[2] = mmcra;
291         return 0;
292 }
293
294 static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
295 {
296         if (pmc <= 3)
297                 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
298 }
299
300 static int power7_generic_events[] = {
301         [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
302         [PERF_COUNT_HW_INSTRUCTIONS] = 2,
303         [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880,      /* LD_REF_L1_LSU*/
304         [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0,         /* LD_MISS_L1   */
305         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068,  /* BRU_FIN      */
306         [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6,        /* BR_MPRED     */
307 };
308
309 #define C(x)    PERF_COUNT_HW_CACHE_##x
310
311 /*
312  * Table of generalized cache-related events.
313  * 0 means not supported, -1 means nonsensical, other values
314  * are event codes.
315  */
316 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
317         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
318                 [C(OP_READ)] = {        0x400f0,        0xc880  },
319                 [C(OP_WRITE)] = {       0,              0x300f0 },
320                 [C(OP_PREFETCH)] = {    0xd8b8,         0       },
321         },
322         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
323                 [C(OP_READ)] = {        0,              0x200fc },
324                 [C(OP_WRITE)] = {       -1,             -1      },
325                 [C(OP_PREFETCH)] = {    0x408a,         0       },
326         },
327         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
328                 [C(OP_READ)] = {        0x6080,         0x6084  },
329                 [C(OP_WRITE)] = {       0x6082,         0x6086  },
330                 [C(OP_PREFETCH)] = {    0,              0       },
331         },
332         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
333                 [C(OP_READ)] = {        0,              0x300fc },
334                 [C(OP_WRITE)] = {       -1,             -1      },
335                 [C(OP_PREFETCH)] = {    -1,             -1      },
336         },
337         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
338                 [C(OP_READ)] = {        0,              0x400fc },
339                 [C(OP_WRITE)] = {       -1,             -1      },
340                 [C(OP_PREFETCH)] = {    -1,             -1      },
341         },
342         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
343                 [C(OP_READ)] = {        0x10068,        0x400f6 },
344                 [C(OP_WRITE)] = {       -1,             -1      },
345                 [C(OP_PREFETCH)] = {    -1,             -1      },
346         },
347 };
348
349 struct power_pmu power7_pmu = {
350         .n_counter              = 6,
351         .max_alternatives       = MAX_ALT + 1,
352         .add_fields             = 0x1555ul,
353         .test_adder             = 0x3000ul,
354         .compute_mmcr           = power7_compute_mmcr,
355         .get_constraint         = power7_get_constraint,
356         .get_alternatives       = power7_get_alternatives,
357         .disable_pmc            = power7_disable_pmc,
358         .n_generic              = ARRAY_SIZE(power7_generic_events),
359         .generic_events         = power7_generic_events,
360         .cache_events           = &power7_cache_events,
361 };