Merge git://git.infradead.org/~dhowells/irq-2.6
[linux-2.6] / arch / powerpc / sysdev / todc.c
1 /*
2  * Time of Day Clock support for the M48T35, M48T37, M48T59, and MC146818
3  * Real Time Clocks/Timekeepers.
4  *
5  * Author: Mark A. Greer <mgreer@mvista.com>
6  *
7  * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
8  * the terms of the GNU General Public License version 2.  This program
9  * is licensed "as is" without any warranty of any kind, whether express
10  * or implied.
11  */
12 #include <linux/errno.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/time.h>
16 #include <linux/timex.h>
17 #include <linux/bcd.h>
18 #include <linux/mc146818rtc.h>
19
20 #include <asm/machdep.h>
21 #include <asm/io.h>
22 #include <asm/time.h>
23 #include <asm/todc.h>
24
25 /*
26  * Depending on the hardware on your board and your board design, the
27  * RTC/NVRAM may be accessed either directly (like normal memory) or via
28  * address/data registers.  If your board uses the direct method, set
29  * 'nvram_data' to the base address of your nvram and leave 'nvram_as0' and
30  * 'nvram_as1' NULL.  If your board uses address/data regs to access nvram,
31  * set 'nvram_as0' to the address of the lower byte, set 'nvram_as1' to the
32  * address of the upper byte (leave NULL if using mc146818), and set
33  * 'nvram_data' to the address of the 8-bit data register.
34  *
35  * Note: Even though the documentation for the various RTC chips say that it
36  *       take up to a second before it starts updating once the 'R' bit is
37  *       cleared, they always seem to update even though we bang on it many
38  *       times a second.  This is true, except for the Dallas Semi 1746/1747
39  *       (possibly others).  Those chips seem to have a real problem whenever
40  *       we set the 'R' bit before reading them, they basically stop counting.
41  *                                              --MAG
42  */
43
44 /*
45  * 'todc_info' should be initialized in your *_setup.c file to
46  * point to a fully initialized 'todc_info_t' structure.
47  * This structure holds all the register offsets for your particular
48  * TODC/RTC chip.
49  * TODC_ALLOC()/TODC_INIT() will allocate and initialize this table for you.
50  */
51
52 #ifdef  RTC_FREQ_SELECT
53 #undef  RTC_FREQ_SELECT
54 #define RTC_FREQ_SELECT         control_b       /* Register A */
55 #endif
56
57 #ifdef  RTC_CONTROL
58 #undef  RTC_CONTROL
59 #define RTC_CONTROL             control_a       /* Register B */
60 #endif
61
62 #ifdef  RTC_INTR_FLAGS
63 #undef  RTC_INTR_FLAGS
64 #define RTC_INTR_FLAGS          watchdog        /* Register C */
65 #endif
66
67 #ifdef  RTC_VALID
68 #undef  RTC_VALID
69 #define RTC_VALID               interrupts      /* Register D */
70 #endif
71
72 /* Access routines when RTC accessed directly (like normal memory) */
73 u_char
74 todc_direct_read_val(int addr)
75 {
76         return readb((void __iomem *)(todc_info->nvram_data + addr));
77 }
78
79 void
80 todc_direct_write_val(int addr, unsigned char val)
81 {
82         writeb(val, (void __iomem *)(todc_info->nvram_data + addr));
83         return;
84 }
85
86 /* Access routines for accessing m48txx type chips via addr/data regs */
87 u_char
88 todc_m48txx_read_val(int addr)
89 {
90         outb(addr, todc_info->nvram_as0);
91         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
92         return inb(todc_info->nvram_data);
93 }
94
95 void
96 todc_m48txx_write_val(int addr, unsigned char val)
97 {
98         outb(addr, todc_info->nvram_as0);
99         outb(addr>>todc_info->as0_bits, todc_info->nvram_as1);
100         outb(val, todc_info->nvram_data);
101         return;
102 }
103
104 /* Access routines for accessing mc146818 type chips via addr/data regs */
105 u_char
106 todc_mc146818_read_val(int addr)
107 {
108         outb_p(addr, todc_info->nvram_as0);
109         return inb_p(todc_info->nvram_data);
110 }
111
112 void
113 todc_mc146818_write_val(int addr, unsigned char val)
114 {
115         outb_p(addr, todc_info->nvram_as0);
116         outb_p(val, todc_info->nvram_data);
117 }
118
119
120 /*
121  * Routines to make RTC chips with NVRAM buried behind an addr/data pair
122  * have the NVRAM and clock regs appear at the same level.
123  * The NVRAM will appear to start at addr 0 and the clock regs will appear
124  * to start immediately after the NVRAM (actually, start at offset
125  * todc_info->nvram_size).
126  */
127 static inline u_char
128 todc_read_val(int addr)
129 {
130         u_char  val;
131
132         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
133                 if (addr < todc_info->nvram_size) { /* NVRAM */
134                         ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
135                         val = ppc_md.rtc_read_val(todc_info->nvram_data_reg);
136                 } else { /* Clock Reg */
137                         addr -= todc_info->nvram_size;
138                         val = ppc_md.rtc_read_val(addr);
139                 }
140         } else
141                 val = ppc_md.rtc_read_val(addr);
142
143         return val;
144 }
145
146 static inline void
147 todc_write_val(int addr, u_char val)
148 {
149         if (todc_info->sw_flags & TODC_FLAG_2_LEVEL_NVRAM) {
150                 if (addr < todc_info->nvram_size) { /* NVRAM */
151                         ppc_md.rtc_write_val(todc_info->nvram_addr_reg, addr);
152                         ppc_md.rtc_write_val(todc_info->nvram_data_reg, val);
153                 } else { /* Clock Reg */
154                         addr -= todc_info->nvram_size;
155                         ppc_md.rtc_write_val(addr, val);
156                 }
157         } else
158                 ppc_md.rtc_write_val(addr, val);
159 }
160
161 /*
162  * TODC routines
163  *
164  * There is some ugly stuff in that there are assumptions for the mc146818.
165  *
166  * Assumptions:
167  *      - todc_info->control_a has the offset as mc146818 Register B reg
168  *      - todc_info->control_b has the offset as mc146818 Register A reg
169  *      - m48txx control reg's write enable or 'W' bit is same as
170  *        mc146818 Register B 'SET' bit (i.e., 0x80)
171  *
172  * These assumptions were made to make the code simpler.
173  */
174 long __init
175 todc_time_init(void)
176 {
177         u_char  cntl_b;
178
179         if (!ppc_md.rtc_read_val)
180                 ppc_md.rtc_read_val = ppc_md.nvram_read_val;
181         if (!ppc_md.rtc_write_val)
182                 ppc_md.rtc_write_val = ppc_md.nvram_write_val;
183
184         cntl_b = todc_read_val(todc_info->control_b);
185
186         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
187                 if ((cntl_b & 0x70) != 0x20) {
188                         printk(KERN_INFO "TODC real-time-clock was stopped."
189                                 "  Now starting...");
190                         cntl_b &= ~0x70;
191                         cntl_b |= 0x20;
192                 }
193
194                 todc_write_val(todc_info->control_b, cntl_b);
195         } else if (todc_info->rtc_type == TODC_TYPE_DS17285) {
196                 u_char mode;
197
198                 mode = todc_read_val(TODC_TYPE_DS17285_CNTL_A);
199                 /* Make sure countdown clear is not set */
200                 mode &= ~0x40;
201                 /* Enable oscillator, extended register set */
202                 mode |= 0x30;
203                 todc_write_val(TODC_TYPE_DS17285_CNTL_A, mode);
204
205         } else if (todc_info->rtc_type == TODC_TYPE_DS1501) {
206                 u_char  month;
207
208                 todc_info->enable_read = TODC_DS1501_CNTL_B_TE;
209                 todc_info->enable_write = TODC_DS1501_CNTL_B_TE;
210
211                 month = todc_read_val(todc_info->month);
212
213                 if ((month & 0x80) == 0x80) {
214                         printk(KERN_INFO "TODC %s %s\n",
215                                 "real-time-clock was stopped.",
216                                 "Now starting...");
217                         month &= ~0x80;
218                         todc_write_val(todc_info->month, month);
219                 }
220
221                 cntl_b &= ~TODC_DS1501_CNTL_B_TE;
222                 todc_write_val(todc_info->control_b, cntl_b);
223         } else { /* must be a m48txx type */
224                 u_char  cntl_a;
225
226                 todc_info->enable_read = TODC_MK48TXX_CNTL_A_R;
227                 todc_info->enable_write = TODC_MK48TXX_CNTL_A_W;
228
229                 cntl_a = todc_read_val(todc_info->control_a);
230
231                 /* Check & clear STOP bit in control B register */
232                 if (cntl_b & TODC_MK48TXX_DAY_CB) {
233                         printk(KERN_INFO "TODC %s %s\n",
234                                 "real-time-clock was stopped.",
235                                 "Now starting...");
236
237                         cntl_a |= todc_info->enable_write;
238                         cntl_b &= ~TODC_MK48TXX_DAY_CB;/* Start Oscil */
239
240                         todc_write_val(todc_info->control_a, cntl_a);
241                         todc_write_val(todc_info->control_b, cntl_b);
242                 }
243
244                 /* Make sure READ & WRITE bits are cleared. */
245                 cntl_a &= ~(todc_info->enable_write | todc_info->enable_read);
246                 todc_write_val(todc_info->control_a, cntl_a);
247         }
248
249         return 0;
250 }
251
252 /*
253  * There is some ugly stuff in that there are assumptions that for a mc146818,
254  * the todc_info->control_a has the offset of the mc146818 Register B reg and
255  * that the register'ss 'SET' bit is the same as the m48txx's write enable
256  * bit in the control register of the m48txx (i.e., 0x80).
257  *
258  * It was done to make the code look simpler.
259  */
260 void
261 todc_get_rtc_time(struct rtc_time *tm)
262 {
263         uint    year = 0, mon = 0, mday = 0, hour = 0, min = 0, sec = 0;
264         uint    limit, i;
265         u_char  save_control, uip = 0;
266         extern void GregorianDay(struct rtc_time *);
267
268         spin_lock(&rtc_lock);
269         save_control = todc_read_val(todc_info->control_a);
270
271         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
272                 limit = 1;
273
274                 switch (todc_info->rtc_type) {
275                 case TODC_TYPE_DS1553:
276                 case TODC_TYPE_DS1557:
277                 case TODC_TYPE_DS1743:
278                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
279                 case TODC_TYPE_DS1747:
280                 case TODC_TYPE_DS17285:
281                         break;
282                 default:
283                         todc_write_val(todc_info->control_a,
284                                 (save_control | todc_info->enable_read));
285                 }
286         } else
287                 limit = 100000000;
288
289         for (i=0; i<limit; i++) {
290                 if (todc_info->rtc_type == TODC_TYPE_MC146818)
291                         uip = todc_read_val(todc_info->RTC_FREQ_SELECT);
292
293                 sec = todc_read_val(todc_info->seconds) & 0x7f;
294                 min = todc_read_val(todc_info->minutes) & 0x7f;
295                 hour = todc_read_val(todc_info->hours) & 0x3f;
296                 mday = todc_read_val(todc_info->day_of_month) & 0x3f;
297                 mon = todc_read_val(todc_info->month) & 0x1f;
298                 year = todc_read_val(todc_info->year) & 0xff;
299
300                 if (todc_info->rtc_type == TODC_TYPE_MC146818) {
301                         uip |= todc_read_val(todc_info->RTC_FREQ_SELECT);
302                         if ((uip & RTC_UIP) == 0)
303                                 break;
304                 }
305         }
306
307         if (todc_info->rtc_type != TODC_TYPE_MC146818) {
308                 switch (todc_info->rtc_type) {
309                 case TODC_TYPE_DS1553:
310                 case TODC_TYPE_DS1557:
311                 case TODC_TYPE_DS1743:
312                 case TODC_TYPE_DS1746:  /* XXXX BAD HACK -> FIX */
313                 case TODC_TYPE_DS1747:
314                 case TODC_TYPE_DS17285:
315                         break;
316                 default:
317                         save_control &= ~(todc_info->enable_read);
318                         todc_write_val(todc_info->control_a, save_control);
319                 }
320         }
321         spin_unlock(&rtc_lock);
322
323         if ((todc_info->rtc_type != TODC_TYPE_MC146818)
324                         || ((save_control & RTC_DM_BINARY) == 0)
325                         || RTC_ALWAYS_BCD) {
326                 BCD_TO_BIN(sec);
327                 BCD_TO_BIN(min);
328                 BCD_TO_BIN(hour);
329                 BCD_TO_BIN(mday);
330                 BCD_TO_BIN(mon);
331                 BCD_TO_BIN(year);
332         }
333
334         if ((year + 1900) < 1970) {
335                 year += 100;
336         }
337
338         tm->tm_sec = sec;
339         tm->tm_min = min;
340         tm->tm_hour = hour;
341         tm->tm_mday = mday;
342         tm->tm_mon = mon;
343         tm->tm_year = year;
344
345         GregorianDay(tm);
346 }
347
348 int
349 todc_set_rtc_time(struct rtc_time *tm)
350 {
351         u_char save_control, save_freq_select = 0;
352
353         spin_lock(&rtc_lock);
354         save_control = todc_read_val(todc_info->control_a);
355
356         /* Assuming MK48T59_RTC_CA_WRITE & RTC_SET are equal */
357         todc_write_val(todc_info->control_a,
358                 (save_control | todc_info->enable_write));
359         save_control &= ~(todc_info->enable_write); /* in case it was set */
360
361         if (todc_info->rtc_type == TODC_TYPE_MC146818) {
362                 save_freq_select = todc_read_val(todc_info->RTC_FREQ_SELECT);
363                 todc_write_val(todc_info->RTC_FREQ_SELECT,
364                         save_freq_select | RTC_DIV_RESET2);
365         }
366
367         if ((todc_info->rtc_type != TODC_TYPE_MC146818)
368                         || ((save_control & RTC_DM_BINARY) == 0)
369                         || RTC_ALWAYS_BCD) {
370                 BIN_TO_BCD(tm->tm_sec);
371                 BIN_TO_BCD(tm->tm_min);
372                 BIN_TO_BCD(tm->tm_hour);
373                 BIN_TO_BCD(tm->tm_mon);
374                 BIN_TO_BCD(tm->tm_mday);
375                 BIN_TO_BCD(tm->tm_year);
376         }
377
378         todc_write_val(todc_info->seconds, tm->tm_sec);
379         todc_write_val(todc_info->minutes, tm->tm_min);
380         todc_write_val(todc_info->hours, tm->tm_hour);
381         todc_write_val(todc_info->month, tm->tm_mon);
382         todc_write_val(todc_info->day_of_month, tm->tm_mday);
383         todc_write_val(todc_info->year, tm->tm_year);
384
385         todc_write_val(todc_info->control_a, save_control);
386
387         if (todc_info->rtc_type == TODC_TYPE_MC146818)
388                 todc_write_val(todc_info->RTC_FREQ_SELECT, save_freq_select);
389
390         spin_unlock(&rtc_lock);
391         return 0;
392 }