git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink GT serial adapters.
   5  *
   6  * written by Paul Fulghum for Microgate Corporation
   7  * paulkf@microgate.com
   8  *
   9  * Microgate and SyncLink are trademarks of Microgate Corporation
  10  *
  11  * This code is released under the GNU General Public License (GPL)
  12  *
  13  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  14  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  16  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  19  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  22  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  23  * OF THE POSSIBILITY OF SUCH DAMAGE.
  24  */
  25
  26 /*
  27  * DEBUG OUTPUT DEFINITIONS
  28  *
  29  * uncomment lines below to enable specific types of debug output
  30  *
  31  * DBGINFO   information - most verbose output
  32  * DBGERR    serious errors
  33  * DBGBH     bottom half service routine debugging
  34  * DBGISR    interrupt service routine debugging
  35  * DBGDATA   output receive and transmit data
  36  * DBGTBUF   output transmit DMA buffers and registers
  37  * DBGRBUF   output receive DMA buffers and registers
  38  */
  39
  40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  45 //#define DBGTBUF(info) dump_tbufs(info)
  46 //#define DBGRBUF(info) dump_rbufs(info)
  47
  48
  49 #include <linux/module.h>
  50 #include <linux/version.h>
  51 #include <linux/errno.h>
  52 #include <linux/signal.h>
  53 #include <linux/sched.h>
  54 #include <linux/timer.h>
  55 #include <linux/interrupt.h>
  56 #include <linux/pci.h>
  57 #include <linux/tty.h>
  58 #include <linux/tty_flip.h>
  59 #include <linux/serial.h>
  60 #include <linux/major.h>
  61 #include <linux/string.h>
  62 #include <linux/fcntl.h>
  63 #include <linux/ptrace.h>
  64 #include <linux/ioport.h>
  65 #include <linux/mm.h>
  66 #include <linux/slab.h>
  67 #include <linux/netdevice.h>
  68 #include <linux/vmalloc.h>
  69 #include <linux/init.h>
  70 #include <linux/delay.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/termios.h>
  73 #include <linux/bitops.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/hdlc.h>
  76 #include <linux/synclink.h>
  77
  78 #include <asm/system.h>
  79 #include <asm/io.h>
  80 #include <asm/irq.h>
  81 #include <asm/dma.h>
  82 #include <asm/types.h>
  83 #include <asm/uaccess.h>
  84
  85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  86 #define SYNCLINK_GENERIC_HDLC 1
  87 #else
  88 #define SYNCLINK_GENERIC_HDLC 0
  89 #endif
  90
  91 /*
  92  * module identification
  93  */
  94 static char *driver_name     = "SyncLink GT";
  95 static char *driver_version  = "$Revision: 4.50 $";
  96 static char *tty_driver_name = "synclink_gt";
  97 static char *tty_dev_prefix  = "ttySLG";
  98 MODULE_LICENSE("GPL");
  99 #define MGSL_MAGIC 0x5401
 100 #define MAX_DEVICES 32
 101
 102 static struct pci_device_id pci_table[] = {
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 105         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 106         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 107         {0,}, /* terminate list */
 108 };
 109 MODULE_DEVICE_TABLE(pci, pci_table);
 110
 111 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 112 static void remove_one(struct pci_dev *dev);
 113 static struct pci_driver pci_driver = {
 114         .name           = "synclink_gt",
 115         .id_table       = pci_table,
 116         .probe          = init_one,
 117         .remove         = __devexit_p(remove_one),
 118 };
 119
 120 static bool pci_registered;
 121
 122 /*
 123  * module configuration and status
 124  */
 125 static struct slgt_info *slgt_device_list;
 126 static int slgt_device_count;
 127
 128 static int ttymajor;
 129 static int debug_level;
 130 static int maxframe[MAX_DEVICES];
 131 static int dosyncppp[MAX_DEVICES];
 132
 133 module_param(ttymajor, int, 0);
 134 module_param(debug_level, int, 0);
 135 module_param_array(maxframe, int, NULL, 0);
 136 module_param_array(dosyncppp, int, NULL, 0);
 137
 138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
 142
 143 /*
 144  * tty support and callbacks
 145  */
 146 static struct tty_driver *serial_driver;
 147
 148 static int  open(struct tty_struct *tty, struct file * filp);
 149 static void close(struct tty_struct *tty, struct file * filp);
 150 static void hangup(struct tty_struct *tty);
 151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 152
 153 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 154 static int put_char(struct tty_struct *tty, unsigned char ch);
 155 static void send_xchar(struct tty_struct *tty, char ch);
 156 static void wait_until_sent(struct tty_struct *tty, int timeout);
 157 static int  write_room(struct tty_struct *tty);
 158 static void flush_chars(struct tty_struct *tty);
 159 static void flush_buffer(struct tty_struct *tty);
 160 static void tx_hold(struct tty_struct *tty);
 161 static void tx_release(struct tty_struct *tty);
 162
 163 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 164 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 165 static int  chars_in_buffer(struct tty_struct *tty);
 166 static void throttle(struct tty_struct * tty);
 167 static void unthrottle(struct tty_struct * tty);
 168 static void set_break(struct tty_struct *tty, int break_state);
 169
 170 /*
 171  * generic HDLC support and callbacks
 172  */
 173 #if SYNCLINK_GENERIC_HDLC
 174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 175 static void hdlcdev_tx_done(struct slgt_info *info);
 176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 177 static int  hdlcdev_init(struct slgt_info *info);
 178 static void hdlcdev_exit(struct slgt_info *info);
 179 #endif
 180
 181
 182 /*
 183  * device specific structures, macros and functions
 184  */
 185
 186 #define SLGT_MAX_PORTS 4
 187 #define SLGT_REG_SIZE  256
 188
 189 /*
 190  * conditional wait facility
 191  */
 192 struct cond_wait {
 193         struct cond_wait *next;
 194         wait_queue_head_t q;
 195         wait_queue_t wait;
 196         unsigned int data;
 197 };
 198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 201 static void flush_cond_wait(struct cond_wait **head);
 202
 203 /*
 204  * DMA buffer descriptor and access macros
 205  */
 206 struct slgt_desc
 207 {
 208         __le16 count;
 209         __le16 status;
 210         __le32 pbuf;  /* physical address of data buffer */
 211         __le32 next;  /* physical address of next descriptor */
 212
 213         /* driver book keeping */
 214         char *buf;          /* virtual  address of data buffer */
 215         unsigned int pdesc; /* physical address of this descriptor */
 216         dma_addr_t buf_dma_addr;
 217 };
 218
 219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 220 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 221 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 222 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 223 #define desc_count(a)      (le16_to_cpu((a).count))
 224 #define desc_status(a)     (le16_to_cpu((a).status))
 225 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 226 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 227 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 228 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 229 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 230
 231 struct _input_signal_events {
 232         int ri_up;
 233         int ri_down;
 234         int dsr_up;
 235         int dsr_down;
 236         int dcd_up;
 237         int dcd_down;
 238         int cts_up;
 239         int cts_down;
 240 };
 241
 242 /*
 243  * device instance data structure
 244  */
 245 struct slgt_info {
 246         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 247         struct tty_port port;
 248
 249         struct slgt_info *next_device;  /* device list link */
 250
 251         int magic;
 252
 253         char device_name[25];
 254         struct pci_dev *pdev;
 255
 256         int port_count;  /* count of ports on adapter */
 257         int adapter_num; /* adapter instance number */
 258         int port_num;    /* port instance number */
 259
 260         /* array of pointers to port contexts on this adapter */
 261         struct slgt_info *port_array[SLGT_MAX_PORTS];
 262
 263         int                     line;           /* tty line instance number */
 264
 265         struct mgsl_icount      icount;
 266
 267         int                     timeout;
 268         int                     x_char;         /* xon/xoff character */
 269         unsigned int            read_status_mask;
 270         unsigned int            ignore_status_mask;
 271
 272         wait_queue_head_t       status_event_wait_q;
 273         wait_queue_head_t       event_wait_q;
 274         struct timer_list       tx_timer;
 275         struct timer_list       rx_timer;
 276
 277         unsigned int            gpio_present;
 278         struct cond_wait        *gpio_wait_q;
 279
 280         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 281
 282         struct work_struct task;
 283         u32 pending_bh;
 284         bool bh_requested;
 285         bool bh_running;
 286
 287         int isr_overflow;
 288         bool irq_requested;     /* true if IRQ requested */
 289         bool irq_occurred;      /* for diagnostics use */
 290
 291         /* device configuration */
 292
 293         unsigned int bus_type;
 294         unsigned int irq_level;
 295         unsigned long irq_flags;
 296
 297         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 298         u32 phys_reg_addr;
 299         bool reg_addr_requested;
 300
 301         MGSL_PARAMS params;       /* communications parameters */
 302         u32 idle_mode;
 303         u32 max_frame_size;       /* as set by device config */
 304
 305         unsigned int raw_rx_size;
 306         unsigned int if_mode;
 307
 308         /* device status */
 309
 310         bool rx_enabled;
 311         bool rx_restart;
 312
 313         bool tx_enabled;
 314         bool tx_active;
 315
 316         unsigned char signals;    /* serial signal states */
 317         int init_error;  /* initialization error */
 318
 319         unsigned char *tx_buf;
 320         int tx_count;
 321
 322         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 323         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 324         bool drop_rts_on_tx_done;
 325         struct  _input_signal_events    input_signal_events;
 326
 327         int dcd_chkcount;       /* check counts to prevent */
 328         int cts_chkcount;       /* too many IRQs if a signal */
 329         int dsr_chkcount;       /* is floating */
 330         int ri_chkcount;
 331
 332         char *bufs;             /* virtual address of DMA buffer lists */
 333         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 334
 335         unsigned int rbuf_count;
 336         struct slgt_desc *rbufs;
 337         unsigned int rbuf_current;
 338         unsigned int rbuf_index;
 339
 340         unsigned int tbuf_count;
 341         struct slgt_desc *tbufs;
 342         unsigned int tbuf_current;
 343         unsigned int tbuf_start;
 344
 345         unsigned char *tmp_rbuf;
 346         unsigned int tmp_rbuf_count;
 347
 348         /* SPPP/Cisco HDLC device parts */
 349
 350         int netcount;
 351         int dosyncppp;
 352         spinlock_t netlock;
 353 #if SYNCLINK_GENERIC_HDLC
 354         struct net_device *netdev;
 355 #endif
 356
 357 };
 358
 359 static MGSL_PARAMS default_params = {
 360         .mode            = MGSL_MODE_HDLC,
 361         .loopback        = 0,
 362         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 363         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 364         .clock_speed     = 0,
 365         .addr_filter     = 0xff,
 366         .crc_type        = HDLC_CRC_16_CCITT,
 367         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 368         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 369         .data_rate       = 9600,
 370         .data_bits       = 8,
 371         .stop_bits       = 1,
 372         .parity          = ASYNC_PARITY_NONE
 373 };
 374
 375
 376 #define BH_RECEIVE  1
 377 #define BH_TRANSMIT 2
 378 #define BH_STATUS   4
 379 #define IO_PIN_SHUTDOWN_LIMIT 100
 380
 381 #define DMABUFSIZE 256
 382 #define DESC_LIST_SIZE 4096
 383
 384 #define MASK_PARITY  BIT1
 385 #define MASK_FRAMING BIT0
 386 #define MASK_BREAK   BIT14
 387 #define MASK_OVERRUN BIT4
 388
 389 #define GSR   0x00 /* global status */
 390 #define JCR   0x04 /* JTAG control */
 391 #define IODR  0x08 /* GPIO direction */
 392 #define IOER  0x0c /* GPIO interrupt enable */
 393 #define IOVR  0x10 /* GPIO value */
 394 #define IOSR  0x14 /* GPIO interrupt status */
 395 #define TDR   0x80 /* tx data */
 396 #define RDR   0x80 /* rx data */
 397 #define TCR   0x82 /* tx control */
 398 #define TIR   0x84 /* tx idle */
 399 #define TPR   0x85 /* tx preamble */
 400 #define RCR   0x86 /* rx control */
 401 #define VCR   0x88 /* V.24 control */
 402 #define CCR   0x89 /* clock control */
 403 #define BDR   0x8a /* baud divisor */
 404 #define SCR   0x8c /* serial control */
 405 #define SSR   0x8e /* serial status */
 406 #define RDCSR 0x90 /* rx DMA control/status */
 407 #define TDCSR 0x94 /* tx DMA control/status */
 408 #define RDDAR 0x98 /* rx DMA descriptor address */
 409 #define TDDAR 0x9c /* tx DMA descriptor address */
 410
 411 #define RXIDLE      BIT14
 412 #define RXBREAK     BIT14
 413 #define IRQ_TXDATA  BIT13
 414 #define IRQ_TXIDLE  BIT12
 415 #define IRQ_TXUNDER BIT11 /* HDLC */
 416 #define IRQ_RXDATA  BIT10
 417 #define IRQ_RXIDLE  BIT9  /* HDLC */
 418 #define IRQ_RXBREAK BIT9  /* async */
 419 #define IRQ_RXOVER  BIT8
 420 #define IRQ_DSR     BIT7
 421 #define IRQ_CTS     BIT6
 422 #define IRQ_DCD     BIT5
 423 #define IRQ_RI      BIT4
 424 #define IRQ_ALL     0x3ff0
 425 #define IRQ_MASTER  BIT0
 426
 427 #define slgt_irq_on(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 429 #define slgt_irq_off(info, mask) \
 430         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 431
 432 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 434 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 436 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 437 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 438
 439 static void  msc_set_vcr(struct slgt_info *info);
 440
 441 static int  startup(struct slgt_info *info);
 442 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 443 static void shutdown(struct slgt_info *info);
 444 static void program_hw(struct slgt_info *info);
 445 static void change_params(struct slgt_info *info);
 446
 447 static int  register_test(struct slgt_info *info);
 448 static int  irq_test(struct slgt_info *info);
 449 static int  loopback_test(struct slgt_info *info);
 450 static int  adapter_test(struct slgt_info *info);
 451
 452 static void reset_adapter(struct slgt_info *info);
 453 static void reset_port(struct slgt_info *info);
 454 static void async_mode(struct slgt_info *info);
 455 static void sync_mode(struct slgt_info *info);
 456
 457 static void rx_stop(struct slgt_info *info);
 458 static void rx_start(struct slgt_info *info);
 459 static void reset_rbufs(struct slgt_info *info);
 460 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 461 static void rdma_reset(struct slgt_info *info);
 462 static bool rx_get_frame(struct slgt_info *info);
 463 static bool rx_get_buf(struct slgt_info *info);
 464
 465 static void tx_start(struct slgt_info *info);
 466 static void tx_stop(struct slgt_info *info);
 467 static void tx_set_idle(struct slgt_info *info);
 468 static unsigned int free_tbuf_count(struct slgt_info *info);
 469 static void reset_tbufs(struct slgt_info *info);
 470 static void tdma_reset(struct slgt_info *info);
 471 static void tdma_start(struct slgt_info *info);
 472 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 473
 474 static void get_signals(struct slgt_info *info);
 475 static void set_signals(struct slgt_info *info);
 476 static void enable_loopback(struct slgt_info *info);
 477 static void set_rate(struct slgt_info *info, u32 data_rate);
 478
 479 static int  bh_action(struct slgt_info *info);
 480 static void bh_handler(struct work_struct *work);
 481 static void bh_transmit(struct slgt_info *info);
 482 static void isr_serial(struct slgt_info *info);
 483 static void isr_rdma(struct slgt_info *info);
 484 static void isr_txeom(struct slgt_info *info, unsigned short status);
 485 static void isr_tdma(struct slgt_info *info);
 486
 487 static int  alloc_dma_bufs(struct slgt_info *info);
 488 static void free_dma_bufs(struct slgt_info *info);
 489 static int  alloc_desc(struct slgt_info *info);
 490 static void free_desc(struct slgt_info *info);
 491 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 493
 494 static int  alloc_tmp_rbuf(struct slgt_info *info);
 495 static void free_tmp_rbuf(struct slgt_info *info);
 496
 497 static void tx_timeout(unsigned long context);
 498 static void rx_timeout(unsigned long context);
 499
 500 /*
 501  * ioctl handlers
 502  */
 503 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 504 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 506 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 507 static int  set_txidle(struct slgt_info *info, int idle_mode);
 508 static int  tx_enable(struct slgt_info *info, int enable);
 509 static int  tx_abort(struct slgt_info *info);
 510 static int  rx_enable(struct slgt_info *info, int enable);
 511 static int  modem_input_wait(struct slgt_info *info,int arg);
 512 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 513 static int  tiocmget(struct tty_struct *tty, struct file *file);
 514 static int  tiocmset(struct tty_struct *tty, struct file *file,
 515                      unsigned int set, unsigned int clear);
 516 static void set_break(struct tty_struct *tty, int break_state);
 517 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 518 static int  set_interface(struct slgt_info *info, int if_mode);
 519 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 522
 523 /*
 524  * driver functions
 525  */
 526 static void add_device(struct slgt_info *info);
 527 static void device_init(int adapter_num, struct pci_dev *pdev);
 528 static int  claim_resources(struct slgt_info *info);
 529 static void release_resources(struct slgt_info *info);
 530
 531 /*
 532  * DEBUG OUTPUT CODE
 533  */
 534 #ifndef DBGINFO
 535 #define DBGINFO(fmt)
 536 #endif
 537 #ifndef DBGERR
 538 #define DBGERR(fmt)
 539 #endif
 540 #ifndef DBGBH
 541 #define DBGBH(fmt)
 542 #endif
 543 #ifndef DBGISR
 544 #define DBGISR(fmt)
 545 #endif
 546
 547 #ifdef DBGDATA
 548 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 549 {
 550         int i;
 551         int linecount;
 552         printk("%s %s data:\n",info->device_name, label);
 553         while(count) {
 554                 linecount = (count > 16) ? 16 : count;
 555                 for(i=0; i < linecount; i++)
 556                         printk("%02X ",(unsigned char)data[i]);
 557                 for(;i<17;i++)
 558                         printk("   ");
 559                 for(i=0;i<linecount;i++) {
 560                         if (data[i]>=040 && data[i]<=0176)
 561                                 printk("%c",data[i]);
 562                         else
 563                                 printk(".");
 564                 }
 565                 printk("\n");
 566                 data  += linecount;
 567                 count -= linecount;
 568         }
 569 }
 570 #else
 571 #define DBGDATA(info, buf, size, label)
 572 #endif
 573
 574 #ifdef DBGTBUF
 575 static void dump_tbufs(struct slgt_info *info)
 576 {
 577         int i;
 578         printk("tbuf_current=%d\n", info->tbuf_current);
 579         for (i=0 ; i < info->tbuf_count ; i++) {
 580                 printk("%d: count=%04X status=%04X\n",
 581                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 582         }
 583 }
 584 #else
 585 #define DBGTBUF(info)
 586 #endif
 587
 588 #ifdef DBGRBUF
 589 static void dump_rbufs(struct slgt_info *info)
 590 {
 591         int i;
 592         printk("rbuf_current=%d\n", info->rbuf_current);
 593         for (i=0 ; i < info->rbuf_count ; i++) {
 594                 printk("%d: count=%04X status=%04X\n",
 595                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 596         }
 597 }
 598 #else
 599 #define DBGRBUF(info)
 600 #endif
 601
 602 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 603 {
 604 #ifdef SANITY_CHECK
 605         if (!info) {
 606                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 607                 return 1;
 608         }
 609         if (info->magic != MGSL_MAGIC) {
 610                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 611                 return 1;
 612         }
 613 #else
 614         if (!info)
 615                 return 1;
 616 #endif
 617         return 0;
 618 }
 619
 620 /**
 621  * line discipline callback wrappers
 622  *
 623  * The wrappers maintain line discipline references
 624  * while calling into the line discipline.
 625  *
 626  * ldisc_receive_buf  - pass receive data to line discipline
 627  */
 628 static void ldisc_receive_buf(struct tty_struct *tty,
 629                               const __u8 *data, char *flags, int count)
 630 {
 631         struct tty_ldisc *ld;
 632         if (!tty)
 633                 return;
 634         ld = tty_ldisc_ref(tty);
 635         if (ld) {
 636                 if (ld->ops->receive_buf)
 637                         ld->ops->receive_buf(tty, data, flags, count);
 638                 tty_ldisc_deref(ld);
 639         }
 640 }
 641
 642 /* tty callbacks */
 643
 644 static int open(struct tty_struct *tty, struct file *filp)
 645 {
 646         struct slgt_info *info;
 647         int retval, line;
 648         unsigned long flags;
 649
 650         line = tty->index;
 651         if ((line < 0) || (line >= slgt_device_count)) {
 652                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 653                 return -ENODEV;
 654         }
 655
 656         info = slgt_device_list;
 657         while(info && info->line != line)
 658                 info = info->next_device;
 659         if (sanity_check(info, tty->name, "open"))
 660                 return -ENODEV;
 661         if (info->init_error) {
 662                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 663                 return -ENODEV;
 664         }
 665
 666         tty->driver_data = info;
 667         info->port.tty = tty;
 668
 669         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 670
 671         /* If port is closing, signal caller to try again */
 672         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 673                 if (info->port.flags & ASYNC_CLOSING)
 674                         interruptible_sleep_on(&info->port.close_wait);
 675                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 676                         -EAGAIN : -ERESTARTSYS);
 677                 goto cleanup;
 678         }
 679
 680         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 681
 682         spin_lock_irqsave(&info->netlock, flags);
 683         if (info->netcount) {
 684                 retval = -EBUSY;
 685                 spin_unlock_irqrestore(&info->netlock, flags);
 686                 goto cleanup;
 687         }
 688         info->port.count++;
 689         spin_unlock_irqrestore(&info->netlock, flags);
 690
 691         if (info->port.count == 1) {
 692                 /* 1st open on this device, init hardware */
 693                 retval = startup(info);
 694                 if (retval < 0)
 695                         goto cleanup;
 696         }
 697
 698         retval = block_til_ready(tty, filp, info);
 699         if (retval) {
 700                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 701                 goto cleanup;
 702         }
 703
 704         retval = 0;
 705
 706 cleanup:
 707         if (retval) {
 708                 if (tty->count == 1)
 709                         info->port.tty = NULL; /* tty layer will release tty struct */
 710                 if(info->port.count)
 711                         info->port.count--;
 712         }
 713
 714         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 715         return retval;
 716 }
 717
 718 static void close(struct tty_struct *tty, struct file *filp)
 719 {
 720         struct slgt_info *info = tty->driver_data;
 721
 722         if (sanity_check(info, tty->name, "close"))
 723                 return;
 724         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 725
 726         if (!info->port.count)
 727                 return;
 728
 729         if (tty_hung_up_p(filp))
 730                 goto cleanup;
 731
 732         if ((tty->count == 1) && (info->port.count != 1)) {
 733                 /*
 734                  * tty->count is 1 and the tty structure will be freed.
 735                  * info->port.count should be one in this case.
 736                  * if it's not, correct it so that the port is shutdown.
 737                  */
 738                 DBGERR(("%s close: bad refcount; tty->count=1, "
 739                        "info->port.count=%d\n", info->device_name, info->port.count));
 740                 info->port.count = 1;
 741         }
 742
 743         info->port.count--;
 744
 745         /* if at least one open remaining, leave hardware active */
 746         if (info->port.count)
 747                 goto cleanup;
 748
 749         info->port.flags |= ASYNC_CLOSING;
 750
 751         /* set tty->closing to notify line discipline to
 752          * only process XON/XOFF characters. Only the N_TTY
 753          * discipline appears to use this (ppp does not).
 754          */
 755         tty->closing = 1;
 756
 757         /* wait for transmit data to clear all layers */
 758
 759         if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 760                 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
 761                 tty_wait_until_sent(tty, info->port.closing_wait);
 762         }
 763
 764         if (info->port.flags & ASYNC_INITIALIZED)
 765                 wait_until_sent(tty, info->timeout);
 766         flush_buffer(tty);
 767         tty_ldisc_flush(tty);
 768
 769         shutdown(info);
 770
 771         tty->closing = 0;
 772         info->port.tty = NULL;
 773
 774         if (info->port.blocked_open) {
 775                 if (info->port.close_delay) {
 776                         msleep_interruptible(jiffies_to_msecs(info->port.close_delay));
 777                 }
 778                 wake_up_interruptible(&info->port.open_wait);
 779         }
 780
 781         info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 782
 783         wake_up_interruptible(&info->port.close_wait);
 784
 785 cleanup:
 786         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 787 }
 788
 789 static void hangup(struct tty_struct *tty)
 790 {
 791         struct slgt_info *info = tty->driver_data;
 792
 793         if (sanity_check(info, tty->name, "hangup"))
 794                 return;
 795         DBGINFO(("%s hangup\n", info->device_name));
 796
 797         flush_buffer(tty);
 798         shutdown(info);
 799
 800         info->port.count = 0;
 801         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 802         info->port.tty = NULL;
 803
 804         wake_up_interruptible(&info->port.open_wait);
 805 }
 806
 807 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 808 {
 809         struct slgt_info *info = tty->driver_data;
 810         unsigned long flags;
 811
 812         DBGINFO(("%s set_termios\n", tty->driver->name));
 813
 814         change_params(info);
 815
 816         /* Handle transition to B0 status */
 817         if (old_termios->c_cflag & CBAUD &&
 818             !(tty->termios->c_cflag & CBAUD)) {
 819                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 820                 spin_lock_irqsave(&info->lock,flags);
 821                 set_signals(info);
 822                 spin_unlock_irqrestore(&info->lock,flags);
 823         }
 824
 825         /* Handle transition away from B0 status */
 826         if (!(old_termios->c_cflag & CBAUD) &&
 827             tty->termios->c_cflag & CBAUD) {
 828                 info->signals |= SerialSignal_DTR;
 829                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 830                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 831                         info->signals |= SerialSignal_RTS;
 832                 }
 833                 spin_lock_irqsave(&info->lock,flags);
 834                 set_signals(info);
 835                 spin_unlock_irqrestore(&info->lock,flags);
 836         }
 837
 838         /* Handle turning off CRTSCTS */
 839         if (old_termios->c_cflag & CRTSCTS &&
 840             !(tty->termios->c_cflag & CRTSCTS)) {
 841                 tty->hw_stopped = 0;
 842                 tx_release(tty);
 843         }
 844 }
 845
 846 static int write(struct tty_struct *tty,
 847                  const unsigned char *buf, int count)
 848 {
 849         int ret = 0;
 850         struct slgt_info *info = tty->driver_data;
 851         unsigned long flags;
 852
 853         if (sanity_check(info, tty->name, "write"))
 854                 goto cleanup;
 855         DBGINFO(("%s write count=%d\n", info->device_name, count));
 856
 857         if (!info->tx_buf)
 858                 goto cleanup;
 859
 860         if (count > info->max_frame_size) {
 861                 ret = -EIO;
 862                 goto cleanup;
 863         }
 864
 865         if (!count)
 866                 goto cleanup;
 867
 868         if (info->params.mode == MGSL_MODE_RAW ||
 869             info->params.mode == MGSL_MODE_MONOSYNC ||
 870             info->params.mode == MGSL_MODE_BISYNC) {
 871                 unsigned int bufs_needed = (count/DMABUFSIZE);
 872                 unsigned int bufs_free = free_tbuf_count(info);
 873                 if (count % DMABUFSIZE)
 874                         ++bufs_needed;
 875                 if (bufs_needed > bufs_free)
 876                         goto cleanup;
 877         } else {
 878                 if (info->tx_active)
 879                         goto cleanup;
 880                 if (info->tx_count) {
 881                         /* send accumulated data from send_char() calls */
 882                         /* as frame and wait before accepting more data. */
 883                         tx_load(info, info->tx_buf, info->tx_count);
 884                         goto start;
 885                 }
 886         }
 887
 888         ret = info->tx_count = count;
 889         tx_load(info, buf, count);
 890         goto start;
 891
 892 start:
 893         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 894                 spin_lock_irqsave(&info->lock,flags);
 895                 if (!info->tx_active)
 896                         tx_start(info);
 897                 else
 898                         tdma_start(info);
 899                 spin_unlock_irqrestore(&info->lock,flags);
 900         }
 901
 902 cleanup:
 903         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 904         return ret;
 905 }
 906
 907 static int put_char(struct tty_struct *tty, unsigned char ch)
 908 {
 909         struct slgt_info *info = tty->driver_data;
 910         unsigned long flags;
 911         int ret = 0;
 912
 913         if (sanity_check(info, tty->name, "put_char"))
 914                 return 0;
 915         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 916         if (!info->tx_buf)
 917                 return 0;
 918         spin_lock_irqsave(&info->lock,flags);
 919         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 920                 info->tx_buf[info->tx_count++] = ch;
 921                 ret = 1;
 922         }
 923         spin_unlock_irqrestore(&info->lock,flags);
 924         return ret;
 925 }
 926
 927 static void send_xchar(struct tty_struct *tty, char ch)
 928 {
 929         struct slgt_info *info = tty->driver_data;
 930         unsigned long flags;
 931
 932         if (sanity_check(info, tty->name, "send_xchar"))
 933                 return;
 934         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 935         info->x_char = ch;
 936         if (ch) {
 937                 spin_lock_irqsave(&info->lock,flags);
 938                 if (!info->tx_enabled)
 939                         tx_start(info);
 940                 spin_unlock_irqrestore(&info->lock,flags);
 941         }
 942 }
 943
 944 static void wait_until_sent(struct tty_struct *tty, int timeout)
 945 {
 946         struct slgt_info *info = tty->driver_data;
 947         unsigned long orig_jiffies, char_time;
 948
 949         if (!info )
 950                 return;
 951         if (sanity_check(info, tty->name, "wait_until_sent"))
 952                 return;
 953         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 954         if (!(info->port.flags & ASYNC_INITIALIZED))
 955                 goto exit;
 956
 957         orig_jiffies = jiffies;
 958
 959         /* Set check interval to 1/5 of estimated time to
 960          * send a character, and make it at least 1. The check
 961          * interval should also be less than the timeout.
 962          * Note: use tight timings here to satisfy the NIST-PCTS.
 963          */
 964
 965         lock_kernel();
 966
 967         if (info->params.data_rate) {
 968                 char_time = info->timeout/(32 * 5);
 969                 if (!char_time)
 970                         char_time++;
 971         } else
 972                 char_time = 1;
 973
 974         if (timeout)
 975                 char_time = min_t(unsigned long, char_time, timeout);
 976
 977         while (info->tx_active) {
 978                 msleep_interruptible(jiffies_to_msecs(char_time));
 979                 if (signal_pending(current))
 980                         break;
 981                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 982                         break;
 983         }
 984         unlock_kernel();
 985
 986 exit:
 987         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 988 }
 989
 990 static int write_room(struct tty_struct *tty)
 991 {
 992         struct slgt_info *info = tty->driver_data;
 993         int ret;
 994
 995         if (sanity_check(info, tty->name, "write_room"))
 996                 return 0;
 997         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 998         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 999         return ret;
1000 }
1001
1002 static void flush_chars(struct tty_struct *tty)
1003 {
1004         struct slgt_info *info = tty->driver_data;
1005         unsigned long flags;
1006
1007         if (sanity_check(info, tty->name, "flush_chars"))
1008                 return;
1009         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1010
1011         if (info->tx_count <= 0 || tty->stopped ||
1012             tty->hw_stopped || !info->tx_buf)
1013                 return;
1014
1015         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1016
1017         spin_lock_irqsave(&info->lock,flags);
1018         if (!info->tx_active && info->tx_count) {
1019                 tx_load(info, info->tx_buf,info->tx_count);
1020                 tx_start(info);
1021         }
1022         spin_unlock_irqrestore(&info->lock,flags);
1023 }
1024
1025 static void flush_buffer(struct tty_struct *tty)
1026 {
1027         struct slgt_info *info = tty->driver_data;
1028         unsigned long flags;
1029
1030         if (sanity_check(info, tty->name, "flush_buffer"))
1031                 return;
1032         DBGINFO(("%s flush_buffer\n", info->device_name));
1033
1034         spin_lock_irqsave(&info->lock,flags);
1035         if (!info->tx_active)
1036                 info->tx_count = 0;
1037         spin_unlock_irqrestore(&info->lock,flags);
1038
1039         tty_wakeup(tty);
1040 }
1041
1042 /*
1043  * throttle (stop) transmitter
1044  */
1045 static void tx_hold(struct tty_struct *tty)
1046 {
1047         struct slgt_info *info = tty->driver_data;
1048         unsigned long flags;
1049
1050         if (sanity_check(info, tty->name, "tx_hold"))
1051                 return;
1052         DBGINFO(("%s tx_hold\n", info->device_name));
1053         spin_lock_irqsave(&info->lock,flags);
1054         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1055                 tx_stop(info);
1056         spin_unlock_irqrestore(&info->lock,flags);
1057 }
1058
1059 /*
1060  * release (start) transmitter
1061  */
1062 static void tx_release(struct tty_struct *tty)
1063 {
1064         struct slgt_info *info = tty->driver_data;
1065         unsigned long flags;
1066
1067         if (sanity_check(info, tty->name, "tx_release"))
1068                 return;
1069         DBGINFO(("%s tx_release\n", info->device_name));
1070         spin_lock_irqsave(&info->lock,flags);
1071         if (!info->tx_active && info->tx_count) {
1072                 tx_load(info, info->tx_buf, info->tx_count);
1073                 tx_start(info);
1074         }
1075         spin_unlock_irqrestore(&info->lock,flags);
1076 }
1077
1078 /*
1079  * Service an IOCTL request
1080  *
1081  * Arguments
1082  *
1083  *      tty     pointer to tty instance data
1084  *      file    pointer to associated file object for device
1085  *      cmd     IOCTL command code
1086  *      arg     command argument/context
1087  *
1088  * Return 0 if success, otherwise error code
1089  */
1090 static int ioctl(struct tty_struct *tty, struct file *file,
1091                  unsigned int cmd, unsigned long arg)
1092 {
1093         struct slgt_info *info = tty->driver_data;
1094         struct mgsl_icount cnow;        /* kernel counter temps */
1095         struct serial_icounter_struct __user *p_cuser;  /* user space */
1096         unsigned long flags;
1097         void __user *argp = (void __user *)arg;
1098         int ret;
1099
1100         if (sanity_check(info, tty->name, "ioctl"))
1101                 return -ENODEV;
1102         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1103
1104         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1105             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1106                 if (tty->flags & (1 << TTY_IO_ERROR))
1107                     return -EIO;
1108         }
1109
1110         lock_kernel();
1111
1112         switch (cmd) {
1113         case MGSL_IOCGPARAMS:
1114                 ret = get_params(info, argp);
1115                 break;
1116         case MGSL_IOCSPARAMS:
1117                 ret = set_params(info, argp);
1118                 break;
1119         case MGSL_IOCGTXIDLE:
1120                 ret = get_txidle(info, argp);
1121                 break;
1122         case MGSL_IOCSTXIDLE:
1123                 ret = set_txidle(info, (int)arg);
1124                 break;
1125         case MGSL_IOCTXENABLE:
1126                 ret = tx_enable(info, (int)arg);
1127                 break;
1128         case MGSL_IOCRXENABLE:
1129                 ret = rx_enable(info, (int)arg);
1130                 break;
1131         case MGSL_IOCTXABORT:
1132                 ret = tx_abort(info);
1133                 break;
1134         case MGSL_IOCGSTATS:
1135                 ret = get_stats(info, argp);
1136                 break;
1137         case MGSL_IOCWAITEVENT:
1138                 ret = wait_mgsl_event(info, argp);
1139                 break;
1140         case TIOCMIWAIT:
1141                 ret = modem_input_wait(info,(int)arg);
1142                 break;
1143         case MGSL_IOCGIF:
1144                 ret = get_interface(info, argp);
1145                 break;
1146         case MGSL_IOCSIF:
1147                 ret = set_interface(info,(int)arg);
1148                 break;
1149         case MGSL_IOCSGPIO:
1150                 ret = set_gpio(info, argp);
1151                 break;
1152         case MGSL_IOCGGPIO:
1153                 ret = get_gpio(info, argp);
1154                 break;
1155         case MGSL_IOCWAITGPIO:
1156                 ret = wait_gpio(info, argp);
1157                 break;
1158         case TIOCGICOUNT:
1159                 spin_lock_irqsave(&info->lock,flags);
1160                 cnow = info->icount;
1161                 spin_unlock_irqrestore(&info->lock,flags);
1162                 p_cuser = argp;
1163                 if (put_user(cnow.cts, &p_cuser->cts) ||
1164                     put_user(cnow.dsr, &p_cuser->dsr) ||
1165                     put_user(cnow.rng, &p_cuser->rng) ||
1166                     put_user(cnow.dcd, &p_cuser->dcd) ||
1167                     put_user(cnow.rx, &p_cuser->rx) ||
1168                     put_user(cnow.tx, &p_cuser->tx) ||
1169                     put_user(cnow.frame, &p_cuser->frame) ||
1170                     put_user(cnow.overrun, &p_cuser->overrun) ||
1171                     put_user(cnow.parity, &p_cuser->parity) ||
1172                     put_user(cnow.brk, &p_cuser->brk) ||
1173                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1174                         ret = -EFAULT;
1175                 ret = 0;
1176                 break;
1177         default:
1178                 ret = -ENOIOCTLCMD;
1179         }
1180         unlock_kernel();
1181         return ret;
1182 }
1183
1184 /*
1185  * support for 32 bit ioctl calls on 64 bit systems
1186  */
1187 #ifdef CONFIG_COMPAT
1188 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1189 {
1190         struct MGSL_PARAMS32 tmp_params;
1191
1192         DBGINFO(("%s get_params32\n", info->device_name));
1193         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1194         tmp_params.loopback        = info->params.loopback;
1195         tmp_params.flags           = info->params.flags;
1196         tmp_params.encoding        = info->params.encoding;
1197         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1198         tmp_params.addr_filter     = info->params.addr_filter;
1199         tmp_params.crc_type        = info->params.crc_type;
1200         tmp_params.preamble_length = info->params.preamble_length;
1201         tmp_params.preamble        = info->params.preamble;
1202         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1203         tmp_params.data_bits       = info->params.data_bits;
1204         tmp_params.stop_bits       = info->params.stop_bits;
1205         tmp_params.parity          = info->params.parity;
1206         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1207                 return -EFAULT;
1208         return 0;
1209 }
1210
1211 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1212 {
1213         struct MGSL_PARAMS32 tmp_params;
1214
1215         DBGINFO(("%s set_params32\n", info->device_name));
1216         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1217                 return -EFAULT;
1218
1219         spin_lock(&info->lock);
1220         info->params.mode            = tmp_params.mode;
1221         info->params.loopback        = tmp_params.loopback;
1222         info->params.flags           = tmp_params.flags;
1223         info->params.encoding        = tmp_params.encoding;
1224         info->params.clock_speed     = tmp_params.clock_speed;
1225         info->params.addr_filter     = tmp_params.addr_filter;
1226         info->params.crc_type        = tmp_params.crc_type;
1227         info->params.preamble_length = tmp_params.preamble_length;
1228         info->params.preamble        = tmp_params.preamble;
1229         info->params.data_rate       = tmp_params.data_rate;
1230         info->params.data_bits       = tmp_params.data_bits;
1231         info->params.stop_bits       = tmp_params.stop_bits;
1232         info->params.parity          = tmp_params.parity;
1233         spin_unlock(&info->lock);
1234
1235         change_params(info);
1236
1237         return 0;
1238 }
1239
1240 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1241                          unsigned int cmd, unsigned long arg)
1242 {
1243         struct slgt_info *info = tty->driver_data;
1244         int rc = -ENOIOCTLCMD;
1245
1246         if (sanity_check(info, tty->name, "compat_ioctl"))
1247                 return -ENODEV;
1248         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1249
1250         switch (cmd) {
1251
1252         case MGSL_IOCSPARAMS32:
1253                 rc = set_params32(info, compat_ptr(arg));
1254                 break;
1255
1256         case MGSL_IOCGPARAMS32:
1257                 rc = get_params32(info, compat_ptr(arg));
1258                 break;
1259
1260         case MGSL_IOCGPARAMS:
1261         case MGSL_IOCSPARAMS:
1262         case MGSL_IOCGTXIDLE:
1263         case MGSL_IOCGSTATS:
1264         case MGSL_IOCWAITEVENT:
1265         case MGSL_IOCGIF:
1266         case MGSL_IOCSGPIO:
1267         case MGSL_IOCGGPIO:
1268         case MGSL_IOCWAITGPIO:
1269         case TIOCGICOUNT:
1270                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1271                 break;
1272
1273         case MGSL_IOCSTXIDLE:
1274         case MGSL_IOCTXENABLE:
1275         case MGSL_IOCRXENABLE:
1276         case MGSL_IOCTXABORT:
1277         case TIOCMIWAIT:
1278         case MGSL_IOCSIF:
1279                 rc = ioctl(tty, file, cmd, arg);
1280                 break;
1281         }
1282
1283         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1284         return rc;
1285 }
1286 #else
1287 #define slgt_compat_ioctl NULL
1288 #endif /* ifdef CONFIG_COMPAT */
1289
1290 /*
1291  * proc fs support
1292  */
1293 static inline int line_info(char *buf, struct slgt_info *info)
1294 {
1295         char stat_buf[30];
1296         int ret;
1297         unsigned long flags;
1298
1299         ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1300                       info->device_name, info->phys_reg_addr,
1301                       info->irq_level, info->max_frame_size);
1302
1303         /* output current serial signal states */
1304         spin_lock_irqsave(&info->lock,flags);
1305         get_signals(info);
1306         spin_unlock_irqrestore(&info->lock,flags);
1307
1308         stat_buf[0] = 0;
1309         stat_buf[1] = 0;
1310         if (info->signals & SerialSignal_RTS)
1311                 strcat(stat_buf, "|RTS");
1312         if (info->signals & SerialSignal_CTS)
1313                 strcat(stat_buf, "|CTS");
1314         if (info->signals & SerialSignal_DTR)
1315                 strcat(stat_buf, "|DTR");
1316         if (info->signals & SerialSignal_DSR)
1317                 strcat(stat_buf, "|DSR");
1318         if (info->signals & SerialSignal_DCD)
1319                 strcat(stat_buf, "|CD");
1320         if (info->signals & SerialSignal_RI)
1321                 strcat(stat_buf, "|RI");
1322
1323         if (info->params.mode != MGSL_MODE_ASYNC) {
1324                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1325                                info->icount.txok, info->icount.rxok);
1326                 if (info->icount.txunder)
1327                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1328                 if (info->icount.txabort)
1329                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1330                 if (info->icount.rxshort)
1331                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1332                 if (info->icount.rxlong)
1333                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1334                 if (info->icount.rxover)
1335                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1336                 if (info->icount.rxcrc)
1337                         ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1338         } else {
1339                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1340                                info->icount.tx, info->icount.rx);
1341                 if (info->icount.frame)
1342                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1343                 if (info->icount.parity)
1344                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1345                 if (info->icount.brk)
1346                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1347                 if (info->icount.overrun)
1348                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1349         }
1350
1351         /* Append serial signal status to end */
1352         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1353
1354         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1355                        info->tx_active,info->bh_requested,info->bh_running,
1356                        info->pending_bh);
1357
1358         return ret;
1359 }
1360
1361 /* Called to print information about devices
1362  */
1363 static int read_proc(char *page, char **start, off_t off, int count,
1364                      int *eof, void *data)
1365 {
1366         int len = 0, l;
1367         off_t   begin = 0;
1368         struct slgt_info *info;
1369
1370         len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1371
1372         info = slgt_device_list;
1373         while( info ) {
1374                 l = line_info(page + len, info);
1375                 len += l;
1376                 if (len+begin > off+count)
1377                         goto done;
1378                 if (len+begin < off) {
1379                         begin += len;
1380                         len = 0;
1381                 }
1382                 info = info->next_device;
1383         }
1384
1385         *eof = 1;
1386 done:
1387         if (off >= len+begin)
1388                 return 0;
1389         *start = page + (off-begin);
1390         return ((count < begin+len-off) ? count : begin+len-off);
1391 }
1392
1393 /*
1394  * return count of bytes in transmit buffer
1395  */
1396 static int chars_in_buffer(struct tty_struct *tty)
1397 {
1398         struct slgt_info *info = tty->driver_data;
1399         if (sanity_check(info, tty->name, "chars_in_buffer"))
1400                 return 0;
1401         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1402         return info->tx_count;
1403 }
1404
1405 /*
1406  * signal remote device to throttle send data (our receive data)
1407  */
1408 static void throttle(struct tty_struct * tty)
1409 {
1410         struct slgt_info *info = tty->driver_data;
1411         unsigned long flags;
1412
1413         if (sanity_check(info, tty->name, "throttle"))
1414                 return;
1415         DBGINFO(("%s throttle\n", info->device_name));
1416         if (I_IXOFF(tty))
1417                 send_xchar(tty, STOP_CHAR(tty));
1418         if (tty->termios->c_cflag & CRTSCTS) {
1419                 spin_lock_irqsave(&info->lock,flags);
1420                 info->signals &= ~SerialSignal_RTS;
1421                 set_signals(info);
1422                 spin_unlock_irqrestore(&info->lock,flags);
1423         }
1424 }
1425
1426 /*
1427  * signal remote device to stop throttling send data (our receive data)
1428  */
1429 static void unthrottle(struct tty_struct * tty)
1430 {
1431         struct slgt_info *info = tty->driver_data;
1432         unsigned long flags;
1433
1434         if (sanity_check(info, tty->name, "unthrottle"))
1435                 return;
1436         DBGINFO(("%s unthrottle\n", info->device_name));
1437         if (I_IXOFF(tty)) {
1438                 if (info->x_char)
1439                         info->x_char = 0;
1440                 else
1441                         send_xchar(tty, START_CHAR(tty));
1442         }
1443         if (tty->termios->c_cflag & CRTSCTS) {
1444                 spin_lock_irqsave(&info->lock,flags);
1445                 info->signals |= SerialSignal_RTS;
1446                 set_signals(info);
1447                 spin_unlock_irqrestore(&info->lock,flags);
1448         }
1449 }
1450
1451 /*
1452  * set or clear transmit break condition
1453  * break_state  -1=set break condition, 0=clear
1454  */
1455 static void set_break(struct tty_struct *tty, int break_state)
1456 {
1457         struct slgt_info *info = tty->driver_data;
1458         unsigned short value;
1459         unsigned long flags;
1460
1461         if (sanity_check(info, tty->name, "set_break"))
1462                 return;
1463         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1464
1465         spin_lock_irqsave(&info->lock,flags);
1466         value = rd_reg16(info, TCR);
1467         if (break_state == -1)
1468                 value |= BIT6;
1469         else
1470                 value &= ~BIT6;
1471         wr_reg16(info, TCR, value);
1472         spin_unlock_irqrestore(&info->lock,flags);
1473 }
1474
1475 #if SYNCLINK_GENERIC_HDLC
1476
1477 /**
1478  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1479  * set encoding and frame check sequence (FCS) options
1480  *
1481  * dev       pointer to network device structure
1482  * encoding  serial encoding setting
1483  * parity    FCS setting
1484  *
1485  * returns 0 if success, otherwise error code
1486  */
1487 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1488                           unsigned short parity)
1489 {
1490         struct slgt_info *info = dev_to_port(dev);
1491         unsigned char  new_encoding;
1492         unsigned short new_crctype;
1493
1494         /* return error if TTY interface open */
1495         if (info->port.count)
1496                 return -EBUSY;
1497
1498         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1499
1500         switch (encoding)
1501         {
1502         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1503         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1504         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1505         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1506         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1507         default: return -EINVAL;
1508         }
1509
1510         switch (parity)
1511         {
1512         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1513         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1514         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1515         default: return -EINVAL;
1516         }
1517
1518         info->params.encoding = new_encoding;
1519         info->params.crc_type = new_crctype;
1520
1521         /* if network interface up, reprogram hardware */
1522         if (info->netcount)
1523                 program_hw(info);
1524
1525         return 0;
1526 }
1527
1528 /**
1529  * called by generic HDLC layer to send frame
1530  *
1531  * skb  socket buffer containing HDLC frame
1532  * dev  pointer to network device structure
1533  *
1534  * returns 0 if success, otherwise error code
1535  */
1536 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1537 {
1538         struct slgt_info *info = dev_to_port(dev);
1539         struct net_device_stats *stats = hdlc_stats(dev);
1540         unsigned long flags;
1541
1542         DBGINFO(("%s hdlc_xmit\n", dev->name));
1543
1544         /* stop sending until this frame completes */
1545         netif_stop_queue(dev);
1546
1547         /* copy data to device buffers */
1548         info->tx_count = skb->len;
1549         tx_load(info, skb->data, skb->len);
1550
1551         /* update network statistics */
1552         stats->tx_packets++;
1553         stats->tx_bytes += skb->len;
1554
1555         /* done with socket buffer, so free it */
1556         dev_kfree_skb(skb);
1557
1558         /* save start time for transmit timeout detection */
1559         dev->trans_start = jiffies;
1560
1561         /* start hardware transmitter if necessary */
1562         spin_lock_irqsave(&info->lock,flags);
1563         if (!info->tx_active)
1564                 tx_start(info);
1565         spin_unlock_irqrestore(&info->lock,flags);
1566
1567         return 0;
1568 }
1569
1570 /**
1571  * called by network layer when interface enabled
1572  * claim resources and initialize hardware
1573  *
1574  * dev  pointer to network device structure
1575  *
1576  * returns 0 if success, otherwise error code
1577  */
1578 static int hdlcdev_open(struct net_device *dev)
1579 {
1580         struct slgt_info *info = dev_to_port(dev);
1581         int rc;
1582         unsigned long flags;
1583
1584         if (!try_module_get(THIS_MODULE))
1585                 return -EBUSY;
1586
1587         DBGINFO(("%s hdlcdev_open\n", dev->name));
1588
1589         /* generic HDLC layer open processing */
1590         if ((rc = hdlc_open(dev)))
1591                 return rc;
1592
1593         /* arbitrate between network and tty opens */
1594         spin_lock_irqsave(&info->netlock, flags);
1595         if (info->port.count != 0 || info->netcount != 0) {
1596                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1597                 spin_unlock_irqrestore(&info->netlock, flags);
1598                 return -EBUSY;
1599         }
1600         info->netcount=1;
1601         spin_unlock_irqrestore(&info->netlock, flags);
1602
1603         /* claim resources and init adapter */
1604         if ((rc = startup(info)) != 0) {
1605                 spin_lock_irqsave(&info->netlock, flags);
1606                 info->netcount=0;
1607                 spin_unlock_irqrestore(&info->netlock, flags);
1608                 return rc;
1609         }
1610
1611         /* assert DTR and RTS, apply hardware settings */
1612         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1613         program_hw(info);
1614
1615         /* enable network layer transmit */
1616         dev->trans_start = jiffies;
1617         netif_start_queue(dev);
1618
1619         /* inform generic HDLC layer of current DCD status */
1620         spin_lock_irqsave(&info->lock, flags);
1621         get_signals(info);
1622         spin_unlock_irqrestore(&info->lock, flags);
1623         if (info->signals & SerialSignal_DCD)
1624                 netif_carrier_on(dev);
1625         else
1626                 netif_carrier_off(dev);
1627         return 0;
1628 }
1629
1630 /**
1631  * called by network layer when interface is disabled
1632  * shutdown hardware and release resources
1633  *
1634  * dev  pointer to network device structure
1635  *
1636  * returns 0 if success, otherwise error code
1637  */
1638 static int hdlcdev_close(struct net_device *dev)
1639 {
1640         struct slgt_info *info = dev_to_port(dev);
1641         unsigned long flags;
1642
1643         DBGINFO(("%s hdlcdev_close\n", dev->name));
1644
1645         netif_stop_queue(dev);
1646
1647         /* shutdown adapter and release resources */
1648         shutdown(info);
1649
1650         hdlc_close(dev);
1651
1652         spin_lock_irqsave(&info->netlock, flags);
1653         info->netcount=0;
1654         spin_unlock_irqrestore(&info->netlock, flags);
1655
1656         module_put(THIS_MODULE);
1657         return 0;
1658 }
1659
1660 /**
1661  * called by network layer to process IOCTL call to network device
1662  *
1663  * dev  pointer to network device structure
1664  * ifr  pointer to network interface request structure
1665  * cmd  IOCTL command code
1666  *
1667  * returns 0 if success, otherwise error code
1668  */
1669 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1670 {
1671         const size_t size = sizeof(sync_serial_settings);
1672         sync_serial_settings new_line;
1673         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1674         struct slgt_info *info = dev_to_port(dev);
1675         unsigned int flags;
1676
1677         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1678
1679         /* return error if TTY interface open */
1680         if (info->port.count)
1681                 return -EBUSY;
1682
1683         if (cmd != SIOCWANDEV)
1684                 return hdlc_ioctl(dev, ifr, cmd);
1685
1686         switch(ifr->ifr_settings.type) {
1687         case IF_GET_IFACE: /* return current sync_serial_settings */
1688
1689                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1690                 if (ifr->ifr_settings.size < size) {
1691                         ifr->ifr_settings.size = size; /* data size wanted */
1692                         return -ENOBUFS;
1693                 }
1694
1695                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1696                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1697                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1698                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1699
1700                 switch (flags){
1701                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1702                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1703                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1704                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1705                 default: new_line.clock_type = CLOCK_DEFAULT;
1706                 }
1707
1708                 new_line.clock_rate = info->params.clock_speed;
1709                 new_line.loopback   = info->params.loopback ? 1:0;
1710
1711                 if (copy_to_user(line, &new_line, size))
1712                         return -EFAULT;
1713                 return 0;
1714
1715         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1716
1717                 if(!capable(CAP_NET_ADMIN))
1718                         return -EPERM;
1719                 if (copy_from_user(&new_line, line, size))
1720                         return -EFAULT;
1721
1722                 switch (new_line.clock_type)
1723                 {
1724                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1725                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1726                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1727                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1728                 case CLOCK_DEFAULT:  flags = info->params.flags &
1729                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1730                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1731                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1732                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1733                 default: return -EINVAL;
1734                 }
1735
1736                 if (new_line.loopback != 0 && new_line.loopback != 1)
1737                         return -EINVAL;
1738
1739                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1740                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1741                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1742                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1743                 info->params.flags |= flags;
1744
1745                 info->params.loopback = new_line.loopback;
1746
1747                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1748                         info->params.clock_speed = new_line.clock_rate;
1749                 else
1750                         info->params.clock_speed = 0;
1751
1752                 /* if network interface up, reprogram hardware */
1753                 if (info->netcount)
1754                         program_hw(info);
1755                 return 0;
1756
1757         default:
1758                 return hdlc_ioctl(dev, ifr, cmd);
1759         }
1760 }
1761
1762 /**
1763  * called by network layer when transmit timeout is detected
1764  *
1765  * dev  pointer to network device structure
1766  */
1767 static void hdlcdev_tx_timeout(struct net_device *dev)
1768 {
1769         struct slgt_info *info = dev_to_port(dev);
1770         struct net_device_stats *stats = hdlc_stats(dev);
1771         unsigned long flags;
1772
1773         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1774
1775         stats->tx_errors++;
1776         stats->tx_aborted_errors++;
1777
1778         spin_lock_irqsave(&info->lock,flags);
1779         tx_stop(info);
1780         spin_unlock_irqrestore(&info->lock,flags);
1781
1782         netif_wake_queue(dev);
1783 }
1784
1785 /**
1786  * called by device driver when transmit completes
1787  * reenable network layer transmit if stopped
1788  *
1789  * info  pointer to device instance information
1790  */
1791 static void hdlcdev_tx_done(struct slgt_info *info)
1792 {
1793         if (netif_queue_stopped(info->netdev))
1794                 netif_wake_queue(info->netdev);
1795 }
1796
1797 /**
1798  * called by device driver when frame received
1799  * pass frame to network layer
1800  *
1801  * info  pointer to device instance information
1802  * buf   pointer to buffer contianing frame data
1803  * size  count of data bytes in buf
1804  */
1805 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1806 {
1807         struct sk_buff *skb = dev_alloc_skb(size);
1808         struct net_device *dev = info->netdev;
1809         struct net_device_stats *stats = hdlc_stats(dev);
1810
1811         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1812
1813         if (skb == NULL) {
1814                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1815                 stats->rx_dropped++;
1816                 return;
1817         }
1818
1819         memcpy(skb_put(skb, size),buf,size);
1820
1821         skb->protocol = hdlc_type_trans(skb, info->netdev);
1822
1823         stats->rx_packets++;
1824         stats->rx_bytes += size;
1825
1826         netif_rx(skb);
1827
1828         info->netdev->last_rx = jiffies;
1829 }
1830
1831 /**
1832  * called by device driver when adding device instance
1833  * do generic HDLC initialization
1834  *
1835  * info  pointer to device instance information
1836  *
1837  * returns 0 if success, otherwise error code
1838  */
1839 static int hdlcdev_init(struct slgt_info *info)
1840 {
1841         int rc;
1842         struct net_device *dev;
1843         hdlc_device *hdlc;
1844
1845         /* allocate and initialize network and HDLC layer objects */
1846
1847         if (!(dev = alloc_hdlcdev(info))) {
1848                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1849                 return -ENOMEM;
1850         }
1851
1852         /* for network layer reporting purposes only */
1853         dev->mem_start = info->phys_reg_addr;
1854         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1855         dev->irq       = info->irq_level;
1856
1857         /* network layer callbacks and settings */
1858         dev->do_ioctl       = hdlcdev_ioctl;
1859         dev->open           = hdlcdev_open;
1860         dev->stop           = hdlcdev_close;
1861         dev->tx_timeout     = hdlcdev_tx_timeout;
1862         dev->watchdog_timeo = 10*HZ;
1863         dev->tx_queue_len   = 50;
1864
1865         /* generic HDLC layer callbacks and settings */
1866         hdlc         = dev_to_hdlc(dev);
1867         hdlc->attach = hdlcdev_attach;
1868         hdlc->xmit   = hdlcdev_xmit;
1869
1870         /* register objects with HDLC layer */
1871         if ((rc = register_hdlc_device(dev))) {
1872                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1873                 free_netdev(dev);
1874                 return rc;
1875         }
1876
1877         info->netdev = dev;
1878         return 0;
1879 }
1880
1881 /**
1882  * called by device driver when removing device instance
1883  * do generic HDLC cleanup
1884  *
1885  * info  pointer to device instance information
1886  */
1887 static void hdlcdev_exit(struct slgt_info *info)
1888 {
1889         unregister_hdlc_device(info->netdev);
1890         free_netdev(info->netdev);
1891         info->netdev = NULL;
1892 }
1893
1894 #endif /* ifdef CONFIG_HDLC */
1895
1896 /*
1897  * get async data from rx DMA buffers
1898  */
1899 static void rx_async(struct slgt_info *info)
1900 {
1901         struct tty_struct *tty = info->port.tty;
1902         struct mgsl_icount *icount = &info->icount;
1903         unsigned int start, end;
1904         unsigned char *p;
1905         unsigned char status;
1906         struct slgt_desc *bufs = info->rbufs;
1907         int i, count;
1908         int chars = 0;
1909         int stat;
1910         unsigned char ch;
1911
1912         start = end = info->rbuf_current;
1913
1914         while(desc_complete(bufs[end])) {
1915                 count = desc_count(bufs[end]) - info->rbuf_index;
1916                 p     = bufs[end].buf + info->rbuf_index;
1917
1918                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1919                 DBGDATA(info, p, count, "rx");
1920
1921                 for(i=0 ; i < count; i+=2, p+=2) {
1922                         ch = *p;
1923                         icount->rx++;
1924
1925                         stat = 0;
1926
1927                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1928                                 if (status & BIT1)
1929                                         icount->parity++;
1930                                 else if (status & BIT0)
1931                                         icount->frame++;
1932                                 /* discard char if tty control flags say so */
1933                                 if (status & info->ignore_status_mask)
1934                                         continue;
1935                                 if (status & BIT1)
1936                                         stat = TTY_PARITY;
1937                                 else if (status & BIT0)
1938                                         stat = TTY_FRAME;
1939                         }
1940                         if (tty) {
1941                                 tty_insert_flip_char(tty, ch, stat);
1942                                 chars++;
1943                         }
1944                 }
1945
1946                 if (i < count) {
1947                         /* receive buffer not completed */
1948                         info->rbuf_index += i;
1949                         mod_timer(&info->rx_timer, jiffies + 1);
1950                         break;
1951                 }
1952
1953                 info->rbuf_index = 0;
1954                 free_rbufs(info, end, end);
1955
1956                 if (++end == info->rbuf_count)
1957                         end = 0;
1958
1959                 /* if entire list searched then no frame available */
1960                 if (end == start)
1961                         break;
1962         }
1963
1964         if (tty && chars)
1965                 tty_flip_buffer_push(tty);
1966 }
1967
1968 /*
1969  * return next bottom half action to perform
1970  */
1971 static int bh_action(struct slgt_info *info)
1972 {
1973         unsigned long flags;
1974         int rc;
1975
1976         spin_lock_irqsave(&info->lock,flags);
1977
1978         if (info->pending_bh & BH_RECEIVE) {
1979                 info->pending_bh &= ~BH_RECEIVE;
1980                 rc = BH_RECEIVE;
1981         } else if (info->pending_bh & BH_TRANSMIT) {
1982                 info->pending_bh &= ~BH_TRANSMIT;
1983                 rc = BH_TRANSMIT;
1984         } else if (info->pending_bh & BH_STATUS) {
1985                 info->pending_bh &= ~BH_STATUS;
1986                 rc = BH_STATUS;
1987         } else {
1988                 /* Mark BH routine as complete */
1989                 info->bh_running = false;
1990                 info->bh_requested = false;
1991                 rc = 0;
1992         }
1993
1994         spin_unlock_irqrestore(&info->lock,flags);
1995
1996         return rc;
1997 }
1998
1999 /*
2000  * perform bottom half processing
2001  */
2002 static void bh_handler(struct work_struct *work)
2003 {
2004         struct slgt_info *info = container_of(work, struct slgt_info, task);
2005         int action;
2006
2007         if (!info)
2008                 return;
2009         info->bh_running = true;
2010
2011         while((action = bh_action(info))) {
2012                 switch (action) {
2013                 case BH_RECEIVE:
2014                         DBGBH(("%s bh receive\n", info->device_name));
2015                         switch(info->params.mode) {
2016                         case MGSL_MODE_ASYNC:
2017                                 rx_async(info);
2018                                 break;
2019                         case MGSL_MODE_HDLC:
2020                                 while(rx_get_frame(info));
2021                                 break;
2022                         case MGSL_MODE_RAW:
2023                         case MGSL_MODE_MONOSYNC:
2024                         case MGSL_MODE_BISYNC:
2025                                 while(rx_get_buf(info));
2026                                 break;
2027                         }
2028                         /* restart receiver if rx DMA buffers exhausted */
2029                         if (info->rx_restart)
2030                                 rx_start(info);
2031                         break;
2032                 case BH_TRANSMIT:
2033                         bh_transmit(info);
2034                         break;
2035                 case BH_STATUS:
2036                         DBGBH(("%s bh status\n", info->device_name));
2037                         info->ri_chkcount = 0;
2038                         info->dsr_chkcount = 0;
2039                         info->dcd_chkcount = 0;
2040                         info->cts_chkcount = 0;
2041                         break;
2042                 default:
2043                         DBGBH(("%s unknown action\n", info->device_name));
2044                         break;
2045                 }
2046         }
2047         DBGBH(("%s bh_handler exit\n", info->device_name));
2048 }
2049
2050 static void bh_transmit(struct slgt_info *info)
2051 {
2052         struct tty_struct *tty = info->port.tty;
2053
2054         DBGBH(("%s bh_transmit\n", info->device_name));
2055         if (tty)
2056                 tty_wakeup(tty);
2057 }
2058
2059 static void dsr_change(struct slgt_info *info, unsigned short status)
2060 {
2061         if (status & BIT3) {
2062                 info->signals |= SerialSignal_DSR;
2063                 info->input_signal_events.dsr_up++;
2064         } else {
2065                 info->signals &= ~SerialSignal_DSR;
2066                 info->input_signal_events.dsr_down++;
2067         }
2068         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2069         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2070                 slgt_irq_off(info, IRQ_DSR);
2071                 return;
2072         }
2073         info->icount.dsr++;
2074         wake_up_interruptible(&info->status_event_wait_q);
2075         wake_up_interruptible(&info->event_wait_q);
2076         info->pending_bh |= BH_STATUS;
2077 }
2078
2079 static void cts_change(struct slgt_info *info, unsigned short status)
2080 {
2081         if (status & BIT2) {
2082                 info->signals |= SerialSignal_CTS;
2083                 info->input_signal_events.cts_up++;
2084         } else {
2085                 info->signals &= ~SerialSignal_CTS;
2086                 info->input_signal_events.cts_down++;
2087         }
2088         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2089         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2090                 slgt_irq_off(info, IRQ_CTS);
2091                 return;
2092         }
2093         info->icount.cts++;
2094         wake_up_interruptible(&info->status_event_wait_q);
2095         wake_up_interruptible(&info->event_wait_q);
2096         info->pending_bh |= BH_STATUS;
2097
2098         if (info->port.flags & ASYNC_CTS_FLOW) {
2099                 if (info->port.tty) {
2100                         if (info->port.tty->hw_stopped) {
2101                                 if (info->signals & SerialSignal_CTS) {
2102                                         info->port.tty->hw_stopped = 0;
2103                                         info->pending_bh |= BH_TRANSMIT;
2104                                         return;
2105                                 }
2106                         } else {
2107                                 if (!(info->signals & SerialSignal_CTS))
2108                                         info->port.tty->hw_stopped = 1;
2109                         }
2110                 }
2111         }
2112 }
2113
2114 static void dcd_change(struct slgt_info *info, unsigned short status)
2115 {
2116         if (status & BIT1) {
2117                 info->signals |= SerialSignal_DCD;
2118                 info->input_signal_events.dcd_up++;
2119         } else {
2120                 info->signals &= ~SerialSignal_DCD;
2121                 info->input_signal_events.dcd_down++;
2122         }
2123         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2124         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2125                 slgt_irq_off(info, IRQ_DCD);
2126                 return;
2127         }
2128         info->icount.dcd++;
2129 #if SYNCLINK_GENERIC_HDLC
2130         if (info->netcount) {
2131                 if (info->signals & SerialSignal_DCD)
2132                         netif_carrier_on(info->netdev);
2133                 else
2134                         netif_carrier_off(info->netdev);
2135         }
2136 #endif
2137         wake_up_interruptible(&info->status_event_wait_q);
2138         wake_up_interruptible(&info->event_wait_q);
2139         info->pending_bh |= BH_STATUS;
2140
2141         if (info->port.flags & ASYNC_CHECK_CD) {
2142                 if (info->signals & SerialSignal_DCD)
2143                         wake_up_interruptible(&info->port.open_wait);
2144                 else {
2145                         if (info->port.tty)
2146                                 tty_hangup(info->port.tty);
2147                 }
2148         }
2149 }
2150
2151 static void ri_change(struct slgt_info *info, unsigned short status)
2152 {
2153         if (status & BIT0) {
2154                 info->signals |= SerialSignal_RI;
2155                 info->input_signal_events.ri_up++;
2156         } else {
2157                 info->signals &= ~SerialSignal_RI;
2158                 info->input_signal_events.ri_down++;
2159         }
2160         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2161         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2162                 slgt_irq_off(info, IRQ_RI);
2163                 return;
2164         }
2165         info->icount.rng++;
2166         wake_up_interruptible(&info->status_event_wait_q);
2167         wake_up_interruptible(&info->event_wait_q);
2168         info->pending_bh |= BH_STATUS;
2169 }
2170
2171 static void isr_serial(struct slgt_info *info)
2172 {
2173         unsigned short status = rd_reg16(info, SSR);
2174
2175         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2176
2177         wr_reg16(info, SSR, status); /* clear pending */
2178
2179         info->irq_occurred = true;
2180
2181         if (info->params.mode == MGSL_MODE_ASYNC) {
2182                 if (status & IRQ_TXIDLE) {
2183                         if (info->tx_count)
2184                                 isr_txeom(info, status);
2185                 }
2186                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2187                         info->icount.brk++;
2188                         /* process break detection if tty control allows */
2189                         if (info->port.tty) {
2190                                 if (!(status & info->ignore_status_mask)) {
2191                                         if (info->read_status_mask & MASK_BREAK) {
2192                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2193                                                 if (info->port.flags & ASYNC_SAK)
2194                                                         do_SAK(info->port.tty);
2195                                         }
2196                                 }
2197                         }
2198                 }
2199         } else {
2200                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2201                         isr_txeom(info, status);
2202
2203                 if (status & IRQ_RXIDLE) {
2204                         if (status & RXIDLE)
2205                                 info->icount.rxidle++;
2206                         else
2207                                 info->icount.exithunt++;
2208                         wake_up_interruptible(&info->event_wait_q);
2209                 }
2210
2211                 if (status & IRQ_RXOVER)
2212                         rx_start(info);
2213         }
2214
2215         if (status & IRQ_DSR)
2216                 dsr_change(info, status);
2217         if (status & IRQ_CTS)
2218                 cts_change(info, status);
2219         if (status & IRQ_DCD)
2220                 dcd_change(info, status);
2221         if (status & IRQ_RI)
2222                 ri_change(info, status);
2223 }
2224
2225 static void isr_rdma(struct slgt_info *info)
2226 {
2227         unsigned int status = rd_reg32(info, RDCSR);
2228
2229         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2230
2231         /* RDCSR (rx DMA control/status)
2232          *
2233          * 31..07  reserved
2234          * 06      save status byte to DMA buffer
2235          * 05      error
2236          * 04      eol (end of list)
2237          * 03      eob (end of buffer)
2238          * 02      IRQ enable
2239          * 01      reset
2240          * 00      enable
2241          */
2242         wr_reg32(info, RDCSR, status);  /* clear pending */
2243
2244         if (status & (BIT5 + BIT4)) {
2245                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2246                 info->rx_restart = true;
2247         }
2248         info->pending_bh |= BH_RECEIVE;
2249 }
2250
2251 static void isr_tdma(struct slgt_info *info)
2252 {
2253         unsigned int status = rd_reg32(info, TDCSR);
2254
2255         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2256
2257         /* TDCSR (tx DMA control/status)
2258          *
2259          * 31..06  reserved
2260          * 05      error
2261          * 04      eol (end of list)
2262          * 03      eob (end of buffer)
2263          * 02      IRQ enable
2264          * 01      reset
2265          * 00      enable
2266          */
2267         wr_reg32(info, TDCSR, status);  /* clear pending */
2268
2269         if (status & (BIT5 + BIT4 + BIT3)) {
2270                 // another transmit buffer has completed
2271                 // run bottom half to get more send data from user
2272                 info->pending_bh |= BH_TRANSMIT;
2273         }
2274 }
2275
2276 static void isr_txeom(struct slgt_info *info, unsigned short status)
2277 {
2278         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2279
2280         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2281         tdma_reset(info);
2282         reset_tbufs(info);
2283         if (status & IRQ_TXUNDER) {
2284                 unsigned short val = rd_reg16(info, TCR);
2285                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2286                 wr_reg16(info, TCR, val); /* clear reset bit */
2287         }
2288
2289         if (info->tx_active) {
2290                 if (info->params.mode != MGSL_MODE_ASYNC) {
2291                         if (status & IRQ_TXUNDER)
2292                                 info->icount.txunder++;
2293                         else if (status & IRQ_TXIDLE)
2294                                 info->icount.txok++;
2295                 }
2296
2297                 info->tx_active = false;
2298                 info->tx_count = 0;
2299
2300                 del_timer(&info->tx_timer);
2301
2302                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2303                         info->signals &= ~SerialSignal_RTS;
2304                         info->drop_rts_on_tx_done = false;
2305                         set_signals(info);
2306                 }
2307
2308 #if SYNCLINK_GENERIC_HDLC
2309                 if (info->netcount)
2310                         hdlcdev_tx_done(info);
2311                 else
2312 #endif
2313                 {
2314                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2315                                 tx_stop(info);
2316                                 return;
2317                         }
2318                         info->pending_bh |= BH_TRANSMIT;
2319                 }
2320         }
2321 }
2322
2323 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2324 {
2325         struct cond_wait *w, *prev;
2326
2327         /* wake processes waiting for specific transitions */
2328         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2329                 if (w->data & changed) {
2330                         w->data = state;
2331                         wake_up_interruptible(&w->q);
2332                         if (prev != NULL)
2333                                 prev->next = w->next;
2334                         else
2335                                 info->gpio_wait_q = w->next;
2336                 } else
2337                         prev = w;
2338         }
2339 }
2340
2341 /* interrupt service routine
2342  *
2343  *      irq     interrupt number
2344  *      dev_id  device ID supplied during interrupt registration
2345  */
2346 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2347 {
2348         struct slgt_info *info = dev_id;
2349         unsigned int gsr;
2350         unsigned int i;
2351
2352         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2353
2354         spin_lock(&info->lock);
2355
2356         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2357                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2358                 info->irq_occurred = true;
2359                 for(i=0; i < info->port_count ; i++) {
2360                         if (info->port_array[i] == NULL)
2361                                 continue;
2362                         if (gsr & (BIT8 << i))
2363                                 isr_serial(info->port_array[i]);
2364                         if (gsr & (BIT16 << (i*2)))
2365                                 isr_rdma(info->port_array[i]);
2366                         if (gsr & (BIT17 << (i*2)))
2367                                 isr_tdma(info->port_array[i]);
2368                 }
2369         }
2370
2371         if (info->gpio_present) {
2372                 unsigned int state;
2373                 unsigned int changed;
2374                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2375                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2376                         /* read latched state of GPIO signals */
2377                         state = rd_reg32(info, IOVR);
2378                         /* clear pending GPIO interrupt bits */
2379                         wr_reg32(info, IOSR, changed);
2380                         for (i=0 ; i < info->port_count ; i++) {
2381                                 if (info->port_array[i] != NULL)
2382                                         isr_gpio(info->port_array[i], changed, state);
2383                         }
2384                 }
2385         }
2386
2387         for(i=0; i < info->port_count ; i++) {
2388                 struct slgt_info *port = info->port_array[i];
2389
2390                 if (port && (port->port.count || port->netcount) &&
2391                     port->pending_bh && !port->bh_running &&
2392                     !port->bh_requested) {
2393                         DBGISR(("%s bh queued\n", port->device_name));
2394                         schedule_work(&port->task);
2395                         port->bh_requested = true;
2396                 }
2397         }
2398
2399         spin_unlock(&info->lock);
2400
2401         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2402         return IRQ_HANDLED;
2403 }
2404
2405 static int startup(struct slgt_info *info)
2406 {
2407         DBGINFO(("%s startup\n", info->device_name));
2408
2409         if (info->port.flags & ASYNC_INITIALIZED)
2410                 return 0;
2411
2412         if (!info->tx_buf) {
2413                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2414                 if (!info->tx_buf) {
2415                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2416                         return -ENOMEM;
2417                 }
2418         }
2419
2420         info->pending_bh = 0;
2421
2422         memset(&info->icount, 0, sizeof(info->icount));
2423
2424         /* program hardware for current parameters */
2425         change_params(info);
2426
2427         if (info->port.tty)
2428                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2429
2430         info->port.flags |= ASYNC_INITIALIZED;
2431
2432         return 0;
2433 }
2434
2435 /*
2436  *  called by close() and hangup() to shutdown hardware
2437  */
2438 static void shutdown(struct slgt_info *info)
2439 {
2440         unsigned long flags;
2441
2442         if (!(info->port.flags & ASYNC_INITIALIZED))
2443                 return;
2444
2445         DBGINFO(("%s shutdown\n", info->device_name));
2446
2447         /* clear status wait queue because status changes */
2448         /* can't happen after shutting down the hardware */
2449         wake_up_interruptible(&info->status_event_wait_q);
2450         wake_up_interruptible(&info->event_wait_q);
2451
2452         del_timer_sync(&info->tx_timer);
2453         del_timer_sync(&info->rx_timer);
2454
2455         kfree(info->tx_buf);
2456         info->tx_buf = NULL;
2457
2458         spin_lock_irqsave(&info->lock,flags);
2459
2460         tx_stop(info);
2461         rx_stop(info);
2462
2463         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2464
2465         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2466                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2467                 set_signals(info);
2468         }
2469
2470         flush_cond_wait(&info->gpio_wait_q);
2471
2472         spin_unlock_irqrestore(&info->lock,flags);
2473
2474         if (info->port.tty)
2475                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2476
2477         info->port.flags &= ~ASYNC_INITIALIZED;
2478 }
2479
2480 static void program_hw(struct slgt_info *info)
2481 {
2482         unsigned long flags;
2483
2484         spin_lock_irqsave(&info->lock,flags);
2485
2486         rx_stop(info);
2487         tx_stop(info);
2488
2489         if (info->params.mode != MGSL_MODE_ASYNC ||
2490             info->netcount)
2491                 sync_mode(info);
2492         else
2493                 async_mode(info);
2494
2495         set_signals(info);
2496
2497         info->dcd_chkcount = 0;
2498         info->cts_chkcount = 0;
2499         info->ri_chkcount = 0;
2500         info->dsr_chkcount = 0;
2501
2502         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2503         get_signals(info);
2504
2505         if (info->netcount ||
2506             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2507                 rx_start(info);
2508
2509         spin_unlock_irqrestore(&info->lock,flags);
2510 }
2511
2512 /*
2513  * reconfigure adapter based on new parameters
2514  */
2515 static void change_params(struct slgt_info *info)
2516 {
2517         unsigned cflag;
2518         int bits_per_char;
2519
2520         if (!info->port.tty || !info->port.tty->termios)
2521                 return;
2522         DBGINFO(("%s change_params\n", info->device_name));
2523
2524         cflag = info->port.tty->termios->c_cflag;
2525
2526         /* if B0 rate (hangup) specified then negate DTR and RTS */
2527         /* otherwise assert DTR and RTS */
2528         if (cflag & CBAUD)
2529                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2530         else
2531                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2532
2533         /* byte size and parity */
2534
2535         switch (cflag & CSIZE) {
2536         case CS5: info->params.data_bits = 5; break;
2537         case CS6: info->params.data_bits = 6; break;
2538         case CS7: info->params.data_bits = 7; break;
2539         case CS8: info->params.data_bits = 8; break;
2540         default:  info->params.data_bits = 7; break;
2541         }
2542
2543         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2544
2545         if (cflag & PARENB)
2546                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2547         else
2548                 info->params.parity = ASYNC_PARITY_NONE;
2549
2550         /* calculate number of jiffies to transmit a full
2551          * FIFO (32 bytes) at specified data rate
2552          */
2553         bits_per_char = info->params.data_bits +
2554                         info->params.stop_bits + 1;
2555
2556         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2557
2558         if (info->params.data_rate) {
2559                 info->timeout = (32*HZ*bits_per_char) /
2560                                 info->params.data_rate;
2561         }
2562         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2563
2564         if (cflag & CRTSCTS)
2565                 info->port.flags |= ASYNC_CTS_FLOW;
2566         else
2567                 info->port.flags &= ~ASYNC_CTS_FLOW;
2568
2569         if (cflag & CLOCAL)
2570                 info->port.flags &= ~ASYNC_CHECK_CD;
2571         else
2572                 info->port.flags |= ASYNC_CHECK_CD;
2573
2574         /* process tty input control flags */
2575
2576         info->read_status_mask = IRQ_RXOVER;
2577         if (I_INPCK(info->port.tty))
2578                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2579         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2580                 info->read_status_mask |= MASK_BREAK;
2581         if (I_IGNPAR(info->port.tty))
2582                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2583         if (I_IGNBRK(info->port.tty)) {
2584                 info->ignore_status_mask |= MASK_BREAK;
2585                 /* If ignoring parity and break indicators, ignore
2586                  * overruns too.  (For real raw support).
2587                  */
2588                 if (I_IGNPAR(info->port.tty))
2589                         info->ignore_status_mask |= MASK_OVERRUN;
2590         }
2591
2592         program_hw(info);
2593 }
2594
2595 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2596 {
2597         DBGINFO(("%s get_stats\n",  info->device_name));
2598         if (!user_icount) {
2599                 memset(&info->icount, 0, sizeof(info->icount));
2600         } else {
2601                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2602                         return -EFAULT;
2603         }
2604         return 0;
2605 }
2606
2607 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2608 {
2609         DBGINFO(("%s get_params\n", info->device_name));
2610         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2611                 return -EFAULT;
2612         return 0;
2613 }
2614
2615 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2616 {
2617         unsigned long flags;
2618         MGSL_PARAMS tmp_params;
2619
2620         DBGINFO(("%s set_params\n", info->device_name));
2621         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2622                 return -EFAULT;
2623
2624         spin_lock_irqsave(&info->lock, flags);
2625         memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2626         spin_unlock_irqrestore(&info->lock, flags);
2627
2628         change_params(info);
2629
2630         return 0;
2631 }
2632
2633 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2634 {
2635         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2636         if (put_user(info->idle_mode, idle_mode))
2637                 return -EFAULT;
2638         return 0;
2639 }
2640
2641 static int set_txidle(struct slgt_info *info, int idle_mode)
2642 {
2643         unsigned long flags;
2644         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2645         spin_lock_irqsave(&info->lock,flags);
2646         info->idle_mode = idle_mode;
2647         if (info->params.mode != MGSL_MODE_ASYNC)
2648                 tx_set_idle(info);
2649         spin_unlock_irqrestore(&info->lock,flags);
2650         return 0;
2651 }
2652
2653 static int tx_enable(struct slgt_info *info, int enable)
2654 {
2655         unsigned long flags;
2656         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2657         spin_lock_irqsave(&info->lock,flags);
2658         if (enable) {
2659                 if (!info->tx_enabled)
2660                         tx_start(info);
2661         } else {
2662                 if (info->tx_enabled)
2663                         tx_stop(info);
2664         }
2665         spin_unlock_irqrestore(&info->lock,flags);
2666         return 0;
2667 }
2668
2669 /*
2670  * abort transmit HDLC frame
2671  */
2672 static int tx_abort(struct slgt_info *info)
2673 {
2674         unsigned long flags;
2675         DBGINFO(("%s tx_abort\n", info->device_name));
2676         spin_lock_irqsave(&info->lock,flags);
2677         tdma_reset(info);
2678         spin_unlock_irqrestore(&info->lock,flags);
2679         return 0;
2680 }
2681
2682 static int rx_enable(struct slgt_info *info, int enable)
2683 {
2684         unsigned long flags;
2685         DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2686         spin_lock_irqsave(&info->lock,flags);
2687         if (enable) {
2688                 if (!info->rx_enabled)
2689                         rx_start(info);
2690                 else if (enable == 2) {
2691                         /* force hunt mode (write 1 to RCR[3]) */
2692                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2693                 }
2694         } else {
2695                 if (info->rx_enabled)
2696                         rx_stop(info);
2697         }
2698         spin_unlock_irqrestore(&info->lock,flags);
2699         return 0;
2700 }
2701
2702 /*
2703  *  wait for specified event to occur
2704  */
2705 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2706 {
2707         unsigned long flags;
2708         int s;
2709         int rc=0;
2710         struct mgsl_icount cprev, cnow;
2711         int events;
2712         int mask;
2713         struct  _input_signal_events oldsigs, newsigs;
2714         DECLARE_WAITQUEUE(wait, current);
2715
2716         if (get_user(mask, mask_ptr))
2717                 return -EFAULT;
2718
2719         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2720
2721         spin_lock_irqsave(&info->lock,flags);
2722
2723         /* return immediately if state matches requested events */
2724         get_signals(info);
2725         s = info->signals;
2726
2727         events = mask &
2728                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2729                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2730                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2731                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2732         if (events) {
2733                 spin_unlock_irqrestore(&info->lock,flags);
2734                 goto exit;
2735         }
2736
2737         /* save current irq counts */
2738         cprev = info->icount;
2739         oldsigs = info->input_signal_events;
2740
2741         /* enable hunt and idle irqs if needed */
2742         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2743                 unsigned short val = rd_reg16(info, SCR);
2744                 if (!(val & IRQ_RXIDLE))
2745                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2746         }
2747
2748         set_current_state(TASK_INTERRUPTIBLE);
2749         add_wait_queue(&info->event_wait_q, &wait);
2750
2751         spin_unlock_irqrestore(&info->lock,flags);
2752
2753         for(;;) {
2754                 schedule();
2755                 if (signal_pending(current)) {
2756                         rc = -ERESTARTSYS;
2757                         break;
2758                 }
2759
2760                 /* get current irq counts */
2761                 spin_lock_irqsave(&info->lock,flags);
2762                 cnow = info->icount;
2763                 newsigs = info->input_signal_events;
2764                 set_current_state(TASK_INTERRUPTIBLE);
2765                 spin_unlock_irqrestore(&info->lock,flags);
2766
2767                 /* if no change, wait aborted for some reason */
2768                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2769                     newsigs.dsr_down == oldsigs.dsr_down &&
2770                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2771                     newsigs.dcd_down == oldsigs.dcd_down &&
2772                     newsigs.cts_up   == oldsigs.cts_up   &&
2773                     newsigs.cts_down == oldsigs.cts_down &&
2774                     newsigs.ri_up    == oldsigs.ri_up    &&
2775                     newsigs.ri_down  == oldsigs.ri_down  &&
2776                     cnow.exithunt    == cprev.exithunt   &&
2777                     cnow.rxidle      == cprev.rxidle) {
2778                         rc = -EIO;
2779                         break;
2780                 }
2781
2782                 events = mask &
2783                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2784                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2785                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2786                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2787                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2788                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2789                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2790                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2791                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2792                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2793                 if (events)
2794                         break;
2795
2796                 cprev = cnow;
2797                 oldsigs = newsigs;
2798         }
2799
2800         remove_wait_queue(&info->event_wait_q, &wait);
2801         set_current_state(TASK_RUNNING);
2802
2803
2804         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2805                 spin_lock_irqsave(&info->lock,flags);
2806                 if (!waitqueue_active(&info->event_wait_q)) {
2807                         /* disable enable exit hunt mode/idle rcvd IRQs */
2808                         wr_reg16(info, SCR,
2809                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2810                 }
2811                 spin_unlock_irqrestore(&info->lock,flags);
2812         }
2813 exit:
2814         if (rc == 0)
2815                 rc = put_user(events, mask_ptr);
2816         return rc;
2817 }
2818
2819 static int get_interface(struct slgt_info *info, int __user *if_mode)
2820 {
2821         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2822         if (put_user(info->if_mode, if_mode))
2823                 return -EFAULT;
2824         return 0;
2825 }
2826
2827 static int set_interface(struct slgt_info *info, int if_mode)
2828 {
2829         unsigned long flags;
2830         unsigned short val;
2831
2832         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2833         spin_lock_irqsave(&info->lock,flags);
2834         info->if_mode = if_mode;
2835
2836         msc_set_vcr(info);
2837
2838         /* TCR (tx control) 07  1=RTS driver control */
2839         val = rd_reg16(info, TCR);
2840         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2841                 val |= BIT7;
2842         else
2843                 val &= ~BIT7;
2844         wr_reg16(info, TCR, val);
2845
2846         spin_unlock_irqrestore(&info->lock,flags);
2847         return 0;
2848 }
2849
2850 /*
2851  * set general purpose IO pin state and direction
2852  *
2853  * user_gpio fields:
2854  * state   each bit indicates a pin state
2855  * smask   set bit indicates pin state to set
2856  * dir     each bit indicates a pin direction (0=input, 1=output)
2857  * dmask   set bit indicates pin direction to set
2858  */
2859 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2860 {
2861         unsigned long flags;
2862         struct gpio_desc gpio;
2863         __u32 data;
2864
2865         if (!info->gpio_present)
2866                 return -EINVAL;
2867         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2868                 return -EFAULT;
2869         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2870                  info->device_name, gpio.state, gpio.smask,
2871                  gpio.dir, gpio.dmask));
2872
2873         spin_lock_irqsave(&info->lock,flags);
2874         if (gpio.dmask) {
2875                 data = rd_reg32(info, IODR);
2876                 data |= gpio.dmask & gpio.dir;
2877                 data &= ~(gpio.dmask & ~gpio.dir);
2878                 wr_reg32(info, IODR, data);
2879         }
2880         if (gpio.smask) {
2881                 data = rd_reg32(info, IOVR);
2882                 data |= gpio.smask & gpio.state;
2883                 data &= ~(gpio.smask & ~gpio.state);
2884                 wr_reg32(info, IOVR, data);
2885         }
2886         spin_unlock_irqrestore(&info->lock,flags);
2887
2888         return 0;
2889 }
2890
2891 /*
2892  * get general purpose IO pin state and direction
2893  */
2894 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2895 {
2896         struct gpio_desc gpio;
2897         if (!info->gpio_present)
2898                 return -EINVAL;
2899         gpio.state = rd_reg32(info, IOVR);
2900         gpio.smask = 0xffffffff;
2901         gpio.dir   = rd_reg32(info, IODR);
2902         gpio.dmask = 0xffffffff;
2903         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2904                 return -EFAULT;
2905         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2906                  info->device_name, gpio.state, gpio.dir));
2907         return 0;
2908 }
2909
2910 /*
2911  * conditional wait facility
2912  */
2913 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2914 {
2915         init_waitqueue_head(&w->q);
2916         init_waitqueue_entry(&w->wait, current);
2917         w->data = data;
2918 }
2919
2920 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2921 {
2922         set_current_state(TASK_INTERRUPTIBLE);
2923         add_wait_queue(&w->q, &w->wait);
2924         w->next = *head;
2925         *head = w;
2926 }
2927
2928 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2929 {
2930         struct cond_wait *w, *prev;
2931         remove_wait_queue(&cw->q, &cw->wait);
2932         set_current_state(TASK_RUNNING);
2933         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2934                 if (w == cw) {
2935                         if (prev != NULL)
2936                                 prev->next = w->next;
2937                         else
2938                                 *head = w->next;
2939                         break;
2940                 }
2941         }
2942 }
2943
2944 static void flush_cond_wait(struct cond_wait **head)
2945 {
2946         while (*head != NULL) {
2947                 wake_up_interruptible(&(*head)->q);
2948                 *head = (*head)->next;
2949         }
2950 }
2951
2952 /*
2953  * wait for general purpose I/O pin(s) to enter specified state
2954  *
2955  * user_gpio fields:
2956  * state - bit indicates target pin state
2957  * smask - set bit indicates watched pin
2958  *
2959  * The wait ends when at least one watched pin enters the specified
2960  * state. When 0 (no error) is returned, user_gpio->state is set to the
2961  * state of all GPIO pins when the wait ends.
2962  *
2963  * Note: Each pin may be a dedicated input, dedicated output, or
2964  * configurable input/output. The number and configuration of pins
2965  * varies with the specific adapter model. Only input pins (dedicated
2966  * or configured) can be monitored with this function.
2967  */
2968 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2969 {
2970         unsigned long flags;
2971         int rc = 0;
2972         struct gpio_desc gpio;
2973         struct cond_wait wait;
2974         u32 state;
2975
2976         if (!info->gpio_present)
2977                 return -EINVAL;
2978         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2979                 return -EFAULT;
2980         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2981                  info->device_name, gpio.state, gpio.smask));
2982         /* ignore output pins identified by set IODR bit */
2983         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2984                 return -EINVAL;
2985         init_cond_wait(&wait, gpio.smask);
2986
2987         spin_lock_irqsave(&info->lock, flags);
2988         /* enable interrupts for watched pins */
2989         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2990         /* get current pin states */
2991         state = rd_reg32(info, IOVR);
2992
2993         if (gpio.smask & ~(state ^ gpio.state)) {
2994                 /* already in target state */
2995                 gpio.state = state;
2996         } else {
2997                 /* wait for target state */
2998                 add_cond_wait(&info->gpio_wait_q, &wait);
2999                 spin_unlock_irqrestore(&info->lock, flags);
3000                 schedule();
3001                 if (signal_pending(current))
3002                         rc = -ERESTARTSYS;
3003                 else
3004                         gpio.state = wait.data;
3005                 spin_lock_irqsave(&info->lock, flags);
3006                 remove_cond_wait(&info->gpio_wait_q, &wait);
3007         }
3008
3009         /* disable all GPIO interrupts if no waiting processes */
3010         if (info->gpio_wait_q == NULL)
3011                 wr_reg32(info, IOER, 0);
3012         spin_unlock_irqrestore(&info->lock,flags);
3013
3014         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3015                 rc = -EFAULT;
3016         return rc;
3017 }
3018
3019 static int modem_input_wait(struct slgt_info *info,int arg)
3020 {
3021         unsigned long flags;
3022         int rc;
3023         struct mgsl_icount cprev, cnow;
3024         DECLARE_WAITQUEUE(wait, current);
3025
3026         /* save current irq counts */
3027         spin_lock_irqsave(&info->lock,flags);
3028         cprev = info->icount;
3029         add_wait_queue(&info->status_event_wait_q, &wait);
3030         set_current_state(TASK_INTERRUPTIBLE);
3031         spin_unlock_irqrestore(&info->lock,flags);
3032
3033         for(;;) {
3034                 schedule();
3035                 if (signal_pending(current)) {
3036                         rc = -ERESTARTSYS;
3037                         break;
3038                 }
3039
3040                 /* get new irq counts */
3041                 spin_lock_irqsave(&info->lock,flags);
3042                 cnow = info->icount;
3043                 set_current_state(TASK_INTERRUPTIBLE);
3044                 spin_unlock_irqrestore(&info->lock,flags);
3045
3046                 /* if no change, wait aborted for some reason */
3047                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3048                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3049                         rc = -EIO;
3050                         break;
3051                 }
3052
3053                 /* check for change in caller specified modem input */
3054                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3055                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3056                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3057                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3058                         rc = 0;
3059                         break;
3060                 }
3061
3062                 cprev = cnow;
3063         }
3064         remove_wait_queue(&info->status_event_wait_q, &wait);
3065         set_current_state(TASK_RUNNING);
3066         return rc;
3067 }
3068
3069 /*
3070  *  return state of serial control and status signals
3071  */
3072 static int tiocmget(struct tty_struct *tty, struct file *file)
3073 {
3074         struct slgt_info *info = tty->driver_data;
3075         unsigned int result;
3076         unsigned long flags;
3077
3078         spin_lock_irqsave(&info->lock,flags);
3079         get_signals(info);
3080         spin_unlock_irqrestore(&info->lock,flags);
3081
3082         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3083                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3084                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3085                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3086                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3087                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3088
3089         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3090         return result;
3091 }
3092
3093 /*
3094  * set modem control signals (DTR/RTS)
3095  *
3096  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3097  *              TIOCMSET = set/clear signal values
3098  *      value   bit mask for command
3099  */
3100 static int tiocmset(struct tty_struct *tty, struct file *file,
3101                     unsigned int set, unsigned int clear)
3102 {
3103         struct slgt_info *info = tty->driver_data;
3104         unsigned long flags;
3105
3106         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3107
3108         if (set & TIOCM_RTS)
3109                 info->signals |= SerialSignal_RTS;
3110         if (set & TIOCM_DTR)
3111                 info->signals |= SerialSignal_DTR;
3112         if (clear & TIOCM_RTS)
3113                 info->signals &= ~SerialSignal_RTS;
3114         if (clear & TIOCM_DTR)
3115                 info->signals &= ~SerialSignal_DTR;
3116
3117         spin_lock_irqsave(&info->lock,flags);
3118         set_signals(info);
3119         spin_unlock_irqrestore(&info->lock,flags);
3120         return 0;
3121 }
3122
3123 /*
3124  *  block current process until the device is ready to open
3125  */
3126 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3127                            struct slgt_info *info)
3128 {
3129         DECLARE_WAITQUEUE(wait, current);
3130         int             retval;
3131         bool            do_clocal = false;
3132         bool            extra_count = false;
3133         unsigned long   flags;
3134
3135         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3136
3137         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3138                 /* nonblock mode is set or port is not enabled */
3139                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3140                 return 0;
3141         }
3142
3143         if (tty->termios->c_cflag & CLOCAL)
3144                 do_clocal = true;
3145
3146         /* Wait for carrier detect and the line to become
3147          * free (i.e., not in use by the callout).  While we are in
3148          * this loop, info->port.count is dropped by one, so that
3149          * close() knows when to free things.  We restore it upon
3150          * exit, either normal or abnormal.
3151          */
3152
3153         retval = 0;
3154         add_wait_queue(&info->port.open_wait, &wait);
3155
3156         spin_lock_irqsave(&info->lock, flags);
3157         if (!tty_hung_up_p(filp)) {
3158                 extra_count = true;
3159                 info->port.count--;
3160         }
3161         spin_unlock_irqrestore(&info->lock, flags);
3162         info->port.blocked_open++;
3163
3164         while (1) {
3165                 if ((tty->termios->c_cflag & CBAUD)) {
3166                         spin_lock_irqsave(&info->lock,flags);
3167                         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3168                         set_signals(info);
3169                         spin_unlock_irqrestore(&info->lock,flags);
3170                 }
3171
3172                 set_current_state(TASK_INTERRUPTIBLE);
3173
3174                 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)){
3175                         retval = (info->port.flags & ASYNC_HUP_NOTIFY) ?
3176                                         -EAGAIN : -ERESTARTSYS;
3177                         break;
3178                 }
3179
3180                 spin_lock_irqsave(&info->lock,flags);
3181                 get_signals(info);
3182                 spin_unlock_irqrestore(&info->lock,flags);
3183
3184                 if (!(info->port.flags & ASYNC_CLOSING) &&
3185                     (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3186                         break;
3187                 }
3188
3189                 if (signal_pending(current)) {
3190                         retval = -ERESTARTSYS;
3191                         break;
3192                 }
3193
3194                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3195                 schedule();
3196         }
3197
3198         set_current_state(TASK_RUNNING);
3199         remove_wait_queue(&info->port.open_wait, &wait);
3200
3201         if (extra_count)
3202                 info->port.count++;
3203         info->port.blocked_open--;
3204
3205         if (!retval)
3206                 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3207
3208         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3209         return retval;
3210 }
3211
3212 static int alloc_tmp_rbuf(struct slgt_info *info)
3213 {
3214         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3215         if (info->tmp_rbuf == NULL)
3216                 return -ENOMEM;
3217         return 0;
3218 }
3219
3220 static void free_tmp_rbuf(struct slgt_info *info)
3221 {
3222         kfree(info->tmp_rbuf);
3223         info->tmp_rbuf = NULL;
3224 }
3225
3226 /*
3227  * allocate DMA descriptor lists.
3228  */
3229 static int alloc_desc(struct slgt_info *info)
3230 {
3231         unsigned int i;
3232         unsigned int pbufs;
3233
3234         /* allocate memory to hold descriptor lists */
3235         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3236         if (info->bufs == NULL)
3237                 return -ENOMEM;
3238
3239         memset(info->bufs, 0, DESC_LIST_SIZE);
3240
3241         info->rbufs = (struct slgt_desc*)info->bufs;
3242         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3243
3244         pbufs = (unsigned int)info->bufs_dma_addr;
3245
3246         /*
3247          * Build circular lists of descriptors
3248          */
3249
3250         for (i=0; i < info->rbuf_count; i++) {
3251                 /* physical address of this descriptor */
3252                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3253
3254                 /* physical address of next descriptor */
3255                 if (i == info->rbuf_count - 1)
3256                         info->rbufs[i].next = cpu_to_le32(pbufs);
3257                 else
3258                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3259                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3260         }
3261
3262         for (i=0; i < info->tbuf_count; i++) {
3263                 /* physical address of this descriptor */
3264                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3265
3266                 /* physical address of next descriptor */
3267                 if (i == info->tbuf_count - 1)
3268                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3269                 else
3270                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3271         }
3272
3273         return 0;
3274 }
3275
3276 static void free_desc(struct slgt_info *info)
3277 {
3278         if (info->bufs != NULL) {
3279                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3280                 info->bufs  = NULL;
3281                 info->rbufs = NULL;
3282                 info->tbufs = NULL;
3283         }
3284 }
3285
3286 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3287 {
3288         int i;
3289         for (i=0; i < count; i++) {
3290                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3291                         return -ENOMEM;
3292                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3293         }
3294         return 0;
3295 }
3296
3297 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3298 {
3299         int i;
3300         for (i=0; i < count; i++) {
3301                 if (bufs[i].buf == NULL)
3302                         continue;
3303                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3304                 bufs[i].buf = NULL;
3305         }
3306 }
3307
3308 static int alloc_dma_bufs(struct slgt_info *info)
3309 {
3310         info->rbuf_count = 32;
3311         info->tbuf_count = 32;
3312
3313         if (alloc_desc(info) < 0 ||
3314             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3315             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3316             alloc_tmp_rbuf(info) < 0) {
3317                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3318                 return -ENOMEM;
3319         }
3320         reset_rbufs(info);
3321         return 0;
3322 }
3323
3324 static void free_dma_bufs(struct slgt_info *info)
3325 {
3326         if (info->bufs) {
3327                 free_bufs(info, info->rbufs, info->rbuf_count);
3328                 free_bufs(info, info->tbufs, info->tbuf_count);
3329                 free_desc(info);
3330         }
3331         free_tmp_rbuf(info);
3332 }
3333
3334 static int claim_resources(struct slgt_info *info)
3335 {
3336         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3337                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3338                         info->device_name, info->phys_reg_addr));
3339                 info->init_error = DiagStatus_AddressConflict;
3340                 goto errout;
3341         }
3342         else
3343                 info->reg_addr_requested = true;
3344
3345         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3346         if (!info->reg_addr) {
3347                 DBGERR(("%s cant map device registers, addr=%08X\n",
3348                         info->device_name, info->phys_reg_addr));
3349                 info->init_error = DiagStatus_CantAssignPciResources;
3350                 goto errout;
3351         }
3352         return 0;
3353
3354 errout:
3355         release_resources(info);
3356         return -ENODEV;
3357 }
3358
3359 static void release_resources(struct slgt_info *info)
3360 {
3361         if (info->irq_requested) {
3362                 free_irq(info->irq_level, info);
3363                 info->irq_requested = false;
3364         }
3365
3366         if (info->reg_addr_requested) {
3367                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3368                 info->reg_addr_requested = false;
3369         }
3370
3371         if (info->reg_addr) {
3372                 iounmap(info->reg_addr);
3373                 info->reg_addr = NULL;
3374         }
3375 }
3376
3377 /* Add the specified device instance data structure to the
3378  * global linked list of devices and increment the device count.
3379  */
3380 static void add_device(struct slgt_info *info)
3381 {
3382         char *devstr;
3383
3384         info->next_device = NULL;
3385         info->line = slgt_device_count;
3386         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3387
3388         if (info->line < MAX_DEVICES) {
3389                 if (maxframe[info->line])
3390                         info->max_frame_size = maxframe[info->line];
3391                 info->dosyncppp = dosyncppp[info->line];
3392         }
3393
3394         slgt_device_count++;
3395
3396         if (!slgt_device_list)
3397                 slgt_device_list = info;
3398         else {
3399                 struct slgt_info *current_dev = slgt_device_list;
3400                 while(current_dev->next_device)
3401                         current_dev = current_dev->next_device;
3402                 current_dev->next_device = info;
3403         }
3404
3405         if (info->max_frame_size < 4096)
3406                 info->max_frame_size = 4096;
3407         else if (info->max_frame_size > 65535)
3408                 info->max_frame_size = 65535;
3409
3410         switch(info->pdev->device) {
3411         case SYNCLINK_GT_DEVICE_ID:
3412                 devstr = "GT";
3413                 break;
3414         case SYNCLINK_GT2_DEVICE_ID:
3415                 devstr = "GT2";
3416                 break;
3417         case SYNCLINK_GT4_DEVICE_ID:
3418                 devstr = "GT4";
3419                 break;
3420         case SYNCLINK_AC_DEVICE_ID:
3421                 devstr = "AC";
3422                 info->params.mode = MGSL_MODE_ASYNC;
3423                 break;
3424         default:
3425                 devstr = "(unknown model)";
3426         }
3427         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3428                 devstr, info->device_name, info->phys_reg_addr,
3429                 info->irq_level, info->max_frame_size);
3430
3431 #if SYNCLINK_GENERIC_HDLC
3432         hdlcdev_init(info);
3433 #endif
3434 }
3435
3436 /*
3437  *  allocate device instance structure, return NULL on failure
3438  */
3439 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3440 {
3441         struct slgt_info *info;
3442
3443         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3444
3445         if (!info) {
3446                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3447                         driver_name, adapter_num, port_num));
3448         } else {
3449                 tty_port_init(&info->port);
3450                 info->magic = MGSL_MAGIC;
3451                 INIT_WORK(&info->task, bh_handler);
3452                 info->max_frame_size = 4096;
3453                 info->raw_rx_size = DMABUFSIZE;
3454                 info->port.close_delay = 5*HZ/10;
3455                 info->port.closing_wait = 30*HZ;
3456                 init_waitqueue_head(&info->status_event_wait_q);
3457                 init_waitqueue_head(&info->event_wait_q);
3458                 spin_lock_init(&info->netlock);
3459                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3460                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3461                 info->adapter_num = adapter_num;
3462                 info->port_num = port_num;
3463
3464                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3465                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3466
3467                 /* Copy configuration info to device instance data */
3468                 info->pdev = pdev;
3469                 info->irq_level = pdev->irq;
3470                 info->phys_reg_addr = pci_resource_start(pdev,0);
3471
3472                 info->bus_type = MGSL_BUS_TYPE_PCI;
3473                 info->irq_flags = IRQF_SHARED;
3474
3475                 info->init_error = -1; /* assume error, set to 0 on successful init */
3476         }
3477
3478         return info;
3479 }
3480
3481 static void device_init(int adapter_num, struct pci_dev *pdev)
3482 {
3483         struct slgt_info *port_array[SLGT_MAX_PORTS];
3484         int i;
3485         int port_count = 1;
3486
3487         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3488                 port_count = 2;
3489         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3490                 port_count = 4;
3491
3492         /* allocate device instances for all ports */
3493         for (i=0; i < port_count; ++i) {
3494                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3495                 if (port_array[i] == NULL) {
3496                         for (--i; i >= 0; --i)
3497                                 kfree(port_array[i]);
3498                         return;
3499                 }
3500         }
3501
3502         /* give copy of port_array to all ports and add to device list  */
3503         for (i=0; i < port_count; ++i) {
3504                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3505                 add_device(port_array[i]);
3506                 port_array[i]->port_count = port_count;
3507                 spin_lock_init(&port_array[i]->lock);
3508         }
3509
3510         /* Allocate and claim adapter resources */
3511         if (!claim_resources(port_array[0])) {
3512
3513                 alloc_dma_bufs(port_array[0]);
3514
3515                 /* copy resource information from first port to others */
3516                 for (i = 1; i < port_count; ++i) {
3517                         port_array[i]->lock      = port_array[0]->lock;
3518                         port_array[i]->irq_level = port_array[0]->irq_level;
3519                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3520                         alloc_dma_bufs(port_array[i]);
3521                 }
3522
3523                 if (request_irq(port_array[0]->irq_level,
3524                                         slgt_interrupt,
3525                                         port_array[0]->irq_flags,
3526                                         port_array[0]->device_name,
3527                                         port_array[0]) < 0) {
3528                         DBGERR(("%s request_irq failed IRQ=%d\n",
3529                                 port_array[0]->device_name,
3530                                 port_array[0]->irq_level));
3531                 } else {
3532                         port_array[0]->irq_requested = true;
3533                         adapter_test(port_array[0]);
3534                         for (i=1 ; i < port_count ; i++) {
3535                                 port_array[i]->init_error = port_array[0]->init_error;
3536                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3537                         }
3538                 }
3539         }
3540
3541         for (i=0; i < port_count; ++i)
3542                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3543 }
3544
3545 static int __devinit init_one(struct pci_dev *dev,
3546                               const struct pci_device_id *ent)
3547 {
3548         if (pci_enable_device(dev)) {
3549                 printk("error enabling pci device %p\n", dev);
3550                 return -EIO;
3551         }
3552         pci_set_master(dev);
3553         device_init(slgt_device_count, dev);
3554         return 0;
3555 }
3556
3557 static void __devexit remove_one(struct pci_dev *dev)
3558 {
3559 }
3560
3561 static const struct tty_operations ops = {
3562         .open = open,
3563         .close = close,
3564         .write = write,
3565         .put_char = put_char,
3566         .flush_chars = flush_chars,
3567         .write_room = write_room,
3568         .chars_in_buffer = chars_in_buffer,
3569         .flush_buffer = flush_buffer,
3570         .ioctl = ioctl,
3571         .compat_ioctl = slgt_compat_ioctl,
3572         .throttle = throttle,
3573         .unthrottle = unthrottle,
3574         .send_xchar = send_xchar,
3575         .break_ctl = set_break,
3576         .wait_until_sent = wait_until_sent,
3577         .read_proc = read_proc,
3578         .set_termios = set_termios,
3579         .stop = tx_hold,
3580         .start = tx_release,
3581         .hangup = hangup,
3582         .tiocmget = tiocmget,
3583         .tiocmset = tiocmset,
3584 };
3585
3586 static void slgt_cleanup(void)
3587 {
3588         int rc;
3589         struct slgt_info *info;
3590         struct slgt_info *tmp;
3591
3592         printk("unload %s %s\n", driver_name, driver_version);
3593
3594         if (serial_driver) {
3595                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3596                         tty_unregister_device(serial_driver, info->line);
3597                 if ((rc = tty_unregister_driver(serial_driver)))
3598                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3599                 put_tty_driver(serial_driver);
3600         }
3601
3602         /* reset devices */
3603         info = slgt_device_list;
3604         while(info) {
3605                 reset_port(info);
3606                 info = info->next_device;
3607         }
3608
3609         /* release devices */
3610         info = slgt_device_list;
3611         while(info) {
3612 #if SYNCLINK_GENERIC_HDLC
3613                 hdlcdev_exit(info);
3614 #endif
3615                 free_dma_bufs(info);
3616                 free_tmp_rbuf(info);
3617                 if (info->port_num == 0)
3618                         release_resources(info);
3619                 tmp = info;
3620                 info = info->next_device;
3621                 kfree(tmp);
3622         }
3623
3624         if (pci_registered)
3625                 pci_unregister_driver(&pci_driver);
3626 }
3627
3628 /*
3629  *  Driver initialization entry point.
3630  */
3631 static int __init slgt_init(void)
3632 {
3633         int rc;
3634
3635         printk("%s %s\n", driver_name, driver_version);
3636
3637         serial_driver = alloc_tty_driver(MAX_DEVICES);
3638         if (!serial_driver) {
3639                 printk("%s can't allocate tty driver\n", driver_name);
3640                 return -ENOMEM;
3641         }
3642
3643         /* Initialize the tty_driver structure */
3644
3645         serial_driver->owner = THIS_MODULE;
3646         serial_driver->driver_name = tty_driver_name;
3647         serial_driver->name = tty_dev_prefix;
3648         serial_driver->major = ttymajor;
3649         serial_driver->minor_start = 64;
3650         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3651         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3652         serial_driver->init_termios = tty_std_termios;
3653         serial_driver->init_termios.c_cflag =
3654                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3655         serial_driver->init_termios.c_ispeed = 9600;
3656         serial_driver->init_termios.c_ospeed = 9600;
3657         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3658         tty_set_operations(serial_driver, &ops);
3659         if ((rc = tty_register_driver(serial_driver)) < 0) {
3660                 DBGERR(("%s can't register serial driver\n", driver_name));
3661                 put_tty_driver(serial_driver);
3662                 serial_driver = NULL;
3663                 goto error;
3664         }
3665
3666         printk("%s %s, tty major#%d\n",
3667                 driver_name, driver_version,
3668                 serial_driver->major);
3669
3670         slgt_device_count = 0;
3671         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3672                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3673                 goto error;
3674         }
3675         pci_registered = true;
3676
3677         if (!slgt_device_list)
3678                 printk("%s no devices found\n",driver_name);
3679
3680         return 0;
3681
3682 error:
3683         slgt_cleanup();
3684         return rc;
3685 }
3686
3687 static void __exit slgt_exit(void)
3688 {
3689         slgt_cleanup();
3690 }
3691
3692 module_init(slgt_init);
3693 module_exit(slgt_exit);
3694
3695 /*
3696  * register access routines
3697  */
3698
3699 #define CALC_REGADDR() \
3700         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3701         if (addr >= 0x80) \
3702                 reg_addr += (info->port_num) * 32;
3703
3704 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3705 {
3706         CALC_REGADDR();
3707         return readb((void __iomem *)reg_addr);
3708 }
3709
3710 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3711 {
3712         CALC_REGADDR();
3713         writeb(value, (void __iomem *)reg_addr);
3714 }
3715
3716 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3717 {
3718         CALC_REGADDR();
3719         return readw((void __iomem *)reg_addr);
3720 }
3721
3722 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3723 {
3724         CALC_REGADDR();
3725         writew(value, (void __iomem *)reg_addr);
3726 }
3727
3728 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3729 {
3730         CALC_REGADDR();
3731         return readl((void __iomem *)reg_addr);
3732 }
3733
3734 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3735 {
3736         CALC_REGADDR();
3737         writel(value, (void __iomem *)reg_addr);
3738 }
3739
3740 static void rdma_reset(struct slgt_info *info)
3741 {
3742         unsigned int i;
3743
3744         /* set reset bit */
3745         wr_reg32(info, RDCSR, BIT1);
3746
3747         /* wait for enable bit cleared */
3748         for(i=0 ; i < 1000 ; i++)
3749                 if (!(rd_reg32(info, RDCSR) & BIT0))
3750                         break;
3751 }
3752
3753 static void tdma_reset(struct slgt_info *info)
3754 {
3755         unsigned int i;
3756
3757         /* set reset bit */
3758         wr_reg32(info, TDCSR, BIT1);
3759
3760         /* wait for enable bit cleared */
3761         for(i=0 ; i < 1000 ; i++)
3762                 if (!(rd_reg32(info, TDCSR) & BIT0))
3763                         break;
3764 }
3765
3766 /*
3767  * enable internal loopback
3768  * TxCLK and RxCLK are generated from BRG
3769  * and TxD is looped back to RxD internally.
3770  */
3771 static void enable_loopback(struct slgt_info *info)
3772 {
3773         /* SCR (serial control) BIT2=looopback enable */
3774         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3775
3776         if (info->params.mode != MGSL_MODE_ASYNC) {
3777                 /* CCR (clock control)
3778                  * 07..05  tx clock source (010 = BRG)
3779                  * 04..02  rx clock source (010 = BRG)
3780                  * 01      auxclk enable   (0 = disable)
3781                  * 00      BRG enable      (1 = enable)
3782                  *
3783                  * 0100 1001
3784                  */
3785                 wr_reg8(info, CCR, 0x49);
3786
3787                 /* set speed if available, otherwise use default */
3788                 if (info->params.clock_speed)
3789                         set_rate(info, info->params.clock_speed);
3790                 else
3791                         set_rate(info, 3686400);
3792         }
3793 }
3794
3795 /*
3796  *  set baud rate generator to specified rate
3797  */
3798 static void set_rate(struct slgt_info *info, u32 rate)
3799 {
3800         unsigned int div;
3801         static unsigned int osc = 14745600;
3802
3803         /* div = osc/rate - 1
3804          *
3805          * Round div up if osc/rate is not integer to
3806          * force to next slowest rate.
3807          */
3808
3809         if (rate) {
3810                 div = osc/rate;
3811                 if (!(osc % rate) && div)
3812                         div--;
3813                 wr_reg16(info, BDR, (unsigned short)div);
3814         }
3815 }
3816
3817 static void rx_stop(struct slgt_info *info)
3818 {
3819         unsigned short val;
3820
3821         /* disable and reset receiver */
3822         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3823         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3824         wr_reg16(info, RCR, val);                  /* clear reset bit */
3825
3826         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3827
3828         /* clear pending rx interrupts */
3829         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3830
3831         rdma_reset(info);
3832
3833         info->rx_enabled = false;
3834         info->rx_restart = false;
3835 }
3836
3837 static void rx_start(struct slgt_info *info)
3838 {
3839         unsigned short val;
3840
3841         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3842
3843         /* clear pending rx overrun IRQ */
3844         wr_reg16(info, SSR, IRQ_RXOVER);
3845
3846         /* reset and disable receiver */
3847         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3848         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3849         wr_reg16(info, RCR, val);                  /* clear reset bit */
3850
3851         rdma_reset(info);
3852         reset_rbufs(info);
3853
3854         /* set 1st descriptor address */
3855         wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3856
3857         if (info->params.mode != MGSL_MODE_ASYNC) {
3858                 /* enable rx DMA and DMA interrupt */
3859                 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3860         } else {
3861                 /* enable saving of rx status, rx DMA and DMA interrupt */
3862                 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3863         }
3864
3865         slgt_irq_on(info, IRQ_RXOVER);
3866
3867         /* enable receiver */
3868         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3869
3870         info->rx_restart = false;
3871         info->rx_enabled = true;
3872 }
3873
3874 static void tx_start(struct slgt_info *info)
3875 {
3876         if (!info->tx_enabled) {
3877                 wr_reg16(info, TCR,
3878                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3879                 info->tx_enabled = true;
3880         }
3881
3882         if (info->tx_count) {
3883                 info->drop_rts_on_tx_done = false;
3884
3885                 if (info->params.mode != MGSL_MODE_ASYNC) {
3886                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3887                                 get_signals(info);
3888                                 if (!(info->signals & SerialSignal_RTS)) {
3889                                         info->signals |= SerialSignal_RTS;
3890                                         set_signals(info);
3891                                         info->drop_rts_on_tx_done = true;
3892                                 }
3893                         }
3894
3895                         slgt_irq_off(info, IRQ_TXDATA);
3896                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3897                         /* clear tx idle and underrun status bits */
3898                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3899                         if (info->params.mode == MGSL_MODE_HDLC)
3900                                 mod_timer(&info->tx_timer, jiffies +
3901                                                 msecs_to_jiffies(5000));
3902                 } else {
3903                         slgt_irq_off(info, IRQ_TXDATA);
3904                         slgt_irq_on(info, IRQ_TXIDLE);
3905                         /* clear tx idle status bit */
3906                         wr_reg16(info, SSR, IRQ_TXIDLE);
3907                 }
3908                 tdma_start(info);
3909                 info->tx_active = true;
3910         }
3911 }
3912
3913 /*
3914  * start transmit DMA if inactive and there are unsent buffers
3915  */
3916 static void tdma_start(struct slgt_info *info)
3917 {
3918         unsigned int i;
3919
3920         if (rd_reg32(info, TDCSR) & BIT0)
3921                 return;
3922
3923         /* transmit DMA inactive, check for unsent buffers */
3924         i = info->tbuf_start;
3925         while (!desc_count(info->tbufs[i])) {
3926                 if (++i == info->tbuf_count)
3927                         i = 0;
3928                 if (i == info->tbuf_current)
3929                         return;
3930         }
3931         info->tbuf_start = i;
3932
3933         /* there are unsent buffers, start transmit DMA */
3934
3935         /* reset needed if previous error condition */
3936         tdma_reset(info);
3937
3938         /* set 1st descriptor address */
3939         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3940         switch(info->params.mode) {
3941         case MGSL_MODE_RAW:
3942         case MGSL_MODE_MONOSYNC:
3943         case MGSL_MODE_BISYNC:
3944                 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3945                 break;
3946         default:
3947                 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3948         }
3949 }
3950
3951 static void tx_stop(struct slgt_info *info)
3952 {
3953         unsigned short val;
3954
3955         del_timer(&info->tx_timer);
3956
3957         tdma_reset(info);
3958
3959         /* reset and disable transmitter */
3960         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
3961         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3962
3963         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3964
3965         /* clear tx idle and underrun status bit */
3966         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3967
3968         reset_tbufs(info);
3969
3970         info->tx_enabled = false;
3971         info->tx_active = false;
3972 }
3973
3974 static void reset_port(struct slgt_info *info)
3975 {
3976         if (!info->reg_addr)
3977                 return;
3978
3979         tx_stop(info);
3980         rx_stop(info);
3981
3982         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3983         set_signals(info);
3984
3985         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3986 }
3987
3988 static void reset_adapter(struct slgt_info *info)
3989 {
3990         int i;
3991         for (i=0; i < info->port_count; ++i) {
3992                 if (info->port_array[i])
3993                         reset_port(info->port_array[i]);
3994         }
3995 }
3996
3997 static void async_mode(struct slgt_info *info)
3998 {
3999         unsigned short val;
4000
4001         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4002         tx_stop(info);
4003         rx_stop(info);
4004
4005         /* TCR (tx control)
4006          *
4007          * 15..13  mode, 010=async
4008          * 12..10  encoding, 000=NRZ
4009          * 09      parity enable
4010          * 08      1=odd parity, 0=even parity
4011          * 07      1=RTS driver control
4012          * 06      1=break enable
4013          * 05..04  character length
4014          *         00=5 bits
4015          *         01=6 bits
4016          *         10=7 bits
4017          *         11=8 bits
4018          * 03      0=1 stop bit, 1=2 stop bits
4019          * 02      reset
4020          * 01      enable
4021          * 00      auto-CTS enable
4022          */
4023         val = 0x4000;
4024
4025         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4026                 val |= BIT7;
4027
4028         if (info->params.parity != ASYNC_PARITY_NONE) {
4029                 val |= BIT9;
4030                 if (info->params.parity == ASYNC_PARITY_ODD)
4031                         val |= BIT8;
4032         }
4033
4034         switch (info->params.data_bits)
4035         {
4036         case 6: val |= BIT4; break;
4037         case 7: val |= BIT5; break;
4038         case 8: val |= BIT5 + BIT4; break;
4039         }
4040
4041         if (info->params.stop_bits != 1)
4042                 val |= BIT3;
4043
4044         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4045                 val |= BIT0;
4046
4047         wr_reg16(info, TCR, val);
4048
4049         /* RCR (rx control)
4050          *
4051          * 15..13  mode, 010=async
4052          * 12..10  encoding, 000=NRZ
4053          * 09      parity enable
4054          * 08      1=odd parity, 0=even parity
4055          * 07..06  reserved, must be 0
4056          * 05..04  character length
4057          *         00=5 bits
4058          *         01=6 bits
4059          *         10=7 bits
4060          *         11=8 bits
4061          * 03      reserved, must be zero
4062          * 02      reset
4063          * 01      enable
4064          * 00      auto-DCD enable
4065          */
4066         val = 0x4000;
4067
4068         if (info->params.parity != ASYNC_PARITY_NONE) {
4069                 val |= BIT9;
4070                 if (info->params.parity == ASYNC_PARITY_ODD)
4071                         val |= BIT8;
4072         }
4073
4074         switch (info->params.data_bits)
4075         {
4076         case 6: val |= BIT4; break;
4077         case 7: val |= BIT5; break;
4078         case 8: val |= BIT5 + BIT4; break;
4079         }
4080
4081         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4082                 val |= BIT0;
4083
4084         wr_reg16(info, RCR, val);
4085
4086         /* CCR (clock control)
4087          *
4088          * 07..05  011 = tx clock source is BRG/16
4089          * 04..02  010 = rx clock source is BRG
4090          * 01      0 = auxclk disabled
4091          * 00      1 = BRG enabled
4092          *
4093          * 0110 1001
4094          */
4095         wr_reg8(info, CCR, 0x69);
4096
4097         msc_set_vcr(info);
4098
4099         /* SCR (serial control)
4100          *
4101          * 15  1=tx req on FIFO half empty
4102          * 14  1=rx req on FIFO half full
4103          * 13  tx data  IRQ enable
4104          * 12  tx idle  IRQ enable
4105          * 11  rx break on IRQ enable
4106          * 10  rx data  IRQ enable
4107          * 09  rx break off IRQ enable
4108          * 08  overrun  IRQ enable
4109          * 07  DSR      IRQ enable
4110          * 06  CTS      IRQ enable
4111          * 05  DCD      IRQ enable
4112          * 04  RI       IRQ enable
4113          * 03  reserved, must be zero
4114          * 02  1=txd->rxd internal loopback enable
4115          * 01  reserved, must be zero
4116          * 00  1=master IRQ enable
4117          */
4118         val = BIT15 + BIT14 + BIT0;
4119         wr_reg16(info, SCR, val);
4120
4121         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4122
4123         set_rate(info, info->params.data_rate * 16);
4124
4125         if (info->params.loopback)
4126                 enable_loopback(info);
4127 }
4128
4129 static void sync_mode(struct slgt_info *info)
4130 {
4131         unsigned short val;
4132
4133         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4134         tx_stop(info);
4135         rx_stop(info);
4136
4137         /* TCR (tx control)
4138          *
4139          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4140          * 12..10  encoding
4141          * 09      CRC enable
4142          * 08      CRC32
4143          * 07      1=RTS driver control
4144          * 06      preamble enable
4145          * 05..04  preamble length
4146          * 03      share open/close flag
4147          * 02      reset
4148          * 01      enable
4149          * 00      auto-CTS enable
4150          */
4151         val = 0;
4152
4153         switch(info->params.mode) {
4154         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4155         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4156         case MGSL_MODE_RAW:      val |= BIT13; break;
4157         }
4158         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4159                 val |= BIT7;
4160
4161         switch(info->params.encoding)
4162         {
4163         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4164         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4165         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4166         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4167         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4168         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4169         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4170         }
4171
4172         switch (info->params.crc_type & HDLC_CRC_MASK)
4173         {
4174         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4175         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4176         }
4177
4178         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4179                 val |= BIT6;
4180
4181         switch (info->params.preamble_length)
4182         {
4183         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4184         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4185         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4186         }
4187
4188         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4189                 val |= BIT0;
4190
4191         wr_reg16(info, TCR, val);
4192
4193         /* TPR (transmit preamble) */
4194
4195         switch (info->params.preamble)
4196         {
4197         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4198         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4199         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4200         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4201         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4202         default:                          val = 0x7e; break;
4203         }
4204         wr_reg8(info, TPR, (unsigned char)val);
4205
4206         /* RCR (rx control)
4207          *
4208          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4209          * 12..10  encoding
4210          * 09      CRC enable
4211          * 08      CRC32
4212          * 07..03  reserved, must be 0
4213          * 02      reset
4214          * 01      enable
4215          * 00      auto-DCD enable
4216          */
4217         val = 0;
4218
4219         switch(info->params.mode) {
4220         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4221         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4222         case MGSL_MODE_RAW:      val |= BIT13; break;
4223         }
4224
4225         switch(info->params.encoding)
4226         {
4227         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4228         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4229         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4230         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4231         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4232         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4233         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4234         }
4235
4236         switch (info->params.crc_type & HDLC_CRC_MASK)
4237         {
4238         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4239         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4240         }
4241
4242         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4243                 val |= BIT0;
4244
4245         wr_reg16(info, RCR, val);
4246
4247         /* CCR (clock control)
4248          *
4249          * 07..05  tx clock source
4250          * 04..02  rx clock source
4251          * 01      auxclk enable
4252          * 00      BRG enable
4253          */
4254         val = 0;
4255
4256         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4257         {
4258                 // when RxC source is DPLL, BRG generates 16X DPLL
4259                 // reference clock, so take TxC from BRG/16 to get
4260                 // transmit clock at actual data rate
4261                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4262                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4263                 else
4264                         val |= BIT6;    /* 010, txclk = BRG */
4265         }
4266         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4267                 val |= BIT7;    /* 100, txclk = DPLL Input */
4268         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4269                 val |= BIT5;    /* 001, txclk = RXC Input */
4270
4271         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4272                 val |= BIT3;    /* 010, rxclk = BRG */
4273         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4274                 val |= BIT4;    /* 100, rxclk = DPLL */
4275         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4276                 val |= BIT2;    /* 001, rxclk = TXC Input */
4277
4278         if (info->params.clock_speed)
4279                 val |= BIT1 + BIT0;
4280
4281         wr_reg8(info, CCR, (unsigned char)val);
4282
4283         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4284         {
4285                 // program DPLL mode
4286                 switch(info->params.encoding)
4287                 {
4288                 case HDLC_ENCODING_BIPHASE_MARK:
4289                 case HDLC_ENCODING_BIPHASE_SPACE:
4290                         val = BIT7; break;
4291                 case HDLC_ENCODING_BIPHASE_LEVEL:
4292                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4293                         val = BIT7 + BIT6; break;
4294                 default: val = BIT6;    // NRZ encodings
4295                 }
4296                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4297
4298                 // DPLL requires a 16X reference clock from BRG
4299                 set_rate(info, info->params.clock_speed * 16);
4300         }
4301         else
4302                 set_rate(info, info->params.clock_speed);
4303
4304         tx_set_idle(info);
4305
4306         msc_set_vcr(info);
4307
4308         /* SCR (serial control)
4309          *
4310          * 15  1=tx req on FIFO half empty
4311          * 14  1=rx req on FIFO half full
4312          * 13  tx data  IRQ enable
4313          * 12  tx idle  IRQ enable
4314          * 11  underrun IRQ enable
4315          * 10  rx data  IRQ enable
4316          * 09  rx idle  IRQ enable
4317          * 08  overrun  IRQ enable
4318          * 07  DSR      IRQ enable
4319          * 06  CTS      IRQ enable
4320          * 05  DCD      IRQ enable
4321          * 04  RI       IRQ enable
4322          * 03  reserved, must be zero
4323          * 02  1=txd->rxd internal loopback enable
4324          * 01  reserved, must be zero
4325          * 00  1=master IRQ enable
4326          */
4327         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4328
4329         if (info->params.loopback)
4330                 enable_loopback(info);
4331 }
4332
4333 /*
4334  *  set transmit idle mode
4335  */
4336 static void tx_set_idle(struct slgt_info *info)
4337 {
4338         unsigned char val;
4339         unsigned short tcr;
4340
4341         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4342          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4343          */
4344         tcr = rd_reg16(info, TCR);
4345         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4346                 /* disable preamble, set idle size to 16 bits */
4347                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4348                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4349                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4350         } else if (!(tcr & BIT6)) {
4351                 /* preamble is disabled, set idle size to 8 bits */
4352                 tcr &= ~(BIT5 + BIT4);
4353         }
4354         wr_reg16(info, TCR, tcr);
4355
4356         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4357                 /* LSB of custom tx idle specified in tx idle register */
4358                 val = (unsigned char)(info->idle_mode & 0xff);
4359         } else {
4360                 /* standard 8 bit idle patterns */
4361                 switch(info->idle_mode)
4362                 {
4363                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4364                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4365                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4366                 case HDLC_TXIDLE_ZEROS:
4367                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4368                 default:                         val = 0xff;
4369                 }
4370         }
4371
4372         wr_reg8(info, TIR, val);
4373 }
4374
4375 /*
4376  * get state of V24 status (input) signals
4377  */
4378 static void get_signals(struct slgt_info *info)
4379 {
4380         unsigned short status = rd_reg16(info, SSR);
4381
4382         /* clear all serial signals except DTR and RTS */
4383         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4384
4385         if (status & BIT3)
4386                 info->signals |= SerialSignal_DSR;
4387         if (status & BIT2)
4388                 info->signals |= SerialSignal_CTS;
4389         if (status & BIT1)
4390                 info->signals |= SerialSignal_DCD;
4391         if (status & BIT0)
4392                 info->signals |= SerialSignal_RI;
4393 }
4394
4395 /*
4396  * set V.24 Control Register based on current configuration
4397  */
4398 static void msc_set_vcr(struct slgt_info *info)
4399 {
4400         unsigned char val = 0;
4401
4402         /* VCR (V.24 control)
4403          *
4404          * 07..04  serial IF select
4405          * 03      DTR
4406          * 02      RTS
4407          * 01      LL
4408          * 00      RL
4409          */
4410
4411         switch(info->if_mode & MGSL_INTERFACE_MASK)
4412         {
4413         case MGSL_INTERFACE_RS232:
4414                 val |= BIT5; /* 0010 */
4415                 break;
4416         case MGSL_INTERFACE_V35:
4417                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4418                 break;
4419         case MGSL_INTERFACE_RS422:
4420                 val |= BIT6; /* 0100 */
4421                 break;
4422         }
4423
4424         if (info->signals & SerialSignal_DTR)
4425                 val |= BIT3;
4426         if (info->signals & SerialSignal_RTS)
4427                 val |= BIT2;
4428         if (info->if_mode & MGSL_INTERFACE_LL)
4429                 val |= BIT1;
4430         if (info->if_mode & MGSL_INTERFACE_RL)
4431                 val |= BIT0;
4432         wr_reg8(info, VCR, val);
4433 }
4434
4435 /*
4436  * set state of V24 control (output) signals
4437  */
4438 static void set_signals(struct slgt_info *info)
4439 {
4440         unsigned char val = rd_reg8(info, VCR);
4441         if (info->signals & SerialSignal_DTR)
4442                 val |= BIT3;
4443         else
4444                 val &= ~BIT3;
4445         if (info->signals & SerialSignal_RTS)
4446                 val |= BIT2;
4447         else
4448                 val &= ~BIT2;
4449         wr_reg8(info, VCR, val);
4450 }
4451
4452 /*
4453  * free range of receive DMA buffers (i to last)
4454  */
4455 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4456 {
4457         int done = 0;
4458
4459         while(!done) {
4460                 /* reset current buffer for reuse */
4461                 info->rbufs[i].status = 0;
4462                 switch(info->params.mode) {
4463                 case MGSL_MODE_RAW:
4464                 case MGSL_MODE_MONOSYNC:
4465                 case MGSL_MODE_BISYNC:
4466                         set_desc_count(info->rbufs[i], info->raw_rx_size);
4467                         break;
4468                 default:
4469                         set_desc_count(info->rbufs[i], DMABUFSIZE);
4470                 }
4471
4472                 if (i == last)
4473                         done = 1;
4474                 if (++i == info->rbuf_count)
4475                         i = 0;
4476         }
4477         info->rbuf_current = i;
4478 }
4479
4480 /*
4481  * mark all receive DMA buffers as free
4482  */
4483 static void reset_rbufs(struct slgt_info *info)
4484 {
4485         free_rbufs(info, 0, info->rbuf_count - 1);
4486 }
4487
4488 /*
4489  * pass receive HDLC frame to upper layer
4490  *
4491  * return true if frame available, otherwise false
4492  */
4493 static bool rx_get_frame(struct slgt_info *info)
4494 {
4495         unsigned int start, end;
4496         unsigned short status;
4497         unsigned int framesize = 0;
4498         unsigned long flags;
4499         struct tty_struct *tty = info->port.tty;
4500         unsigned char addr_field = 0xff;
4501         unsigned int crc_size = 0;
4502
4503         switch (info->params.crc_type & HDLC_CRC_MASK) {
4504         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4505         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4506         }
4507
4508 check_again:
4509
4510         framesize = 0;
4511         addr_field = 0xff;
4512         start = end = info->rbuf_current;
4513
4514         for (;;) {
4515                 if (!desc_complete(info->rbufs[end]))
4516                         goto cleanup;
4517
4518                 if (framesize == 0 && info->params.addr_filter != 0xff)
4519                         addr_field = info->rbufs[end].buf[0];
4520
4521                 framesize += desc_count(info->rbufs[end]);
4522
4523                 if (desc_eof(info->rbufs[end]))
4524                         break;
4525
4526                 if (++end == info->rbuf_count)
4527                         end = 0;
4528
4529                 if (end == info->rbuf_current) {
4530                         if (info->rx_enabled){
4531                                 spin_lock_irqsave(&info->lock,flags);
4532                                 rx_start(info);
4533                                 spin_unlock_irqrestore(&info->lock,flags);
4534                         }
4535                         goto cleanup;
4536                 }
4537         }
4538
4539         /* status
4540          *
4541          * 15      buffer complete
4542          * 14..06  reserved
4543          * 05..04  residue
4544          * 02      eof (end of frame)
4545          * 01      CRC error
4546          * 00      abort
4547          */
4548         status = desc_status(info->rbufs[end]);
4549
4550         /* ignore CRC bit if not using CRC (bit is undefined) */
4551         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4552                 status &= ~BIT1;
4553
4554         if (framesize == 0 ||
4555                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4556                 free_rbufs(info, start, end);
4557                 goto check_again;
4558         }
4559
4560         if (framesize < (2 + crc_size) || status & BIT0) {
4561                 info->icount.rxshort++;
4562                 framesize = 0;
4563         } else if (status & BIT1) {
4564                 info->icount.rxcrc++;
4565                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4566                         framesize = 0;
4567         }
4568
4569 #if SYNCLINK_GENERIC_HDLC
4570         if (framesize == 0) {
4571                 struct net_device_stats *stats = hdlc_stats(info->netdev);
4572                 stats->rx_errors++;
4573                 stats->rx_frame_errors++;
4574         }
4575 #endif
4576
4577         DBGBH(("%s rx frame status=%04X size=%d\n",
4578                 info->device_name, status, framesize));
4579         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4580
4581         if (framesize) {
4582                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4583                         framesize -= crc_size;
4584                         crc_size = 0;
4585                 }
4586
4587                 if (framesize > info->max_frame_size + crc_size)
4588                         info->icount.rxlong++;
4589                 else {
4590                         /* copy dma buffer(s) to contiguous temp buffer */
4591                         int copy_count = framesize;
4592                         int i = start;
4593                         unsigned char *p = info->tmp_rbuf;
4594                         info->tmp_rbuf_count = framesize;
4595
4596                         info->icount.rxok++;
4597
4598                         while(copy_count) {
4599                                 int partial_count = min(copy_count, DMABUFSIZE);
4600                                 memcpy(p, info->rbufs[i].buf, partial_count);
4601                                 p += partial_count;
4602                                 copy_count -= partial_count;
4603                                 if (++i == info->rbuf_count)
4604                                         i = 0;
4605                         }
4606
4607                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4608                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4609                                 framesize++;
4610                         }
4611
4612 #if SYNCLINK_GENERIC_HDLC
4613                         if (info->netcount)
4614                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4615                         else
4616 #endif
4617                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4618                 }
4619         }
4620         free_rbufs(info, start, end);
4621         return true;
4622
4623 cleanup:
4624         return false;
4625 }
4626
4627 /*
4628  * pass receive buffer (RAW synchronous mode) to tty layer
4629  * return true if buffer available, otherwise false
4630  */
4631 static bool rx_get_buf(struct slgt_info *info)
4632 {
4633         unsigned int i = info->rbuf_current;
4634         unsigned int count;
4635
4636         if (!desc_complete(info->rbufs[i]))
4637                 return false;
4638         count = desc_count(info->rbufs[i]);
4639         switch(info->params.mode) {
4640         case MGSL_MODE_MONOSYNC:
4641         case MGSL_MODE_BISYNC:
4642                 /* ignore residue in byte synchronous modes */
4643                 if (desc_residue(info->rbufs[i]))
4644                         count--;
4645                 break;
4646         }
4647         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4648         DBGINFO(("rx_get_buf size=%d\n", count));
4649         if (count)
4650                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4651                                   info->flag_buf, count);
4652         free_rbufs(info, i, i);
4653         return true;
4654 }
4655
4656 static void reset_tbufs(struct slgt_info *info)
4657 {
4658         unsigned int i;
4659         info->tbuf_current = 0;
4660         for (i=0 ; i < info->tbuf_count ; i++) {
4661                 info->tbufs[i].status = 0;
4662                 info->tbufs[i].count  = 0;
4663         }
4664 }
4665
4666 /*
4667  * return number of free transmit DMA buffers
4668  */
4669 static unsigned int free_tbuf_count(struct slgt_info *info)
4670 {
4671         unsigned int count = 0;
4672         unsigned int i = info->tbuf_current;
4673
4674         do
4675         {
4676                 if (desc_count(info->tbufs[i]))
4677                         break; /* buffer in use */
4678                 ++count;
4679                 if (++i == info->tbuf_count)
4680                         i=0;
4681         } while (i != info->tbuf_current);
4682
4683         /* if tx DMA active, last zero count buffer is in use */
4684         if (count && (rd_reg32(info, TDCSR) & BIT0))
4685                 --count;
4686
4687         return count;
4688 }
4689
4690 /*
4691  * load transmit DMA buffer(s) with data
4692  */
4693 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4694 {
4695         unsigned short count;
4696         unsigned int i;
4697         struct slgt_desc *d;
4698
4699         if (size == 0)
4700                 return;
4701
4702         DBGDATA(info, buf, size, "tx");
4703
4704         info->tbuf_start = i = info->tbuf_current;
4705
4706         while (size) {
4707                 d = &info->tbufs[i];
4708                 if (++i == info->tbuf_count)
4709                         i = 0;
4710
4711                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4712                 memcpy(d->buf, buf, count);
4713
4714                 size -= count;
4715                 buf  += count;
4716
4717                 /*
4718                  * set EOF bit for last buffer of HDLC frame or
4719                  * for every buffer in raw mode
4720                  */
4721                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4722                     info->params.mode == MGSL_MODE_RAW)
4723                         set_desc_eof(*d, 1);
4724                 else
4725                         set_desc_eof(*d, 0);
4726
4727                 set_desc_count(*d, count);
4728         }
4729
4730         info->tbuf_current = i;
4731 }
4732
4733 static int register_test(struct slgt_info *info)
4734 {
4735         static unsigned short patterns[] =
4736                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4737         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4738         unsigned int i;
4739         int rc = 0;
4740
4741         for (i=0 ; i < count ; i++) {
4742                 wr_reg16(info, TIR, patterns[i]);
4743                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4744                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4745                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4746                         rc = -ENODEV;
4747                         break;
4748                 }
4749         }
4750         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4751         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4752         return rc;
4753 }
4754
4755 static int irq_test(struct slgt_info *info)
4756 {
4757         unsigned long timeout;
4758         unsigned long flags;
4759         struct tty_struct *oldtty = info->port.tty;
4760         u32 speed = info->params.data_rate;
4761
4762         info->params.data_rate = 921600;
4763         info->port.tty = NULL;
4764
4765         spin_lock_irqsave(&info->lock, flags);
4766         async_mode(info);
4767         slgt_irq_on(info, IRQ_TXIDLE);
4768
4769         /* enable transmitter */
4770         wr_reg16(info, TCR,
4771                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4772
4773         /* write one byte and wait for tx idle */
4774         wr_reg16(info, TDR, 0);
4775
4776         /* assume failure */
4777         info->init_error = DiagStatus_IrqFailure;
4778         info->irq_occurred = false;
4779
4780         spin_unlock_irqrestore(&info->lock, flags);
4781
4782         timeout=100;
4783         while(timeout-- && !info->irq_occurred)
4784                 msleep_interruptible(10);
4785
4786         spin_lock_irqsave(&info->lock,flags);
4787         reset_port(info);
4788         spin_unlock_irqrestore(&info->lock,flags);
4789
4790         info->params.data_rate = speed;
4791         info->port.tty = oldtty;
4792
4793         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4794         return info->irq_occurred ? 0 : -ENODEV;
4795 }
4796
4797 static int loopback_test_rx(struct slgt_info *info)
4798 {
4799         unsigned char *src, *dest;
4800         int count;
4801
4802         if (desc_complete(info->rbufs[0])) {
4803                 count = desc_count(info->rbufs[0]);
4804                 src   = info->rbufs[0].buf;
4805                 dest  = info->tmp_rbuf;
4806
4807                 for( ; count ; count-=2, src+=2) {
4808                         /* src=data byte (src+1)=status byte */
4809                         if (!(*(src+1) & (BIT9 + BIT8))) {
4810                                 *dest = *src;
4811                                 dest++;
4812                                 info->tmp_rbuf_count++;
4813                         }
4814                 }
4815                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4816                 return 1;
4817         }
4818         return 0;
4819 }
4820
4821 static int loopback_test(struct slgt_info *info)
4822 {
4823 #define TESTFRAMESIZE 20
4824
4825         unsigned long timeout;
4826         u16 count = TESTFRAMESIZE;
4827         unsigned char buf[TESTFRAMESIZE];
4828         int rc = -ENODEV;
4829         unsigned long flags;
4830
4831         struct tty_struct *oldtty = info->port.tty;
4832         MGSL_PARAMS params;
4833
4834         memcpy(&params, &info->params, sizeof(params));
4835
4836         info->params.mode = MGSL_MODE_ASYNC;
4837         info->params.data_rate = 921600;
4838         info->params.loopback = 1;
4839         info->port.tty = NULL;
4840
4841         /* build and send transmit frame */
4842         for (count = 0; count < TESTFRAMESIZE; ++count)
4843                 buf[count] = (unsigned char)count;
4844
4845         info->tmp_rbuf_count = 0;
4846         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4847
4848         /* program hardware for HDLC and enabled receiver */
4849         spin_lock_irqsave(&info->lock,flags);
4850         async_mode(info);
4851         rx_start(info);
4852         info->tx_count = count;
4853         tx_load(info, buf, count);
4854         tx_start(info);
4855         spin_unlock_irqrestore(&info->lock, flags);
4856
4857         /* wait for receive complete */
4858         for (timeout = 100; timeout; --timeout) {
4859                 msleep_interruptible(10);
4860                 if (loopback_test_rx(info)) {
4861                         rc = 0;
4862                         break;
4863                 }
4864         }
4865
4866         /* verify received frame length and contents */
4867         if (!rc && (info->tmp_rbuf_count != count ||
4868                   memcmp(buf, info->tmp_rbuf, count))) {
4869                 rc = -ENODEV;
4870         }
4871
4872         spin_lock_irqsave(&info->lock,flags);
4873         reset_adapter(info);
4874         spin_unlock_irqrestore(&info->lock,flags);
4875
4876         memcpy(&info->params, &params, sizeof(info->params));
4877         info->port.tty = oldtty;
4878
4879         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4880         return rc;
4881 }
4882
4883 static int adapter_test(struct slgt_info *info)
4884 {
4885         DBGINFO(("testing %s\n", info->device_name));
4886         if (register_test(info) < 0) {
4887                 printk("register test failure %s addr=%08X\n",
4888                         info->device_name, info->phys_reg_addr);
4889         } else if (irq_test(info) < 0) {
4890                 printk("IRQ test failure %s IRQ=%d\n",
4891                         info->device_name, info->irq_level);
4892         } else if (loopback_test(info) < 0) {
4893                 printk("loopback test failure %s\n", info->device_name);
4894         }
4895         return info->init_error;
4896 }
4897
4898 /*
4899  * transmit timeout handler
4900  */
4901 static void tx_timeout(unsigned long context)
4902 {
4903         struct slgt_info *info = (struct slgt_info*)context;
4904         unsigned long flags;
4905
4906         DBGINFO(("%s tx_timeout\n", info->device_name));
4907         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4908                 info->icount.txtimeout++;
4909         }
4910         spin_lock_irqsave(&info->lock,flags);
4911         info->tx_active = false;
4912         info->tx_count = 0;
4913         spin_unlock_irqrestore(&info->lock,flags);
4914
4915 #if SYNCLINK_GENERIC_HDLC
4916         if (info->netcount)
4917                 hdlcdev_tx_done(info);
4918         else
4919 #endif
4920                 bh_transmit(info);
4921 }
4922
4923 /*
4924  * receive buffer polling timer
4925  */
4926 static void rx_timeout(unsigned long context)
4927 {
4928         struct slgt_info *info = (struct slgt_info*)context;
4929         unsigned long flags;
4930
4931         DBGINFO(("%s rx_timeout\n", info->device_name));
4932         spin_lock_irqsave(&info->lock, flags);
4933         info->pending_bh |= BH_RECEIVE;
4934         spin_unlock_irqrestore(&info->lock, flags);
4935         bh_handler(&info->task);
4936 }
4937