1 #ifndef __ASM_AVR32_IO_H
2 #define __ASM_AVR32_IO_H
4 #include <linux/string.h>
8 #include <asm/addrspace.h>
9 #include <asm/byteorder.h>
11 /* virt_to_phys will only work when address is in P1 or P2 */
12 static __inline__ unsigned long virt_to_phys(volatile void *address)
14 return PHYSADDR(address);
17 static __inline__ void * phys_to_virt(unsigned long address)
19 return (void *)P1SEGADDR(address);
22 #define cached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
23 #define uncached_to_phys(addr) ((unsigned long)PHYSADDR(addr))
24 #define phys_to_cached(addr) ((void *)P1SEGADDR(addr))
25 #define phys_to_uncached(addr) ((void *)P2SEGADDR(addr))
28 * Generic IO read/write. These perform native-endian accesses. Note
29 * that some architectures will want to re-define __raw_{read,write}w.
31 extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
32 extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
33 extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
35 extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
36 extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
37 extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
39 static inline void writeb(unsigned char b, volatile void __iomem *addr)
41 *(volatile unsigned char __force *)addr = b;
43 static inline void writew(unsigned short b, volatile void __iomem *addr)
45 *(volatile unsigned short __force *)addr = b;
47 static inline void writel(unsigned int b, volatile void __iomem *addr)
49 *(volatile unsigned int __force *)addr = b;
51 #define __raw_writeb writeb
52 #define __raw_writew writew
53 #define __raw_writel writel
55 static inline unsigned char readb(const volatile void __iomem *addr)
57 return *(const volatile unsigned char __force *)addr;
59 static inline unsigned short readw(const volatile void __iomem *addr)
61 return *(const volatile unsigned short __force *)addr;
63 static inline unsigned int readl(const volatile void __iomem *addr)
65 return *(const volatile unsigned int __force *)addr;
67 #define __raw_readb readb
68 #define __raw_readw readw
69 #define __raw_readl readl
71 #define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l)
72 #define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l)
73 #define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l)
75 #define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l)
76 #define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l)
77 #define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l)
81 * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
85 #define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
87 #define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
88 #define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
90 #define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
91 #define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
93 #define iowrite8(v,p) __raw_writeb(v, p)
95 #define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
96 #define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p)
98 #define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
99 #define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p)
101 #define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
102 #define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
103 #define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
105 #define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
106 #define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
107 #define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
113 * These two are only here because ALSA _thinks_ it needs them...
115 static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
127 static inline void memcpy_toio(volatile void __iomem *to, const void * from,
130 const char *p = from;
139 static inline void memset_io(volatile void __iomem *addr, unsigned char val,
142 memset((void __force *)addr, val, count);
146 * Bad read/write accesses...
148 extern void __readwrite_bug(const char *fn);
150 #define IO_SPACE_LIMIT 0xffffffff
152 /* Convert I/O port address to virtual address */
153 #define __io(p) ((void __iomem *)phys_to_uncached(p))
156 * IO port access primitives
157 * -------------------------
159 * The AVR32 doesn't have special IO access instructions; all IO is memory
160 * mapped. Note that these are defined to perform little endian accesses
161 * only. Their primary purpose is to access PCI and ISA peripherals.
163 * Note that for a big endian machine, this implies that the following
164 * big endian mode connectivity is in place.
166 * The machine specific io.h include defines __io to translate an "IO"
167 * address to a memory address.
169 * Note that we prevent GCC re-ordering or caching values in expressions
170 * by introducing sequence points into the in*() definitions. Note that
171 * __raw_* do not guarantee this behaviour.
173 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
175 #define outb(v, p) __raw_writeb(v, __io(p))
176 #define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
177 #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
179 #define inb(p) __raw_readb(__io(p))
180 #define inw(p) le16_to_cpu(__raw_readw(__io(p)))
181 #define inl(p) le32_to_cpu(__raw_readl(__io(p)))
183 static inline void __outsb(unsigned long port, void *addr, unsigned int count)
186 outb(*(u8 *)addr, port);
191 static inline void __insb(unsigned long port, void *addr, unsigned int count)
194 *(u8 *)addr = inb(port);
199 static inline void __outsw(unsigned long port, void *addr, unsigned int count)
202 outw(*(u16 *)addr, port);
207 static inline void __insw(unsigned long port, void *addr, unsigned int count)
210 *(u16 *)addr = inw(port);
215 static inline void __outsl(unsigned long port, void *addr, unsigned int count)
218 outl(*(u32 *)addr, port);
223 static inline void __insl(unsigned long port, void *addr, unsigned int count)
226 *(u32 *)addr = inl(port);
231 #define outsb(port, addr, count) __outsb(port, addr, count)
232 #define insb(port, addr, count) __insb(port, addr, count)
233 #define outsw(port, addr, count) __outsw(port, addr, count)
234 #define insw(port, addr, count) __insw(port, addr, count)
235 #define outsl(port, addr, count) __outsl(port, addr, count)
236 #define insl(port, addr, count) __insl(port, addr, count)
238 extern void __iomem *__ioremap(unsigned long offset, size_t size,
239 unsigned long flags);
240 extern void __iounmap(void __iomem *addr);
243 * ioremap - map bus memory into CPU space
244 * @offset bus address of the memory
245 * @size size of the resource to map
247 * ioremap performs a platform specific sequence of operations to make
248 * bus memory CPU accessible via the readb/.../writel functions and
249 * the other mmio helpers. The returned address is not guaranteed to
250 * be usable directly as a virtual address.
252 #define ioremap(offset, size) \
253 __ioremap((offset), (size), 0)
255 #define ioremap_nocache(offset, size) \
256 __ioremap((offset), (size), 0)
258 #define iounmap(addr) \
261 #define cached(addr) P1SEGADDR(addr)
262 #define uncached(addr) P2SEGADDR(addr)
264 #define virt_to_bus virt_to_phys
265 #define bus_to_virt phys_to_virt
266 #define page_to_bus page_to_phys
267 #define bus_to_page phys_to_page
270 * Create a virtual mapping cookie for an IO port range. There exists
271 * no such thing as port-based I/O on AVR32, so a regular ioremap()
272 * should do what we need.
274 #define ioport_map(port, nr) ioremap(port, nr)
275 #define ioport_unmap(port) iounmap(port)
277 #define dma_cache_wback_inv(_start, _size) \
278 flush_dcache_region(_start, _size)
279 #define dma_cache_inv(_start, _size) \
280 invalidate_dcache_region(_start, _size)
281 #define dma_cache_wback(_start, _size) \
282 clean_dcache_region(_start, _size)
285 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
288 #define xlate_dev_mem_ptr(p) __va(p)
291 * Convert a virtual cached pointer to an uncached pointer
293 #define xlate_dev_kmem_ptr(p) p
295 #endif /* __KERNEL__ */
297 #endif /* __ASM_AVR32_IO_H */