2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/gpio.h>
24 #include <mach/hardware.h>
25 #include <mach/irqs.h>
26 #include <mach/common.h>
27 #include <mach/imx-uart.h>
31 static struct resource uart0[] = {
33 .start = UART1_BASE_ADDR,
34 .end = UART1_BASE_ADDR + 0x0B5,
35 .flags = IORESOURCE_MEM,
37 .start = MXC_INT_UART1,
39 .flags = IORESOURCE_IRQ,
43 struct platform_device mxc_uart_device0 = {
47 .num_resources = ARRAY_SIZE(uart0),
50 static struct resource uart1[] = {
52 .start = UART2_BASE_ADDR,
53 .end = UART2_BASE_ADDR + 0x0B5,
54 .flags = IORESOURCE_MEM,
56 .start = MXC_INT_UART2,
58 .flags = IORESOURCE_IRQ,
62 struct platform_device mxc_uart_device1 = {
66 .num_resources = ARRAY_SIZE(uart1),
69 static struct resource uart2[] = {
71 .start = UART3_BASE_ADDR,
72 .end = UART3_BASE_ADDR + 0x0B5,
73 .flags = IORESOURCE_MEM,
75 .start = MXC_INT_UART3,
77 .flags = IORESOURCE_IRQ,
81 struct platform_device mxc_uart_device2 = {
85 .num_resources = ARRAY_SIZE(uart2),
88 #ifdef CONFIG_ARCH_MX31
89 static struct resource uart3[] = {
91 .start = UART4_BASE_ADDR,
92 .end = UART4_BASE_ADDR + 0x0B5,
93 .flags = IORESOURCE_MEM,
95 .start = MXC_INT_UART4,
97 .flags = IORESOURCE_IRQ,
101 struct platform_device mxc_uart_device3 = {
105 .num_resources = ARRAY_SIZE(uart3),
108 static struct resource uart4[] = {
110 .start = UART5_BASE_ADDR,
111 .end = UART5_BASE_ADDR + 0x0B5,
112 .flags = IORESOURCE_MEM,
114 .start = MXC_INT_UART5,
115 .end = MXC_INT_UART5,
116 .flags = IORESOURCE_IRQ,
120 struct platform_device mxc_uart_device4 = {
124 .num_resources = ARRAY_SIZE(uart4),
126 #endif /* CONFIG_ARCH_MX31 */
128 /* GPIO port description */
129 static struct mxc_gpio_port imx_gpio_ports[] = {
131 .chip.label = "gpio-0",
132 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
133 .irq = MXC_INT_GPIO1,
134 .virtual_irq_start = MXC_GPIO_IRQ_START,
137 .chip.label = "gpio-1",
138 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
139 .irq = MXC_INT_GPIO2,
140 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
143 .chip.label = "gpio-2",
144 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
145 .irq = MXC_INT_GPIO3,
146 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
150 int __init mxc_register_gpios(void)
152 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
155 static struct resource mxc_w1_master_resources[] = {
157 .start = OWIRE_BASE_ADDR,
158 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
159 .flags = IORESOURCE_MEM,
163 struct platform_device mxc_w1_master_device = {
166 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
167 .resource = mxc_w1_master_resources,
170 static struct resource mxc_nand_resources[] = {
172 .start = 0, /* runtime dependent */
174 .flags = IORESOURCE_MEM
176 .start = MXC_INT_NANDFC,
177 .end = MXC_INT_NANDFC,
178 .flags = IORESOURCE_IRQ
182 struct platform_device mxc_nand_device = {
185 .num_resources = ARRAY_SIZE(mxc_nand_resources),
186 .resource = mxc_nand_resources,
189 static struct resource mxc_i2c0_resources[] = {
191 .start = I2C_BASE_ADDR,
192 .end = I2C_BASE_ADDR + SZ_4K - 1,
193 .flags = IORESOURCE_MEM,
196 .start = MXC_INT_I2C,
198 .flags = IORESOURCE_IRQ,
202 struct platform_device mxc_i2c_device0 = {
205 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
206 .resource = mxc_i2c0_resources,
209 static struct resource mxc_i2c1_resources[] = {
211 .start = I2C2_BASE_ADDR,
212 .end = I2C2_BASE_ADDR + SZ_4K - 1,
213 .flags = IORESOURCE_MEM,
216 .start = MXC_INT_I2C2,
218 .flags = IORESOURCE_IRQ,
222 struct platform_device mxc_i2c_device1 = {
225 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
226 .resource = mxc_i2c1_resources,
229 static struct resource mxc_i2c2_resources[] = {
231 .start = I2C3_BASE_ADDR,
232 .end = I2C3_BASE_ADDR + SZ_4K - 1,
233 .flags = IORESOURCE_MEM,
236 .start = MXC_INT_I2C3,
238 .flags = IORESOURCE_IRQ,
242 struct platform_device mxc_i2c_device2 = {
245 .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
246 .resource = mxc_i2c2_resources,
249 #ifdef CONFIG_ARCH_MX31
250 static struct resource mxcsdhc0_resources[] = {
252 .start = MMC_SDHC1_BASE_ADDR,
253 .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
254 .flags = IORESOURCE_MEM,
256 .start = MXC_INT_MMC_SDHC1,
257 .end = MXC_INT_MMC_SDHC1,
258 .flags = IORESOURCE_IRQ,
262 static struct resource mxcsdhc1_resources[] = {
264 .start = MMC_SDHC2_BASE_ADDR,
265 .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
266 .flags = IORESOURCE_MEM,
268 .start = MXC_INT_MMC_SDHC2,
269 .end = MXC_INT_MMC_SDHC2,
270 .flags = IORESOURCE_IRQ,
274 struct platform_device mxcsdhc_device0 = {
277 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
278 .resource = mxcsdhc0_resources,
281 struct platform_device mxcsdhc_device1 = {
284 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
285 .resource = mxcsdhc1_resources,
288 static struct resource rnga_resources[] = {
290 .start = RNGA_BASE_ADDR,
291 .end = RNGA_BASE_ADDR + 0x28,
292 .flags = IORESOURCE_MEM,
296 struct platform_device mxc_rnga_device = {
300 .resource = rnga_resources,
302 #endif /* CONFIG_ARCH_MX31 */
304 /* i.MX31 Image Processing Unit */
306 /* The resource order is important! */
307 static struct resource mx3_ipu_rsrc[] = {
309 .start = IPU_CTRL_BASE_ADDR,
310 .end = IPU_CTRL_BASE_ADDR + 0x5F,
311 .flags = IORESOURCE_MEM,
313 .start = IPU_CTRL_BASE_ADDR + 0x88,
314 .end = IPU_CTRL_BASE_ADDR + 0xB3,
315 .flags = IORESOURCE_MEM,
317 .start = MXC_INT_IPU_SYN,
318 .end = MXC_INT_IPU_SYN,
319 .flags = IORESOURCE_IRQ,
321 .start = MXC_INT_IPU_ERR,
322 .end = MXC_INT_IPU_ERR,
323 .flags = IORESOURCE_IRQ,
327 struct platform_device mx3_ipu = {
330 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
331 .resource = mx3_ipu_rsrc,
334 static struct resource fb_resources[] = {
336 .start = IPU_CTRL_BASE_ADDR + 0xB4,
337 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
338 .flags = IORESOURCE_MEM,
342 struct platform_device mx3_fb = {
343 .name = "mx3_sdc_fb",
345 .num_resources = ARRAY_SIZE(fb_resources),
346 .resource = fb_resources,
348 .coherent_dma_mask = 0xffffffff,
352 #ifdef CONFIG_ARCH_MX35
353 static struct resource mxc_fec_resources[] = {
355 .start = MXC_FEC_BASE_ADDR,
356 .end = MXC_FEC_BASE_ADDR + 0xfff,
357 .flags = IORESOURCE_MEM
359 .start = MXC_INT_FEC,
361 .flags = IORESOURCE_IRQ
365 struct platform_device mxc_fec_device = {
368 .num_resources = ARRAY_SIZE(mxc_fec_resources),
369 .resource = mxc_fec_resources,
373 static int mx3_devices_init(void)
376 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
377 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
378 mxc_register_device(&mxc_rnga_device, NULL);
381 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
382 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
388 subsys_initcall(mx3_devices_init);