Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
[linux-2.6] / arch / ppc / syslib / ibm44x_common.c
1 /*
2  * PPC44x system library
3  *
4  * Matt Porter <mporter@kernel.crashing.org>
5  * Copyright 2002-2005 MontaVista Software Inc.
6  *
7  * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8  * Copyright (c) 2003, 2004 Zultys Technologies
9  *
10  * This program is free software; you can redistribute  it and/or modify it
11  * under  the terms of  the GNU General  Public License as published by the
12  * Free Software Foundation;  either version 2 of the  License, or (at your
13  * option) any later version.
14  *
15  */
16 #include <linux/config.h>
17 #include <linux/time.h>
18 #include <linux/types.h>
19 #include <linux/serial.h>
20 #include <linux/module.h>
21 #include <linux/initrd.h>
22
23 #include <asm/ibm44x.h>
24 #include <asm/mmu.h>
25 #include <asm/machdep.h>
26 #include <asm/time.h>
27 #include <asm/ppc4xx_pic.h>
28 #include <asm/param.h>
29 #include <asm/bootinfo.h>
30 #include <asm/ppcboot.h>
31
32 #include <syslib/gen550.h>
33
34 /* Global Variables */
35 bd_t __res;
36
37 phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
38 {
39         phys_addr_t page_4gb = 0;
40
41         /*
42          * Trap the least significant 32-bit portions of an
43          * address in the 440's 36-bit address space.  Fix
44          * them up with the appropriate ERPN
45          */
46         if ((addr >= PPC44x_IO_LO) && (addr <= PPC44x_IO_HI))
47                 page_4gb = PPC44x_IO_PAGE;
48         else if ((addr >= PPC44x_PCI0CFG_LO) && (addr <= PPC44x_PCI0CFG_HI))
49                 page_4gb = PPC44x_PCICFG_PAGE;
50 #ifdef CONFIG_440SP
51         else if ((addr >= PPC44x_PCI1CFG_LO) && (addr <= PPC44x_PCI1CFG_HI))
52                 page_4gb = PPC44x_PCICFG_PAGE;
53         else if ((addr >= PPC44x_PCI2CFG_LO) && (addr <= PPC44x_PCI2CFG_HI))
54                 page_4gb = PPC44x_PCICFG_PAGE;
55 #endif
56         else if ((addr >= PPC44x_PCIMEM_LO) && (addr <= PPC44x_PCIMEM_HI))
57                 page_4gb = PPC44x_PCIMEM_PAGE;
58
59         return (page_4gb | addr);
60 };
61 EXPORT_SYMBOL(fixup_bigphys_addr);
62
63 void __init ibm44x_calibrate_decr(unsigned int freq)
64 {
65         tb_ticks_per_jiffy = freq / HZ;
66         tb_to_us = mulhwu_scale_factor(freq, 1000000);
67
68         /* Set the time base to zero */
69         mtspr(SPRN_TBWL, 0);
70         mtspr(SPRN_TBWU, 0);
71
72         /* Clear any pending timer interrupts */
73         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
74
75         /* Enable decrementer interrupt */
76         mtspr(SPRN_TCR, TCR_DIE);
77 }
78
79 extern void abort(void);
80
81 static void ibm44x_restart(char *cmd)
82 {
83         local_irq_disable();
84         abort();
85 }
86
87 static void ibm44x_power_off(void)
88 {
89         local_irq_disable();
90         for(;;);
91 }
92
93 static void ibm44x_halt(void)
94 {
95         local_irq_disable();
96         for(;;);
97 }
98
99 /*
100  * Read the 44x memory controller to get size of system memory.
101  */
102 static unsigned long __init ibm44x_find_end_of_memory(void)
103 {
104         u32 i, bank_config;
105         u32 mem_size = 0;
106
107         for (i=0; i<4; i++)
108         {
109                 switch (i)
110                 {
111                         case 0:
112                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B0CR);
113                                 break;
114                         case 1:
115                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B1CR);
116                                 break;
117                         case 2:
118                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B2CR);
119                                 break;
120                         case 3:
121                                 mtdcr(DCRN_SDRAM0_CFGADDR, SDRAM0_B3CR);
122                                 break;
123                 }
124
125                 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
126
127                 if (!(bank_config & SDRAM_CONFIG_BANK_ENABLE))
128                         continue;
129                 switch (SDRAM_CONFIG_BANK_SIZE(bank_config))
130                 {
131                         case SDRAM_CONFIG_SIZE_8M:
132                                 mem_size += PPC44x_MEM_SIZE_8M;
133                                 break;
134                         case SDRAM_CONFIG_SIZE_16M:
135                                 mem_size += PPC44x_MEM_SIZE_16M;
136                                 break;
137                         case SDRAM_CONFIG_SIZE_32M:
138                                 mem_size += PPC44x_MEM_SIZE_32M;
139                                 break;
140                         case SDRAM_CONFIG_SIZE_64M:
141                                 mem_size += PPC44x_MEM_SIZE_64M;
142                                 break;
143                         case SDRAM_CONFIG_SIZE_128M:
144                                 mem_size += PPC44x_MEM_SIZE_128M;
145                                 break;
146                         case SDRAM_CONFIG_SIZE_256M:
147                                 mem_size += PPC44x_MEM_SIZE_256M;
148                                 break;
149                         case SDRAM_CONFIG_SIZE_512M:
150                                 mem_size += PPC44x_MEM_SIZE_512M;
151                                 break;
152                 }
153         }
154         return mem_size;
155 }
156
157 void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
158                                  unsigned long r6, unsigned long r7)
159 {
160         parse_bootinfo(find_bootinfo());
161
162         /*
163          * If we were passed in a board information, copy it into the
164          * residual data area.
165          */
166         if (r3)
167                 __res = *(bd_t *)(r3 + KERNELBASE);
168
169 #if defined(CONFIG_BLK_DEV_INITRD)
170         /*
171          * If the init RAM disk has been configured in, and there's a valid
172          * starting address for it, set it up.
173          */
174         if (r4) {
175                 initrd_start = r4 + KERNELBASE;
176                 initrd_end = r5 + KERNELBASE;
177         }
178 #endif  /* CONFIG_BLK_DEV_INITRD */
179
180         /* Copy the kernel command line arguments to a safe place. */
181
182         if (r6) {
183                 *(char *) (r7 + KERNELBASE) = 0;
184                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
185         }
186
187         ppc_md.init_IRQ = ppc4xx_pic_init;
188         ppc_md.find_end_of_memory = ibm44x_find_end_of_memory;
189         ppc_md.restart = ibm44x_restart;
190         ppc_md.power_off = ibm44x_power_off;
191         ppc_md.halt = ibm44x_halt;
192
193 #ifdef CONFIG_SERIAL_TEXT_DEBUG
194         ppc_md.progress = gen550_progress;
195 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
196 #ifdef CONFIG_KGDB
197         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
198 #endif
199
200         /*
201          * The Abatron BDI JTAG debugger does not tolerate others
202          * mucking with the debug registers.
203          */
204 #if !defined(CONFIG_BDI_SWITCH)
205         /* Enable internal debug mode */
206         mtspr(SPRN_DBCR0, (DBCR0_IDM));
207
208         /* Clear any residual debug events */
209         mtspr(SPRN_DBSR, 0xffffffff);
210 #endif
211 }
212
213 /* Called from machine_check_exception */
214 void platform_machine_check(struct pt_regs *regs)
215 {
216 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
217         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
218                mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
219                mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH),
220                mfdcr(DCRN_PLB0_BESRL));
221         printk("PLB1: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x%08x\n",
222                mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL),
223                mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH),
224                mfdcr(DCRN_PLB1_BESRL));
225 #else
226         printk("PLB0: BEAR=0x%08x%08x ACR=  0x%08x BESR= 0x%08x\n",
227                 mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL),
228                 mfdcr(DCRN_PLB0_ACR),  mfdcr(DCRN_PLB0_BESR));
229 #endif
230         printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n",
231                 mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL),
232                 mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1));
233         printk("OPB0: BEAR=0x%08x%08x BSTAT=0x%08x\n",
234                 mfdcr(DCRN_OPB0_BEARH), mfdcr(DCRN_OPB0_BEARL),
235                 mfdcr(DCRN_OPB0_BSTAT));
236 }