2 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
3 * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
5 * This driver is a port from stlc45xx:
6 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/firmware.h>
27 #include <linux/delay.h>
28 #include <linux/irq.h>
29 #include <linux/spi/spi.h>
30 #include <linux/etherdevice.h>
31 #include <linux/gpio.h>
34 #include "p54spi_eeprom.h"
37 #include "p54common.h"
39 MODULE_FIRMWARE("3826.arm");
40 MODULE_ALIAS("stlc45xx");
43 * gpios should be handled in board files and provided via platform data,
44 * but because it's currently impossible for p54spi to have a header file
45 * in include/linux, let's use module paramaters for now
48 static int p54spi_gpio_power = 97;
49 module_param(p54spi_gpio_power, int, 0444);
50 MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
52 static int p54spi_gpio_irq = 87;
53 module_param(p54spi_gpio_irq, int, 0444);
54 MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
56 static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
57 void *buf, size_t len)
59 struct spi_transfer t[2];
63 /* We first push the address */
64 addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
67 memset(t, 0, sizeof(t));
70 t[0].len = sizeof(addr);
71 spi_message_add_tail(&t[0], &m);
75 spi_message_add_tail(&t[1], &m);
77 spi_sync(priv->spi, &m);
81 static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
82 const void *buf, size_t len)
84 struct spi_transfer t[3];
88 /* We first push the address */
89 addr = cpu_to_le16(address << 8);
92 memset(t, 0, sizeof(t));
95 t[0].len = sizeof(addr);
96 spi_message_add_tail(&t[0], &m);
100 spi_message_add_tail(&t[1], &m);
104 last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
106 t[2].tx_buf = &last_word;
107 t[2].len = sizeof(last_word);
108 spi_message_add_tail(&t[2], &m);
111 spi_sync(priv->spi, &m);
114 static u16 p54spi_read16(struct p54s_priv *priv, u8 addr)
118 p54spi_spi_read(priv, addr, &val, sizeof(val));
120 return le16_to_cpu(val);
123 static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
127 p54spi_spi_read(priv, addr, &val, sizeof(val));
129 return le32_to_cpu(val);
132 static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
134 p54spi_spi_write(priv, addr, &val, sizeof(val));
137 static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
139 p54spi_spi_write(priv, addr, &val, sizeof(val));
142 struct p54spi_spi_reg {
143 u16 address; /* __le16 ? */
148 static const struct p54spi_spi_reg p54spi_registers_array[] =
150 { SPI_ADRS_ARM_INTERRUPTS, 32, "ARM_INT " },
151 { SPI_ADRS_ARM_INT_EN, 32, "ARM_INT_ENA " },
152 { SPI_ADRS_HOST_INTERRUPTS, 32, "HOST_INT " },
153 { SPI_ADRS_HOST_INT_EN, 32, "HOST_INT_ENA" },
154 { SPI_ADRS_HOST_INT_ACK, 32, "HOST_INT_ACK" },
155 { SPI_ADRS_GEN_PURP_1, 32, "GP1_COMM " },
156 { SPI_ADRS_GEN_PURP_2, 32, "GP2_COMM " },
157 { SPI_ADRS_DEV_CTRL_STAT, 32, "DEV_CTRL_STA" },
158 { SPI_ADRS_DMA_DATA, 16, "DMA_DATA " },
159 { SPI_ADRS_DMA_WRITE_CTRL, 16, "DMA_WR_CTRL " },
160 { SPI_ADRS_DMA_WRITE_LEN, 16, "DMA_WR_LEN " },
161 { SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_WR_BASE " },
162 { SPI_ADRS_DMA_READ_CTRL, 16, "DMA_RD_CTRL " },
163 { SPI_ADRS_DMA_READ_LEN, 16, "DMA_RD_LEN " },
164 { SPI_ADRS_DMA_WRITE_BASE, 32, "DMA_RD_BASE " }
167 static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, __le32 bits)
171 for (i = 0; i < 2000; i++) {
172 __le32 buffer = p54spi_read32(priv, reg);
173 if ((buffer & bits) == bits)
181 static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
182 const void *buf, size_t len)
184 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
185 cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
187 if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL,
188 cpu_to_le32(HOST_ALLOWED))) {
189 dev_err(&priv->spi->dev, "spi_write_dma not allowed "
194 p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
195 p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
196 p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
200 static int p54spi_request_firmware(struct ieee80211_hw *dev)
202 struct p54s_priv *priv = dev->priv;
205 /* FIXME: should driver use it's own struct device? */
206 ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
209 dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
213 ret = p54_parse_firmware(dev, priv->firmware);
215 release_firmware(priv->firmware);
222 static int p54spi_request_eeprom(struct ieee80211_hw *dev)
224 struct p54s_priv *priv = dev->priv;
225 const struct firmware *eeprom;
229 * allow users to customize their eeprom.
232 ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
234 dev_info(&priv->spi->dev, "loading default eeprom...\n");
235 ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
236 sizeof(p54spi_eeprom));
238 dev_info(&priv->spi->dev, "loading user eeprom...\n");
239 ret = p54_parse_eeprom(dev, (void *) eeprom->data,
241 release_firmware(eeprom);
246 static int p54spi_upload_firmware(struct ieee80211_hw *dev)
248 struct p54s_priv *priv = dev->priv;
249 unsigned long fw_len, _fw_len;
250 unsigned int offset = 0;
254 fw_len = priv->firmware->size;
255 fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
259 /* stop the device */
260 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
261 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
262 SPI_CTRL_STAT_START_HALTED));
264 msleep(TARGET_BOOT_SLEEP);
266 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
267 SPI_CTRL_STAT_HOST_OVERRIDE |
268 SPI_CTRL_STAT_START_HALTED));
270 msleep(TARGET_BOOT_SLEEP);
273 _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
275 err = p54spi_spi_write_dma(priv, cpu_to_le32(
276 ISL38XX_DEV_FIRMWARE_ADDR + offset),
277 (fw + offset), _fw_len);
287 /* enable host interrupts */
288 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
289 cpu_to_le32(SPI_HOST_INTS_DEFAULT));
291 /* boot the device */
292 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
293 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
294 SPI_CTRL_STAT_RAM_BOOT));
296 msleep(TARGET_BOOT_SLEEP);
298 p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
299 SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
300 msleep(TARGET_BOOT_SLEEP);
307 static void p54spi_power_off(struct p54s_priv *priv)
309 disable_irq(gpio_to_irq(p54spi_gpio_irq));
310 gpio_set_value(p54spi_gpio_power, 0);
313 static void p54spi_power_on(struct p54s_priv *priv)
315 gpio_set_value(p54spi_gpio_power, 1);
316 enable_irq(gpio_to_irq(p54spi_gpio_irq));
319 * need to wait a while before device can be accessed, the lenght
325 static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
327 p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
330 static void p54spi_wakeup(struct p54s_priv *priv)
333 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
334 cpu_to_le32(SPI_TARGET_INT_WAKEUP));
336 /* And wait for the READY interrupt */
337 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
338 cpu_to_le32(SPI_HOST_INT_READY))) {
339 dev_err(&priv->spi->dev, "INT_READY timeout\n");
343 p54spi_int_ack(priv, SPI_HOST_INT_READY);
349 static inline void p54spi_sleep(struct p54s_priv *priv)
351 p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
352 cpu_to_le32(SPI_TARGET_INT_SLEEP));
355 static void p54spi_int_ready(struct p54s_priv *priv)
357 p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
358 SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
360 switch (priv->fw_state) {
361 case FW_STATE_BOOTING:
362 priv->fw_state = FW_STATE_READY;
363 complete(&priv->fw_comp);
365 case FW_STATE_RESETTING:
366 priv->fw_state = FW_STATE_READY;
367 /* TODO: reinitialize state */
374 static int p54spi_rx(struct p54s_priv *priv)
381 /* dummy read to flush SPI DMA controller bug */
382 p54spi_read16(priv, SPI_ADRS_GEN_PURP_1);
384 len = p54spi_read16(priv, SPI_ADRS_DMA_DATA);
387 dev_err(&priv->spi->dev, "rx request of zero bytes");
392 /* Firmware may insert up to 4 padding bytes after the lmac header,
393 * but it does not amend the size of SPI data transfer.
394 * Such packets has correct data size in header, thus referencing
395 * past the end of allocated skb. Reserve extra 4 bytes for this case */
396 skb = dev_alloc_skb(len + 4);
398 dev_err(&priv->spi->dev, "could not alloc skb");
402 p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, skb_put(skb, len), len);
404 /* Put additional bytes to compensate for the possible
405 * alignment-caused truncation */
408 if (p54_rx(priv->hw, skb) == 0)
415 static irqreturn_t p54spi_interrupt(int irq, void *config)
417 struct spi_device *spi = config;
418 struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
420 queue_work(priv->hw->workqueue, &priv->work);
425 static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
427 struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
432 ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
436 if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
437 cpu_to_le32(SPI_HOST_INT_WR_READY))) {
438 dev_err(&priv->spi->dev, "WR_READY timeout\n");
443 p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
446 if (FREE_AFTER_TX(skb))
447 p54_free_skb(priv->hw, skb);
452 static int p54spi_wq_tx(struct p54s_priv *priv)
454 struct p54s_tx_info *entry;
456 struct ieee80211_tx_info *info;
457 struct p54_tx_info *minfo;
458 struct p54s_tx_info *dinfo;
462 spin_lock_irqsave(&priv->tx_lock, flags);
464 while (!list_empty(&priv->tx_pending)) {
465 entry = list_entry(priv->tx_pending.next,
466 struct p54s_tx_info, tx_list);
468 list_del_init(&entry->tx_list);
470 spin_unlock_irqrestore(&priv->tx_lock, flags);
472 dinfo = container_of((void *) entry, struct p54s_tx_info,
474 minfo = container_of((void *) dinfo, struct p54_tx_info,
476 info = container_of((void *) minfo, struct ieee80211_tx_info,
478 skb = container_of((void *) info, struct sk_buff, cb);
480 ret = p54spi_tx_frame(priv, skb);
483 p54_free_skb(priv->hw, skb);
487 spin_lock_irqsave(&priv->tx_lock, flags);
489 spin_unlock_irqrestore(&priv->tx_lock, flags);
493 static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
495 struct p54s_priv *priv = dev->priv;
496 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
497 struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
498 struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
501 BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
503 spin_lock_irqsave(&priv->tx_lock, flags);
504 list_add_tail(&di->tx_list, &priv->tx_pending);
505 spin_unlock_irqrestore(&priv->tx_lock, flags);
507 queue_work(priv->hw->workqueue, &priv->work);
510 static void p54spi_work(struct work_struct *work)
512 struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
516 mutex_lock(&priv->mutex);
518 if (priv->fw_state == FW_STATE_OFF &&
519 priv->fw_state == FW_STATE_RESET)
522 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
524 if (ints & SPI_HOST_INT_READY) {
525 p54spi_int_ready(priv);
526 p54spi_int_ack(priv, SPI_HOST_INT_READY);
529 if (priv->fw_state != FW_STATE_READY)
532 if (ints & SPI_HOST_INT_UPDATE) {
533 p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
534 ret = p54spi_rx(priv);
538 if (ints & SPI_HOST_INT_SW_UPDATE) {
539 p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
540 ret = p54spi_rx(priv);
545 ret = p54spi_wq_tx(priv);
549 ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
552 mutex_unlock(&priv->mutex);
555 static int p54spi_op_start(struct ieee80211_hw *dev)
557 struct p54s_priv *priv = dev->priv;
558 unsigned long timeout;
561 if (mutex_lock_interruptible(&priv->mutex)) {
566 priv->fw_state = FW_STATE_BOOTING;
568 p54spi_power_on(priv);
570 ret = p54spi_upload_firmware(dev);
572 p54spi_power_off(priv);
576 mutex_unlock(&priv->mutex);
578 timeout = msecs_to_jiffies(2000);
579 timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
582 dev_err(&priv->spi->dev, "firmware boot failed");
583 p54spi_power_off(priv);
588 if (mutex_lock_interruptible(&priv->mutex)) {
590 p54spi_power_off(priv);
594 WARN_ON(priv->fw_state != FW_STATE_READY);
597 mutex_unlock(&priv->mutex);
603 static void p54spi_op_stop(struct ieee80211_hw *dev)
605 struct p54s_priv *priv = dev->priv;
608 if (mutex_lock_interruptible(&priv->mutex)) {
609 /* FIXME: how to handle this error? */
613 WARN_ON(priv->fw_state != FW_STATE_READY);
615 cancel_work_sync(&priv->work);
617 p54spi_power_off(priv);
618 spin_lock_irqsave(&priv->tx_lock, flags);
619 INIT_LIST_HEAD(&priv->tx_pending);
620 spin_unlock_irqrestore(&priv->tx_lock, flags);
622 priv->fw_state = FW_STATE_OFF;
623 mutex_unlock(&priv->mutex);
626 static int __devinit p54spi_probe(struct spi_device *spi)
628 struct p54s_priv *priv = NULL;
629 struct ieee80211_hw *hw;
632 hw = p54_init_common(sizeof(*priv));
634 dev_err(&priv->spi->dev, "could not alloc ieee80211_hw");
640 dev_set_drvdata(&spi->dev, priv);
643 spi->bits_per_word = 16;
644 spi->max_speed_hz = 24000000;
646 ret = spi_setup(spi);
648 dev_err(&priv->spi->dev, "spi_setup failed");
649 goto err_free_common;
652 ret = gpio_request(p54spi_gpio_power, "p54spi power");
654 dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
655 goto err_free_common;
658 ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
660 dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
661 goto err_free_common;
664 gpio_direction_output(p54spi_gpio_power, 0);
665 gpio_direction_input(p54spi_gpio_irq);
667 ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
668 p54spi_interrupt, IRQF_DISABLED, "p54spi",
671 dev_err(&priv->spi->dev, "request_irq() failed");
672 goto err_free_common;
675 set_irq_type(gpio_to_irq(p54spi_gpio_irq),
676 IRQ_TYPE_EDGE_RISING);
678 disable_irq(gpio_to_irq(p54spi_gpio_irq));
680 INIT_WORK(&priv->work, p54spi_work);
681 init_completion(&priv->fw_comp);
682 INIT_LIST_HEAD(&priv->tx_pending);
683 mutex_init(&priv->mutex);
684 SET_IEEE80211_DEV(hw, &spi->dev);
685 priv->common.open = p54spi_op_start;
686 priv->common.stop = p54spi_op_stop;
687 priv->common.tx = p54spi_op_tx;
689 ret = p54spi_request_firmware(hw);
691 goto err_free_common;
693 ret = p54spi_request_eeprom(hw);
695 goto err_free_common;
697 ret = p54_register_common(hw, &priv->spi->dev);
699 goto err_free_common;
704 p54_free_common(priv->hw);
708 static int __devexit p54spi_remove(struct spi_device *spi)
710 struct p54s_priv *priv = dev_get_drvdata(&spi->dev);
712 ieee80211_unregister_hw(priv->hw);
714 free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
716 gpio_free(p54spi_gpio_power);
717 gpio_free(p54spi_gpio_irq);
718 release_firmware(priv->firmware);
720 mutex_destroy(&priv->mutex);
722 p54_free_common(priv->hw);
723 ieee80211_free_hw(priv->hw);
729 static struct spi_driver p54spi_driver = {
731 /* use cx3110x name because board-n800.c uses that for the
734 .bus = &spi_bus_type,
735 .owner = THIS_MODULE,
738 .probe = p54spi_probe,
739 .remove = __devexit_p(p54spi_remove),
742 static int __init p54spi_init(void)
746 ret = spi_register_driver(&p54spi_driver);
748 printk(KERN_ERR "failed to register SPI driver: %d", ret);
756 static void __exit p54spi_exit(void)
758 spi_unregister_driver(&p54spi_driver);
761 module_init(p54spi_init);
762 module_exit(p54spi_exit);
764 MODULE_LICENSE("GPL");
765 MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");