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   1 /*
   2  * linux/drivers/video/s3c2410fb.c
   3  *      Copyright (c) Arnaud Patard, Ben Dooks
   4  *
   5  * This file is subject to the terms and conditions of the GNU General Public
   6  * License.  See the file COPYING in the main directory of this archive for
   7  * more details.
   8  *
   9  *          S3C2410 LCD Controller Frame Buffer Driver
  10  *          based on skeletonfb.c, sa1100fb.c and others
  11  *
  12  * ChangeLog
  13  * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14  *      - u32 state -> pm_message_t state
  15  *      - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16  *
  17  * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18  *      - Removed the ioctl
  19  *      - use readl/writel instead of __raw_writel/__raw_readl
  20  *
  21  * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22  *      - Added the possibility to set on or off the
  23  *      debugging messages
  24  *      - Replaced 0 and 1 by on or off when reading the
  25  *      /sys files
  26  *
  27  * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28  *      - added non 16bpp modes
  29  *      - updated platform information for range of x/y/bpp
  30  *      - add code to ensure palette is written correctly
  31  *      - add pixel clock divisor control
  32  *
  33  * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34  *      - Removed the use of currcon as it no more exists
  35  *      - Added LCD power sysfs interface
  36  *
  37  * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38  *      - minor cleanups
  39  *      - add suspend/resume support
  40  *      - s3c2410fb_setcolreg() not valid in >8bpp modes
  41  *      - removed last CONFIG_FB_S3C2410_FIXED
  42  *      - ensure lcd controller stopped before cleanup
  43  *      - added sysfs interface for backlight power
  44  *      - added mask for gpio configuration
  45  *      - ensured IRQs disabled during GPIO configuration
  46  *      - disable TPAL before enabling video
  47  *
  48  * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49  *      - Suppress command line options
  50  *
  51  * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52  *      - code cleanup
  53  *
  54  * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55  *      - Renamed from h1940fb.c to s3c2410fb.c
  56  *      - Add support for different devices
  57  *      - Backlight support
  58  *
  59  * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60  *      - added clock (de-)allocation code
  61  *      - added fixem fbmem option
  62  *
  63  * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64  *      - code cleanup
  65  *      - added a forgotten return in h1940fb_init
  66  *
  67  * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68  *      - code cleanup and extended debugging
  69  *
  70  * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71  *      - First version
  72  */
  73
  74 #include <linux/module.h>
  75 #include <linux/kernel.h>
  76 #include <linux/errno.h>
  77 #include <linux/string.h>
  78 #include <linux/mm.h>
  79 #include <linux/slab.h>
  80 #include <linux/delay.h>
  81 #include <linux/fb.h>
  82 #include <linux/init.h>
  83 #include <linux/dma-mapping.h>
  84 #include <linux/interrupt.h>
  85 #include <linux/platform_device.h>
  86 #include <linux/clk.h>
  87
  88 #include <asm/io.h>
  89 #include <asm/div64.h>
  90
  91 #include <asm/mach/map.h>
  92 #include <asm/arch/regs-lcd.h>
  93 #include <asm/arch/regs-gpio.h>
  94 #include <asm/arch/fb.h>
  95
  96 #ifdef CONFIG_PM
  97 #include <linux/pm.h>
  98 #endif
  99
 100 #include "s3c2410fb.h"
 101
 102 /* Debugging stuff */
 103 #ifdef CONFIG_FB_S3C2410_DEBUG
 104 static int debug        = 1;
 105 #else
 106 static int debug        = 0;
 107 #endif
 108
 109 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
 110
 111 /* useful functions */
 112
 113 /* s3c2410fb_set_lcdaddr
 114  *
 115  * initialise lcd controller address pointers
 116  */
 117 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
 118 {
 119         unsigned long saddr1, saddr2, saddr3;
 120         struct s3c2410fb_info *fbi = info->par;
 121         void __iomem *regs = fbi->io;
 122
 123         saddr1  = info->fix.smem_start >> 1;
 124         saddr2  = info->fix.smem_start;
 125         saddr2 += info->fix.line_length * info->var.yres;
 126         saddr2 >>= 1;
 127
 128         saddr3 = S3C2410_OFFSIZE(0) |
 129                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
 130
 131         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
 132         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
 133         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
 134
 135         writel(saddr1, regs + S3C2410_LCDSADDR1);
 136         writel(saddr2, regs + S3C2410_LCDSADDR2);
 137         writel(saddr3, regs + S3C2410_LCDSADDR3);
 138 }
 139
 140 /* s3c2410fb_calc_pixclk()
 141  *
 142  * calculate divisor for clk->pixclk
 143  */
 144 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
 145                                           unsigned long pixclk)
 146 {
 147         unsigned long clk = clk_get_rate(fbi->clk);
 148         unsigned long long div;
 149
 150         /* pixclk is in picoseconds, our clock is in Hz
 151          *
 152          * Hz -> picoseconds is / 10^-12
 153          */
 154
 155         div = (unsigned long long)clk * pixclk;
 156         div >>= 12;                     /* div / 2^12 */
 157         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 158
 159         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 160         return div;
 161 }
 162
 163 /*
 164  *      s3c2410fb_check_var():
 165  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 166  *      if it's too big, return -EINVAL.
 167  *
 168  */
 169 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 170                                struct fb_info *info)
 171 {
 172         struct s3c2410fb_info *fbi = info->par;
 173         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 174         struct s3c2410fb_display *display = NULL;
 175         struct s3c2410fb_display *default_display = mach_info->displays +
 176                                                     mach_info->default_display;
 177         int type = default_display->type;
 178         unsigned i;
 179
 180         dprintk("check_var(var=%p, info=%p)\n", var, info);
 181
 182         /* validate x/y resolution */
 183         /* choose default mode if possible */
 184         if (var->yres == default_display->yres &&
 185             var->xres == default_display->xres &&
 186             var->bits_per_pixel == default_display->bpp)
 187                 display = default_display;
 188         else
 189                 for (i = 0; i < mach_info->num_displays; i++)
 190                         if (type == mach_info->displays[i].type &&
 191                             var->yres == mach_info->displays[i].yres &&
 192                             var->xres == mach_info->displays[i].xres &&
 193                             var->bits_per_pixel == mach_info->displays[i].bpp) {
 194                                 display = mach_info->displays + i;
 195                                 break;
 196                         }
 197
 198         if (!display) {
 199                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 200                         var->xres, var->yres, var->bits_per_pixel);
 201                 return -EINVAL;
 202         }
 203
 204         /* it is always the size as the display */
 205         var->xres_virtual = display->xres;
 206         var->yres_virtual = display->yres;
 207         var->height = display->height;
 208         var->width = display->width;
 209
 210         /* copy lcd settings */
 211         var->pixclock = display->pixclock;
 212         var->left_margin = display->left_margin;
 213         var->right_margin = display->right_margin;
 214         var->upper_margin = display->upper_margin;
 215         var->lower_margin = display->lower_margin;
 216         var->vsync_len = display->vsync_len;
 217         var->hsync_len = display->hsync_len;
 218
 219         fbi->regs.lcdcon5 = display->lcdcon5;
 220         /* set display type */
 221         fbi->regs.lcdcon1 = display->type;
 222
 223         var->transp.offset = 0;
 224         var->transp.length = 0;
 225         /* set r/g/b positions */
 226         switch (var->bits_per_pixel) {
 227         case 1:
 228         case 2:
 229         case 4:
 230                 var->red.offset = 0;
 231                 var->red.length = var->bits_per_pixel;
 232                 var->green      = var->red;
 233                 var->blue       = var->red;
 234                 break;
 235         case 8:
 236                 if (display->type != S3C2410_LCDCON1_TFT) {
 237                         /* 8 bpp 332 */
 238                         var->red.length         = 3;
 239                         var->red.offset         = 5;
 240                         var->green.length       = 3;
 241                         var->green.offset       = 2;
 242                         var->blue.length        = 2;
 243                         var->blue.offset        = 0;
 244                 } else {
 245                         var->red.offset         = 0;
 246                         var->red.length         = 8;
 247                         var->green              = var->red;
 248                         var->blue               = var->red;
 249                 }
 250                 break;
 251         case 12:
 252                 /* 12 bpp 444 */
 253                 var->red.length         = 4;
 254                 var->red.offset         = 8;
 255                 var->green.length       = 4;
 256                 var->green.offset       = 4;
 257                 var->blue.length        = 4;
 258                 var->blue.offset        = 0;
 259                 break;
 260
 261         default:
 262         case 16:
 263                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 264                         /* 16 bpp, 565 format */
 265                         var->red.offset         = 11;
 266                         var->green.offset       = 5;
 267                         var->blue.offset        = 0;
 268                         var->red.length         = 5;
 269                         var->green.length       = 6;
 270                         var->blue.length        = 5;
 271                 } else {
 272                         /* 16 bpp, 5551 format */
 273                         var->red.offset         = 11;
 274                         var->green.offset       = 6;
 275                         var->blue.offset        = 1;
 276                         var->red.length         = 5;
 277                         var->green.length       = 5;
 278                         var->blue.length        = 5;
 279                 }
 280                 break;
 281         case 32:
 282                 /* 24 bpp 888 and 8 dummy */
 283                 var->red.length         = 8;
 284                 var->red.offset         = 16;
 285                 var->green.length       = 8;
 286                 var->green.offset       = 8;
 287                 var->blue.length        = 8;
 288                 var->blue.offset        = 0;
 289                 break;
 290         }
 291         return 0;
 292 }
 293
 294 /* s3c2410fb_calculate_stn_lcd_regs
 295  *
 296  * calculate register values from var settings
 297  */
 298 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 299                                              struct s3c2410fb_hw *regs)
 300 {
 301         const struct s3c2410fb_info *fbi = info->par;
 302         const struct fb_var_screeninfo *var = &info->var;
 303         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 304         int hs = var->xres >> 2;
 305         unsigned wdly = (var->left_margin >> 4) - 1;
 306         unsigned wlh = (var->hsync_len >> 4) - 1;
 307
 308         if (type != S3C2410_LCDCON1_STN4)
 309                 hs >>= 1;
 310
 311         switch (var->bits_per_pixel) {
 312         case 1:
 313                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 314                 break;
 315         case 2:
 316                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 317                 break;
 318         case 4:
 319                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 320                 break;
 321         case 8:
 322                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 323                 hs *= 3;
 324                 break;
 325         case 12:
 326                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 327                 hs *= 3;
 328                 break;
 329
 330         default:
 331                 /* invalid pixel depth */
 332                 dev_err(fbi->dev, "invalid bpp %d\n",
 333                         var->bits_per_pixel);
 334         }
 335         /* update X/Y info */
 336         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 337                 var->left_margin, var->right_margin, var->hsync_len);
 338
 339         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 340
 341         if (wdly > 3)
 342                 wdly = 3;
 343
 344         if (wlh > 3)
 345                 wlh = 3;
 346
 347         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 348                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 349                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 350
 351         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 352 }
 353
 354 /* s3c2410fb_calculate_tft_lcd_regs
 355  *
 356  * calculate register values from var settings
 357  */
 358 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 359                                              struct s3c2410fb_hw *regs)
 360 {
 361         const struct s3c2410fb_info *fbi = info->par;
 362         const struct fb_var_screeninfo *var = &info->var;
 363
 364         switch (var->bits_per_pixel) {
 365         case 1:
 366                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 367                 break;
 368         case 2:
 369                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 370                 break;
 371         case 4:
 372                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 373                 break;
 374         case 8:
 375                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 376                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 377                                  S3C2410_LCDCON5_FRM565;
 378                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 379                 break;
 380         case 16:
 381                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 382                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 383                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 384                 break;
 385         case 32:
 386                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 387                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 388                                    S3C2410_LCDCON5_HWSWP |
 389                                    S3C2410_LCDCON5_BPP24BL);
 390                 break;
 391         default:
 392                 /* invalid pixel depth */
 393                 dev_err(fbi->dev, "invalid bpp %d\n",
 394                         var->bits_per_pixel);
 395         }
 396         /* update X/Y info */
 397         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 398                 var->upper_margin, var->lower_margin, var->vsync_len);
 399
 400         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 401                 var->left_margin, var->right_margin, var->hsync_len);
 402
 403         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 404                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 405                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 406                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 407
 408         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 409                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 410                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 411
 412         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 413 }
 414
 415 /* s3c2410fb_activate_var
 416  *
 417  * activate (set) the controller from the given framebuffer
 418  * information
 419  */
 420 static void s3c2410fb_activate_var(struct fb_info *info)
 421 {
 422         struct s3c2410fb_info *fbi = info->par;
 423         void __iomem *regs = fbi->io;
 424         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 425         struct fb_var_screeninfo *var = &info->var;
 426         int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
 427
 428         dprintk("%s: var->xres  = %d\n", __FUNCTION__, var->xres);
 429         dprintk("%s: var->yres  = %d\n", __FUNCTION__, var->yres);
 430         dprintk("%s: var->bpp   = %d\n", __FUNCTION__, var->bits_per_pixel);
 431
 432         if (type == S3C2410_LCDCON1_TFT) {
 433                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 434                 --clkdiv;
 435                 if (clkdiv < 0)
 436                         clkdiv = 0;
 437         } else {
 438                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 439                 if (clkdiv < 2)
 440                         clkdiv = 2;
 441         }
 442
 443         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 444
 445         /* write new registers */
 446
 447         dprintk("new register set:\n");
 448         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 449         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 450         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 451         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 452         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 453
 454         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 455                 regs + S3C2410_LCDCON1);
 456         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 457         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 458         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 459         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 460
 461         /* set lcd address pointers */
 462         s3c2410fb_set_lcdaddr(info);
 463
 464         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 465         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 466 }
 467
 468 /*
 469  *      s3c2410fb_set_par - Alters the hardware state.
 470  *      @info: frame buffer structure that represents a single frame buffer
 471  *
 472  */
 473 static int s3c2410fb_set_par(struct fb_info *info)
 474 {
 475         struct fb_var_screeninfo *var = &info->var;
 476
 477         switch (var->bits_per_pixel) {
 478         case 32:
 479         case 16:
 480         case 12:
 481                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 482                 break;
 483         case 1:
 484                 info->fix.visual = FB_VISUAL_MONO01;
 485                 break;
 486         default:
 487                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 488                 break;
 489         }
 490
 491         info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
 492
 493         /* activate this new configuration */
 494
 495         s3c2410fb_activate_var(info);
 496         return 0;
 497 }
 498
 499 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 500                                     unsigned int regno, unsigned int val)
 501 {
 502         unsigned long flags;
 503         unsigned long irqen;
 504         void __iomem *regs = fbi->io;
 505
 506         local_irq_save(flags);
 507
 508         fbi->palette_buffer[regno] = val;
 509
 510         if (!fbi->palette_ready) {
 511                 fbi->palette_ready = 1;
 512
 513                 /* enable IRQ */
 514                 irqen = readl(regs + S3C2410_LCDINTMSK);
 515                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 516                 writel(irqen, regs + S3C2410_LCDINTMSK);
 517         }
 518
 519         local_irq_restore(flags);
 520 }
 521
 522 /* from pxafb.c */
 523 static inline unsigned int chan_to_field(unsigned int chan,
 524                                          struct fb_bitfield *bf)
 525 {
 526         chan &= 0xffff;
 527         chan >>= 16 - bf->length;
 528         return chan << bf->offset;
 529 }
 530
 531 static int s3c2410fb_setcolreg(unsigned regno,
 532                                unsigned red, unsigned green, unsigned blue,
 533                                unsigned transp, struct fb_info *info)
 534 {
 535         struct s3c2410fb_info *fbi = info->par;
 536         void __iomem *regs = fbi->io;
 537         unsigned int val;
 538
 539         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 540                    regno, red, green, blue); */
 541
 542         switch (info->fix.visual) {
 543         case FB_VISUAL_TRUECOLOR:
 544                 /* true-colour, use pseudo-palette */
 545
 546                 if (regno < 16) {
 547                         u32 *pal = info->pseudo_palette;
 548
 549                         val  = chan_to_field(red,   &info->var.red);
 550                         val |= chan_to_field(green, &info->var.green);
 551                         val |= chan_to_field(blue,  &info->var.blue);
 552
 553                         pal[regno] = val;
 554                 }
 555                 break;
 556
 557         case FB_VISUAL_PSEUDOCOLOR:
 558                 if (regno < 256) {
 559                         /* currently assume RGB 5-6-5 mode */
 560
 561                         val  = (red   >>  0) & 0xf800;
 562                         val |= (green >>  5) & 0x07e0;
 563                         val |= (blue  >> 11) & 0x001f;
 564
 565                         writel(val, regs + S3C2410_TFTPAL(regno));
 566                         schedule_palette_update(fbi, regno, val);
 567                 }
 568
 569                 break;
 570
 571         default:
 572                 return 1;       /* unknown type */
 573         }
 574
 575         return 0;
 576 }
 577
 578 /*
 579  *      s3c2410fb_blank
 580  *      @blank_mode: the blank mode we want.
 581  *      @info: frame buffer structure that represents a single frame buffer
 582  *
 583  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 584  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 585  *      video mode which doesn't support it. Implements VESA suspend
 586  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 587  *      blank_mode == 2: suspend vsync
 588  *      blank_mode == 3: suspend hsync
 589  *      blank_mode == 4: powerdown
 590  *
 591  *      Returns negative errno on error, or zero on success.
 592  *
 593  */
 594 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 595 {
 596         struct s3c2410fb_info *fbi = info->par;
 597         void __iomem *regs = fbi->io;
 598
 599         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 600
 601         if (blank_mode == FB_BLANK_UNBLANK)
 602                 writel(0x0, regs + S3C2410_TPAL);
 603         else {
 604                 dprintk("setting TPAL to output 0x000000\n");
 605                 writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int s3c2410fb_debug_show(struct device *dev,
 612                                 struct device_attribute *attr, char *buf)
 613 {
 614         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 615 }
 616
 617 static int s3c2410fb_debug_store(struct device *dev,
 618                                  struct device_attribute *attr,
 619                                  const char *buf, size_t len)
 620 {
 621         if (len < 1)
 622                 return -EINVAL;
 623
 624         if (strnicmp(buf, "on", 2) == 0 ||
 625             strnicmp(buf, "1", 1) == 0) {
 626                 debug = 1;
 627                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 628         } else if (strnicmp(buf, "off", 3) == 0 ||
 629                    strnicmp(buf, "0", 1) == 0) {
 630                 debug = 0;
 631                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 632         } else {
 633                 return -EINVAL;
 634         }
 635
 636         return len;
 637 }
 638
 639 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 640
 641 static struct fb_ops s3c2410fb_ops = {
 642         .owner          = THIS_MODULE,
 643         .fb_check_var   = s3c2410fb_check_var,
 644         .fb_set_par     = s3c2410fb_set_par,
 645         .fb_blank       = s3c2410fb_blank,
 646         .fb_setcolreg   = s3c2410fb_setcolreg,
 647         .fb_fillrect    = cfb_fillrect,
 648         .fb_copyarea    = cfb_copyarea,
 649         .fb_imageblit   = cfb_imageblit,
 650 };
 651
 652 /*
 653  * s3c2410fb_map_video_memory():
 654  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 655  *      remapped into a non-cached, non-buffered, memory region to
 656  *      allow palette and pixel writes to occur without flushing the
 657  *      cache.  Once this area is remapped, all virtual memory
 658  *      access to the video memory should occur at the new region.
 659  */
 660 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 661 {
 662         struct s3c2410fb_info *fbi = info->par;
 663         dma_addr_t map_dma;
 664         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 665
 666         dprintk("map_video_memory(fbi=%p)\n", fbi);
 667
 668         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 669                                                    &map_dma, GFP_KERNEL);
 670
 671         if (info->screen_base) {
 672                 /* prevent initial garbage on screen */
 673                 dprintk("map_video_memory: clear %p:%08x\n",
 674                         info->screen_base, map_size);
 675                 memset(info->screen_base, 0xf0, map_size);
 676
 677                 info->fix.smem_start = map_dma;
 678
 679                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 680                         info->fix.smem_start, info->screen_base, map_size);
 681         }
 682
 683         return info->screen_base ? 0 : -ENOMEM;
 684 }
 685
 686 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 687 {
 688         struct s3c2410fb_info *fbi = info->par;
 689
 690         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 691                               info->screen_base, info->fix.smem_start);
 692 }
 693
 694 static inline void modify_gpio(void __iomem *reg,
 695                                unsigned long set, unsigned long mask)
 696 {
 697         unsigned long tmp;
 698
 699         tmp = readl(reg) & ~mask;
 700         writel(tmp | set, reg);
 701 }
 702
 703 /*
 704  * s3c2410fb_init_registers - Initialise all LCD-related registers
 705  */
 706 static int s3c2410fb_init_registers(struct fb_info *info)
 707 {
 708         struct s3c2410fb_info *fbi = info->par;
 709         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 710         unsigned long flags;
 711         void __iomem *regs = fbi->io;
 712
 713         /* Initialise LCD with values from haret */
 714
 715         local_irq_save(flags);
 716
 717         /* modify the gpio(s) with interrupts set (bjd) */
 718
 719         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 720         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 721         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 722         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 723
 724         local_irq_restore(flags);
 725
 726         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 727         writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
 728
 729         dprintk("replacing TPAL %08x\n", readl(regs + S3C2410_TPAL));
 730
 731         /* ensure temporary palette disabled */
 732         writel(0x00, regs + S3C2410_TPAL);
 733
 734         return 0;
 735 }
 736
 737 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 738 {
 739         unsigned int i;
 740         void __iomem *regs = fbi->io;
 741
 742         fbi->palette_ready = 0;
 743
 744         for (i = 0; i < 256; i++) {
 745                 unsigned long ent = fbi->palette_buffer[i];
 746                 if (ent == PALETTE_BUFF_CLEAR)
 747                         continue;
 748
 749                 writel(ent, regs + S3C2410_TFTPAL(i));
 750
 751                 /* it seems the only way to know exactly
 752                  * if the palette wrote ok, is to check
 753                  * to see if the value verifies ok
 754                  */
 755
 756                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 757                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 758                 else
 759                         fbi->palette_ready = 1;   /* retry */
 760         }
 761 }
 762
 763 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 764 {
 765         struct s3c2410fb_info *fbi = dev_id;
 766         void __iomem *regs = fbi->io;
 767         unsigned long lcdirq = readl(regs + S3C2410_LCDINTPND);
 768
 769         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 770                 if (fbi->palette_ready)
 771                         s3c2410fb_write_palette(fbi);
 772
 773                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDINTPND);
 774                 writel(S3C2410_LCDINT_FRSYNC, regs + S3C2410_LCDSRCPND);
 775         }
 776
 777         return IRQ_HANDLED;
 778 }
 779
 780 static char driver_name[] = "s3c2410fb";
 781
 782 static int __init s3c2410fb_probe(struct platform_device *pdev)
 783 {
 784         struct s3c2410fb_info *info;
 785         struct s3c2410fb_display *display;
 786         struct fb_info *fbinfo;
 787         struct s3c2410fb_mach_info *mach_info;
 788         struct resource *res;
 789         int ret;
 790         int irq;
 791         int i;
 792         int size;
 793         u32 lcdcon1;
 794
 795         mach_info = pdev->dev.platform_data;
 796         if (mach_info == NULL) {
 797                 dev_err(&pdev->dev,
 798                         "no platform data for lcd, cannot attach\n");
 799                 return -EINVAL;
 800         }
 801
 802         display = mach_info->displays + mach_info->default_display;
 803
 804         irq = platform_get_irq(pdev, 0);
 805         if (irq < 0) {
 806                 dev_err(&pdev->dev, "no irq for device\n");
 807                 return -ENOENT;
 808         }
 809
 810         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 811         if (!fbinfo)
 812                 return -ENOMEM;
 813
 814         platform_set_drvdata(pdev, fbinfo);
 815
 816         info = fbinfo->par;
 817         info->dev = &pdev->dev;
 818
 819         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 820         if (res == NULL) {
 821                 dev_err(&pdev->dev, "failed to get memory registers\n");
 822                 ret = -ENXIO;
 823                 goto dealloc_fb;
 824         }
 825
 826         size = (res->end - res->start) + 1;
 827         info->mem = request_mem_region(res->start, size, pdev->name);
 828         if (info->mem == NULL) {
 829                 dev_err(&pdev->dev, "failed to get memory region\n");
 830                 ret = -ENOENT;
 831                 goto dealloc_fb;
 832         }
 833
 834         info->io = ioremap(res->start, size);
 835         if (info->io == NULL) {
 836                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 837                 ret = -ENXIO;
 838                 goto release_mem;
 839         }
 840
 841         dprintk("devinit\n");
 842
 843         strcpy(fbinfo->fix.id, driver_name);
 844
 845         /* Stop the video */
 846         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 847         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 848
 849         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 850         fbinfo->fix.type_aux        = 0;
 851         fbinfo->fix.xpanstep        = 0;
 852         fbinfo->fix.ypanstep        = 0;
 853         fbinfo->fix.ywrapstep       = 0;
 854         fbinfo->fix.accel           = FB_ACCEL_NONE;
 855
 856         fbinfo->var.nonstd          = 0;
 857         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 858         fbinfo->var.accel_flags     = 0;
 859         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 860
 861         fbinfo->fbops               = &s3c2410fb_ops;
 862         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 863         fbinfo->pseudo_palette      = &info->pseudo_pal;
 864
 865         for (i = 0; i < 256; i++)
 866                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 867
 868         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 869         if (ret) {
 870                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 871                 ret = -EBUSY;
 872                 goto release_regs;
 873         }
 874
 875         info->clk = clk_get(NULL, "lcd");
 876         if (!info->clk || IS_ERR(info->clk)) {
 877                 printk(KERN_ERR "failed to get lcd clock source\n");
 878                 ret = -ENOENT;
 879                 goto release_irq;
 880         }
 881
 882         clk_enable(info->clk);
 883         dprintk("got and enabled clock\n");
 884
 885         msleep(1);
 886
 887         /* find maximum required memory size for display */
 888         for (i = 0; i < mach_info->num_displays; i++) {
 889                 unsigned long smem_len = mach_info->displays[i].xres;
 890
 891                 smem_len *= mach_info->displays[i].yres;
 892                 smem_len *= mach_info->displays[i].bpp;
 893                 smem_len >>= 3;
 894                 if (fbinfo->fix.smem_len < smem_len)
 895                         fbinfo->fix.smem_len = smem_len;
 896         }
 897
 898         /* Initialize video memory */
 899         ret = s3c2410fb_map_video_memory(fbinfo);
 900         if (ret) {
 901                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 902                 ret = -ENOMEM;
 903                 goto release_clock;
 904         }
 905
 906         dprintk("got video memory\n");
 907
 908         fbinfo->var.xres = display->xres;
 909         fbinfo->var.yres = display->yres;
 910         fbinfo->var.bits_per_pixel = display->bpp;
 911
 912         s3c2410fb_init_registers(fbinfo);
 913
 914         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 915
 916         ret = register_framebuffer(fbinfo);
 917         if (ret < 0) {
 918                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 919                         ret);
 920                 goto free_video_memory;
 921         }
 922
 923         /* create device files */
 924         device_create_file(&pdev->dev, &dev_attr_debug);
 925
 926         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 927                 fbinfo->node, fbinfo->fix.id);
 928
 929         return 0;
 930
 931 free_video_memory:
 932         s3c2410fb_unmap_video_memory(fbinfo);
 933 release_clock:
 934         clk_disable(info->clk);
 935         clk_put(info->clk);
 936 release_irq:
 937         free_irq(irq, info);
 938 release_regs:
 939         iounmap(info->io);
 940 release_mem:
 941         release_resource(info->mem);
 942         kfree(info->mem);
 943 dealloc_fb:
 944         platform_set_drvdata(pdev, NULL);
 945         framebuffer_release(fbinfo);
 946         return ret;
 947 }
 948
 949 /* s3c2410fb_stop_lcd
 950  *
 951  * shutdown the lcd controller
 952  */
 953 static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
 954 {
 955         unsigned long flags;
 956
 957         local_irq_save(flags);
 958
 959         fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 960         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 961
 962         local_irq_restore(flags);
 963 }
 964
 965 /*
 966  *  Cleanup
 967  */
 968 static int s3c2410fb_remove(struct platform_device *pdev)
 969 {
 970         struct fb_info *fbinfo = platform_get_drvdata(pdev);
 971         struct s3c2410fb_info *info = fbinfo->par;
 972         int irq;
 973
 974         unregister_framebuffer(fbinfo);
 975
 976         s3c2410fb_stop_lcd(info);
 977         msleep(1);
 978
 979         s3c2410fb_unmap_video_memory(fbinfo);
 980
 981         if (info->clk) {
 982                 clk_disable(info->clk);
 983                 clk_put(info->clk);
 984                 info->clk = NULL;
 985         }
 986
 987         irq = platform_get_irq(pdev, 0);
 988         free_irq(irq, info);
 989
 990         iounmap(info->io);
 991
 992         release_resource(info->mem);
 993         kfree(info->mem);
 994
 995         platform_set_drvdata(pdev, NULL);
 996         framebuffer_release(fbinfo);
 997
 998         return 0;
 999 }
1000
1001 #ifdef CONFIG_PM
1002
1003 /* suspend and resume support for the lcd controller */
1004 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1005 {
1006         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1007         struct s3c2410fb_info *info = fbinfo->par;
1008
1009         s3c2410fb_stop_lcd(info);
1010
1011         /* sleep before disabling the clock, we need to ensure
1012          * the LCD DMA engine is not going to get back on the bus
1013          * before the clock goes off again (bjd) */
1014
1015         msleep(1);
1016         clk_disable(info->clk);
1017
1018         return 0;
1019 }
1020
1021 static int s3c2410fb_resume(struct platform_device *dev)
1022 {
1023         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1024         struct s3c2410fb_info *info = fbinfo->par;
1025
1026         clk_enable(info->clk);
1027         msleep(1);
1028
1029         s3c2410fb_init_registers(info);
1030
1031         return 0;
1032 }
1033
1034 #else
1035 #define s3c2410fb_suspend NULL
1036 #define s3c2410fb_resume  NULL
1037 #endif
1038
1039 static struct platform_driver s3c2410fb_driver = {
1040         .probe          = s3c2410fb_probe,
1041         .remove         = s3c2410fb_remove,
1042         .suspend        = s3c2410fb_suspend,
1043         .resume         = s3c2410fb_resume,
1044         .driver         = {
1045                 .name   = "s3c2410-lcd",
1046                 .owner  = THIS_MODULE,
1047         },
1048 };
1049
1050 int __init s3c2410fb_init(void)
1051 {
1052         return platform_driver_register(&s3c2410fb_driver);
1053 }
1054
1055 static void __exit s3c2410fb_cleanup(void)
1056 {
1057         platform_driver_unregister(&s3c2410fb_driver);
1058 }
1059
1060 module_init(s3c2410fb_init);
1061 module_exit(s3c2410fb_cleanup);
1062
1063 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1064               "Ben Dooks <ben-linux@fluff.org>");
1065 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1066 MODULE_LICENSE("GPL");