git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void kvm_reput_irq(struct vcpu_svm *svm);
  74 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  75
  76 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  77 static int nested_svm_vmexit(struct vcpu_svm *svm);
  78 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  79                              void *arg2, void *opaque);
  80 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  81                                       bool has_error_code, u32 error_code);
  82
  83 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  84 {
  85         return container_of(vcpu, struct vcpu_svm, vcpu);
  86 }
  87
  88 static inline bool is_nested(struct vcpu_svm *svm)
  89 {
  90         return svm->nested_vmcb;
  91 }
  92
  93 static unsigned long iopm_base;
  94
  95 struct kvm_ldttss_desc {
  96         u16 limit0;
  97         u16 base0;
  98         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  99         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
 100         u32 base3;
 101         u32 zero1;
 102 } __attribute__((packed));
 103
 104 struct svm_cpu_data {
 105         int cpu;
 106
 107         u64 asid_generation;
 108         u32 max_asid;
 109         u32 next_asid;
 110         struct kvm_ldttss_desc *tss_desc;
 111
 112         struct page *save_area;
 113 };
 114
 115 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 116 static uint32_t svm_features;
 117
 118 struct svm_init_data {
 119         int cpu;
 120         int r;
 121 };
 122
 123 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 124
 125 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 126 #define MSRS_RANGE_SIZE 2048
 127 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 128
 129 #define MAX_INST_SIZE 15
 130
 131 static inline u32 svm_has(u32 feat)
 132 {
 133         return svm_features & feat;
 134 }
 135
 136 static inline void clgi(void)
 137 {
 138         asm volatile (__ex(SVM_CLGI));
 139 }
 140
 141 static inline void stgi(void)
 142 {
 143         asm volatile (__ex(SVM_STGI));
 144 }
 145
 146 static inline void invlpga(unsigned long addr, u32 asid)
 147 {
 148         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 149 }
 150
 151 static inline unsigned long kvm_read_cr2(void)
 152 {
 153         unsigned long cr2;
 154
 155         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 156         return cr2;
 157 }
 158
 159 static inline void kvm_write_cr2(unsigned long val)
 160 {
 161         asm volatile ("mov %0, %%cr2" :: "r" (val));
 162 }
 163
 164 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 165 {
 166         to_svm(vcpu)->asid_generation--;
 167 }
 168
 169 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 170 {
 171         force_new_asid(vcpu);
 172 }
 173
 174 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 175 {
 176         if (!npt_enabled && !(efer & EFER_LMA))
 177                 efer &= ~EFER_LME;
 178
 179         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 180         vcpu->arch.shadow_efer = efer;
 181 }
 182
 183 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 184                                 bool has_error_code, u32 error_code)
 185 {
 186         struct vcpu_svm *svm = to_svm(vcpu);
 187
 188         /* If we are within a nested VM we'd better #VMEXIT and let the
 189            guest handle the exception */
 190         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 191                 return;
 192
 193         svm->vmcb->control.event_inj = nr
 194                 | SVM_EVTINJ_VALID
 195                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 196                 | SVM_EVTINJ_TYPE_EXEPT;
 197         svm->vmcb->control.event_inj_err = error_code;
 198 }
 199
 200 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 201 {
 202         struct vcpu_svm *svm = to_svm(vcpu);
 203
 204         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 205 }
 206
 207 static int is_external_interrupt(u32 info)
 208 {
 209         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 210         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 211 }
 212
 213 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 214 {
 215         struct vcpu_svm *svm = to_svm(vcpu);
 216
 217         if (!svm->next_rip) {
 218                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 219                 return;
 220         }
 221         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 222                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 223                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 224
 225         kvm_rip_write(vcpu, svm->next_rip);
 226         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 227
 228         vcpu->arch.interrupt_window_open = (svm->vcpu.arch.hflags & HF_GIF_MASK);
 229 }
 230
 231 static int has_svm(void)
 232 {
 233         const char *msg;
 234
 235         if (!cpu_has_svm(&msg)) {
 236                 printk(KERN_INFO "has_svm: %s\n", msg);
 237                 return 0;
 238         }
 239
 240         return 1;
 241 }
 242
 243 static void svm_hardware_disable(void *garbage)
 244 {
 245         cpu_svm_disable();
 246 }
 247
 248 static void svm_hardware_enable(void *garbage)
 249 {
 250
 251         struct svm_cpu_data *svm_data;
 252         uint64_t efer;
 253         struct desc_ptr gdt_descr;
 254         struct desc_struct *gdt;
 255         int me = raw_smp_processor_id();
 256
 257         if (!has_svm()) {
 258                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 259                 return;
 260         }
 261         svm_data = per_cpu(svm_data, me);
 262
 263         if (!svm_data) {
 264                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 265                        me);
 266                 return;
 267         }
 268
 269         svm_data->asid_generation = 1;
 270         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 271         svm_data->next_asid = svm_data->max_asid + 1;
 272
 273         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 274         gdt = (struct desc_struct *)gdt_descr.address;
 275         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 276
 277         rdmsrl(MSR_EFER, efer);
 278         wrmsrl(MSR_EFER, efer | EFER_SVME);
 279
 280         wrmsrl(MSR_VM_HSAVE_PA,
 281                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 282 }
 283
 284 static void svm_cpu_uninit(int cpu)
 285 {
 286         struct svm_cpu_data *svm_data
 287                 = per_cpu(svm_data, raw_smp_processor_id());
 288
 289         if (!svm_data)
 290                 return;
 291
 292         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 293         __free_page(svm_data->save_area);
 294         kfree(svm_data);
 295 }
 296
 297 static int svm_cpu_init(int cpu)
 298 {
 299         struct svm_cpu_data *svm_data;
 300         int r;
 301
 302         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 303         if (!svm_data)
 304                 return -ENOMEM;
 305         svm_data->cpu = cpu;
 306         svm_data->save_area = alloc_page(GFP_KERNEL);
 307         r = -ENOMEM;
 308         if (!svm_data->save_area)
 309                 goto err_1;
 310
 311         per_cpu(svm_data, cpu) = svm_data;
 312
 313         return 0;
 314
 315 err_1:
 316         kfree(svm_data);
 317         return r;
 318
 319 }
 320
 321 static void set_msr_interception(u32 *msrpm, unsigned msr,
 322                                  int read, int write)
 323 {
 324         int i;
 325
 326         for (i = 0; i < NUM_MSR_MAPS; i++) {
 327                 if (msr >= msrpm_ranges[i] &&
 328                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 329                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 330                                           msrpm_ranges[i]) * 2;
 331
 332                         u32 *base = msrpm + (msr_offset / 32);
 333                         u32 msr_shift = msr_offset % 32;
 334                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 335                         *base = (*base & ~(0x3 << msr_shift)) |
 336                                 (mask << msr_shift);
 337                         return;
 338                 }
 339         }
 340         BUG();
 341 }
 342
 343 static void svm_vcpu_init_msrpm(u32 *msrpm)
 344 {
 345         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 346
 347 #ifdef CONFIG_X86_64
 348         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 349         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 350         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 351         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 352         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 353         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 354 #endif
 355         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 356         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 357         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 358         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 359 }
 360
 361 static void svm_enable_lbrv(struct vcpu_svm *svm)
 362 {
 363         u32 *msrpm = svm->msrpm;
 364
 365         svm->vmcb->control.lbr_ctl = 1;
 366         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 367         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 368         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 369         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 370 }
 371
 372 static void svm_disable_lbrv(struct vcpu_svm *svm)
 373 {
 374         u32 *msrpm = svm->msrpm;
 375
 376         svm->vmcb->control.lbr_ctl = 0;
 377         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 378         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 379         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 380         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 381 }
 382
 383 static __init int svm_hardware_setup(void)
 384 {
 385         int cpu;
 386         struct page *iopm_pages;
 387         void *iopm_va;
 388         int r;
 389
 390         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 391
 392         if (!iopm_pages)
 393                 return -ENOMEM;
 394
 395         iopm_va = page_address(iopm_pages);
 396         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 397         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 398
 399         if (boot_cpu_has(X86_FEATURE_NX))
 400                 kvm_enable_efer_bits(EFER_NX);
 401
 402         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 403                 kvm_enable_efer_bits(EFER_FFXSR);
 404
 405         if (nested) {
 406                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 407                 kvm_enable_efer_bits(EFER_SVME);
 408         }
 409
 410         for_each_online_cpu(cpu) {
 411                 r = svm_cpu_init(cpu);
 412                 if (r)
 413                         goto err;
 414         }
 415
 416         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 417
 418         if (!svm_has(SVM_FEATURE_NPT))
 419                 npt_enabled = false;
 420
 421         if (npt_enabled && !npt) {
 422                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 423                 npt_enabled = false;
 424         }
 425
 426         if (npt_enabled) {
 427                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 428                 kvm_enable_tdp();
 429         } else
 430                 kvm_disable_tdp();
 431
 432         return 0;
 433
 434 err:
 435         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 436         iopm_base = 0;
 437         return r;
 438 }
 439
 440 static __exit void svm_hardware_unsetup(void)
 441 {
 442         int cpu;
 443
 444         for_each_online_cpu(cpu)
 445                 svm_cpu_uninit(cpu);
 446
 447         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 448         iopm_base = 0;
 449 }
 450
 451 static void init_seg(struct vmcb_seg *seg)
 452 {
 453         seg->selector = 0;
 454         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 455                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 456         seg->limit = 0xffff;
 457         seg->base = 0;
 458 }
 459
 460 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 461 {
 462         seg->selector = 0;
 463         seg->attrib = SVM_SELECTOR_P_MASK | type;
 464         seg->limit = 0xffff;
 465         seg->base = 0;
 466 }
 467
 468 static void init_vmcb(struct vcpu_svm *svm)
 469 {
 470         struct vmcb_control_area *control = &svm->vmcb->control;
 471         struct vmcb_save_area *save = &svm->vmcb->save;
 472
 473         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 474                                         INTERCEPT_CR3_MASK |
 475                                         INTERCEPT_CR4_MASK;
 476
 477         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 478                                         INTERCEPT_CR3_MASK |
 479                                         INTERCEPT_CR4_MASK |
 480                                         INTERCEPT_CR8_MASK;
 481
 482         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 483                                         INTERCEPT_DR1_MASK |
 484                                         INTERCEPT_DR2_MASK |
 485                                         INTERCEPT_DR3_MASK;
 486
 487         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 488                                         INTERCEPT_DR1_MASK |
 489                                         INTERCEPT_DR2_MASK |
 490                                         INTERCEPT_DR3_MASK |
 491                                         INTERCEPT_DR5_MASK |
 492                                         INTERCEPT_DR7_MASK;
 493
 494         control->intercept_exceptions = (1 << PF_VECTOR) |
 495                                         (1 << UD_VECTOR) |
 496                                         (1 << MC_VECTOR);
 497
 498
 499         control->intercept =    (1ULL << INTERCEPT_INTR) |
 500                                 (1ULL << INTERCEPT_NMI) |
 501                                 (1ULL << INTERCEPT_SMI) |
 502                                 (1ULL << INTERCEPT_CPUID) |
 503                                 (1ULL << INTERCEPT_INVD) |
 504                                 (1ULL << INTERCEPT_HLT) |
 505                                 (1ULL << INTERCEPT_INVLPG) |
 506                                 (1ULL << INTERCEPT_INVLPGA) |
 507                                 (1ULL << INTERCEPT_IOIO_PROT) |
 508                                 (1ULL << INTERCEPT_MSR_PROT) |
 509                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 510                                 (1ULL << INTERCEPT_SHUTDOWN) |
 511                                 (1ULL << INTERCEPT_VMRUN) |
 512                                 (1ULL << INTERCEPT_VMMCALL) |
 513                                 (1ULL << INTERCEPT_VMLOAD) |
 514                                 (1ULL << INTERCEPT_VMSAVE) |
 515                                 (1ULL << INTERCEPT_STGI) |
 516                                 (1ULL << INTERCEPT_CLGI) |
 517                                 (1ULL << INTERCEPT_SKINIT) |
 518                                 (1ULL << INTERCEPT_WBINVD) |
 519                                 (1ULL << INTERCEPT_MONITOR) |
 520                                 (1ULL << INTERCEPT_MWAIT);
 521
 522         control->iopm_base_pa = iopm_base;
 523         control->msrpm_base_pa = __pa(svm->msrpm);
 524         control->tsc_offset = 0;
 525         control->int_ctl = V_INTR_MASKING_MASK;
 526
 527         init_seg(&save->es);
 528         init_seg(&save->ss);
 529         init_seg(&save->ds);
 530         init_seg(&save->fs);
 531         init_seg(&save->gs);
 532
 533         save->cs.selector = 0xf000;
 534         /* Executable/Readable Code Segment */
 535         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 536                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 537         save->cs.limit = 0xffff;
 538         /*
 539          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 540          * be consistent with it.
 541          *
 542          * Replace when we have real mode working for vmx.
 543          */
 544         save->cs.base = 0xf0000;
 545
 546         save->gdtr.limit = 0xffff;
 547         save->idtr.limit = 0xffff;
 548
 549         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 550         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 551
 552         save->efer = EFER_SVME;
 553         save->dr6 = 0xffff0ff0;
 554         save->dr7 = 0x400;
 555         save->rflags = 2;
 556         save->rip = 0x0000fff0;
 557         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 558
 559         /*
 560          * cr0 val on cpu init should be 0x60000010, we enable cpu
 561          * cache by default. the orderly way is to enable cache in bios.
 562          */
 563         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 564         save->cr4 = X86_CR4_PAE;
 565         /* rdx = ?? */
 566
 567         if (npt_enabled) {
 568                 /* Setup VMCB for Nested Paging */
 569                 control->nested_ctl = 1;
 570                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 571                                         (1ULL << INTERCEPT_INVLPG));
 572                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 573                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 574                                                 INTERCEPT_CR3_MASK);
 575                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 576                                                  INTERCEPT_CR3_MASK);
 577                 save->g_pat = 0x0007040600070406ULL;
 578                 /* enable caching because the QEMU Bios doesn't enable it */
 579                 save->cr0 = X86_CR0_ET;
 580                 save->cr3 = 0;
 581                 save->cr4 = 0;
 582         }
 583         force_new_asid(&svm->vcpu);
 584
 585         svm->nested_vmcb = 0;
 586         svm->vcpu.arch.hflags = HF_GIF_MASK;
 587 }
 588
 589 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 590 {
 591         struct vcpu_svm *svm = to_svm(vcpu);
 592
 593         init_vmcb(svm);
 594
 595         if (vcpu->vcpu_id != 0) {
 596                 kvm_rip_write(vcpu, 0);
 597                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 598                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 599         }
 600         vcpu->arch.regs_avail = ~0;
 601         vcpu->arch.regs_dirty = ~0;
 602
 603         return 0;
 604 }
 605
 606 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 607 {
 608         struct vcpu_svm *svm;
 609         struct page *page;
 610         struct page *msrpm_pages;
 611         struct page *hsave_page;
 612         struct page *nested_msrpm_pages;
 613         int err;
 614
 615         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 616         if (!svm) {
 617                 err = -ENOMEM;
 618                 goto out;
 619         }
 620
 621         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 622         if (err)
 623                 goto free_svm;
 624
 625         page = alloc_page(GFP_KERNEL);
 626         if (!page) {
 627                 err = -ENOMEM;
 628                 goto uninit;
 629         }
 630
 631         err = -ENOMEM;
 632         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 633         if (!msrpm_pages)
 634                 goto uninit;
 635
 636         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 637         if (!nested_msrpm_pages)
 638                 goto uninit;
 639
 640         svm->msrpm = page_address(msrpm_pages);
 641         svm_vcpu_init_msrpm(svm->msrpm);
 642
 643         hsave_page = alloc_page(GFP_KERNEL);
 644         if (!hsave_page)
 645                 goto uninit;
 646         svm->hsave = page_address(hsave_page);
 647
 648         svm->nested_msrpm = page_address(nested_msrpm_pages);
 649
 650         svm->vmcb = page_address(page);
 651         clear_page(svm->vmcb);
 652         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 653         svm->asid_generation = 0;
 654         init_vmcb(svm);
 655
 656         fx_init(&svm->vcpu);
 657         svm->vcpu.fpu_active = 1;
 658         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 659         if (svm->vcpu.vcpu_id == 0)
 660                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 661
 662         return &svm->vcpu;
 663
 664 uninit:
 665         kvm_vcpu_uninit(&svm->vcpu);
 666 free_svm:
 667         kmem_cache_free(kvm_vcpu_cache, svm);
 668 out:
 669         return ERR_PTR(err);
 670 }
 671
 672 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 673 {
 674         struct vcpu_svm *svm = to_svm(vcpu);
 675
 676         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 677         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 678         __free_page(virt_to_page(svm->hsave));
 679         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 680         kvm_vcpu_uninit(vcpu);
 681         kmem_cache_free(kvm_vcpu_cache, svm);
 682 }
 683
 684 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 685 {
 686         struct vcpu_svm *svm = to_svm(vcpu);
 687         int i;
 688
 689         if (unlikely(cpu != vcpu->cpu)) {
 690                 u64 tsc_this, delta;
 691
 692                 /*
 693                  * Make sure that the guest sees a monotonically
 694                  * increasing TSC.
 695                  */
 696                 rdtscll(tsc_this);
 697                 delta = vcpu->arch.host_tsc - tsc_this;
 698                 svm->vmcb->control.tsc_offset += delta;
 699                 vcpu->cpu = cpu;
 700                 kvm_migrate_timers(vcpu);
 701         }
 702
 703         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 704                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 705 }
 706
 707 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 708 {
 709         struct vcpu_svm *svm = to_svm(vcpu);
 710         int i;
 711
 712         ++vcpu->stat.host_state_reload;
 713         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 714                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 715
 716         rdtscll(vcpu->arch.host_tsc);
 717 }
 718
 719 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 720 {
 721         return to_svm(vcpu)->vmcb->save.rflags;
 722 }
 723
 724 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 725 {
 726         to_svm(vcpu)->vmcb->save.rflags = rflags;
 727 }
 728
 729 static void svm_set_vintr(struct vcpu_svm *svm)
 730 {
 731         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 732 }
 733
 734 static void svm_clear_vintr(struct vcpu_svm *svm)
 735 {
 736         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 737 }
 738
 739 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 740 {
 741         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 742
 743         switch (seg) {
 744         case VCPU_SREG_CS: return &save->cs;
 745         case VCPU_SREG_DS: return &save->ds;
 746         case VCPU_SREG_ES: return &save->es;
 747         case VCPU_SREG_FS: return &save->fs;
 748         case VCPU_SREG_GS: return &save->gs;
 749         case VCPU_SREG_SS: return &save->ss;
 750         case VCPU_SREG_TR: return &save->tr;
 751         case VCPU_SREG_LDTR: return &save->ldtr;
 752         }
 753         BUG();
 754         return NULL;
 755 }
 756
 757 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 758 {
 759         struct vmcb_seg *s = svm_seg(vcpu, seg);
 760
 761         return s->base;
 762 }
 763
 764 static void svm_get_segment(struct kvm_vcpu *vcpu,
 765                             struct kvm_segment *var, int seg)
 766 {
 767         struct vmcb_seg *s = svm_seg(vcpu, seg);
 768
 769         var->base = s->base;
 770         var->limit = s->limit;
 771         var->selector = s->selector;
 772         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 773         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 774         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 775         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 776         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 777         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 778         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 779         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 780
 781         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 782          * for cross vendor migration purposes by "not present"
 783          */
 784         var->unusable = !var->present || (var->type == 0);
 785
 786         switch (seg) {
 787         case VCPU_SREG_CS:
 788                 /*
 789                  * SVM always stores 0 for the 'G' bit in the CS selector in
 790                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 791                  * Intel's VMENTRY has a check on the 'G' bit.
 792                  */
 793                 var->g = s->limit > 0xfffff;
 794                 break;
 795         case VCPU_SREG_TR:
 796                 /*
 797                  * Work around a bug where the busy flag in the tr selector
 798                  * isn't exposed
 799                  */
 800                 var->type |= 0x2;
 801                 break;
 802         case VCPU_SREG_DS:
 803         case VCPU_SREG_ES:
 804         case VCPU_SREG_FS:
 805         case VCPU_SREG_GS:
 806                 /*
 807                  * The accessed bit must always be set in the segment
 808                  * descriptor cache, although it can be cleared in the
 809                  * descriptor, the cached bit always remains at 1. Since
 810                  * Intel has a check on this, set it here to support
 811                  * cross-vendor migration.
 812                  */
 813                 if (!var->unusable)
 814                         var->type |= 0x1;
 815                 break;
 816         }
 817 }
 818
 819 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 820 {
 821         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 822
 823         return save->cpl;
 824 }
 825
 826 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 827 {
 828         struct vcpu_svm *svm = to_svm(vcpu);
 829
 830         dt->limit = svm->vmcb->save.idtr.limit;
 831         dt->base = svm->vmcb->save.idtr.base;
 832 }
 833
 834 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 835 {
 836         struct vcpu_svm *svm = to_svm(vcpu);
 837
 838         svm->vmcb->save.idtr.limit = dt->limit;
 839         svm->vmcb->save.idtr.base = dt->base ;
 840 }
 841
 842 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 843 {
 844         struct vcpu_svm *svm = to_svm(vcpu);
 845
 846         dt->limit = svm->vmcb->save.gdtr.limit;
 847         dt->base = svm->vmcb->save.gdtr.base;
 848 }
 849
 850 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 851 {
 852         struct vcpu_svm *svm = to_svm(vcpu);
 853
 854         svm->vmcb->save.gdtr.limit = dt->limit;
 855         svm->vmcb->save.gdtr.base = dt->base ;
 856 }
 857
 858 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 859 {
 860 }
 861
 862 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 863 {
 864         struct vcpu_svm *svm = to_svm(vcpu);
 865
 866 #ifdef CONFIG_X86_64
 867         if (vcpu->arch.shadow_efer & EFER_LME) {
 868                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 869                         vcpu->arch.shadow_efer |= EFER_LMA;
 870                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 871                 }
 872
 873                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 874                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 875                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 876                 }
 877         }
 878 #endif
 879         if (npt_enabled)
 880                 goto set;
 881
 882         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 883                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 884                 vcpu->fpu_active = 1;
 885         }
 886
 887         vcpu->arch.cr0 = cr0;
 888         cr0 |= X86_CR0_PG | X86_CR0_WP;
 889         if (!vcpu->fpu_active) {
 890                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 891                 cr0 |= X86_CR0_TS;
 892         }
 893 set:
 894         /*
 895          * re-enable caching here because the QEMU bios
 896          * does not do it - this results in some delay at
 897          * reboot
 898          */
 899         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 900         svm->vmcb->save.cr0 = cr0;
 901 }
 902
 903 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 904 {
 905         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 906         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 907
 908         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 909                 force_new_asid(vcpu);
 910
 911         vcpu->arch.cr4 = cr4;
 912         if (!npt_enabled)
 913                 cr4 |= X86_CR4_PAE;
 914         cr4 |= host_cr4_mce;
 915         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 916 }
 917
 918 static void svm_set_segment(struct kvm_vcpu *vcpu,
 919                             struct kvm_segment *var, int seg)
 920 {
 921         struct vcpu_svm *svm = to_svm(vcpu);
 922         struct vmcb_seg *s = svm_seg(vcpu, seg);
 923
 924         s->base = var->base;
 925         s->limit = var->limit;
 926         s->selector = var->selector;
 927         if (var->unusable)
 928                 s->attrib = 0;
 929         else {
 930                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 931                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 932                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 933                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 934                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 935                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 936                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 937                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 938         }
 939         if (seg == VCPU_SREG_CS)
 940                 svm->vmcb->save.cpl
 941                         = (svm->vmcb->save.cs.attrib
 942                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 943
 944 }
 945
 946 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 947 {
 948         int old_debug = vcpu->guest_debug;
 949         struct vcpu_svm *svm = to_svm(vcpu);
 950
 951         vcpu->guest_debug = dbg->control;
 952
 953         svm->vmcb->control.intercept_exceptions &=
 954                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 955         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 956                 if (vcpu->guest_debug &
 957                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 958                         svm->vmcb->control.intercept_exceptions |=
 959                                 1 << DB_VECTOR;
 960                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 961                         svm->vmcb->control.intercept_exceptions |=
 962                                 1 << BP_VECTOR;
 963         } else
 964                 vcpu->guest_debug = 0;
 965
 966         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
 967                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
 968         else
 969                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
 970
 971         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
 972                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
 973         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
 974                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 975
 976         return 0;
 977 }
 978
 979 static int svm_get_irq(struct kvm_vcpu *vcpu)
 980 {
 981         struct vcpu_svm *svm = to_svm(vcpu);
 982         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 983
 984         if (is_external_interrupt(exit_int_info))
 985                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 986         return -1;
 987 }
 988
 989 static void load_host_msrs(struct kvm_vcpu *vcpu)
 990 {
 991 #ifdef CONFIG_X86_64
 992         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 993 #endif
 994 }
 995
 996 static void save_host_msrs(struct kvm_vcpu *vcpu)
 997 {
 998 #ifdef CONFIG_X86_64
 999         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1000 #endif
1001 }
1002
1003 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1004 {
1005         if (svm_data->next_asid > svm_data->max_asid) {
1006                 ++svm_data->asid_generation;
1007                 svm_data->next_asid = 1;
1008                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1009         }
1010
1011         svm->vcpu.cpu = svm_data->cpu;
1012         svm->asid_generation = svm_data->asid_generation;
1013         svm->vmcb->control.asid = svm_data->next_asid++;
1014 }
1015
1016 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1017 {
1018         struct vcpu_svm *svm = to_svm(vcpu);
1019         unsigned long val;
1020
1021         switch (dr) {
1022         case 0 ... 3:
1023                 val = vcpu->arch.db[dr];
1024                 break;
1025         case 6:
1026                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027                         val = vcpu->arch.dr6;
1028                 else
1029                         val = svm->vmcb->save.dr6;
1030                 break;
1031         case 7:
1032                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1033                         val = vcpu->arch.dr7;
1034                 else
1035                         val = svm->vmcb->save.dr7;
1036                 break;
1037         default:
1038                 val = 0;
1039         }
1040
1041         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1042         return val;
1043 }
1044
1045 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1046                        int *exception)
1047 {
1048         struct vcpu_svm *svm = to_svm(vcpu);
1049
1050         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1051
1052         *exception = 0;
1053
1054         switch (dr) {
1055         case 0 ... 3:
1056                 vcpu->arch.db[dr] = value;
1057                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1058                         vcpu->arch.eff_db[dr] = value;
1059                 return;
1060         case 4 ... 5:
1061                 if (vcpu->arch.cr4 & X86_CR4_DE)
1062                         *exception = UD_VECTOR;
1063                 return;
1064         case 6:
1065                 if (value & 0xffffffff00000000ULL) {
1066                         *exception = GP_VECTOR;
1067                         return;
1068                 }
1069                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1070                 return;
1071         case 7:
1072                 if (value & 0xffffffff00000000ULL) {
1073                         *exception = GP_VECTOR;
1074                         return;
1075                 }
1076                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1077                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1078                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1079                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1080                 }
1081                 return;
1082         default:
1083                 /* FIXME: Possible case? */
1084                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1085                        __func__, dr);
1086                 *exception = UD_VECTOR;
1087                 return;
1088         }
1089 }
1090
1091 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1092 {
1093         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1094         struct kvm *kvm = svm->vcpu.kvm;
1095         u64 fault_address;
1096         u32 error_code;
1097         bool event_injection = false;
1098
1099         if (!irqchip_in_kernel(kvm) &&
1100             is_external_interrupt(exit_int_info)) {
1101                 event_injection = true;
1102                 kvm_push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1103         }
1104
1105         fault_address  = svm->vmcb->control.exit_info_2;
1106         error_code = svm->vmcb->control.exit_info_1;
1107
1108         if (!npt_enabled)
1109                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1110                             (u32)fault_address, (u32)(fault_address >> 32),
1111                             handler);
1112         else
1113                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1114                             (u32)fault_address, (u32)(fault_address >> 32),
1115                             handler);
1116         /*
1117          * FIXME: Tis shouldn't be necessary here, but there is a flush
1118          * missing in the MMU code. Until we find this bug, flush the
1119          * complete TLB here on an NPF
1120          */
1121         if (npt_enabled)
1122                 svm_flush_tlb(&svm->vcpu);
1123
1124         if (!npt_enabled && event_injection)
1125                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1126         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1127 }
1128
1129 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1130 {
1131         if (!(svm->vcpu.guest_debug &
1132               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
1133                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1134                 return 1;
1135         }
1136         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1137         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1138         kvm_run->debug.arch.exception = DB_VECTOR;
1139         return 0;
1140 }
1141
1142 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1143 {
1144         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1145         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1146         kvm_run->debug.arch.exception = BP_VECTOR;
1147         return 0;
1148 }
1149
1150 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1151 {
1152         int er;
1153
1154         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1155         if (er != EMULATE_DONE)
1156                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1157         return 1;
1158 }
1159
1160 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1161 {
1162         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1163         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1164                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1165         svm->vcpu.fpu_active = 1;
1166
1167         return 1;
1168 }
1169
1170 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172         /*
1173          * On an #MC intercept the MCE handler is not called automatically in
1174          * the host. So do it by hand here.
1175          */
1176         asm volatile (
1177                 "int $0x12\n");
1178         /* not sure if we ever come back to this point */
1179
1180         return 1;
1181 }
1182
1183 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1184 {
1185         /*
1186          * VMCB is undefined after a SHUTDOWN intercept
1187          * so reinitialize it.
1188          */
1189         clear_page(svm->vmcb);
1190         init_vmcb(svm);
1191
1192         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1193         return 0;
1194 }
1195
1196 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1197 {
1198         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1199         int size, in, string;
1200         unsigned port;
1201
1202         ++svm->vcpu.stat.io_exits;
1203
1204         svm->next_rip = svm->vmcb->control.exit_info_2;
1205
1206         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1207
1208         if (string) {
1209                 if (emulate_instruction(&svm->vcpu,
1210                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1211                         return 0;
1212                 return 1;
1213         }
1214
1215         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1216         port = io_info >> 16;
1217         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1218
1219         skip_emulated_instruction(&svm->vcpu);
1220         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1221 }
1222
1223 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1224 {
1225         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1226         return 1;
1227 }
1228
1229 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1230 {
1231         ++svm->vcpu.stat.irq_exits;
1232         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1233         return 1;
1234 }
1235
1236 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1237 {
1238         return 1;
1239 }
1240
1241 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1242 {
1243         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1244         skip_emulated_instruction(&svm->vcpu);
1245         return kvm_emulate_halt(&svm->vcpu);
1246 }
1247
1248 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1249 {
1250         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1251         skip_emulated_instruction(&svm->vcpu);
1252         kvm_emulate_hypercall(&svm->vcpu);
1253         return 1;
1254 }
1255
1256 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1257 {
1258         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1259             || !is_paging(&svm->vcpu)) {
1260                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1261                 return 1;
1262         }
1263
1264         if (svm->vmcb->save.cpl) {
1265                 kvm_inject_gp(&svm->vcpu, 0);
1266                 return 1;
1267         }
1268
1269        return 0;
1270 }
1271
1272 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1273                                       bool has_error_code, u32 error_code)
1274 {
1275         if (is_nested(svm)) {
1276                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1277                 svm->vmcb->control.exit_code_hi = 0;
1278                 svm->vmcb->control.exit_info_1 = error_code;
1279                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1280                 if (nested_svm_exit_handled(svm, false)) {
1281                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1282
1283                         nested_svm_vmexit(svm);
1284                         return 1;
1285                 }
1286         }
1287
1288         return 0;
1289 }
1290
1291 static inline int nested_svm_intr(struct vcpu_svm *svm)
1292 {
1293         if (is_nested(svm)) {
1294                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1295                         return 0;
1296
1297                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1298                         return 0;
1299
1300                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1301
1302                 if (nested_svm_exit_handled(svm, false)) {
1303                         nsvm_printk("VMexit -> INTR\n");
1304                         nested_svm_vmexit(svm);
1305                         return 1;
1306                 }
1307         }
1308
1309         return 0;
1310 }
1311
1312 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1313 {
1314         struct page *page;
1315
1316         down_read(&current->mm->mmap_sem);
1317         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1318         up_read(&current->mm->mmap_sem);
1319
1320         if (is_error_page(page)) {
1321                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1322                        __func__, gpa);
1323                 kvm_release_page_clean(page);
1324                 kvm_inject_gp(&svm->vcpu, 0);
1325                 return NULL;
1326         }
1327         return page;
1328 }
1329
1330 static int nested_svm_do(struct vcpu_svm *svm,
1331                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1332                          int (*handler)(struct vcpu_svm *svm,
1333                                         void *arg1,
1334                                         void *arg2,
1335                                         void *opaque))
1336 {
1337         struct page *arg1_page;
1338         struct page *arg2_page = NULL;
1339         void *arg1;
1340         void *arg2 = NULL;
1341         int retval;
1342
1343         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1344         if(arg1_page == NULL)
1345                 return 1;
1346
1347         if (arg2_gpa) {
1348                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1349                 if(arg2_page == NULL) {
1350                         kvm_release_page_clean(arg1_page);
1351                         return 1;
1352                 }
1353         }
1354
1355         arg1 = kmap_atomic(arg1_page, KM_USER0);
1356         if (arg2_gpa)
1357                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1358
1359         retval = handler(svm, arg1, arg2, opaque);
1360
1361         kunmap_atomic(arg1, KM_USER0);
1362         if (arg2_gpa)
1363                 kunmap_atomic(arg2, KM_USER1);
1364
1365         kvm_release_page_dirty(arg1_page);
1366         if (arg2_gpa)
1367                 kvm_release_page_dirty(arg2_page);
1368
1369         return retval;
1370 }
1371
1372 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1373                                         void *arg1,
1374                                         void *arg2,
1375                                         void *opaque)
1376 {
1377         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1378         bool kvm_overrides = *(bool *)opaque;
1379         u32 exit_code = svm->vmcb->control.exit_code;
1380
1381         if (kvm_overrides) {
1382                 switch (exit_code) {
1383                 case SVM_EXIT_INTR:
1384                 case SVM_EXIT_NMI:
1385                         return 0;
1386                 /* For now we are always handling NPFs when using them */
1387                 case SVM_EXIT_NPF:
1388                         if (npt_enabled)
1389                                 return 0;
1390                         break;
1391                 /* When we're shadowing, trap PFs */
1392                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1393                         if (!npt_enabled)
1394                                 return 0;
1395                         break;
1396                 default:
1397                         break;
1398                 }
1399         }
1400
1401         switch (exit_code) {
1402         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1403                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1404                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1405                         return 1;
1406                 break;
1407         }
1408         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1409                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1410                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1411                         return 1;
1412                 break;
1413         }
1414         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1415                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1416                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1417                         return 1;
1418                 break;
1419         }
1420         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1421                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1422                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1423                         return 1;
1424                 break;
1425         }
1426         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1427                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1428                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1429                         return 1;
1430                 break;
1431         }
1432         default: {
1433                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1434                 nsvm_printk("exit code: 0x%x\n", exit_code);
1435                 if (nested_vmcb->control.intercept & exit_bits)
1436                         return 1;
1437         }
1438         }
1439
1440         return 0;
1441 }
1442
1443 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1444                                        void *arg1, void *arg2,
1445                                        void *opaque)
1446 {
1447         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1448         u8 *msrpm = (u8 *)arg2;
1449         u32 t0, t1;
1450         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1451         u32 param = svm->vmcb->control.exit_info_1 & 1;
1452
1453         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1454                 return 0;
1455
1456         switch(msr) {
1457         case 0 ... 0x1fff:
1458                 t0 = (msr * 2) % 8;
1459                 t1 = msr / 8;
1460                 break;
1461         case 0xc0000000 ... 0xc0001fff:
1462                 t0 = (8192 + msr - 0xc0000000) * 2;
1463                 t1 = (t0 / 8);
1464                 t0 %= 8;
1465                 break;
1466         case 0xc0010000 ... 0xc0011fff:
1467                 t0 = (16384 + msr - 0xc0010000) * 2;
1468                 t1 = (t0 / 8);
1469                 t0 %= 8;
1470                 break;
1471         default:
1472                 return 1;
1473                 break;
1474         }
1475         if (msrpm[t1] & ((1 << param) << t0))
1476                 return 1;
1477
1478         return 0;
1479 }
1480
1481 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1482 {
1483         bool k = kvm_override;
1484
1485         switch (svm->vmcb->control.exit_code) {
1486         case SVM_EXIT_MSR:
1487                 return nested_svm_do(svm, svm->nested_vmcb,
1488                                      svm->nested_vmcb_msrpm, NULL,
1489                                      nested_svm_exit_handled_msr);
1490         default: break;
1491         }
1492
1493         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1494                              nested_svm_exit_handled_real);
1495 }
1496
1497 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1498                                   void *arg2, void *opaque)
1499 {
1500         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1501         struct vmcb *hsave = svm->hsave;
1502         u64 nested_save[] = { nested_vmcb->save.cr0,
1503                               nested_vmcb->save.cr3,
1504                               nested_vmcb->save.cr4,
1505                               nested_vmcb->save.efer,
1506                               nested_vmcb->control.intercept_cr_read,
1507                               nested_vmcb->control.intercept_cr_write,
1508                               nested_vmcb->control.intercept_dr_read,
1509                               nested_vmcb->control.intercept_dr_write,
1510                               nested_vmcb->control.intercept_exceptions,
1511                               nested_vmcb->control.intercept,
1512                               nested_vmcb->control.msrpm_base_pa,
1513                               nested_vmcb->control.iopm_base_pa,
1514                               nested_vmcb->control.tsc_offset };
1515
1516         /* Give the current vmcb to the guest */
1517         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1518         nested_vmcb->save.cr0 = nested_save[0];
1519         if (!npt_enabled)
1520                 nested_vmcb->save.cr3 = nested_save[1];
1521         nested_vmcb->save.cr4 = nested_save[2];
1522         nested_vmcb->save.efer = nested_save[3];
1523         nested_vmcb->control.intercept_cr_read = nested_save[4];
1524         nested_vmcb->control.intercept_cr_write = nested_save[5];
1525         nested_vmcb->control.intercept_dr_read = nested_save[6];
1526         nested_vmcb->control.intercept_dr_write = nested_save[7];
1527         nested_vmcb->control.intercept_exceptions = nested_save[8];
1528         nested_vmcb->control.intercept = nested_save[9];
1529         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1530         nested_vmcb->control.iopm_base_pa = nested_save[11];
1531         nested_vmcb->control.tsc_offset = nested_save[12];
1532
1533         /* We always set V_INTR_MASKING and remember the old value in hflags */
1534         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1535                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1536
1537         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1538             (nested_vmcb->control.int_vector)) {
1539                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1540                                 nested_vmcb->control.int_vector);
1541         }
1542
1543         /* Restore the original control entries */
1544         svm->vmcb->control = hsave->control;
1545
1546         /* Kill any pending exceptions */
1547         if (svm->vcpu.arch.exception.pending == true)
1548                 nsvm_printk("WARNING: Pending Exception\n");
1549         svm->vcpu.arch.exception.pending = false;
1550
1551         /* Restore selected save entries */
1552         svm->vmcb->save.es = hsave->save.es;
1553         svm->vmcb->save.cs = hsave->save.cs;
1554         svm->vmcb->save.ss = hsave->save.ss;
1555         svm->vmcb->save.ds = hsave->save.ds;
1556         svm->vmcb->save.gdtr = hsave->save.gdtr;
1557         svm->vmcb->save.idtr = hsave->save.idtr;
1558         svm->vmcb->save.rflags = hsave->save.rflags;
1559         svm_set_efer(&svm->vcpu, hsave->save.efer);
1560         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1561         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1562         if (npt_enabled) {
1563                 svm->vmcb->save.cr3 = hsave->save.cr3;
1564                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1565         } else {
1566                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1567         }
1568         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1569         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1570         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1571         svm->vmcb->save.dr7 = 0;
1572         svm->vmcb->save.cpl = 0;
1573         svm->vmcb->control.exit_int_info = 0;
1574
1575         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1576         /* Exit nested SVM mode */
1577         svm->nested_vmcb = 0;
1578
1579         return 0;
1580 }
1581
1582 static int nested_svm_vmexit(struct vcpu_svm *svm)
1583 {
1584         nsvm_printk("VMexit\n");
1585         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1586                           NULL, nested_svm_vmexit_real))
1587                 return 1;
1588
1589         kvm_mmu_reset_context(&svm->vcpu);
1590         kvm_mmu_load(&svm->vcpu);
1591
1592         return 0;
1593 }
1594
1595 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1596                                   void *arg2, void *opaque)
1597 {
1598         int i;
1599         u32 *nested_msrpm = (u32*)arg1;
1600         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1601                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1602         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1603
1604         return 0;
1605 }
1606
1607 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1608                             void *arg2, void *opaque)
1609 {
1610         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1611         struct vmcb *hsave = svm->hsave;
1612
1613         /* nested_vmcb is our indicator if nested SVM is activated */
1614         svm->nested_vmcb = svm->vmcb->save.rax;
1615
1616         /* Clear internal status */
1617         svm->vcpu.arch.exception.pending = false;
1618
1619         /* Save the old vmcb, so we don't need to pick what we save, but
1620            can restore everything when a VMEXIT occurs */
1621         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1622         /* We need to remember the original CR3 in the SPT case */
1623         if (!npt_enabled)
1624                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1625         hsave->save.cr4 = svm->vcpu.arch.cr4;
1626         hsave->save.rip = svm->next_rip;
1627
1628         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1629                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1630         else
1631                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1632
1633         /* Load the nested guest state */
1634         svm->vmcb->save.es = nested_vmcb->save.es;
1635         svm->vmcb->save.cs = nested_vmcb->save.cs;
1636         svm->vmcb->save.ss = nested_vmcb->save.ss;
1637         svm->vmcb->save.ds = nested_vmcb->save.ds;
1638         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1639         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1640         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1641         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1642         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1643         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1644         if (npt_enabled) {
1645                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1646                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1647         } else {
1648                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1649                 kvm_mmu_reset_context(&svm->vcpu);
1650         }
1651         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1652         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1653         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1654         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1655         /* In case we don't even reach vcpu_run, the fields are not updated */
1656         svm->vmcb->save.rax = nested_vmcb->save.rax;
1657         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1658         svm->vmcb->save.rip = nested_vmcb->save.rip;
1659         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1660         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1661         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1662
1663         /* We don't want a nested guest to be more powerful than the guest,
1664            so all intercepts are ORed */
1665         svm->vmcb->control.intercept_cr_read |=
1666                 nested_vmcb->control.intercept_cr_read;
1667         svm->vmcb->control.intercept_cr_write |=
1668                 nested_vmcb->control.intercept_cr_write;
1669         svm->vmcb->control.intercept_dr_read |=
1670                 nested_vmcb->control.intercept_dr_read;
1671         svm->vmcb->control.intercept_dr_write |=
1672                 nested_vmcb->control.intercept_dr_write;
1673         svm->vmcb->control.intercept_exceptions |=
1674                 nested_vmcb->control.intercept_exceptions;
1675
1676         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1677
1678         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1679
1680         force_new_asid(&svm->vcpu);
1681         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1682         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1683         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1684         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1685                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1686                                 nested_vmcb->control.int_ctl);
1687         }
1688         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1689                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1690         else
1691                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1692
1693         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1694                         nested_vmcb->control.exit_int_info,
1695                         nested_vmcb->control.int_state);
1696
1697         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1698         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1699         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1700         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1701                 nsvm_printk("Injecting Event: 0x%x\n",
1702                                 nested_vmcb->control.event_inj);
1703         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1704         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1705
1706         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1707
1708         return 0;
1709 }
1710
1711 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1712 {
1713         to_vmcb->save.fs = from_vmcb->save.fs;
1714         to_vmcb->save.gs = from_vmcb->save.gs;
1715         to_vmcb->save.tr = from_vmcb->save.tr;
1716         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1717         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1718         to_vmcb->save.star = from_vmcb->save.star;
1719         to_vmcb->save.lstar = from_vmcb->save.lstar;
1720         to_vmcb->save.cstar = from_vmcb->save.cstar;
1721         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1722         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1723         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1724         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1725
1726         return 1;
1727 }
1728
1729 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1730                              void *arg2, void *opaque)
1731 {
1732         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1733 }
1734
1735 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1736                              void *arg2, void *opaque)
1737 {
1738         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1739 }
1740
1741 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1742 {
1743         if (nested_svm_check_permissions(svm))
1744                 return 1;
1745
1746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1747         skip_emulated_instruction(&svm->vcpu);
1748
1749         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1750
1751         return 1;
1752 }
1753
1754 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1755 {
1756         if (nested_svm_check_permissions(svm))
1757                 return 1;
1758
1759         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1760         skip_emulated_instruction(&svm->vcpu);
1761
1762         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1763
1764         return 1;
1765 }
1766
1767 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1768 {
1769         nsvm_printk("VMrun\n");
1770         if (nested_svm_check_permissions(svm))
1771                 return 1;
1772
1773         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1774         skip_emulated_instruction(&svm->vcpu);
1775
1776         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1777                           NULL, nested_svm_vmrun))
1778                 return 1;
1779
1780         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1781                       NULL, nested_svm_vmrun_msrpm))
1782                 return 1;
1783
1784         return 1;
1785 }
1786
1787 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1788 {
1789         if (nested_svm_check_permissions(svm))
1790                 return 1;
1791
1792         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1793         skip_emulated_instruction(&svm->vcpu);
1794
1795         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1796
1797         return 1;
1798 }
1799
1800 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1801 {
1802         if (nested_svm_check_permissions(svm))
1803                 return 1;
1804
1805         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1806         skip_emulated_instruction(&svm->vcpu);
1807
1808         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1809
1810         /* After a CLGI no interrupts should come */
1811         svm_clear_vintr(svm);
1812         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1813
1814         return 1;
1815 }
1816
1817 static int invalid_op_interception(struct vcpu_svm *svm,
1818                                    struct kvm_run *kvm_run)
1819 {
1820         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1821         return 1;
1822 }
1823
1824 static int task_switch_interception(struct vcpu_svm *svm,
1825                                     struct kvm_run *kvm_run)
1826 {
1827         u16 tss_selector;
1828         int reason;
1829         int int_type = svm->vmcb->control.exit_int_info &
1830                 SVM_EXITINTINFO_TYPE_MASK;
1831         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1832
1833         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1834
1835         if (svm->vmcb->control.exit_info_2 &
1836             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1837                 reason = TASK_SWITCH_IRET;
1838         else if (svm->vmcb->control.exit_info_2 &
1839                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1840                 reason = TASK_SWITCH_JMP;
1841         else if (svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID)
1842                 reason = TASK_SWITCH_GATE;
1843         else
1844                 reason = TASK_SWITCH_CALL;
1845
1846
1847         if (reason != TASK_SWITCH_GATE ||
1848             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1849             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1850              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
1851                 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0,
1852                                         EMULTYPE_SKIP) != EMULATE_DONE)
1853                         return 0;
1854         }
1855
1856         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1857 }
1858
1859 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1860 {
1861         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1862         kvm_emulate_cpuid(&svm->vcpu);
1863         return 1;
1864 }
1865
1866 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1867 {
1868         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1869                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1870         return 1;
1871 }
1872
1873 static int emulate_on_interception(struct vcpu_svm *svm,
1874                                    struct kvm_run *kvm_run)
1875 {
1876         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1877                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1878         return 1;
1879 }
1880
1881 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1882 {
1883         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1884         if (irqchip_in_kernel(svm->vcpu.kvm))
1885                 return 1;
1886         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1887         return 0;
1888 }
1889
1890 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1891 {
1892         struct vcpu_svm *svm = to_svm(vcpu);
1893
1894         switch (ecx) {
1895         case MSR_IA32_TIME_STAMP_COUNTER: {
1896                 u64 tsc;
1897
1898                 rdtscll(tsc);
1899                 *data = svm->vmcb->control.tsc_offset + tsc;
1900                 break;
1901         }
1902         case MSR_K6_STAR:
1903                 *data = svm->vmcb->save.star;
1904                 break;
1905 #ifdef CONFIG_X86_64
1906         case MSR_LSTAR:
1907                 *data = svm->vmcb->save.lstar;
1908                 break;
1909         case MSR_CSTAR:
1910                 *data = svm->vmcb->save.cstar;
1911                 break;
1912         case MSR_KERNEL_GS_BASE:
1913                 *data = svm->vmcb->save.kernel_gs_base;
1914                 break;
1915         case MSR_SYSCALL_MASK:
1916                 *data = svm->vmcb->save.sfmask;
1917                 break;
1918 #endif
1919         case MSR_IA32_SYSENTER_CS:
1920                 *data = svm->vmcb->save.sysenter_cs;
1921                 break;
1922         case MSR_IA32_SYSENTER_EIP:
1923                 *data = svm->vmcb->save.sysenter_eip;
1924                 break;
1925         case MSR_IA32_SYSENTER_ESP:
1926                 *data = svm->vmcb->save.sysenter_esp;
1927                 break;
1928         /* Nobody will change the following 5 values in the VMCB so
1929            we can safely return them on rdmsr. They will always be 0
1930            until LBRV is implemented. */
1931         case MSR_IA32_DEBUGCTLMSR:
1932                 *data = svm->vmcb->save.dbgctl;
1933                 break;
1934         case MSR_IA32_LASTBRANCHFROMIP:
1935                 *data = svm->vmcb->save.br_from;
1936                 break;
1937         case MSR_IA32_LASTBRANCHTOIP:
1938                 *data = svm->vmcb->save.br_to;
1939                 break;
1940         case MSR_IA32_LASTINTFROMIP:
1941                 *data = svm->vmcb->save.last_excp_from;
1942                 break;
1943         case MSR_IA32_LASTINTTOIP:
1944                 *data = svm->vmcb->save.last_excp_to;
1945                 break;
1946         case MSR_VM_HSAVE_PA:
1947                 *data = svm->hsave_msr;
1948                 break;
1949         case MSR_VM_CR:
1950                 *data = 0;
1951                 break;
1952         case MSR_IA32_UCODE_REV:
1953                 *data = 0x01000065;
1954                 break;
1955         default:
1956                 return kvm_get_msr_common(vcpu, ecx, data);
1957         }
1958         return 0;
1959 }
1960
1961 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1962 {
1963         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1964         u64 data;
1965
1966         if (svm_get_msr(&svm->vcpu, ecx, &data))
1967                 kvm_inject_gp(&svm->vcpu, 0);
1968         else {
1969                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1970                             (u32)(data >> 32), handler);
1971
1972                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1973                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1974                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1975                 skip_emulated_instruction(&svm->vcpu);
1976         }
1977         return 1;
1978 }
1979
1980 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1981 {
1982         struct vcpu_svm *svm = to_svm(vcpu);
1983
1984         switch (ecx) {
1985         case MSR_IA32_TIME_STAMP_COUNTER: {
1986                 u64 tsc;
1987
1988                 rdtscll(tsc);
1989                 svm->vmcb->control.tsc_offset = data - tsc;
1990                 break;
1991         }
1992         case MSR_K6_STAR:
1993                 svm->vmcb->save.star = data;
1994                 break;
1995 #ifdef CONFIG_X86_64
1996         case MSR_LSTAR:
1997                 svm->vmcb->save.lstar = data;
1998                 break;
1999         case MSR_CSTAR:
2000                 svm->vmcb->save.cstar = data;
2001                 break;
2002         case MSR_KERNEL_GS_BASE:
2003                 svm->vmcb->save.kernel_gs_base = data;
2004                 break;
2005         case MSR_SYSCALL_MASK:
2006                 svm->vmcb->save.sfmask = data;
2007                 break;
2008 #endif
2009         case MSR_IA32_SYSENTER_CS:
2010                 svm->vmcb->save.sysenter_cs = data;
2011                 break;
2012         case MSR_IA32_SYSENTER_EIP:
2013                 svm->vmcb->save.sysenter_eip = data;
2014                 break;
2015         case MSR_IA32_SYSENTER_ESP:
2016                 svm->vmcb->save.sysenter_esp = data;
2017                 break;
2018         case MSR_IA32_DEBUGCTLMSR:
2019                 if (!svm_has(SVM_FEATURE_LBRV)) {
2020                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2021                                         __func__, data);
2022                         break;
2023                 }
2024                 if (data & DEBUGCTL_RESERVED_BITS)
2025                         return 1;
2026
2027                 svm->vmcb->save.dbgctl = data;
2028                 if (data & (1ULL<<0))
2029                         svm_enable_lbrv(svm);
2030                 else
2031                         svm_disable_lbrv(svm);
2032                 break;
2033         case MSR_K7_EVNTSEL0:
2034         case MSR_K7_EVNTSEL1:
2035         case MSR_K7_EVNTSEL2:
2036         case MSR_K7_EVNTSEL3:
2037         case MSR_K7_PERFCTR0:
2038         case MSR_K7_PERFCTR1:
2039         case MSR_K7_PERFCTR2:
2040         case MSR_K7_PERFCTR3:
2041                 /*
2042                  * Just discard all writes to the performance counters; this
2043                  * should keep both older linux and windows 64-bit guests
2044                  * happy
2045                  */
2046                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2047
2048                 break;
2049         case MSR_VM_HSAVE_PA:
2050                 svm->hsave_msr = data;
2051                 break;
2052         default:
2053                 return kvm_set_msr_common(vcpu, ecx, data);
2054         }
2055         return 0;
2056 }
2057
2058 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2059 {
2060         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2061         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2062                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2063
2064         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2065                     handler);
2066
2067         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2068         if (svm_set_msr(&svm->vcpu, ecx, data))
2069                 kvm_inject_gp(&svm->vcpu, 0);
2070         else
2071                 skip_emulated_instruction(&svm->vcpu);
2072         return 1;
2073 }
2074
2075 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2076 {
2077         if (svm->vmcb->control.exit_info_1)
2078                 return wrmsr_interception(svm, kvm_run);
2079         else
2080                 return rdmsr_interception(svm, kvm_run);
2081 }
2082
2083 static int interrupt_window_interception(struct vcpu_svm *svm,
2084                                    struct kvm_run *kvm_run)
2085 {
2086         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2087
2088         svm_clear_vintr(svm);
2089         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2090         /*
2091          * If the user space waits to inject interrupts, exit as soon as
2092          * possible
2093          */
2094         if (kvm_run->request_interrupt_window &&
2095             !svm->vcpu.arch.irq_summary) {
2096                 ++svm->vcpu.stat.irq_window_exits;
2097                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2098                 return 0;
2099         }
2100
2101         return 1;
2102 }
2103
2104 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2105                                       struct kvm_run *kvm_run) = {
2106         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2107         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2108         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2109         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2110         /* for now: */
2111         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2112         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2113         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2114         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2115         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2116         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2117         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2118         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2119         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2120         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2121         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2122         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2123         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2124         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2125         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2126         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2127         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2128         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2129         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2130         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2131         [SVM_EXIT_INTR]                         = intr_interception,
2132         [SVM_EXIT_NMI]                          = nmi_interception,
2133         [SVM_EXIT_SMI]                          = nop_on_interception,
2134         [SVM_EXIT_INIT]                         = nop_on_interception,
2135         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2136         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2137         [SVM_EXIT_CPUID]                        = cpuid_interception,
2138         [SVM_EXIT_INVD]                         = emulate_on_interception,
2139         [SVM_EXIT_HLT]                          = halt_interception,
2140         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2141         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2142         [SVM_EXIT_IOIO]                         = io_interception,
2143         [SVM_EXIT_MSR]                          = msr_interception,
2144         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2145         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2146         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2147         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2148         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2149         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2150         [SVM_EXIT_STGI]                         = stgi_interception,
2151         [SVM_EXIT_CLGI]                         = clgi_interception,
2152         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2153         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2154         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2155         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2156         [SVM_EXIT_NPF]                          = pf_interception,
2157 };
2158
2159 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2160 {
2161         struct vcpu_svm *svm = to_svm(vcpu);
2162         u32 exit_code = svm->vmcb->control.exit_code;
2163
2164         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2165                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2166
2167         if (is_nested(svm)) {
2168                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2169                             exit_code, svm->vmcb->control.exit_info_1,
2170                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2171                 if (nested_svm_exit_handled(svm, true)) {
2172                         nested_svm_vmexit(svm);
2173                         nsvm_printk("-> #VMEXIT\n");
2174                         return 1;
2175                 }
2176         }
2177
2178         if (npt_enabled) {
2179                 int mmu_reload = 0;
2180                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2181                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2182                         mmu_reload = 1;
2183                 }
2184                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2185                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2186                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2187                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2188                                 kvm_inject_gp(vcpu, 0);
2189                                 return 1;
2190                         }
2191                 }
2192                 if (mmu_reload) {
2193                         kvm_mmu_reset_context(vcpu);
2194                         kvm_mmu_load(vcpu);
2195                 }
2196         }
2197
2198         kvm_reput_irq(svm);
2199
2200         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2201                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2202                 kvm_run->fail_entry.hardware_entry_failure_reason
2203                         = svm->vmcb->control.exit_code;
2204                 return 0;
2205         }
2206
2207         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2208             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2209             exit_code != SVM_EXIT_NPF)
2210                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2211                        "exit_code 0x%x\n",
2212                        __func__, svm->vmcb->control.exit_int_info,
2213                        exit_code);
2214
2215         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2216             || !svm_exit_handlers[exit_code]) {
2217                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2218                 kvm_run->hw.hardware_exit_reason = exit_code;
2219                 return 0;
2220         }
2221
2222         return svm_exit_handlers[exit_code](svm, kvm_run);
2223 }
2224
2225 static void reload_tss(struct kvm_vcpu *vcpu)
2226 {
2227         int cpu = raw_smp_processor_id();
2228
2229         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2230         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2231         load_TR_desc();
2232 }
2233
2234 static void pre_svm_run(struct vcpu_svm *svm)
2235 {
2236         int cpu = raw_smp_processor_id();
2237
2238         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2239
2240         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2241         if (svm->vcpu.cpu != cpu ||
2242             svm->asid_generation != svm_data->asid_generation)
2243                 new_asid(svm, svm_data);
2244 }
2245
2246
2247 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2248 {
2249         struct vmcb_control_area *control;
2250
2251         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2252
2253         ++svm->vcpu.stat.irq_injections;
2254         control = &svm->vmcb->control;
2255         control->int_vector = irq;
2256         control->int_ctl &= ~V_INTR_PRIO_MASK;
2257         control->int_ctl |= V_IRQ_MASK |
2258                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2259 }
2260
2261 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
2262 {
2263         struct vcpu_svm *svm = to_svm(vcpu);
2264
2265         nested_svm_intr(svm);
2266
2267         svm_inject_irq(svm, irq);
2268 }
2269
2270 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
2271 {
2272         struct vcpu_svm *svm = to_svm(vcpu);
2273         struct vmcb *vmcb = svm->vmcb;
2274         int max_irr, tpr;
2275
2276         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
2277                 return;
2278
2279         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2280
2281         max_irr = kvm_lapic_find_highest_irr(vcpu);
2282         if (max_irr == -1)
2283                 return;
2284
2285         tpr = kvm_lapic_get_cr8(vcpu) << 4;
2286
2287         if (tpr >= (max_irr & 0xf0))
2288                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2289 }
2290
2291 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2292 {
2293         struct vcpu_svm *svm = to_svm(vcpu);
2294         struct vmcb *vmcb = svm->vmcb;
2295         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2296                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2297                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2298 }
2299
2300 static void svm_intr_assist(struct kvm_vcpu *vcpu)
2301 {
2302         struct vcpu_svm *svm = to_svm(vcpu);
2303         struct vmcb *vmcb = svm->vmcb;
2304         int intr_vector = -1;
2305
2306         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
2307             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
2308                 intr_vector = vmcb->control.exit_int_info &
2309                               SVM_EVTINJ_VEC_MASK;
2310                 vmcb->control.exit_int_info = 0;
2311                 svm_inject_irq(svm, intr_vector);
2312                 goto out;
2313         }
2314
2315         if (vmcb->control.int_ctl & V_IRQ_MASK)
2316                 goto out;
2317
2318         if (!kvm_cpu_has_interrupt(vcpu))
2319                 goto out;
2320
2321         if (nested_svm_intr(svm))
2322                 goto out;
2323
2324         if (!(svm->vcpu.arch.hflags & HF_GIF_MASK))
2325                 goto out;
2326
2327         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
2328             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
2329             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
2330                 /* unable to deliver irq, set pending irq */
2331                 svm_set_vintr(svm);
2332                 svm_inject_irq(svm, 0x0);
2333                 goto out;
2334         }
2335         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
2336         intr_vector = kvm_cpu_get_interrupt(vcpu);
2337         svm_inject_irq(svm, intr_vector);
2338 out:
2339         update_cr8_intercept(vcpu);
2340 }
2341
2342 static void kvm_reput_irq(struct vcpu_svm *svm)
2343 {
2344         struct vmcb_control_area *control = &svm->vmcb->control;
2345
2346         if ((control->int_ctl & V_IRQ_MASK)
2347             && !irqchip_in_kernel(svm->vcpu.kvm)) {
2348                 control->int_ctl &= ~V_IRQ_MASK;
2349                 kvm_push_irq(&svm->vcpu, control->int_vector);
2350         }
2351
2352         svm->vcpu.arch.interrupt_window_open =
2353                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2354                  (svm->vcpu.arch.hflags & HF_GIF_MASK);
2355 }
2356
2357 static void svm_do_inject_vector(struct vcpu_svm *svm)
2358 {
2359         svm_inject_irq(svm, kvm_pop_irq(&svm->vcpu));
2360 }
2361
2362 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2363                                        struct kvm_run *kvm_run)
2364 {
2365         struct vcpu_svm *svm = to_svm(vcpu);
2366         struct vmcb_control_area *control = &svm->vmcb->control;
2367
2368         if (nested_svm_intr(svm))
2369                 return;
2370
2371         svm->vcpu.arch.interrupt_window_open =
2372                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2373                  (svm->vmcb->save.rflags & X86_EFLAGS_IF) &&
2374                  (svm->vcpu.arch.hflags & HF_GIF_MASK));
2375
2376         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
2377                 /*
2378                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
2379                  */
2380                 svm_do_inject_vector(svm);
2381
2382         /*
2383          * Interrupts blocked.  Wait for unblock.
2384          */
2385         if (!svm->vcpu.arch.interrupt_window_open &&
2386             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
2387                 svm_set_vintr(svm);
2388         else
2389                 svm_clear_vintr(svm);
2390 }
2391
2392 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2393 {
2394         return 0;
2395 }
2396
2397 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2398 {
2399         force_new_asid(vcpu);
2400 }
2401
2402 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2403 {
2404 }
2405
2406 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2407 {
2408         struct vcpu_svm *svm = to_svm(vcpu);
2409
2410         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2411                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2412                 kvm_lapic_set_tpr(vcpu, cr8);
2413         }
2414 }
2415
2416 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2417 {
2418         struct vcpu_svm *svm = to_svm(vcpu);
2419         u64 cr8;
2420
2421         if (!irqchip_in_kernel(vcpu->kvm))
2422                 return;
2423
2424         cr8 = kvm_get_cr8(vcpu);
2425         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2426         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2427 }
2428
2429 #ifdef CONFIG_X86_64
2430 #define R "r"
2431 #else
2432 #define R "e"
2433 #endif
2434
2435 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2436 {
2437         struct vcpu_svm *svm = to_svm(vcpu);
2438         u16 fs_selector;
2439         u16 gs_selector;
2440         u16 ldt_selector;
2441
2442         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2443         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2444         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2445
2446         pre_svm_run(svm);
2447
2448         sync_lapic_to_cr8(vcpu);
2449
2450         save_host_msrs(vcpu);
2451         fs_selector = kvm_read_fs();
2452         gs_selector = kvm_read_gs();
2453         ldt_selector = kvm_read_ldt();
2454         svm->host_cr2 = kvm_read_cr2();
2455         if (!is_nested(svm))
2456                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2457         /* required for live migration with NPT */
2458         if (npt_enabled)
2459                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2460
2461         clgi();
2462
2463         local_irq_enable();
2464
2465         asm volatile (
2466                 "push %%"R"bp; \n\t"
2467                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2468                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2469                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2470                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2471                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2472                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2473 #ifdef CONFIG_X86_64
2474                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2475                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2476                 "mov %c[r10](%[svm]), %%r10 \n\t"
2477                 "mov %c[r11](%[svm]), %%r11 \n\t"
2478                 "mov %c[r12](%[svm]), %%r12 \n\t"
2479                 "mov %c[r13](%[svm]), %%r13 \n\t"
2480                 "mov %c[r14](%[svm]), %%r14 \n\t"
2481                 "mov %c[r15](%[svm]), %%r15 \n\t"
2482 #endif
2483
2484                 /* Enter guest mode */
2485                 "push %%"R"ax \n\t"
2486                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2487                 __ex(SVM_VMLOAD) "\n\t"
2488                 __ex(SVM_VMRUN) "\n\t"
2489                 __ex(SVM_VMSAVE) "\n\t"
2490                 "pop %%"R"ax \n\t"
2491
2492                 /* Save guest registers, load host registers */
2493                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2494                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2495                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2496                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2497                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2498                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2499 #ifdef CONFIG_X86_64
2500                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2501                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2502                 "mov %%r10, %c[r10](%[svm]) \n\t"
2503                 "mov %%r11, %c[r11](%[svm]) \n\t"
2504                 "mov %%r12, %c[r12](%[svm]) \n\t"
2505                 "mov %%r13, %c[r13](%[svm]) \n\t"
2506                 "mov %%r14, %c[r14](%[svm]) \n\t"
2507                 "mov %%r15, %c[r15](%[svm]) \n\t"
2508 #endif
2509                 "pop %%"R"bp"
2510                 :
2511                 : [svm]"a"(svm),
2512                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2513                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2514                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2515                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2516                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2517                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2518                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2519 #ifdef CONFIG_X86_64
2520                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2521                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2522                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2523                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2524                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2525                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2526                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2527                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2528 #endif
2529                 : "cc", "memory"
2530                 , R"bx", R"cx", R"dx", R"si", R"di"
2531 #ifdef CONFIG_X86_64
2532                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2533 #endif
2534                 );
2535
2536         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2537         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2538         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2539         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2540
2541         kvm_write_cr2(svm->host_cr2);
2542
2543         kvm_load_fs(fs_selector);
2544         kvm_load_gs(gs_selector);
2545         kvm_load_ldt(ldt_selector);
2546         load_host_msrs(vcpu);
2547
2548         reload_tss(vcpu);
2549
2550         local_irq_disable();
2551
2552         stgi();
2553
2554         sync_cr8_to_lapic(vcpu);
2555
2556         svm->next_rip = 0;
2557 }
2558
2559 #undef R
2560
2561 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2562 {
2563         struct vcpu_svm *svm = to_svm(vcpu);
2564
2565         if (npt_enabled) {
2566                 svm->vmcb->control.nested_cr3 = root;
2567                 force_new_asid(vcpu);
2568                 return;
2569         }
2570
2571         svm->vmcb->save.cr3 = root;
2572         force_new_asid(vcpu);
2573
2574         if (vcpu->fpu_active) {
2575                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2576                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2577                 vcpu->fpu_active = 0;
2578         }
2579 }
2580
2581 static int is_disabled(void)
2582 {
2583         u64 vm_cr;
2584
2585         rdmsrl(MSR_VM_CR, vm_cr);
2586         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2587                 return 1;
2588
2589         return 0;
2590 }
2591
2592 static void
2593 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2594 {
2595         /*
2596          * Patch in the VMMCALL instruction:
2597          */
2598         hypercall[0] = 0x0f;
2599         hypercall[1] = 0x01;
2600         hypercall[2] = 0xd9;
2601 }
2602
2603 static void svm_check_processor_compat(void *rtn)
2604 {
2605         *(int *)rtn = 0;
2606 }
2607
2608 static bool svm_cpu_has_accelerated_tpr(void)
2609 {
2610         return false;
2611 }
2612
2613 static int get_npt_level(void)
2614 {
2615 #ifdef CONFIG_X86_64
2616         return PT64_ROOT_LEVEL;
2617 #else
2618         return PT32E_ROOT_LEVEL;
2619 #endif
2620 }
2621
2622 static int svm_get_mt_mask_shift(void)
2623 {
2624         return 0;
2625 }
2626
2627 static struct kvm_x86_ops svm_x86_ops = {
2628         .cpu_has_kvm_support = has_svm,
2629         .disabled_by_bios = is_disabled,
2630         .hardware_setup = svm_hardware_setup,
2631         .hardware_unsetup = svm_hardware_unsetup,
2632         .check_processor_compatibility = svm_check_processor_compat,
2633         .hardware_enable = svm_hardware_enable,
2634         .hardware_disable = svm_hardware_disable,
2635         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2636
2637         .vcpu_create = svm_create_vcpu,
2638         .vcpu_free = svm_free_vcpu,
2639         .vcpu_reset = svm_vcpu_reset,
2640
2641         .prepare_guest_switch = svm_prepare_guest_switch,
2642         .vcpu_load = svm_vcpu_load,
2643         .vcpu_put = svm_vcpu_put,
2644
2645         .set_guest_debug = svm_guest_debug,
2646         .get_msr = svm_get_msr,
2647         .set_msr = svm_set_msr,
2648         .get_segment_base = svm_get_segment_base,
2649         .get_segment = svm_get_segment,
2650         .set_segment = svm_set_segment,
2651         .get_cpl = svm_get_cpl,
2652         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2653         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2654         .set_cr0 = svm_set_cr0,
2655         .set_cr3 = svm_set_cr3,
2656         .set_cr4 = svm_set_cr4,
2657         .set_efer = svm_set_efer,
2658         .get_idt = svm_get_idt,
2659         .set_idt = svm_set_idt,
2660         .get_gdt = svm_get_gdt,
2661         .set_gdt = svm_set_gdt,
2662         .get_dr = svm_get_dr,
2663         .set_dr = svm_set_dr,
2664         .get_rflags = svm_get_rflags,
2665         .set_rflags = svm_set_rflags,
2666
2667         .tlb_flush = svm_flush_tlb,
2668
2669         .run = svm_vcpu_run,
2670         .handle_exit = handle_exit,
2671         .skip_emulated_instruction = skip_emulated_instruction,
2672         .patch_hypercall = svm_patch_hypercall,
2673         .get_irq = svm_get_irq,
2674         .set_irq = svm_set_irq,
2675         .queue_exception = svm_queue_exception,
2676         .exception_injected = svm_exception_injected,
2677         .inject_pending_irq = svm_intr_assist,
2678         .inject_pending_vectors = do_interrupt_requests,
2679         .interrupt_allowed = svm_interrupt_allowed,
2680
2681         .set_tss_addr = svm_set_tss_addr,
2682         .get_tdp_level = get_npt_level,
2683         .get_mt_mask_shift = svm_get_mt_mask_shift,
2684 };
2685
2686 static int __init svm_init(void)
2687 {
2688         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2689                               THIS_MODULE);
2690 }
2691
2692 static void __exit svm_exit(void)
2693 {
2694         kvm_exit();
2695 }
2696
2697 module_init(svm_init)
2698 module_exit(svm_exit)