git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/htirq.h>
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 /*
  47  * This lists the InfiniPath registers, in the actual chip layout.
  48  * This structure should never be directly accessed.
  49  *
  50  * The names are in InterCap form because they're taken straight from
  51  * the chip specification.  Since they're only used in this file, they
  52  * don't pollute the rest of the source.
  53 */
  54
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long DebugPort;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long ReservedMisc1;
  67         unsigned long long InterruptConfig;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long ReservedRcv[10];
 103         unsigned long long SendCtrl;
 104         unsigned long long SendPIOBufBase;
 105         unsigned long long SendPIOSize;
 106         unsigned long long SendPIOBufCnt;
 107         unsigned long long SendPIOAvailAddr;
 108         unsigned long long TxIntMemBase;
 109         unsigned long long TxIntMemSize;
 110         unsigned long long ReservedSend[9];
 111         unsigned long long SendBufferError;
 112         unsigned long long SendBufferErrorCONT1;
 113         unsigned long long SendBufferErrorCONT2;
 114         unsigned long long SendBufferErrorCONT3;
 115         unsigned long long ReservedSBE[4];
 116         unsigned long long RcvHdrAddr0;
 117         unsigned long long RcvHdrAddr1;
 118         unsigned long long RcvHdrAddr2;
 119         unsigned long long RcvHdrAddr3;
 120         unsigned long long RcvHdrAddr4;
 121         unsigned long long RcvHdrAddr5;
 122         unsigned long long RcvHdrAddr6;
 123         unsigned long long RcvHdrAddr7;
 124         unsigned long long RcvHdrAddr8;
 125         unsigned long long ReservedRHA[7];
 126         unsigned long long RcvHdrTailAddr0;
 127         unsigned long long RcvHdrTailAddr1;
 128         unsigned long long RcvHdrTailAddr2;
 129         unsigned long long RcvHdrTailAddr3;
 130         unsigned long long RcvHdrTailAddr4;
 131         unsigned long long RcvHdrTailAddr5;
 132         unsigned long long RcvHdrTailAddr6;
 133         unsigned long long RcvHdrTailAddr7;
 134         unsigned long long RcvHdrTailAddr8;
 135         unsigned long long ReservedRHTA[7];
 136         unsigned long long Sync;        /* Software only */
 137         unsigned long long Dump;        /* Software only */
 138         unsigned long long SimVer;      /* Software only */
 139         unsigned long long ReservedSW[5];
 140         unsigned long long SerdesConfig0;
 141         unsigned long long SerdesConfig1;
 142         unsigned long long SerdesStatus;
 143         unsigned long long XGXSConfig;
 144         unsigned long long ReservedSW2[4];
 145 };
 146
 147 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 148     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 149 #define IPATH_CREG_OFFSET(field) (offsetof( \
 150     struct infinipath_counters, field) / sizeof(u64))
 151
 152 static const struct ipath_kregs ipath_ht_kregs = {
 153         .kr_control = IPATH_KREG_OFFSET(Control),
 154         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 155         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 156         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 157         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 158         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 159         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 160         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 161         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 162         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 163         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 164         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 165         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 166         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 167         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 168         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 169         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 170         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 171         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 172         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 173         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 174         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 175         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 176         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 177         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 178         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 179         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 180         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 181         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 182         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 183         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 184         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 185         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 186         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 187         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 188         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 189         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 190         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 191         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 192         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 193         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 194         .kr_revision = IPATH_KREG_OFFSET(Revision),
 195         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 196         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 197         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 198         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 199         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 200         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 201         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 202         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 203         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 204         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 205         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 206         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 207         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 208         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 209         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 210         /*
 211          * These should not be used directly via ipath_read_kreg64(),
 212          * use them with ipath_read_kreg64_port(),
 213          */
 214         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 215         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 216 };
 217
 218 static const struct ipath_cregs ipath_ht_cregs = {
 219         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 220         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 221         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 222         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 223         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 224         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 225         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 226         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 227         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 228         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 229         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 230         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 231         /* calc from Reg_CounterRegBase + offset */
 232         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 233         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 234         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 235         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 236         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 237         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 238         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 239         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 240         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 241         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 242         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 243         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 244         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 245         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 246         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 247         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 248         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 249         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 250         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 251         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 252         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 253 };
 254
 255 /* kr_intstatus, kr_intclear, kr_intmask bits */
 256 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 257 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 258
 259 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 260 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 261 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 262 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 263 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 264 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 265 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 266 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 267 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 268 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 269 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 270 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 271 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 272 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 273 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 274 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 275 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 276 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 277 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 278 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 279 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 280
 281 /* kr_extstatus bits */
 282 #define INFINIPATH_EXTS_FREQSEL 0x2
 283 #define INFINIPATH_EXTS_SERDESSEL 0x4
 284 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 285 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 286
 287 /*
 288  * masks and bits that are different in different chips, or present only
 289  * in one
 290  */
 291 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 292     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 293 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 294     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 295
 296 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 297     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 298 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 299     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 300 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 301     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 302 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 303     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 304
 305 #define _IPATH_GPIO_SDA_NUM 1
 306 #define _IPATH_GPIO_SCL_NUM 0
 307
 308 #define IPATH_GPIO_SDA \
 309         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 310 #define IPATH_GPIO_SCL \
 311         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 312
 313 /* keep the code below somewhat more readonable; not used elsewhere */
 314 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 315                                 infinipath_hwe_htclnkabyte1crcerr)
 316 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 317                                 infinipath_hwe_htclnkbbyte1crcerr)
 318 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 319                                 infinipath_hwe_htclnkbbyte0crcerr)
 320 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 321                                 infinipath_hwe_htclnkbbyte1crcerr)
 322
 323 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 324                           char *msg, size_t msgl)
 325 {
 326         char bitsmsg[64];
 327         ipath_err_t crcbits = hwerrs &
 328                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 329         /* don't check if 8bit HT */
 330         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 331                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 332         /* don't check if 8bit HT */
 333         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 334                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 335         /*
 336          * we'll want to ignore link errors on link that is
 337          * not in use, if any.  For now, complain about both
 338          */
 339         if (crcbits) {
 340                 u16 ctrl0, ctrl1;
 341                 snprintf(bitsmsg, sizeof bitsmsg,
 342                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 343                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 344                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 345                                     ? "1 (B)" : "0+1 (A+B)"),
 346                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 347                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 348                             "0+1"), (unsigned long long) crcbits);
 349                 strlcat(msg, bitsmsg, msgl);
 350
 351                 /*
 352                  * print extra info for debugging.  slave/primary
 353                  * config word 4, 8 (link control 0, 1)
 354                  */
 355
 356                 if (pci_read_config_word(dd->pcidev,
 357                                          dd->ipath_ht_slave_off + 0x4,
 358                                          &ctrl0))
 359                         dev_info(&dd->pcidev->dev, "Couldn't read "
 360                                  "linkctrl0 of slave/primary "
 361                                  "config block\n");
 362                 else if (!(ctrl0 & 1 << 6))
 363                         /* not if EOC bit set */
 364                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 365                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 366                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 367                                   "");
 368                 if (pci_read_config_word(dd->pcidev,
 369                                          dd->ipath_ht_slave_off + 0x8,
 370                                          &ctrl1))
 371                         dev_info(&dd->pcidev->dev, "Couldn't read "
 372                                  "linkctrl1 of slave/primary "
 373                                  "config block\n");
 374                 else if (!(ctrl1 & 1 << 6))
 375                         /* not if EOC bit set */
 376                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 377                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 378                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 379                                   "");
 380
 381                 /* disable until driver reloaded */
 382                 dd->ipath_hwerrmask &= ~crcbits;
 383                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 384                                  dd->ipath_hwerrmask);
 385                 ipath_dbg("HT crc errs: %s\n", msg);
 386         } else
 387                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 388                           "not in use\n", (unsigned long long)
 389                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 390                                      _IPATH_HTLINK1_CRCBITS)));
 391 }
 392
 393 /* 6110 specific hardware errors... */
 394 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 395         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 396         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 397         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 398         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 399         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 400         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 401         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 402         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 403 };
 404
 405 /**
 406  * ipath_ht_handle_hwerrors - display hardware errors.
 407  * @dd: the infinipath device
 408  * @msg: the output buffer
 409  * @msgl: the size of the output buffer
 410  *
 411  * Use same msg buffer as regular errors to avoid excessive stack
 412  * use.  Most hardware errors are catastrophic, but for right now,
 413  * we'll print them and continue.  We reuse the same message buffer as
 414  * ipath_handle_errors() to avoid excessive stack usage.
 415  */
 416 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 417                                      size_t msgl)
 418 {
 419         ipath_err_t hwerrs;
 420         u32 bits, ctrl;
 421         int isfatal = 0;
 422         char bitsmsg[64];
 423
 424         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 425
 426         if (!hwerrs) {
 427                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 428                 /*
 429                  * better than printing cofusing messages
 430                  * This seems to be related to clearing the crc error, or
 431                  * the pll error during init.
 432                  */
 433                 goto bail;
 434         } else if (hwerrs == -1LL) {
 435                 ipath_dev_err(dd, "Read of hardware error status failed "
 436                               "(all bits set); ignoring\n");
 437                 goto bail;
 438         }
 439         ipath_stats.sps_hwerrs++;
 440
 441         /* Always clear the error status register, except MEMBISTFAIL,
 442          * regardless of whether we continue or stop using the chip.
 443          * We want that set so we know it failed, even across driver reload.
 444          * We'll still ignore it in the hwerrmask.  We do this partly for
 445          * diagnostics, but also for support */
 446         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 447                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 448
 449         hwerrs &= dd->ipath_hwerrmask;
 450
 451         /*
 452          * make sure we get this much out, unless told to be quiet,
 453          * or it's occurred within the last 5 seconds
 454          */
 455         if ((hwerrs & ~(dd->ipath_lasthwerror |
 456                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 457                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 458                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 459             (ipath_debug & __IPATH_VERBDBG))
 460                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 461                          "(cleared)\n", (unsigned long long) hwerrs);
 462         dd->ipath_lasthwerror |= hwerrs;
 463
 464         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 465                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 466                               "%llx set\n", (unsigned long long)
 467                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 468
 469         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 470         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 471                 /*
 472                  * parity errors in send memory are recoverable,
 473                  * just cancel the send (if indicated in * sendbuffererror),
 474                  * count the occurrence, unfreeze (if no other handled
 475                  * hardware error bits are set), and continue. They can
 476                  * occur if a processor speculative read is done to the PIO
 477                  * buffer while we are sending a packet, for example.
 478                  */
 479                 if (hwerrs & ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 480                                INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 481                               << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
 482                         ipath_stats.sps_txeparity++;
 483                         ipath_dbg("Recovering from TXE parity error (%llu), "
 484                                   "hwerrstatus=%llx\n",
 485                                   (unsigned long long) ipath_stats.sps_txeparity,
 486                                   (unsigned long long) hwerrs);
 487                         ipath_disarm_senderrbufs(dd);
 488                         hwerrs &= ~((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 489                                      INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 490                                     << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT);
 491                         if (!hwerrs) { /* else leave in freeze mode */
 492                                 ipath_write_kreg(dd,
 493                                                  dd->ipath_kregs->kr_control,
 494                                                  dd->ipath_control);
 495                                 return;
 496                         }
 497                 }
 498                 if (hwerrs) {
 499                         /*
 500                          * if any set that we aren't ignoring; only
 501                          * make the complaint once, in case it's stuck
 502                          * or recurring, and we get here multiple
 503                          * times.
 504                          */
 505                         if (dd->ipath_flags & IPATH_INITTED) {
 506                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 507                                               "mode), no longer usable, SN %.16s\n",
 508                                                   dd->ipath_serial);
 509                                 isfatal = 1;
 510                         }
 511                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 512                         /* mark as having had error */
 513                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 514                         /*
 515                          * mark as not usable, at a minimum until driver
 516                          * is reloaded, probably until reboot, since no
 517                          * other reset is possible.
 518                          */
 519                         dd->ipath_flags &= ~IPATH_INITTED;
 520                 } else {
 521                         ipath_dbg("Clearing freezemode on ignored hardware "
 522                                   "error\n");
 523                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 524                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 525                                          ctrl);
 526                 }
 527         }
 528
 529         *msg = '\0';
 530
 531         /*
 532          * may someday want to decode into which bits are which
 533          * functional area for parity errors, etc.
 534          */
 535         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 536                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 537                 bits = (u32) ((hwerrs >>
 538                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 539                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 540                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 541                          bits);
 542                 strlcat(msg, bitsmsg, msgl);
 543         }
 544
 545         ipath_format_hwerrors(hwerrs,
 546                               ipath_6110_hwerror_msgs,
 547                               sizeof(ipath_6110_hwerror_msgs) /
 548                               sizeof(ipath_6110_hwerror_msgs[0]),
 549                               msg, msgl);
 550
 551         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 552                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 553
 554         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 555                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 556                         msgl);
 557                 /* ignore from now on, so disable until driver reloaded */
 558                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 559                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 560                                  dd->ipath_hwerrmask);
 561         }
 562 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 563                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 564                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 565                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 566                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 567                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 568
 569         if (hwerrs & _IPATH_PLL_FAIL) {
 570                 snprintf(bitsmsg, sizeof bitsmsg,
 571                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 572                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 573                 strlcat(msg, bitsmsg, msgl);
 574                 /* ignore from now on, so disable until driver reloaded */
 575                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 576                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 577                                  dd->ipath_hwerrmask);
 578         }
 579
 580         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 581                 /*
 582                  * If it occurs, it is left masked since the eternal
 583                  * interface is unused
 584                  */
 585                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 586                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 587                                  dd->ipath_hwerrmask);
 588         }
 589
 590         ipath_dev_err(dd, "%s hardware error\n", msg);
 591         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 592                 /*
 593                  * for status file; if no trailing brace is copied,
 594                  * we'll know it was truncated.
 595                  */
 596                 snprintf(dd->ipath_freezemsg,
 597                          dd->ipath_freezelen, "{%s}", msg);
 598
 599 bail:;
 600 }
 601
 602 /**
 603  * ipath_ht_boardname - fill in the board name
 604  * @dd: the infinipath device
 605  * @name: the output buffer
 606  * @namelen: the size of the output buffer
 607  *
 608  * fill in the board name, based on the board revision register
 609  */
 610 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 611                               size_t namelen)
 612 {
 613         char *n = NULL;
 614         u8 boardrev = dd->ipath_boardrev;
 615         int ret;
 616
 617         switch (boardrev) {
 618         case 4:         /* Ponderosa is one of the bringup boards */
 619                 n = "Ponderosa";
 620                 break;
 621         case 5:
 622                 /*
 623                  * original production board; two production levels, with
 624                  * different serial number ranges.   See ipath_ht_early_init() for
 625                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 626                  */
 627                 n = "InfiniPath_QHT7040";
 628                 break;
 629         case 6:
 630                 n = "OEM_Board_3";
 631                 break;
 632         case 7:
 633                 /* small form factor production board */
 634                 n = "InfiniPath_QHT7140";
 635                 break;
 636         case 8:
 637                 n = "LS/X-1";
 638                 break;
 639         case 9:         /* Comstock bringup test board */
 640                 n = "Comstock";
 641                 break;
 642         case 10:
 643                 n = "OEM_Board_2";
 644                 break;
 645         case 11:
 646                 n = "InfiniPath_HT-470"; /* obsoleted */
 647                 break;
 648         case 12:
 649                 n = "OEM_Board_4";
 650                 break;
 651         default:                /* don't know, just print the number */
 652                 ipath_dev_err(dd, "Don't yet know about board "
 653                               "with ID %u\n", boardrev);
 654                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 655                          boardrev);
 656                 break;
 657         }
 658         if (n)
 659                 snprintf(name, namelen, "%s", n);
 660
 661         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
 662                 /*
 663                  * This version of the driver only supports Rev 3.2 and 3.3
 664                  */
 665                 ipath_dev_err(dd,
 666                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 667                               dd->ipath_majrev, dd->ipath_minrev);
 668                 ret = 1;
 669                 goto bail;
 670         }
 671         /*
 672          * pkt/word counters are 32 bit, and therefore wrap fast enough
 673          * that we snapshot them from a timer, and maintain 64 bit shadow
 674          * copies
 675          */
 676         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 677         if (dd->ipath_htspeed != 800)
 678                 ipath_dev_err(dd,
 679                               "Incorrectly configured for HT @ %uMHz\n",
 680                               dd->ipath_htspeed);
 681         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 682             dd->ipath_boardrev == 6)
 683                 dd->ipath_flags |= IPATH_GPIO_INTR;
 684         else
 685                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 686         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 687                 u64 val;
 688                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 689                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 690                         /*
 691                          * hardware disabled
 692                          *
 693                          * This means that the chip is hardware disabled,
 694                          * and will not be able to bring up the link,
 695                          * in any case.  We special case this and abort
 696                          * early, to avoid later messages.  We also set
 697                          * the DISABLED status bit
 698                          */
 699                         ipath_dbg("Unit %u is hardware-disabled\n",
 700                                   dd->ipath_unit);
 701                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 702                         /* this value is handled differently */
 703                         ret = 2;
 704                         goto bail;
 705                 }
 706         }
 707         ret = 0;
 708
 709 bail:
 710         return ret;
 711 }
 712
 713 static void ipath_check_htlink(struct ipath_devdata *dd)
 714 {
 715         u8 linkerr, link_off, i;
 716
 717         for (i = 0; i < 2; i++) {
 718                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 719                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 720                         dev_info(&dd->pcidev->dev, "Couldn't read "
 721                                  "linkerror%d of HT slave/primary block\n",
 722                                  i);
 723                 else if (linkerr & 0xf0) {
 724                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 725                                    "clearing\n", linkerr >> 4, i);
 726                         /*
 727                          * writing the linkerr bits that are set should
 728                          * clear them
 729                          */
 730                         if (pci_write_config_byte(dd->pcidev, link_off,
 731                                                   linkerr))
 732                                 ipath_dbg("Failed write to clear HT "
 733                                           "linkerror%d\n", i);
 734                         if (pci_read_config_byte(dd->pcidev, link_off,
 735                                                  &linkerr))
 736                                 dev_info(&dd->pcidev->dev,
 737                                          "Couldn't reread linkerror%d of "
 738                                          "HT slave/primary block\n", i);
 739                         else if (linkerr & 0xf0)
 740                                 dev_info(&dd->pcidev->dev,
 741                                          "HT linkerror%d bits 0x%x "
 742                                          "couldn't be cleared\n",
 743                                          i, linkerr >> 4);
 744                 }
 745         }
 746 }
 747
 748 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 749 {
 750         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 751         return 0;
 752 }
 753
 754 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 755 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 756
 757 /*
 758  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 759  * errors.  We only bother to do this at load time, because it's OK if
 760  * it happened before we were loaded (first time after boot/reset),
 761  * but any time after that, it's fatal anyway.  Also need to not check
 762  * for for upper byte errors if we are in 8 bit mode, so figure out
 763  * our width.  For now, at least, also complain if it's 8 bit.
 764  */
 765 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 766                              int pos, u8 cap_type)
 767 {
 768         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 769         u16 linkctrl = 0;
 770         int i;
 771
 772         dd->ipath_ht_slave_off = pos;
 773         /* command word, master_host bit */
 774         /* master host || slave */
 775         if ((cap_type >> 2) & 1)
 776                 link_a_b_off = 4;
 777         else
 778                 link_a_b_off = 0;
 779         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 780                    link_a_b_off ? 1 : 0,
 781                    link_a_b_off ? 'B' : 'A');
 782
 783         link_a_b_off += pos;
 784
 785         /*
 786          * check both link control registers; clear both HT CRC sets if
 787          * necessary.
 788          */
 789         for (i = 0; i < 2; i++) {
 790                 link_off = pos + i * 4 + 0x4;
 791                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 792                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 793                                       "register\n", i);
 794                 else if (linkctrl & (0xf << 8)) {
 795                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 796                                    "bits %x\n", i, linkctrl & (0xf << 8));
 797                         /*
 798                          * now write them back to clear the error.
 799                          */
 800                         pci_write_config_byte(pdev, link_off,
 801                                               linkctrl & (0xf << 8));
 802                 }
 803         }
 804
 805         /*
 806          * As with HT CRC bits, same for protocol errors that might occur
 807          * during boot.
 808          */
 809         for (i = 0; i < 2; i++) {
 810                 link_off = pos + i * 4 + 0xd;
 811                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 812                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 813                                  "of HT slave/primary block\n", i);
 814                 else if (linkerr & 0xf0) {
 815                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 816                                    "clearing\n", linkerr >> 4, i);
 817                         /*
 818                          * writing the linkerr bits that are set will clear
 819                          * them
 820                          */
 821                         if (pci_write_config_byte
 822                             (pdev, link_off, linkerr))
 823                                 ipath_dbg("Failed write to clear HT "
 824                                           "linkerror%d\n", i);
 825                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 826                                 dev_info(&pdev->dev, "Couldn't reread "
 827                                          "linkerror%d of HT slave/primary "
 828                                          "block\n", i);
 829                         else if (linkerr & 0xf0)
 830                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 831                                          "0x%x couldn't be cleared\n",
 832                                          i, linkerr >> 4);
 833                 }
 834         }
 835
 836         /*
 837          * this is just for our link to the host, not devices connected
 838          * through tunnel.
 839          */
 840
 841         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 842                 ipath_dev_err(dd, "Couldn't read HT link width "
 843                               "config register\n");
 844         else {
 845                 u32 width;
 846                 switch (linkwidth & 7) {
 847                 case 5:
 848                         width = 4;
 849                         break;
 850                 case 4:
 851                         width = 2;
 852                         break;
 853                 case 3:
 854                         width = 32;
 855                         break;
 856                 case 1:
 857                         width = 16;
 858                         break;
 859                 case 0:
 860                 default:        /* if wrong, assume 8 bit */
 861                         width = 8;
 862                         break;
 863                 }
 864
 865                 dd->ipath_htwidth = width;
 866
 867                 if (linkwidth != 0x11) {
 868                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 869                                       "(%x)\n", linkwidth);
 870                         if (!(linkwidth & 0xf)) {
 871                                 ipath_dbg("Will ignore HT lane1 errors\n");
 872                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 873                         }
 874                 }
 875         }
 876
 877         /*
 878          * this is just for our link to the host, not devices connected
 879          * through tunnel.
 880          */
 881         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 882                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 883                               "config register\n");
 884         else {
 885                 u32 speed;
 886                 switch (linkwidth & 0xf) {
 887                 case 6:
 888                         speed = 1000;
 889                         break;
 890                 case 5:
 891                         speed = 800;
 892                         break;
 893                 case 4:
 894                         speed = 600;
 895                         break;
 896                 case 3:
 897                         speed = 500;
 898                         break;
 899                 case 2:
 900                         speed = 400;
 901                         break;
 902                 case 1:
 903                         speed = 300;
 904                         break;
 905                 default:
 906                         /*
 907                          * assume reserved and vendor-specific are 200...
 908                          */
 909                 case 0:
 910                         speed = 200;
 911                         break;
 912                 }
 913                 dd->ipath_htspeed = speed;
 914         }
 915 }
 916
 917 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 918 {
 919         int ret;
 920
 921         if (dd->ipath_intconfig) {
 922                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 923                                  dd->ipath_intconfig);  /* interrupt address */
 924                 ret = 0;
 925         } else {
 926                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 927                               "interrupt address\n");
 928                 ret = -EINVAL;
 929         }
 930
 931         return ret;
 932 }
 933
 934 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 935                                 struct ht_irq_msg *msg)
 936 {
 937         struct ipath_devdata *dd = pci_get_drvdata(dev);
 938         u64 prev_intconfig = dd->ipath_intconfig;
 939
 940         dd->ipath_intconfig = msg->address_lo;
 941         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 942
 943         /*
 944          * If the previous value of dd->ipath_intconfig is zero, we're
 945          * getting configured for the first time, and must not program the
 946          * intconfig register here (it will be programmed later, when the
 947          * hardware is ready).  Otherwise, we should.
 948          */
 949         if (prev_intconfig)
 950                 ipath_ht_intconfig(dd);
 951 }
 952
 953 /**
 954  * ipath_setup_ht_config - setup the interruptconfig register
 955  * @dd: the infinipath device
 956  * @pdev: the PCI device
 957  *
 958  * setup the interruptconfig register from the HT config info.
 959  * Also clear CRC errors in HT linkcontrol, if necessary.
 960  * This is done only for the real hardware.  It is done before
 961  * chip address space is initted, so can't touch infinipath registers
 962  */
 963 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 964                                  struct pci_dev *pdev)
 965 {
 966         int pos, ret;
 967
 968         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
 969         if (ret < 0) {
 970                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
 971                               "err %d\n", ret);
 972                 goto bail;
 973         }
 974         dd->ipath_irq = ret;
 975         ret = 0;
 976
 977         /*
 978          * Handle clearing CRC errors in linkctrl register if necessary.  We
 979          * do this early, before we ever enable errors or hardware errors,
 980          * mostly to avoid causing the chip to enter freeze mode.
 981          */
 982         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
 983         if (!pos) {
 984                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 985                               "capability; no interrupts\n");
 986                 ret = -ENODEV;
 987                 goto bail;
 988         }
 989         do {
 990                 u8 cap_type;
 991
 992                 /* the HT capability type byte is 3 bytes after the
 993                  * capability byte.
 994                  */
 995                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
 996                         dev_info(&pdev->dev, "Couldn't read config "
 997                                  "command @ %d\n", pos);
 998                         continue;
 999                 }
1000                 if (!(cap_type & 0xE0))
1001                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1002         } while ((pos = pci_find_next_capability(pdev, pos,
1003                                                  PCI_CAP_ID_HT)));
1004
1005 bail:
1006         return ret;
1007 }
1008
1009 /**
1010  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1011  * @dd: the infinipath device
1012  *
1013  * Called during driver unload.
1014  * This is currently a nop for the HT chip, not for all chips
1015  */
1016 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1017 {
1018 }
1019
1020 /**
1021  * ipath_setup_ht_setextled - set the state of the two external LEDs
1022  * @dd: the infinipath device
1023  * @lst: the L state
1024  * @ltst: the LT state
1025  *
1026  * Set the state of the two external LEDs, to indicate physical and
1027  * logical state of IB link.   For this chip (at least with recommended
1028  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1029  * (logical state)
1030  *
1031  * Note:  We try to match the Mellanox HCA LED behavior as best
1032  * we can.  Green indicates physical link state is OK (something is
1033  * plugged in, and we can train).
1034  * Amber indicates the link is logically up (ACTIVE).
1035  * Mellanox further blinks the amber LED to indicate data packet
1036  * activity, but we have no hardware support for that, so it would
1037  * require waking up every 10-20 msecs and checking the counters
1038  * on the chip, and then turning the LED off if appropriate.  That's
1039  * visible overhead, so not something we will do.
1040  *
1041  */
1042 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1043                                      u64 lst, u64 ltst)
1044 {
1045         u64 extctl;
1046
1047         /* the diags use the LED to indicate diag info, so we leave
1048          * the external LED alone when the diags are running */
1049         if (ipath_diag_inuse)
1050                 return;
1051
1052         /*
1053          * start by setting both LED control bits to off, then turn
1054          * on the appropriate bit(s).
1055          */
1056         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1057                 /*
1058                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1059                  * is inverted,  because it is normally used to indicate
1060                  * a hardware fault at reset, if there were errors
1061                  */
1062                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1063                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1064                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1065                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1066                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1067                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1068         }
1069         else {
1070                 extctl = dd->ipath_extctrl &
1071                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1072                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1073                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1074                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1075                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1076                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1077         }
1078         dd->ipath_extctrl = extctl;
1079         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1080 }
1081
1082 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1083 {
1084         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1085         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1086         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1087         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1088
1089         dd->ipath_i_bitsextant =
1090                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1091                 (INFINIPATH_I_RCVAVAIL_MASK <<
1092                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1093                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1094                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1095
1096         dd->ipath_e_bitsextant =
1097                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1098                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1099                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1100                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1101                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1102                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1103                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1104                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1105                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1106                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1107                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1108                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1109                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1110                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1111                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1112                 INFINIPATH_E_HARDWARE;
1113
1114         dd->ipath_hwe_bitsextant =
1115                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1116                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1117                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1118                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1119                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1120                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1121                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1122                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1123                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1124                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1125                 INFINIPATH_HWE_HTCMISCERR4 |
1126                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1127                 INFINIPATH_HWE_HTCMISCERR7 |
1128                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1129                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1130                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1131                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1132                 INFINIPATH_HWE_MEMBISTFAILED |
1133                 INFINIPATH_HWE_COREPLL_FBSLIP |
1134                 INFINIPATH_HWE_COREPLL_RFSLIP |
1135                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1136                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1137                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1138                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1139                 INFINIPATH_HWE_SERDESPLLFAILED |
1140                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1141                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1142
1143         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1144         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1145 }
1146
1147 /**
1148  * ipath_ht_init_hwerrors - enable hardware errors
1149  * @dd: the infinipath device
1150  *
1151  * now that we have finished initializing everything that might reasonably
1152  * cause a hardware error, and cleared those errors bits as they occur,
1153  * we can enable hardware errors in the mask (potentially enabling
1154  * freeze mode), and enable hardware errors as errors (along with
1155  * everything else) in errormask
1156  */
1157 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1158 {
1159         ipath_err_t val;
1160         u64 extsval;
1161
1162         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1163
1164         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1165                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1166
1167         ipath_check_htlink(dd);
1168
1169         /* barring bugs, all hwerrors become interrupts, which can */
1170         val = -1LL;
1171         /* don't look at crc lane1 if 8 bit */
1172         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1173                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1174         /* don't look at crc lane1 if 8 bit */
1175         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1176                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1177
1178         /*
1179          * disable RXDSYNCMEMPARITY because external serdes is unused,
1180          * and therefore the logic will never be used or initialized,
1181          * and uninitialized state will normally result in this error
1182          * being asserted.  Similarly for the external serdess pll
1183          * lock signal.
1184          */
1185         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1186                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1187
1188         /*
1189          * Disable MISCERR4 because of an inversion in the HT core
1190          * logic checking for errors that cause this bit to be set.
1191          * The errata can also cause the protocol error bit to be set
1192          * in the HT config space linkerror register(s).
1193          */
1194         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1195
1196         /*
1197          * PLL ignored because MDIO interface has a logic problem
1198          * for reads, on Comstock and Ponderosa.  BRINGUP
1199          */
1200         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1201                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1202         dd->ipath_hwerrmask = val;
1203 }
1204
1205 /**
1206  * ipath_ht_bringup_serdes - bring up the serdes
1207  * @dd: the infinipath device
1208  */
1209 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1210 {
1211         u64 val, config1;
1212         int ret = 0, change = 0;
1213
1214         ipath_dbg("Trying to bringup serdes\n");
1215
1216         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1217             INFINIPATH_HWE_SERDESPLLFAILED)
1218         {
1219                 ipath_dbg("At start, serdes PLL failed bit set in "
1220                           "hwerrstatus, clearing and continuing\n");
1221                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1222                                  INFINIPATH_HWE_SERDESPLLFAILED);
1223         }
1224
1225         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1226         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1227
1228         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1229                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1230                    (unsigned long long) val, (unsigned long long) config1,
1231                    (unsigned long long)
1232                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1233                    (unsigned long long)
1234                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1235
1236         /* force reset on */
1237         val |= INFINIPATH_SERDC0_RESET_PLL
1238                 /* | INFINIPATH_SERDC0_RESET_MASK */
1239                 ;
1240         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1241         udelay(15);             /* need pll reset set at least for a bit */
1242
1243         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1244                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1245                 /* set lane resets, and tx idle, during pll reset */
1246                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1247                         INFINIPATH_SERDC0_TXIDLE;
1248                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1249                            "%llx)\n", (unsigned long long) val2);
1250                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1251                                  val2);
1252                 /*
1253                  * be sure chip saw it
1254                  */
1255                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1256                 /*
1257                  * need pll reset clear at least 11 usec before lane
1258                  * resets cleared; give it a few more
1259                  */
1260                 udelay(15);
1261                 val = val2;     /* for check below */
1262         }
1263
1264         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1265                    INFINIPATH_SERDC0_RESET_MASK |
1266                    INFINIPATH_SERDC0_TXIDLE)) {
1267                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1268                          INFINIPATH_SERDC0_RESET_MASK |
1269                          INFINIPATH_SERDC0_TXIDLE);
1270                 /* clear them */
1271                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1272                                  val);
1273         }
1274
1275         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1276         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1277              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1278                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1279                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1280                 /*
1281                  * we use address 3
1282                  */
1283                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1284                 change = 1;
1285         }
1286         if (val & INFINIPATH_XGXS_RESET) {
1287                 /* normally true after boot */
1288                 val &= ~INFINIPATH_XGXS_RESET;
1289                 change = 1;
1290         }
1291         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1292              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1293                 /* need to compensate for Tx inversion in partner */
1294                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1295                          INFINIPATH_XGXS_RX_POL_SHIFT);
1296                 val |= dd->ipath_rx_pol_inv <<
1297                         INFINIPATH_XGXS_RX_POL_SHIFT;
1298                 change = 1;
1299         }
1300         if (change)
1301                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1302
1303         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1304
1305         /* clear current and de-emphasis bits */
1306         config1 &= ~0x0ffffffff00ULL;
1307         /* set current to 20ma */
1308         config1 |= 0x00000000000ULL;
1309         /* set de-emphasis to -5.68dB */
1310         config1 |= 0x0cccc000000ULL;
1311         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1312
1313         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1314                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1315                    (unsigned long long) val, (unsigned long long) config1,
1316                    (unsigned long long)
1317                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1318                    (unsigned long long)
1319                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1320
1321         if (!ipath_waitfor_mdio_cmdready(dd)) {
1322                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1323                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1324                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1325                                                 0));
1326                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1327                                            IPATH_MDIO_DATAVALID, &val))
1328                         ipath_dbg("Never got MDIO data for XGXS status "
1329                                   "read\n");
1330                 else
1331                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1332                                    "'bank' 31 %x\n", (u32) val);
1333         } else
1334                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1335
1336         return ret;             /* for now, say we always succeeded */
1337 }
1338
1339 /**
1340  * ipath_ht_quiet_serdes - set serdes to txidle
1341  * @dd: the infinipath device
1342  * driver is being unloaded
1343  */
1344 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1345 {
1346         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1347
1348         val |= INFINIPATH_SERDC0_TXIDLE;
1349         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1350                   (unsigned long long) val);
1351         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1352 }
1353
1354 /**
1355  * ipath_pe_put_tid - write a TID in chip
1356  * @dd: the infinipath device
1357  * @tidptr: pointer to the expected TID (in chip) to udpate
1358  * @tidtype: 0 for eager, 1 for expected
1359  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1360  *
1361  * This exists as a separate routine to allow for special locking etc.
1362  * It's used for both the full cleanup on exit, as well as the normal
1363  * setup and teardown.
1364  */
1365 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1366                              u64 __iomem *tidptr, u32 type,
1367                              unsigned long pa)
1368 {
1369         if (pa != dd->ipath_tidinvalid) {
1370                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1371                         dev_info(&dd->pcidev->dev,
1372                                  "physaddr %lx has more than "
1373                                  "40 bits, using only 40!!!\n", pa);
1374                         pa &= INFINIPATH_RT_ADDR_MASK;
1375                 }
1376                 if (type == 0)
1377                         pa |= dd->ipath_tidtemplate;
1378                 else {
1379                         /* in words (fixed, full page).  */
1380                         u64 lenvalid = PAGE_SIZE >> 2;
1381                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1382                         pa |= lenvalid | INFINIPATH_RT_VALID;
1383                 }
1384         }
1385         if (dd->ipath_kregbase)
1386                 writeq(pa, tidptr);
1387 }
1388
1389 /**
1390  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1391  * @dd: the infinipath device
1392  * @port: the port
1393  *
1394  * Used from ipath_close(), and at chip initialization.
1395  */
1396 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1397 {
1398         u64 __iomem *tidbase;
1399         int i;
1400
1401         if (!dd->ipath_kregbase)
1402                 return;
1403
1404         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1405
1406         /*
1407          * need to invalidate all of the expected TID entries for this
1408          * port, so we don't have valid entries that might somehow get
1409          * used (early in next use of this port, or through some bug)
1410          */
1411         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1412                                    dd->ipath_rcvtidbase +
1413                                    port * dd->ipath_rcvtidcnt *
1414                                    sizeof(*tidbase));
1415         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1416                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1417
1418         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1419                                    dd->ipath_rcvegrbase +
1420                                    port * dd->ipath_rcvegrcnt *
1421                                    sizeof(*tidbase));
1422
1423         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1424                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1425 }
1426
1427 /**
1428  * ipath_ht_tidtemplate - setup constants for TID updates
1429  * @dd: the infinipath device
1430  *
1431  * We setup stuff that we use a lot, to avoid calculating each time
1432  */
1433 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1434 {
1435         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1436         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1437         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1438
1439         /*
1440          * work around chip errata bug 7358, by marking invalid tids
1441          * as having max length
1442          */
1443         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1444                 INFINIPATH_RT_BUFSIZE_SHIFT;
1445 }
1446
1447 static int ipath_ht_early_init(struct ipath_devdata *dd)
1448 {
1449         u32 __iomem *piobuf;
1450         u32 pioincr, val32;
1451         int i;
1452
1453         /*
1454          * one cache line; long IB headers will spill over into received
1455          * buffer
1456          */
1457         dd->ipath_rcvhdrentsize = 16;
1458         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1459
1460         /*
1461          * For HT, we allocate a somewhat overly large eager buffer,
1462          * such that we can guarantee that we can receive the largest
1463          * packet that we can send out.  To truly support a 4KB MTU,
1464          * we need to bump this to a large value.  To date, other than
1465          * testing, we have never encountered an HCA that can really
1466          * send 4KB MTU packets, so we do not handle that (we'll get
1467          * errors interrupts if we ever see one).
1468          */
1469         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1470
1471         /*
1472          * the min() check here is currently a nop, but it may not
1473          * always be, depending on just how we do ipath_rcvegrbufsize
1474          */
1475         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1476                                  dd->ipath_rcvegrbufsize);
1477         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1478         ipath_ht_tidtemplate(dd);
1479
1480         /*
1481          * zero all the TID entries at startup.  We do this for sanity,
1482          * in case of a previous driver crash of some kind, and also
1483          * because the chip powers up with these memories in an unknown
1484          * state.  Use portcnt, not cfgports, since this is for the
1485          * full chip, not for current (possibly different) configuration
1486          * value.
1487          * Chip Errata bug 6447
1488          */
1489         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1490                 ipath_ht_clear_tids(dd, val32);
1491
1492         /*
1493          * write the pbc of each buffer, to be sure it's initialized, then
1494          * cancel all the buffers, and also abort any packets that might
1495          * have been in flight for some reason (the latter is for driver
1496          * unload/reload, but isn't a bad idea at first init).  PIO send
1497          * isn't enabled at this point, so there is no danger of sending
1498          * these out on the wire.
1499          * Chip Errata bug 6610
1500          */
1501         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1502                                   dd->ipath_piobufbase);
1503         pioincr = dd->ipath_palign / sizeof(*piobuf);
1504         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1505                 /*
1506                  * reasonable word count, just to init pbc
1507                  */
1508                 writel(16, piobuf);
1509                 piobuf += pioincr;
1510         }
1511         /*
1512          * self-clearing
1513          */
1514         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1515                          INFINIPATH_S_ABORT);
1516
1517         ipath_get_eeprom_info(dd);
1518         if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1519                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1520                 /*
1521                  * Later production QHT7040 has same changes as QHT7140, so
1522                  * can use GPIO interrupts.  They have serial #'s starting
1523                  * with 128, rather than 112.
1524                  */
1525                 dd->ipath_flags |= IPATH_GPIO_INTR;
1526                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1527         }
1528         return 0;
1529 }
1530
1531 /**
1532  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1533  * @dd: the infinipath device
1534  * @kbase: ipath_base_info pointer
1535  *
1536  * We set the PCIE flag because the lower bandwidth on PCIe vs
1537  * HyperTransport can affect some user packet algorithims.
1538  */
1539 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1540 {
1541         struct ipath_base_info *kinfo = kbase;
1542
1543         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1544                 IPATH_RUNTIME_RCVHDR_COPY;
1545
1546         return 0;
1547 }
1548
1549 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1550 {
1551         free_irq(dd->ipath_irq, dd);
1552         ht_destroy_irq(dd->ipath_irq);
1553         dd->ipath_irq = 0;
1554         dd->ipath_intconfig = 0;
1555 }
1556
1557 /**
1558  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1559  * @dd: the infinipath device
1560  *
1561  * This is global, and is called directly at init to set up the
1562  * chip-specific function pointers for later use.
1563  */
1564 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1565 {
1566         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1567         dd->ipath_f_bus = ipath_setup_ht_config;
1568         dd->ipath_f_reset = ipath_setup_ht_reset;
1569         dd->ipath_f_get_boardname = ipath_ht_boardname;
1570         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1571         dd->ipath_f_early_init = ipath_ht_early_init;
1572         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1573         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1574         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1575         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1576         dd->ipath_f_put_tid = ipath_ht_put_tid;
1577         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1578         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1579         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1580         dd->ipath_f_free_irq = ipath_ht_free_irq;
1581
1582         /*
1583          * initialize chip-specific variables
1584          */
1585         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1586
1587         /*
1588          * setup the register offsets, since they are different for each
1589          * chip
1590          */
1591         dd->ipath_kregs = &ipath_ht_kregs;
1592         dd->ipath_cregs = &ipath_ht_cregs;
1593
1594         /*
1595          * do very early init that is needed before ipath_f_bus is
1596          * called
1597          */
1598         ipath_init_ht_variables(dd);
1599 }