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   1 /*
   2  * cpu.h: Values of the PRId register used to match up
   3  *        various MIPS cpu types.
   4  *
   5  * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
   6  */
   7 #ifndef _ASM_CPU_H
   8 #define _ASM_CPU_H
   9
  10 /* Assigned Company values for bits 23:16 of the PRId Register
  11    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
  12    MTI, the PRId register is defined in this (backwards compatible)
  13    way:
  14
  15   +----------------+----------------+----------------+----------------+
  16   | Company Options| Company ID     | Processor ID   | Revision       |
  17   +----------------+----------------+----------------+----------------+
  18    31            24 23            16 15             8 7
  19
  20    I don't have docs for all the previous processors, but my impression is
  21    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  22    spec.
  23 */
  24
  25 #define PRID_COMP_LEGACY       0x000000
  26 #define PRID_COMP_MIPS         0x010000
  27 #define PRID_COMP_BROADCOM     0x020000
  28 #define PRID_COMP_ALCHEMY      0x030000
  29 #define PRID_COMP_SIBYTE       0x040000
  30 #define PRID_COMP_SANDCRAFT    0x050000
  31
  32 /*
  33  * Assigned values for the product ID register.  In order to detect a
  34  * certain CPU type exactly eventually additional registers may need to
  35  * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
  36  */
  37 #define PRID_IMP_R2000          0x0100
  38 #define PRID_IMP_AU1_REV1       0x0100
  39 #define PRID_IMP_AU1_REV2       0x0200
  40 #define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
  41 #define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
  42 #define PRID_IMP_R4000          0x0400
  43 #define PRID_IMP_R6000A         0x0600
  44 #define PRID_IMP_R10000         0x0900
  45 #define PRID_IMP_R4300          0x0b00
  46 #define PRID_IMP_VR41XX         0x0c00
  47 #define PRID_IMP_R12000         0x0e00
  48 #define PRID_IMP_R8000          0x1000
  49 #define PRID_IMP_R4600          0x2000
  50 #define PRID_IMP_R4700          0x2100
  51 #define PRID_IMP_TX39           0x2200
  52 #define PRID_IMP_R4640          0x2200
  53 #define PRID_IMP_R4650          0x2200          /* Same as R4640 */
  54 #define PRID_IMP_R5000          0x2300
  55 #define PRID_IMP_TX49           0x2d00
  56 #define PRID_IMP_SONIC          0x2400
  57 #define PRID_IMP_MAGIC          0x2500
  58 #define PRID_IMP_RM7000         0x2700
  59 #define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
  60 #define PRID_IMP_RM9000         0x3400
  61 #define PRID_IMP_R5432          0x5400
  62 #define PRID_IMP_R5500          0x5500
  63 #define PRID_IMP_4KC            0x8000
  64 #define PRID_IMP_5KC            0x8100
  65 #define PRID_IMP_20KC           0x8200
  66 #define PRID_IMP_4KEC           0x8400
  67 #define PRID_IMP_4KSC           0x8600
  68 #define PRID_IMP_25KF           0x8800
  69 #define PRID_IMP_5KE            0x8900
  70 #define PRID_IMP_4KECR2         0x9000
  71 #define PRID_IMP_4KEMPR2        0x9100
  72 #define PRID_IMP_4KSD           0x9200
  73 #define PRID_IMP_24K            0x9300
  74
  75 #define PRID_IMP_UNKNOWN        0xff00
  76
  77 /*
  78  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  79  */
  80
  81 #define PRID_IMP_SB1            0x0100
  82
  83 /*
  84  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
  85  */
  86
  87 #define PRID_IMP_SR71000        0x0400
  88
  89 /*
  90  * Definitions for 7:0 on legacy processors
  91  */
  92
  93
  94 #define PRID_REV_TX4927         0x0022
  95 #define PRID_REV_TX4937         0x0030
  96 #define PRID_REV_R4400          0x0040
  97 #define PRID_REV_R3000A         0x0030
  98 #define PRID_REV_R3000          0x0020
  99 #define PRID_REV_R2000A         0x0010
 100 #define PRID_REV_TX3912         0x0010
 101 #define PRID_REV_TX3922         0x0030
 102 #define PRID_REV_TX3927         0x0040
 103 #define PRID_REV_VR4111         0x0050
 104 #define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
 105 #define PRID_REV_VR4121         0x0060
 106 #define PRID_REV_VR4122         0x0070
 107 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 108 #define PRID_REV_VR4130         0x0080
 109
 110 /*
 111  * FPU implementation/revision register (CP1 control register 0).
 112  *
 113  * +---------------------------------+----------------+----------------+
 114  * | 0                               | Implementation | Revision       |
 115  * +---------------------------------+----------------+----------------+
 116  *  31                             16 15             8 7              0
 117  */
 118
 119 #define FPIR_IMP_NONE           0x0000
 120
 121 #define CPU_UNKNOWN              0
 122 #define CPU_R2000                1
 123 #define CPU_R3000                2
 124 #define CPU_R3000A               3
 125 #define CPU_R3041                4
 126 #define CPU_R3051                5
 127 #define CPU_R3052                6
 128 #define CPU_R3081                7
 129 #define CPU_R3081E               8
 130 #define CPU_R4000PC              9
 131 #define CPU_R4000SC             10
 132 #define CPU_R4000MC             11
 133 #define CPU_R4200               12
 134 #define CPU_R4400PC             13
 135 #define CPU_R4400SC             14
 136 #define CPU_R4400MC             15
 137 #define CPU_R4600               16
 138 #define CPU_R6000               17
 139 #define CPU_R6000A              18
 140 #define CPU_R8000               19
 141 #define CPU_R10000              20
 142 #define CPU_R12000              21
 143 #define CPU_R4300               22
 144 #define CPU_R4650               23
 145 #define CPU_R4700               24
 146 #define CPU_R5000               25
 147 #define CPU_R5000A              26
 148 #define CPU_R4640               27
 149 #define CPU_NEVADA              28
 150 #define CPU_RM7000              29
 151 #define CPU_R5432               30
 152 #define CPU_4KC                 31
 153 #define CPU_5KC                 32
 154 #define CPU_R4310               33
 155 #define CPU_SB1                 34
 156 #define CPU_TX3912              35
 157 #define CPU_TX3922              36
 158 #define CPU_TX3927              37
 159 #define CPU_AU1000              38
 160 #define CPU_4KEC                39
 161 #define CPU_4KSC                40
 162 #define CPU_VR41XX              41
 163 #define CPU_R5500               42
 164 #define CPU_TX49XX              43
 165 #define CPU_AU1500              44
 166 #define CPU_20KC                45
 167 #define CPU_VR4111              46
 168 #define CPU_VR4121              47
 169 #define CPU_VR4122              48
 170 #define CPU_VR4131              49
 171 #define CPU_VR4181              50
 172 #define CPU_VR4181A             51
 173 #define CPU_AU1100              52
 174 #define CPU_SR71000             53
 175 #define CPU_RM9000              54
 176 #define CPU_25KF                55
 177 #define CPU_VR4133              56
 178 #define CPU_AU1550              57
 179 #define CPU_24K                 58
 180 #define CPU_LAST                58
 181
 182 /*
 183  * ISA Level encodings
 184  *
 185  */
 186 #define MIPS_CPU_ISA_I          0x00000001
 187 #define MIPS_CPU_ISA_II         0x00000002
 188 #define MIPS_CPU_ISA_III        0x00008003
 189 #define MIPS_CPU_ISA_IV         0x00008004
 190 #define MIPS_CPU_ISA_V          0x00008005
 191 #define MIPS_CPU_ISA_M32        0x00000020
 192 #define MIPS_CPU_ISA_M64        0x00008040
 193
 194 /*
 195  * Bit 15 encodes if an ISA level supports 64-bit operations.
 196  */
 197 #define MIPS_CPU_ISA_64BIT      0x00008000
 198
 199 /*
 200  * CPU Option encodings
 201  */
 202 #define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
 203 /* Leave a spare bit for variant MMU types... */
 204 #define MIPS_CPU_4KEX           0x00000004 /* "R4K" exception model */
 205 #define MIPS_CPU_4KTLB          0x00000008 /* "R4K" TLB handler */
 206 #define MIPS_CPU_FPU            0x00000010 /* CPU has FPU */
 207 #define MIPS_CPU_32FPR          0x00000020 /* 32 dbl. prec. FP registers */
 208 #define MIPS_CPU_COUNTER        0x00000040 /* Cycle count/compare */
 209 #define MIPS_CPU_WATCH          0x00000080 /* watchpoint registers */
 210 #define MIPS_CPU_MIPS16         0x00000100 /* code compression */
 211 #define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
 212 #define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
 213 #define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
 214 #define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
 215 #define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
 216 #define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
 217 #define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
 218 #define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
 219 #define MIPS_CPU_SUBSET_CACHES  0x00020000 /* P-cache subset enforced */
 220 #define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
 221
 222 #endif /* _ASM_CPU_H */