2 * Copyright (C) 1995 Linus Torvalds
6 * This file handles the architecture-dependent parts of initialization
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
42 #include <linux/uaccess.h>
43 #include <linux/init_ohci1394_dma.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
53 #include <video/edid.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
62 #include <asm/sections.h>
64 #include <asm/cacheflush.h>
67 #include <asm/topology.h>
68 #include <asm/trampoline.h>
70 #include <mach_apic.h>
71 #ifdef CONFIG_PARAVIRT
72 #include <asm/paravirt.h>
81 struct cpuinfo_x86 boot_cpu_data __read_mostly;
82 EXPORT_SYMBOL(boot_cpu_data);
84 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
86 unsigned long mmu_cr4_features;
88 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
91 unsigned long saved_video_mode;
93 int force_mwait __cpuinitdata;
99 char dmi_alloc_data[DMI_MAX_DATA];
104 struct screen_info screen_info;
105 EXPORT_SYMBOL(screen_info);
106 struct sys_desc_table_struct {
107 unsigned short length;
108 unsigned char table[0];
111 struct edid_info edid_info;
112 EXPORT_SYMBOL_GPL(edid_info);
114 extern int root_mountflags;
116 char __initdata command_line[COMMAND_LINE_SIZE];
118 struct resource standard_io_resources[] = {
119 { .name = "dma1", .start = 0x00, .end = 0x1f,
120 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
121 { .name = "pic1", .start = 0x20, .end = 0x21,
122 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
123 { .name = "timer0", .start = 0x40, .end = 0x43,
124 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
125 { .name = "timer1", .start = 0x50, .end = 0x53,
126 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
127 { .name = "keyboard", .start = 0x60, .end = 0x6f,
128 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
129 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
130 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
131 { .name = "pic2", .start = 0xa0, .end = 0xa1,
132 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
133 { .name = "dma2", .start = 0xc0, .end = 0xdf,
134 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
135 { .name = "fpu", .start = 0xf0, .end = 0xff,
136 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
139 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
141 static struct resource data_resource = {
142 .name = "Kernel data",
145 .flags = IORESOURCE_RAM,
147 static struct resource code_resource = {
148 .name = "Kernel code",
151 .flags = IORESOURCE_RAM,
153 static struct resource bss_resource = {
154 .name = "Kernel bss",
157 .flags = IORESOURCE_RAM,
160 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
162 #ifdef CONFIG_PROC_VMCORE
163 /* elfcorehdr= specifies the location of elf core header
164 * stored by the crashed kernel. This option will be passed
165 * by kexec loader to the capture kernel.
167 static int __init setup_elfcorehdr(char *arg)
172 elfcorehdr_addr = memparse(arg, &end);
173 return end > arg ? 0 : -EINVAL;
175 early_param("elfcorehdr", setup_elfcorehdr);
180 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
182 unsigned long bootmap_size, bootmap;
184 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
185 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
188 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
189 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
190 e820_register_active_regions(0, start_pfn, end_pfn);
191 free_bootmem_with_active_regions(0, end_pfn);
192 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
196 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
198 #ifdef CONFIG_EDD_MODULE
202 * copy_edd() - Copy the BIOS EDD information
203 * from boot_params into a safe place.
206 static inline void copy_edd(void)
208 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
209 sizeof(edd.mbr_signature));
210 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
211 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
212 edd.edd_info_nr = boot_params.eddbuf_entries;
215 static inline void copy_edd(void)
221 static void __init reserve_crashkernel(void)
223 unsigned long long total_mem;
224 unsigned long long crash_size, crash_base;
227 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
229 ret = parse_crashkernel(boot_command_line, total_mem,
230 &crash_size, &crash_base);
231 if (ret == 0 && crash_size) {
232 if (crash_base <= 0) {
233 printk(KERN_INFO "crashkernel reservation failed - "
234 "you have to specify a base address\n");
238 if (reserve_bootmem(crash_base, crash_size,
239 BOOTMEM_EXCLUSIVE) < 0) {
240 printk(KERN_INFO "crashkernel reservation failed - "
241 "memory is in use\n");
245 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
246 "for crashkernel (System RAM: %ldMB)\n",
247 (unsigned long)(crash_size >> 20),
248 (unsigned long)(crash_base >> 20),
249 (unsigned long)(total_mem >> 20));
250 crashk_res.start = crash_base;
251 crashk_res.end = crash_base + crash_size - 1;
252 insert_resource(&iomem_resource, &crashk_res);
256 static inline void __init reserve_crashkernel(void)
260 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
261 void __attribute__((weak)) __init memory_setup(void)
263 machine_specific_memory_setup();
267 * setup_arch - architecture-specific boot-time initializations
269 * Note: On x86_64, fixmaps are ready for use even before this is called.
271 void __init setup_arch(char **cmdline_p)
275 printk(KERN_INFO "Command line: %s\n", boot_command_line);
277 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
278 screen_info = boot_params.screen_info;
279 edid_info = boot_params.edid_info;
280 saved_video_mode = boot_params.hdr.vid_mode;
281 bootloader_type = boot_params.hdr.type_of_loader;
283 #ifdef CONFIG_BLK_DEV_RAM
284 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
285 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
286 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
289 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
299 if (!boot_params.hdr.root_flags)
300 root_mountflags &= ~MS_RDONLY;
301 init_mm.start_code = (unsigned long) &_text;
302 init_mm.end_code = (unsigned long) &_etext;
303 init_mm.end_data = (unsigned long) &_edata;
304 init_mm.brk = (unsigned long) &_end;
306 code_resource.start = virt_to_phys(&_text);
307 code_resource.end = virt_to_phys(&_etext)-1;
308 data_resource.start = virt_to_phys(&_etext);
309 data_resource.end = virt_to_phys(&_edata)-1;
310 bss_resource.start = virt_to_phys(&__bss_start);
311 bss_resource.end = virt_to_phys(&__bss_stop)-1;
313 early_identify_cpu(&boot_cpu_data);
315 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
316 *cmdline_p = command_line;
320 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
321 if (init_ohci1394_dma_early)
322 init_ohci1394_dma_on_all_controllers();
325 finish_e820_parsing();
327 /* after parse_early_param, so could debug it */
328 insert_resource(&iomem_resource, &code_resource);
329 insert_resource(&iomem_resource, &data_resource);
330 insert_resource(&iomem_resource, &bss_resource);
332 early_gart_iommu_check();
334 e820_register_active_regions(0, 0, -1UL);
336 * partially used pages are not usable - thus
337 * we are rounding upwards:
339 end_pfn = e820_end_of_ram();
340 /* update e820 for memory not covered by WB MTRRs */
342 if (mtrr_trim_uncached_memory(end_pfn)) {
343 e820_register_active_regions(0, 0, -1UL);
344 end_pfn = e820_end_of_ram();
347 num_physpages = end_pfn;
351 max_pfn_mapped = init_memory_mapping(0, (max_pfn_mapped << PAGE_SHIFT));
362 /* setup to use the early static init tables during kernel startup */
363 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
364 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
366 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
372 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
373 * Call this early for SRAT node setup.
375 acpi_boot_table_init();
378 /* How many end-of-memory variables you have, grandma! */
379 max_low_pfn = end_pfn;
381 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
383 /* Remove active ranges so rediscovery with NUMA-awareness happens */
384 remove_all_active_ranges();
386 #ifdef CONFIG_ACPI_NUMA
388 * Parse SRAT to discover nodes.
394 numa_initmem_init(0, end_pfn);
396 contig_initmem_init(0, end_pfn);
399 early_res_to_bootmem();
401 #ifdef CONFIG_ACPI_SLEEP
403 * Reserve low memory region for sleep support.
405 acpi_reserve_bootmem();
409 efi_reserve_bootmem();
412 * Find and reserve possible boot-time SMP configuration:
415 #ifdef CONFIG_BLK_DEV_INITRD
416 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
417 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
418 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
419 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
420 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
422 if (ramdisk_end <= end_of_mem) {
423 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
424 initrd_start = ramdisk_image + PAGE_OFFSET;
425 initrd_end = initrd_start+ramdisk_size;
427 /* Assumes everything on node 0 */
428 free_bootmem(ramdisk_image, ramdisk_size);
429 printk(KERN_ERR "initrd extends beyond end of memory "
430 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
431 ramdisk_end, end_of_mem);
436 reserve_crashkernel();
444 * Read APIC and some other early information from ACPI tables.
452 * get boot-time SMP configuration:
454 if (smp_found_config)
456 init_apic_mappings();
457 ioapic_init_mappings();
460 * We trust e820 completely. No explicit ROM probing in memory.
462 e820_reserve_resources();
463 e820_mark_nosave_regions();
465 /* request I/O space for devices used on all i[345]86 PCs */
466 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
467 request_resource(&ioport_resource, &standard_io_resources[i]);
472 #if defined(CONFIG_VGA_CONSOLE)
473 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
474 conswitchp = &vga_con;
475 #elif defined(CONFIG_DUMMY_CONSOLE)
476 conswitchp = &dummy_con;
481 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
485 if (c->extended_cpuid_level < 0x80000004)
488 v = (unsigned int *) c->x86_model_id;
489 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
490 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
491 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
492 c->x86_model_id[48] = 0;
497 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
499 unsigned int n, dummy, eax, ebx, ecx, edx;
501 n = c->extended_cpuid_level;
503 if (n >= 0x80000005) {
504 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
505 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
506 "D cache %dK (%d bytes/line)\n",
507 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
508 c->x86_cache_size = (ecx>>24) + (edx>>24);
509 /* On K8 L1 TLB is inclusive, so don't count it */
513 if (n >= 0x80000006) {
514 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
515 ecx = cpuid_ecx(0x80000006);
516 c->x86_cache_size = ecx >> 16;
517 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
519 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
520 c->x86_cache_size, ecx & 0xFF);
522 if (n >= 0x80000008) {
523 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
524 c->x86_virt_bits = (eax >> 8) & 0xff;
525 c->x86_phys_bits = eax & 0xff;
530 static int __cpuinit nearby_node(int apicid)
534 for (i = apicid - 1; i >= 0; i--) {
535 node = apicid_to_node[i];
536 if (node != NUMA_NO_NODE && node_online(node))
539 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
540 node = apicid_to_node[i];
541 if (node != NUMA_NO_NODE && node_online(node))
544 return first_node(node_online_map); /* Shouldn't happen */
549 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
550 * Assumes number of cores is a power of two.
552 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
557 int cpu = smp_processor_id();
559 unsigned apicid = hard_smp_processor_id();
561 bits = c->x86_coreid_bits;
563 /* Low order bits define the core id (index of core in socket) */
564 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
565 /* Convert the initial APIC ID into the socket ID */
566 c->phys_proc_id = c->initial_apicid >> bits;
569 node = c->phys_proc_id;
570 if (apicid_to_node[apicid] != NUMA_NO_NODE)
571 node = apicid_to_node[apicid];
572 if (!node_online(node)) {
573 /* Two possibilities here:
574 - The CPU is missing memory and no node was created.
575 In that case try picking one from a nearby CPU
576 - The APIC IDs differ from the HyperTransport node IDs
577 which the K8 northbridge parsing fills in.
578 Assume they are all increased by a constant offset,
579 but in the same order as the HT nodeids.
580 If that doesn't result in a usable node fall back to the
581 path for the previous case. */
583 int ht_nodeid = c->initial_apicid;
585 if (ht_nodeid >= 0 &&
586 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
587 node = apicid_to_node[ht_nodeid];
588 /* Pick a nearby node */
589 if (!node_online(node))
590 node = nearby_node(apicid);
592 numa_set_node(cpu, node);
594 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
599 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
604 /* Multi core CPU? */
605 if (c->extended_cpuid_level < 0x80000008)
608 ecx = cpuid_ecx(0x80000008);
610 c->x86_max_cores = (ecx & 0xff) + 1;
612 /* CPU telling us the core id bits shift? */
613 bits = (ecx >> 12) & 0xF;
615 /* Otherwise recompute */
617 while ((1 << bits) < c->x86_max_cores)
621 c->x86_coreid_bits = bits;
626 #define ENABLE_C1E_MASK 0x18000000
627 #define CPUID_PROCESSOR_SIGNATURE 1
628 #define CPUID_XFAM 0x0ff00000
629 #define CPUID_XFAM_K8 0x00000000
630 #define CPUID_XFAM_10H 0x00100000
631 #define CPUID_XFAM_11H 0x00200000
632 #define CPUID_XMOD 0x000f0000
633 #define CPUID_XMOD_REV_F 0x00040000
635 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
636 static __cpuinit int amd_apic_timer_broken(void)
638 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
640 switch (eax & CPUID_XFAM) {
642 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
646 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
647 if (lo & ENABLE_C1E_MASK)
651 /* err on the side of caution */
657 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
659 early_init_amd_mc(c);
661 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
662 if (c->x86_power & (1<<8))
663 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
666 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
674 * Disable TLB flush filter by setting HWCR.FFDIS on K8
675 * bit 6 of msr C001_0015
677 * Errata 63 for SH-B3 steppings
678 * Errata 122 for all steppings (F+ have it disabled by default)
681 rdmsrl(MSR_K8_HWCR, value);
683 wrmsrl(MSR_K8_HWCR, value);
687 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
688 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
689 clear_cpu_cap(c, 0*32+31);
691 /* On C+ stepping K8 rep microcode works well for copy/memset */
692 level = cpuid_eax(1);
693 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
695 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
696 if (c->x86 == 0x10 || c->x86 == 0x11)
697 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
699 /* Enable workaround for FXSAVE leak */
701 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
703 level = get_model_name(c);
707 /* Should distinguish Models here, but this is only
708 a fallback anyways. */
709 strcpy(c->x86_model_id, "Hammer");
713 display_cacheinfo(c);
715 /* Multi core CPU? */
716 if (c->extended_cpuid_level >= 0x80000008)
719 if (c->extended_cpuid_level >= 0x80000006 &&
720 (cpuid_edx(0x80000006) & 0xf000))
721 num_cache_leaves = 4;
723 num_cache_leaves = 3;
725 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
726 set_cpu_cap(c, X86_FEATURE_K8);
728 /* MFENCE stops RDTSC speculation */
729 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
731 if (amd_apic_timer_broken())
732 disable_apic_timer = 1;
734 if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
735 unsigned long long tseg;
738 * Split up direct mapping around the TSEG SMM area.
739 * Don't do it for gbpages because there seems very little
740 * benefit in doing so.
742 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
743 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
744 set_memory_4k((unsigned long)__va(tseg), 1);
748 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
751 u32 eax, ebx, ecx, edx;
752 int index_msb, core_bits;
754 cpuid(1, &eax, &ebx, &ecx, &edx);
757 if (!cpu_has(c, X86_FEATURE_HT))
759 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
762 smp_num_siblings = (ebx & 0xff0000) >> 16;
764 if (smp_num_siblings == 1) {
765 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
766 } else if (smp_num_siblings > 1) {
768 if (smp_num_siblings > NR_CPUS) {
769 printk(KERN_WARNING "CPU: Unsupported number of "
770 "siblings %d", smp_num_siblings);
771 smp_num_siblings = 1;
775 index_msb = get_count_order(smp_num_siblings);
776 c->phys_proc_id = phys_pkg_id(index_msb);
778 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
780 index_msb = get_count_order(smp_num_siblings);
782 core_bits = get_count_order(c->x86_max_cores);
784 c->cpu_core_id = phys_pkg_id(index_msb) &
785 ((1 << core_bits) - 1);
788 if ((c->x86_max_cores * smp_num_siblings) > 1) {
789 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
791 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
799 * find out the number of processor cores on the die
801 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
805 if (c->cpuid_level < 4)
808 cpuid_count(4, 0, &eax, &t, &t, &t);
811 return ((eax >> 26) + 1);
816 static void __cpuinit srat_detect_node(void)
820 int cpu = smp_processor_id();
821 int apicid = hard_smp_processor_id();
823 /* Don't do the funky fallback heuristics the AMD version employs
825 node = apicid_to_node[apicid];
826 if (node == NUMA_NO_NODE || !node_online(node))
827 node = first_node(node_online_map);
828 numa_set_node(cpu, node);
830 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
834 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
836 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
837 (c->x86 == 0x6 && c->x86_model >= 0x0e))
838 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
841 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
846 init_intel_cacheinfo(c);
847 if (c->cpuid_level > 9) {
848 unsigned eax = cpuid_eax(10);
849 /* Check for version and the number of counters */
850 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
851 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
856 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
858 set_cpu_cap(c, X86_FEATURE_BTS);
860 set_cpu_cap(c, X86_FEATURE_PEBS);
867 n = c->extended_cpuid_level;
868 if (n >= 0x80000008) {
869 unsigned eax = cpuid_eax(0x80000008);
870 c->x86_virt_bits = (eax >> 8) & 0xff;
871 c->x86_phys_bits = eax & 0xff;
872 /* CPUID workaround for Intel 0F34 CPU */
873 if (c->x86_vendor == X86_VENDOR_INTEL &&
874 c->x86 == 0xF && c->x86_model == 0x3 &&
876 c->x86_phys_bits = 36;
880 c->x86_cache_alignment = c->x86_clflush_size * 2;
882 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
883 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
884 c->x86_max_cores = intel_num_cpu_cores(c);
889 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
891 if (c->x86 == 0x6 && c->x86_model >= 0xf)
892 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
895 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
900 n = c->extended_cpuid_level;
901 if (n >= 0x80000008) {
902 unsigned eax = cpuid_eax(0x80000008);
903 c->x86_virt_bits = (eax >> 8) & 0xff;
904 c->x86_phys_bits = eax & 0xff;
907 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
908 c->x86_cache_alignment = c->x86_clflush_size * 2;
909 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
910 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
912 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
915 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
917 char *v = c->x86_vendor_id;
919 if (!strcmp(v, "AuthenticAMD"))
920 c->x86_vendor = X86_VENDOR_AMD;
921 else if (!strcmp(v, "GenuineIntel"))
922 c->x86_vendor = X86_VENDOR_INTEL;
923 else if (!strcmp(v, "CentaurHauls"))
924 c->x86_vendor = X86_VENDOR_CENTAUR;
926 c->x86_vendor = X86_VENDOR_UNKNOWN;
929 /* Do some early cpuid on the boot CPU to get some parameter that are
930 needed before check_bugs. Everything advanced is in identify_cpu
932 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
936 c->loops_per_jiffy = loops_per_jiffy;
937 c->x86_cache_size = -1;
938 c->x86_vendor = X86_VENDOR_UNKNOWN;
939 c->x86_model = c->x86_mask = 0; /* So far unknown... */
940 c->x86_vendor_id[0] = '\0'; /* Unset */
941 c->x86_model_id[0] = '\0'; /* Unset */
942 c->x86_clflush_size = 64;
943 c->x86_cache_alignment = c->x86_clflush_size;
944 c->x86_max_cores = 1;
945 c->x86_coreid_bits = 0;
946 c->extended_cpuid_level = 0;
947 memset(&c->x86_capability, 0, sizeof c->x86_capability);
949 /* Get vendor name */
950 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
951 (unsigned int *)&c->x86_vendor_id[0],
952 (unsigned int *)&c->x86_vendor_id[8],
953 (unsigned int *)&c->x86_vendor_id[4]);
957 /* Initialize the standard set of capabilities */
958 /* Note that the vendor-specific code below might override */
960 /* Intel-defined flags: level 0x00000001 */
961 if (c->cpuid_level >= 0x00000001) {
963 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
964 &c->x86_capability[0]);
965 c->x86 = (tfms >> 8) & 0xf;
966 c->x86_model = (tfms >> 4) & 0xf;
967 c->x86_mask = tfms & 0xf;
969 c->x86 += (tfms >> 20) & 0xff;
971 c->x86_model += ((tfms >> 16) & 0xF) << 4;
972 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
973 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
975 /* Have CPUID level 0 only - unheard of */
979 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
981 c->phys_proc_id = c->initial_apicid;
983 /* AMD-defined flags: level 0x80000001 */
984 xlvl = cpuid_eax(0x80000000);
985 c->extended_cpuid_level = xlvl;
986 if ((xlvl & 0xffff0000) == 0x80000000) {
987 if (xlvl >= 0x80000001) {
988 c->x86_capability[1] = cpuid_edx(0x80000001);
989 c->x86_capability[6] = cpuid_ecx(0x80000001);
991 if (xlvl >= 0x80000004)
992 get_model_name(c); /* Default name */
995 /* Transmeta-defined flags: level 0x80860001 */
996 xlvl = cpuid_eax(0x80860000);
997 if ((xlvl & 0xffff0000) == 0x80860000) {
998 /* Don't set x86_cpuid_level here for now to not confuse. */
999 if (xlvl >= 0x80860001)
1000 c->x86_capability[2] = cpuid_edx(0x80860001);
1003 c->extended_cpuid_level = cpuid_eax(0x80000000);
1004 if (c->extended_cpuid_level >= 0x80000007)
1005 c->x86_power = cpuid_edx(0x80000007);
1008 clear_cpu_cap(c, X86_FEATURE_PAT);
1010 switch (c->x86_vendor) {
1011 case X86_VENDOR_AMD:
1013 if (c->x86 >= 0xf && c->x86 <= 0x11)
1014 set_cpu_cap(c, X86_FEATURE_PAT);
1016 case X86_VENDOR_INTEL:
1017 early_init_intel(c);
1018 if (c->x86 == 0xF || (c->x86 == 6 && c->x86_model >= 15))
1019 set_cpu_cap(c, X86_FEATURE_PAT);
1021 case X86_VENDOR_CENTAUR:
1022 early_init_centaur(c);
1029 * This does the hard work of actually picking apart the CPU stuff...
1031 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1035 early_identify_cpu(c);
1037 init_scattered_cpuid_features(c);
1039 c->apicid = phys_pkg_id(0);
1042 * Vendor-specific initialization. In this section we
1043 * canonicalize the feature flags, meaning if there are
1044 * features a certain CPU supports which CPUID doesn't
1045 * tell us, CPUID claiming incorrect flags, or other bugs,
1046 * we handle them here.
1048 * At the end of this section, c->x86_capability better
1049 * indicate the features this CPU genuinely supports!
1051 switch (c->x86_vendor) {
1052 case X86_VENDOR_AMD:
1056 case X86_VENDOR_INTEL:
1060 case X86_VENDOR_CENTAUR:
1064 case X86_VENDOR_UNKNOWN:
1066 display_cacheinfo(c);
1073 * On SMP, boot_cpu_data holds the common feature set between
1074 * all CPUs; so make sure that we indicate which features are
1075 * common between the CPUs. The first time this routine gets
1076 * executed, c == &boot_cpu_data.
1078 if (c != &boot_cpu_data) {
1079 /* AND the already accumulated flags with these */
1080 for (i = 0; i < NCAPINTS; i++)
1081 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1084 /* Clear all flags overriden by options */
1085 for (i = 0; i < NCAPINTS; i++)
1086 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1088 #ifdef CONFIG_X86_MCE
1091 select_idle_routine(c);
1094 numa_add_cpu(smp_processor_id());
1099 void __cpuinit identify_boot_cpu(void)
1101 identify_cpu(&boot_cpu_data);
1104 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1106 BUG_ON(c == &boot_cpu_data);
1111 static __init int setup_noclflush(char *arg)
1113 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1116 __setup("noclflush", setup_noclflush);
1118 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1120 if (c->x86_model_id[0])
1121 printk(KERN_CONT "%s", c->x86_model_id);
1123 if (c->x86_mask || c->cpuid_level >= 0)
1124 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1126 printk(KERN_CONT "\n");
1129 static __init int setup_disablecpuid(char *arg)
1132 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1133 setup_clear_cpu_cap(bit);
1138 __setup("clearcpuid=", setup_disablecpuid);