git.oblomov.eu Git - linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/errno.h>
  25 #include <linux/string.h>
  26 #include <linux/mm.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/ioport.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/pagemap.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38
  39 #include "intelfb.h"
  40 #include "intelfbhw.h"
  41
  42 struct pll_min_max {
  43         int min_m, max_m, min_m1, max_m1;
  44         int min_m2, max_m2, min_n, max_n;
  45         int min_p, max_p, min_p1, max_p1;
  46         int min_vco, max_vco, p_transition_clk, ref_clk;
  47         int p_inc_lo, p_inc_hi;
  48 };
  49
  50 #define PLLS_I8xx 0
  51 #define PLLS_I9xx 1
  52 #define PLLS_MAX 2
  53
  54 static struct pll_min_max plls[PLLS_MAX] = {
  55         { 108, 140, 18, 26,
  56           6, 16, 3, 16,
  57           4, 128, 0, 31,
  58           930000, 1400000, 165000, 48000,
  59           4, 2 },               /* I8xx */
  60
  61         { 75, 120, 10, 20,
  62           5, 9, 4, 7,
  63           5, 80, 1, 8,
  64           1400000, 2800000, 200000, 96000,
  65           10, 5 }               /* I9xx */
  66 };
  67
  68 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  69 {
  70         u32 tmp;
  71         if (!pdev || !dinfo)
  72                 return 1;
  73
  74         switch (pdev->device) {
  75         case PCI_DEVICE_ID_INTEL_830M:
  76                 dinfo->name = "Intel(R) 830M";
  77                 dinfo->chipset = INTEL_830M;
  78                 dinfo->mobile = 1;
  79                 dinfo->pll_index = PLLS_I8xx;
  80                 return 0;
  81         case PCI_DEVICE_ID_INTEL_845G:
  82                 dinfo->name = "Intel(R) 845G";
  83                 dinfo->chipset = INTEL_845G;
  84                 dinfo->mobile = 0;
  85                 dinfo->pll_index = PLLS_I8xx;
  86                 return 0;
  87         case PCI_DEVICE_ID_INTEL_85XGM:
  88                 tmp = 0;
  89                 dinfo->mobile = 1;
  90                 dinfo->pll_index = PLLS_I8xx;
  91                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  92                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  93                         INTEL_85X_VARIANT_MASK) {
  94                 case INTEL_VAR_855GME:
  95                         dinfo->name = "Intel(R) 855GME";
  96                         dinfo->chipset = INTEL_855GME;
  97                         return 0;
  98                 case INTEL_VAR_855GM:
  99                         dinfo->name = "Intel(R) 855GM";
 100                         dinfo->chipset = INTEL_855GM;
 101                         return 0;
 102                 case INTEL_VAR_852GME:
 103                         dinfo->name = "Intel(R) 852GME";
 104                         dinfo->chipset = INTEL_852GME;
 105                         return 0;
 106                 case INTEL_VAR_852GM:
 107                         dinfo->name = "Intel(R) 852GM";
 108                         dinfo->chipset = INTEL_852GM;
 109                         return 0;
 110                 default:
 111                         dinfo->name = "Intel(R) 852GM/855GM";
 112                         dinfo->chipset = INTEL_85XGM;
 113                         return 0;
 114                 }
 115                 break;
 116         case PCI_DEVICE_ID_INTEL_865G:
 117                 dinfo->name = "Intel(R) 865G";
 118                 dinfo->chipset = INTEL_865G;
 119                 dinfo->mobile = 0;
 120                 dinfo->pll_index = PLLS_I8xx;
 121                 return 0;
 122         case PCI_DEVICE_ID_INTEL_915G:
 123                 dinfo->name = "Intel(R) 915G";
 124                 dinfo->chipset = INTEL_915G;
 125                 dinfo->mobile = 0;
 126                 dinfo->pll_index = PLLS_I9xx;
 127                 return 0;
 128         case PCI_DEVICE_ID_INTEL_915GM:
 129                 dinfo->name = "Intel(R) 915GM";
 130                 dinfo->chipset = INTEL_915GM;
 131                 dinfo->mobile = 1;
 132                 dinfo->pll_index = PLLS_I9xx;
 133                 return 0;
 134         case PCI_DEVICE_ID_INTEL_945G:
 135                 dinfo->name = "Intel(R) 945G";
 136                 dinfo->chipset = INTEL_945G;
 137                 dinfo->mobile = 0;
 138                 dinfo->pll_index = PLLS_I9xx;
 139                 return 0;
 140         case PCI_DEVICE_ID_INTEL_945GM:
 141                 dinfo->name = "Intel(R) 945GM";
 142                 dinfo->chipset = INTEL_945GM;
 143                 dinfo->mobile = 1;
 144                 dinfo->pll_index = PLLS_I9xx;
 145                 return 0;
 146         case PCI_DEVICE_ID_INTEL_965G:
 147                 dinfo->name = "Intel(R) 965G";
 148                 dinfo->chipset = INTEL_965G;
 149                 dinfo->mobile = 0;
 150                 dinfo->pll_index = PLLS_I9xx;
 151                 return 0;
 152         case PCI_DEVICE_ID_INTEL_965GM:
 153                 dinfo->name = "Intel(R) 965GM";
 154                 dinfo->chipset = INTEL_965GM;
 155                 dinfo->mobile = 1;
 156                 dinfo->pll_index = PLLS_I9xx;
 157                 return 0;
 158         default:
 159                 return 1;
 160         }
 161 }
 162
 163 int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 164                          int *stolen_size)
 165 {
 166         struct pci_dev *bridge_dev;
 167         u16 tmp;
 168         int stolen_overhead;
 169
 170         if (!pdev || !aperture_size || !stolen_size)
 171                 return 1;
 172
 173         /* Find the bridge device.  It is always 0:0.0 */
 174         if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
 175                 ERR_MSG("cannot find bridge device\n");
 176                 return 1;
 177         }
 178
 179         /* Get the fb aperture size and "stolen" memory amount. */
 180         tmp = 0;
 181         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 182         pci_dev_put(bridge_dev);
 183
 184         switch (pdev->device) {
 185         case PCI_DEVICE_ID_INTEL_915G:
 186         case PCI_DEVICE_ID_INTEL_915GM:
 187         case PCI_DEVICE_ID_INTEL_945G:
 188         case PCI_DEVICE_ID_INTEL_945GM:
 189         case PCI_DEVICE_ID_INTEL_965G:
 190         case PCI_DEVICE_ID_INTEL_965GM:
 191                 /* 915, 945 and 965 chipsets support a 256MB aperture.
 192                    Aperture size is determined by inspected the
 193                    base address of the aperture. */
 194                 if (pci_resource_start(pdev, 2) & 0x08000000)
 195                         *aperture_size = MB(128);
 196                 else
 197                         *aperture_size = MB(256);
 198                 break;
 199         default:
 200                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 201                         *aperture_size = MB(64);
 202                 else
 203                         *aperture_size = MB(128);
 204                 break;
 205         }
 206
 207         /* Stolen memory size is reduced by the GTT and the popup.
 208            GTT is 1K per MB of aperture size, and popup is 4K. */
 209         stolen_overhead = (*aperture_size / MB(1)) + 4;
 210         switch(pdev->device) {
 211         case PCI_DEVICE_ID_INTEL_830M:
 212         case PCI_DEVICE_ID_INTEL_845G:
 213                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 214                 case INTEL_830_GMCH_GMS_STOLEN_512:
 215                         *stolen_size = KB(512) - KB(stolen_overhead);
 216                         return 0;
 217                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 218                         *stolen_size = MB(1) - KB(stolen_overhead);
 219                         return 0;
 220                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 221                         *stolen_size = MB(8) - KB(stolen_overhead);
 222                         return 0;
 223                 case INTEL_830_GMCH_GMS_LOCAL:
 224                         ERR_MSG("only local memory found\n");
 225                         return 1;
 226                 case INTEL_830_GMCH_GMS_DISABLED:
 227                         ERR_MSG("video memory is disabled\n");
 228                         return 1;
 229                 default:
 230                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 231                                 tmp & INTEL_830_GMCH_GMS_MASK);
 232                         return 1;
 233                 }
 234                 break;
 235         default:
 236                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 237                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 238                         *stolen_size = MB(1) - KB(stolen_overhead);
 239                         return 0;
 240                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 241                         *stolen_size = MB(4) - KB(stolen_overhead);
 242                         return 0;
 243                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 244                         *stolen_size = MB(8) - KB(stolen_overhead);
 245                         return 0;
 246                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 247                         *stolen_size = MB(16) - KB(stolen_overhead);
 248                         return 0;
 249                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 250                         *stolen_size = MB(32) - KB(stolen_overhead);
 251                         return 0;
 252                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 253                         *stolen_size = MB(48) - KB(stolen_overhead);
 254                         return 0;
 255                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 256                         *stolen_size = MB(64) - KB(stolen_overhead);
 257                         return 0;
 258                 case INTEL_855_GMCH_GMS_DISABLED:
 259                         ERR_MSG("video memory is disabled\n");
 260                         return 0;
 261                 default:
 262                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 263                                 tmp & INTEL_855_GMCH_GMS_MASK);
 264                         return 1;
 265                 }
 266         }
 267 }
 268
 269 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 270 {
 271         int dvo = 0;
 272
 273         if (INREG(LVDS) & PORT_ENABLE)
 274                 dvo |= LVDS_PORT;
 275         if (INREG(DVOA) & PORT_ENABLE)
 276                 dvo |= DVOA_PORT;
 277         if (INREG(DVOB) & PORT_ENABLE)
 278                 dvo |= DVOB_PORT;
 279         if (INREG(DVOC) & PORT_ENABLE)
 280                 dvo |= DVOC_PORT;
 281
 282         return dvo;
 283 }
 284
 285 const char * intelfbhw_dvo_to_string(int dvo)
 286 {
 287         if (dvo & DVOA_PORT)
 288                 return "DVO port A";
 289         else if (dvo & DVOB_PORT)
 290                 return "DVO port B";
 291         else if (dvo & DVOC_PORT)
 292                 return "DVO port C";
 293         else if (dvo & LVDS_PORT)
 294                 return "LVDS port";
 295         else
 296                 return NULL;
 297 }
 298
 299
 300 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
 301                             struct fb_var_screeninfo *var)
 302 {
 303         int bytes_per_pixel;
 304         int tmp;
 305
 306 #if VERBOSE > 0
 307         DBG_MSG("intelfbhw_validate_mode\n");
 308 #endif
 309
 310         bytes_per_pixel = var->bits_per_pixel / 8;
 311         if (bytes_per_pixel == 3)
 312                 bytes_per_pixel = 4;
 313
 314         /* Check if enough video memory. */
 315         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 316         if (tmp > dinfo->fb.size) {
 317                 WRN_MSG("Not enough video ram for mode "
 318                         "(%d KByte vs %d KByte).\n",
 319                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 320                 return 1;
 321         }
 322
 323         /* Check if x/y limits are OK. */
 324         if (var->xres - 1 > HACTIVE_MASK) {
 325                 WRN_MSG("X resolution too large (%d vs %d).\n",
 326                         var->xres, HACTIVE_MASK + 1);
 327                 return 1;
 328         }
 329         if (var->yres - 1 > VACTIVE_MASK) {
 330                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 331                         var->yres, VACTIVE_MASK + 1);
 332                 return 1;
 333         }
 334         if (var->xres < 4) {
 335                 WRN_MSG("X resolution too small (%d vs 4).\n", var->xres);
 336                 return 1;
 337         }
 338         if (var->yres < 4) {
 339                 WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres);
 340                 return 1;
 341         }
 342
 343         /* Check for doublescan modes. */
 344         if (var->vmode & FB_VMODE_DOUBLE) {
 345                 WRN_MSG("Mode is double-scan.\n");
 346                 return 1;
 347         }
 348
 349         if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) {
 350                 WRN_MSG("Odd number of lines in interlaced mode\n");
 351                 return 1;
 352         }
 353
 354         /* Check if clock is OK. */
 355         tmp = 1000000000 / var->pixclock;
 356         if (tmp < MIN_CLOCK) {
 357                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 358                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 359                 return 1;
 360         }
 361         if (tmp > MAX_CLOCK) {
 362                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 363                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 364                 return 1;
 365         }
 366
 367         return 0;
 368 }
 369
 370 int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 371 {
 372         struct intelfb_info *dinfo = GET_DINFO(info);
 373         u32 offset, xoffset, yoffset;
 374
 375 #if VERBOSE > 0
 376         DBG_MSG("intelfbhw_pan_display\n");
 377 #endif
 378
 379         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 380         yoffset = var->yoffset;
 381
 382         if ((xoffset + var->xres > var->xres_virtual) ||
 383             (yoffset + var->yres > var->yres_virtual))
 384                 return -EINVAL;
 385
 386         offset = (yoffset * dinfo->pitch) +
 387                  (xoffset * var->bits_per_pixel) / 8;
 388
 389         offset += dinfo->fb.offset << 12;
 390
 391         dinfo->vsync.pan_offset = offset;
 392         if ((var->activate & FB_ACTIVATE_VBL) &&
 393             !intelfbhw_enable_irq(dinfo))
 394                 dinfo->vsync.pan_display = 1;
 395         else {
 396                 dinfo->vsync.pan_display = 0;
 397                 OUTREG(DSPABASE, offset);
 398         }
 399
 400         return 0;
 401 }
 402
 403 /* Blank the screen. */
 404 void intelfbhw_do_blank(int blank, struct fb_info *info)
 405 {
 406         struct intelfb_info *dinfo = GET_DINFO(info);
 407         u32 tmp;
 408
 409 #if VERBOSE > 0
 410         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 411 #endif
 412
 413         /* Turn plane A on or off */
 414         tmp = INREG(DSPACNTR);
 415         if (blank)
 416                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 417         else
 418                 tmp |= DISPPLANE_PLANE_ENABLE;
 419         OUTREG(DSPACNTR, tmp);
 420         /* Flush */
 421         tmp = INREG(DSPABASE);
 422         OUTREG(DSPABASE, tmp);
 423
 424         /* Turn off/on the HW cursor */
 425 #if VERBOSE > 0
 426         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 427 #endif
 428         if (dinfo->cursor_on) {
 429                 if (blank)
 430                         intelfbhw_cursor_hide(dinfo);
 431                 else
 432                         intelfbhw_cursor_show(dinfo);
 433                 dinfo->cursor_on = 1;
 434         }
 435         dinfo->cursor_blanked = blank;
 436
 437         /* Set DPMS level */
 438         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 439         switch (blank) {
 440         case FB_BLANK_UNBLANK:
 441         case FB_BLANK_NORMAL:
 442                 tmp |= ADPA_DPMS_D0;
 443                 break;
 444         case FB_BLANK_VSYNC_SUSPEND:
 445                 tmp |= ADPA_DPMS_D1;
 446                 break;
 447         case FB_BLANK_HSYNC_SUSPEND:
 448                 tmp |= ADPA_DPMS_D2;
 449                 break;
 450         case FB_BLANK_POWERDOWN:
 451                 tmp |= ADPA_DPMS_D3;
 452                 break;
 453         }
 454         OUTREG(ADPA, tmp);
 455
 456         return;
 457 }
 458
 459
 460 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 461                          unsigned red, unsigned green, unsigned blue,
 462                          unsigned transp)
 463 {
 464         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 465                           PALETTE_A : PALETTE_B;
 466
 467 #if VERBOSE > 0
 468         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 469                 regno, red, green, blue);
 470 #endif
 471
 472         OUTREG(palette_reg + (regno << 2),
 473                (red << PALETTE_8_RED_SHIFT) |
 474                (green << PALETTE_8_GREEN_SHIFT) |
 475                (blue << PALETTE_8_BLUE_SHIFT));
 476 }
 477
 478
 479 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
 480                             struct intelfb_hwstate *hw, int flag)
 481 {
 482         int i;
 483
 484 #if VERBOSE > 0
 485         DBG_MSG("intelfbhw_read_hw_state\n");
 486 #endif
 487
 488         if (!hw || !dinfo)
 489                 return -1;
 490
 491         /* Read in as much of the HW state as possible. */
 492         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 493         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 494         hw->vga_pd = INREG(VGAPD);
 495         hw->dpll_a = INREG(DPLL_A);
 496         hw->dpll_b = INREG(DPLL_B);
 497         hw->fpa0 = INREG(FPA0);
 498         hw->fpa1 = INREG(FPA1);
 499         hw->fpb0 = INREG(FPB0);
 500         hw->fpb1 = INREG(FPB1);
 501
 502         if (flag == 1)
 503                 return flag;
 504
 505 #if 0
 506         /* This seems to be a problem with the 852GM/855GM */
 507         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 508                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 509                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 510         }
 511 #endif
 512
 513         if (flag == 2)
 514                 return flag;
 515
 516         hw->htotal_a = INREG(HTOTAL_A);
 517         hw->hblank_a = INREG(HBLANK_A);
 518         hw->hsync_a = INREG(HSYNC_A);
 519         hw->vtotal_a = INREG(VTOTAL_A);
 520         hw->vblank_a = INREG(VBLANK_A);
 521         hw->vsync_a = INREG(VSYNC_A);
 522         hw->src_size_a = INREG(SRC_SIZE_A);
 523         hw->bclrpat_a = INREG(BCLRPAT_A);
 524         hw->htotal_b = INREG(HTOTAL_B);
 525         hw->hblank_b = INREG(HBLANK_B);
 526         hw->hsync_b = INREG(HSYNC_B);
 527         hw->vtotal_b = INREG(VTOTAL_B);
 528         hw->vblank_b = INREG(VBLANK_B);
 529         hw->vsync_b = INREG(VSYNC_B);
 530         hw->src_size_b = INREG(SRC_SIZE_B);
 531         hw->bclrpat_b = INREG(BCLRPAT_B);
 532
 533         if (flag == 3)
 534                 return flag;
 535
 536         hw->adpa = INREG(ADPA);
 537         hw->dvoa = INREG(DVOA);
 538         hw->dvob = INREG(DVOB);
 539         hw->dvoc = INREG(DVOC);
 540         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 541         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 542         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 543         hw->lvds = INREG(LVDS);
 544
 545         if (flag == 4)
 546                 return flag;
 547
 548         hw->pipe_a_conf = INREG(PIPEACONF);
 549         hw->pipe_b_conf = INREG(PIPEBCONF);
 550         hw->disp_arb = INREG(DISPARB);
 551
 552         if (flag == 5)
 553                 return flag;
 554
 555         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 556         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 557         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 558         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 559
 560         if (flag == 6)
 561                 return flag;
 562
 563         for (i = 0; i < 4; i++) {
 564                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 565                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 566         }
 567
 568         if (flag == 7)
 569                 return flag;
 570
 571         hw->cursor_size = INREG(CURSOR_SIZE);
 572
 573         if (flag == 8)
 574                 return flag;
 575
 576         hw->disp_a_ctrl = INREG(DSPACNTR);
 577         hw->disp_b_ctrl = INREG(DSPBCNTR);
 578         hw->disp_a_base = INREG(DSPABASE);
 579         hw->disp_b_base = INREG(DSPBBASE);
 580         hw->disp_a_stride = INREG(DSPASTRIDE);
 581         hw->disp_b_stride = INREG(DSPBSTRIDE);
 582
 583         if (flag == 9)
 584                 return flag;
 585
 586         hw->vgacntrl = INREG(VGACNTRL);
 587
 588         if (flag == 10)
 589                 return flag;
 590
 591         hw->add_id = INREG(ADD_ID);
 592
 593         if (flag == 11)
 594                 return flag;
 595
 596         for (i = 0; i < 7; i++) {
 597                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 598                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 599                 if (i < 3)
 600                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 601         }
 602
 603         for (i = 0; i < 8; i++)
 604                 hw->fence[i] = INREG(FENCE + (i << 2));
 605
 606         hw->instpm = INREG(INSTPM);
 607         hw->mem_mode = INREG(MEM_MODE);
 608         hw->fw_blc_0 = INREG(FW_BLC_0);
 609         hw->fw_blc_1 = INREG(FW_BLC_1);
 610
 611         hw->hwstam = INREG16(HWSTAM);
 612         hw->ier = INREG16(IER);
 613         hw->iir = INREG16(IIR);
 614         hw->imr = INREG16(IMR);
 615
 616         return 0;
 617 }
 618
 619
 620 static int calc_vclock3(int index, int m, int n, int p)
 621 {
 622         if (p == 0 || n == 0)
 623                 return 0;
 624         return plls[index].ref_clk * m / n / p;
 625 }
 626
 627 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
 628                        int lvds)
 629 {
 630         struct pll_min_max *pll = &plls[index];
 631         u32 m, vco, p;
 632
 633         m = (5 * (m1 + 2)) + (m2 + 2);
 634         n += 2;
 635         vco = pll->ref_clk * m / n;
 636
 637         if (index == PLLS_I8xx)
 638                 p = ((p1 + 2) * (1 << (p2 + 1)));
 639         else
 640                 p = ((p1) * (p2 ? 5 : 10));
 641         return vco / p;
 642 }
 643
 644 #if REGDUMP
 645 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
 646                                int *o_p1, int *o_p2)
 647 {
 648         int p1, p2;
 649
 650         if (IS_I9XX(dinfo)) {
 651                 if (dpll & DPLL_P1_FORCE_DIV2)
 652                         p1 = 1;
 653                 else
 654                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 655
 656                 p1 = ffs(p1);
 657
 658                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 659         } else {
 660                 if (dpll & DPLL_P1_FORCE_DIV2)
 661                         p1 = 0;
 662                 else
 663                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 664                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 665         }
 666
 667         *o_p1 = p1;
 668         *o_p2 = p2;
 669 }
 670 #endif
 671
 672
 673 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
 674                               struct intelfb_hwstate *hw)
 675 {
 676 #if REGDUMP
 677         int i, m1, m2, n, p1, p2;
 678         int index = dinfo->pll_index;
 679         DBG_MSG("intelfbhw_print_hw_state\n");
 680
 681         if (!hw)
 682                 return;
 683         /* Read in as much of the HW state as possible. */
 684         printk("hw state dump start\n");
 685         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 686         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 687         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 688         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 689         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 690         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 691
 692         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 693
 694         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 695                m1, m2, n, p1, p2);
 696         printk("        VGA0: clock is %d\n",
 697                calc_vclock(index, m1, m2, n, p1, p2, 0));
 698
 699         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 700         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 701         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 702
 703         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 704         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 705                m1, m2, n, p1, p2);
 706         printk("        VGA1: clock is %d\n",
 707                calc_vclock(index, m1, m2, n, p1, p2, 0));
 708
 709         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 710         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 711         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 712         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 713         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 714         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 715
 716         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 717         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 718         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 719
 720         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 721
 722         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 723                m1, m2, n, p1, p2);
 724         printk("        PLLA0: clock is %d\n",
 725                calc_vclock(index, m1, m2, n, p1, p2, 0));
 726
 727         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 728         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 729         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 730
 731         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 732
 733         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 734                m1, m2, n, p1, p2);
 735         printk("        PLLA1: clock is %d\n",
 736                calc_vclock(index, m1, m2, n, p1, p2, 0));
 737
 738 #if 0
 739         printk("        PALETTE_A:\n");
 740         for (i = 0; i < PALETTE_8_ENTRIES)
 741                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 742         printk("        PALETTE_B:\n");
 743         for (i = 0; i < PALETTE_8_ENTRIES)
 744                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 745 #endif
 746
 747         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 748         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 749         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 750         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 751         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 752         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 753         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 754         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 755         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 756         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 757         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 758         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 759         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 760         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 761         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 762         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 763
 764         printk("        ADPA:                   0x%08x\n", hw->adpa);
 765         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 766         printk("        DVOB:                   0x%08x\n", hw->dvob);
 767         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 768         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 769         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 770         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 771         printk("        LVDS:                   0x%08x\n", hw->lvds);
 772
 773         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 774         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 775         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 776
 777         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 778         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 779         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 780         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 781
 782         printk("        CURSOR_A_PALETTE:       ");
 783         for (i = 0; i < 4; i++) {
 784                 printk("0x%08x", hw->cursor_a_palette[i]);
 785                 if (i < 3)
 786                         printk(", ");
 787         }
 788         printk("\n");
 789         printk("        CURSOR_B_PALETTE:       ");
 790         for (i = 0; i < 4; i++) {
 791                 printk("0x%08x", hw->cursor_b_palette[i]);
 792                 if (i < 3)
 793                         printk(", ");
 794         }
 795         printk("\n");
 796
 797         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 798
 799         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 800         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 801         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 802         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 803         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 804         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 805
 806         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 807         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 808
 809         for (i = 0; i < 7; i++) {
 810                 printk("        SWF0%d                  0x%08x\n", i,
 811                         hw->swf0x[i]);
 812         }
 813         for (i = 0; i < 7; i++) {
 814                 printk("        SWF1%d                  0x%08x\n", i,
 815                         hw->swf1x[i]);
 816         }
 817         for (i = 0; i < 3; i++) {
 818                 printk("        SWF3%d                  0x%08x\n", i,
 819                        hw->swf3x[i]);
 820         }
 821         for (i = 0; i < 8; i++)
 822                 printk("        FENCE%d                 0x%08x\n", i,
 823                        hw->fence[i]);
 824
 825         printk("        INSTPM                  0x%08x\n", hw->instpm);
 826         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 827         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 828         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 829
 830         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 831         printk("        IER                     0x%04x\n", hw->ier);
 832         printk("        IIR                     0x%04x\n", hw->iir);
 833         printk("        IMR                     0x%04x\n", hw->imr);
 834         printk("hw state dump end\n");
 835 #endif
 836 }
 837
 838
 839
 840 /* Split the M parameter into M1 and M2. */
 841 static int splitm(int index, unsigned int m, unsigned int *retm1,
 842                   unsigned int *retm2)
 843 {
 844         int m1, m2;
 845         int testm;
 846         struct pll_min_max *pll = &plls[index];
 847
 848         /* no point optimising too much - brute force m */
 849         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 850                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 851                         testm = (5 * (m1 + 2)) + (m2 + 2);
 852                         if (testm == m) {
 853                                 *retm1 = (unsigned int)m1;
 854                                 *retm2 = (unsigned int)m2;
 855                                 return 0;
 856                         }
 857                 }
 858         }
 859         return 1;
 860 }
 861
 862 /* Split the P parameter into P1 and P2. */
 863 static int splitp(int index, unsigned int p, unsigned int *retp1,
 864                   unsigned int *retp2)
 865 {
 866         int p1, p2;
 867         struct pll_min_max *pll = &plls[index];
 868
 869         if (index == PLLS_I9xx) {
 870                 p2 = (p % 10) ? 1 : 0;
 871
 872                 p1 = p / (p2 ? 5 : 10);
 873
 874                 *retp1 = (unsigned int)p1;
 875                 *retp2 = (unsigned int)p2;
 876                 return 0;
 877         }
 878
 879         if (p % 4 == 0)
 880                 p2 = 1;
 881         else
 882                 p2 = 0;
 883         p1 = (p / (1 << (p2 + 1))) - 2;
 884         if (p % 4 == 0 && p1 < pll->min_p1) {
 885                 p2 = 0;
 886                 p1 = (p / (1 << (p2 + 1))) - 2;
 887         }
 888         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 889             (p1 + 2) * (1 << (p2 + 1)) != p) {
 890                 return 1;
 891         } else {
 892                 *retp1 = (unsigned int)p1;
 893                 *retp2 = (unsigned int)p2;
 894                 return 0;
 895         }
 896 }
 897
 898 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
 899                            u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
 900 {
 901         u32 m1, m2, n, p1, p2, n1, testm;
 902         u32 f_vco, p, p_best = 0, m, f_out = 0;
 903         u32 err_max, err_target, err_best = 10000000;
 904         u32 n_best = 0, m_best = 0, f_best, f_err;
 905         u32 p_min, p_max, p_inc, div_max;
 906         struct pll_min_max *pll = &plls[index];
 907
 908         /* Accept 0.5% difference, but aim for 0.1% */
 909         err_max = 5 * clock / 1000;
 910         err_target = clock / 1000;
 911
 912         DBG_MSG("Clock is %d\n", clock);
 913
 914         div_max = pll->max_vco / clock;
 915
 916         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 917         p_min = p_inc;
 918         p_max = ROUND_DOWN_TO(div_max, p_inc);
 919         if (p_min < pll->min_p)
 920                 p_min = pll->min_p;
 921         if (p_max > pll->max_p)
 922                 p_max = pll->max_p;
 923
 924         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 925
 926         p = p_min;
 927         do {
 928                 if (splitp(index, p, &p1, &p2)) {
 929                         WRN_MSG("cannot split p = %d\n", p);
 930                         p += p_inc;
 931                         continue;
 932                 }
 933                 n = pll->min_n;
 934                 f_vco = clock * p;
 935
 936                 do {
 937                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 938                         if (m < pll->min_m)
 939                                 m = pll->min_m + 1;
 940                         if (m > pll->max_m)
 941                                 m = pll->max_m - 1;
 942                         for (testm = m - 1; testm <= m; testm++) {
 943                                 f_out = calc_vclock3(index, testm, n, p);
 944                                 if (splitm(index, testm, &m1, &m2)) {
 945                                         WRN_MSG("cannot split m = %d\n",
 946                                                 testm);
 947                                         continue;
 948                                 }
 949                                 if (clock > f_out)
 950                                         f_err = clock - f_out;
 951                                 else/* slightly bias the error for bigger clocks */
 952                                         f_err = f_out - clock + 1;
 953
 954                                 if (f_err < err_best) {
 955                                         m_best = testm;
 956                                         n_best = n;
 957                                         p_best = p;
 958                                         f_best = f_out;
 959                                         err_best = f_err;
 960                                 }
 961                         }
 962                         n++;
 963                 } while ((n <= pll->max_n) && (f_out >= clock));
 964                 p += p_inc;
 965         } while ((p <= p_max));
 966
 967         if (!m_best) {
 968                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 969                 return 1;
 970         }
 971         m = m_best;
 972         n = n_best;
 973         p = p_best;
 974         splitm(index, m, &m1, &m2);
 975         splitp(index, p, &p1, &p2);
 976         n1 = n - 2;
 977
 978         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 979                 "f: %d (%d), VCO: %d\n",
 980                 m, m1, m2, n, n1, p, p1, p2,
 981                 calc_vclock3(index, m, n, p),
 982                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 983                 calc_vclock3(index, m, n, p) * p);
 984         *retm1 = m1;
 985         *retm2 = m2;
 986         *retn = n1;
 987         *retp1 = p1;
 988         *retp2 = p2;
 989         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 990
 991         return 0;
 992 }
 993
 994 static __inline__ int check_overflow(u32 value, u32 limit,
 995                                      const char *description)
 996 {
 997         if (value > limit) {
 998                 WRN_MSG("%s value %d exceeds limit %d\n",
 999                         description, value, limit);
1000                 return 1;
1001         }
1002         return 0;
1003 }
1004
1005 /* It is assumed that hw is filled in with the initial state information. */
1006 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
1007                          struct intelfb_hwstate *hw,
1008                          struct fb_var_screeninfo *var)
1009 {
1010         int pipe = PIPE_A;
1011         u32 *dpll, *fp0, *fp1;
1012         u32 m1, m2, n, p1, p2, clock_target, clock;
1013         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1014         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1015         u32 vsync_pol, hsync_pol;
1016         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1017         u32 stride_alignment;
1018
1019         DBG_MSG("intelfbhw_mode_to_hw\n");
1020
1021         /* Disable VGA */
1022         hw->vgacntrl |= VGA_DISABLE;
1023
1024         /* Check whether pipe A or pipe B is enabled. */
1025         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1026                 pipe = PIPE_A;
1027         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1028                 pipe = PIPE_B;
1029
1030         /* Set which pipe's registers will be set. */
1031         if (pipe == PIPE_B) {
1032                 dpll = &hw->dpll_b;
1033                 fp0 = &hw->fpb0;
1034                 fp1 = &hw->fpb1;
1035                 hs = &hw->hsync_b;
1036                 hb = &hw->hblank_b;
1037                 ht = &hw->htotal_b;
1038                 vs = &hw->vsync_b;
1039                 vb = &hw->vblank_b;
1040                 vt = &hw->vtotal_b;
1041                 ss = &hw->src_size_b;
1042                 pipe_conf = &hw->pipe_b_conf;
1043         } else {
1044                 dpll = &hw->dpll_a;
1045                 fp0 = &hw->fpa0;
1046                 fp1 = &hw->fpa1;
1047                 hs = &hw->hsync_a;
1048                 hb = &hw->hblank_a;
1049                 ht = &hw->htotal_a;
1050                 vs = &hw->vsync_a;
1051                 vb = &hw->vblank_a;
1052                 vt = &hw->vtotal_a;
1053                 ss = &hw->src_size_a;
1054                 pipe_conf = &hw->pipe_a_conf;
1055         }
1056
1057         /* Use ADPA register for sync control. */
1058         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1059
1060         /* sync polarity */
1061         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1062                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1063         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1064                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1065         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1066                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1067         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1068                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1069
1070         /* Connect correct pipe to the analog port DAC */
1071         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1072         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1073
1074         /* Set DPMS state to D0 (on) */
1075         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1076         hw->adpa |= ADPA_DPMS_D0;
1077
1078         hw->adpa |= ADPA_DAC_ENABLE;
1079
1080         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1081         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1082         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1083
1084         /* Desired clock in kHz */
1085         clock_target = 1000000000 / var->pixclock;
1086
1087         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1088                             &n, &p1, &p2, &clock)) {
1089                 WRN_MSG("calc_pll_params failed\n");
1090                 return 1;
1091         }
1092
1093         /* Check for overflow. */
1094         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1095                 return 1;
1096         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1097                 return 1;
1098         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1099                 return 1;
1100         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1101                 return 1;
1102         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1103                 return 1;
1104
1105         *dpll &= ~DPLL_P1_FORCE_DIV2;
1106         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1107                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1108
1109         if (IS_I9XX(dinfo)) {
1110                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1111                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1112         } else
1113                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1114
1115         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1116                (m1 << FP_M1_DIVISOR_SHIFT) |
1117                (m2 << FP_M2_DIVISOR_SHIFT);
1118         *fp1 = *fp0;
1119
1120         hw->dvob &= ~PORT_ENABLE;
1121         hw->dvoc &= ~PORT_ENABLE;
1122
1123         /* Use display plane A. */
1124         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1125         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1126         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1127         switch (intelfb_var_to_depth(var)) {
1128         case 8:
1129                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1130                 break;
1131         case 15:
1132                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1133                 break;
1134         case 16:
1135                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1136                 break;
1137         case 24:
1138                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1139                 break;
1140         }
1141         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1142         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1143
1144         /* Set CRTC registers. */
1145         hactive = var->xres;
1146         hsync_start = hactive + var->right_margin;
1147         hsync_end = hsync_start + var->hsync_len;
1148         htotal = hsync_end + var->left_margin;
1149         hblank_start = hactive;
1150         hblank_end = htotal;
1151
1152         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1153                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1154                 hblank_end);
1155
1156         vactive = var->yres;
1157         if (var->vmode & FB_VMODE_INTERLACED)
1158                 vactive--; /* the chip adds 2 halflines automatically */
1159         vsync_start = vactive + var->lower_margin;
1160         vsync_end = vsync_start + var->vsync_len;
1161         vtotal = vsync_end + var->upper_margin;
1162         vblank_start = vactive;
1163         vblank_end = vtotal;
1164         vblank_end = vsync_end + 1;
1165
1166         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1167                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1168                 vblank_end);
1169
1170         /* Adjust for register values, and check for overflow. */
1171         hactive--;
1172         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1173                 return 1;
1174         hsync_start--;
1175         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1176                 return 1;
1177         hsync_end--;
1178         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1179                 return 1;
1180         htotal--;
1181         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1182                 return 1;
1183         hblank_start--;
1184         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1185                 return 1;
1186         hblank_end--;
1187         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1188                 return 1;
1189
1190         vactive--;
1191         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1192                 return 1;
1193         vsync_start--;
1194         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1195                 return 1;
1196         vsync_end--;
1197         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1198                 return 1;
1199         vtotal--;
1200         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1201                 return 1;
1202         vblank_start--;
1203         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1204                 return 1;
1205         vblank_end--;
1206         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1207                 return 1;
1208
1209         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1210         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1211               (hblank_end << HSYNCEND_SHIFT);
1212         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1213
1214         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1215         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1216               (vblank_end << VSYNCEND_SHIFT);
1217         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1218         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1219               (vactive << SRC_SIZE_VERT_SHIFT);
1220
1221         hw->disp_a_stride = dinfo->pitch;
1222         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1223
1224         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1225                           var->xoffset * var->bits_per_pixel / 8;
1226
1227         hw->disp_a_base += dinfo->fb.offset << 12;
1228
1229         /* Check stride alignment. */
1230         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1231                                             STRIDE_ALIGNMENT;
1232         if (hw->disp_a_stride % stride_alignment != 0) {
1233                 WRN_MSG("display stride %d has bad alignment %d\n",
1234                         hw->disp_a_stride, stride_alignment);
1235                 return 1;
1236         }
1237
1238         /* Set the palette to 8-bit mode. */
1239         *pipe_conf &= ~PIPECONF_GAMMA;
1240
1241         if (var->vmode & FB_VMODE_INTERLACED)
1242                 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1243         else
1244                 *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1245
1246         return 0;
1247 }
1248
1249 /* Program a (non-VGA) video mode. */
1250 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1251                            const struct intelfb_hwstate *hw, int blank)
1252 {
1253         int pipe = PIPE_A;
1254         u32 tmp;
1255         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1256         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1257         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg;
1258         u32 hsync_reg, htotal_reg, hblank_reg;
1259         u32 vsync_reg, vtotal_reg, vblank_reg;
1260         u32 src_size_reg;
1261         u32 count, tmp_val[3];
1262
1263         /* Assume single pipe, display plane A, analog CRT. */
1264
1265 #if VERBOSE > 0
1266         DBG_MSG("intelfbhw_program_mode\n");
1267 #endif
1268
1269         /* Disable VGA */
1270         tmp = INREG(VGACNTRL);
1271         tmp |= VGA_DISABLE;
1272         OUTREG(VGACNTRL, tmp);
1273
1274         /* Check whether pipe A or pipe B is enabled. */
1275         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1276                 pipe = PIPE_A;
1277         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1278                 pipe = PIPE_B;
1279
1280         dinfo->pipe = pipe;
1281
1282         if (pipe == PIPE_B) {
1283                 dpll = &hw->dpll_b;
1284                 fp0 = &hw->fpb0;
1285                 fp1 = &hw->fpb1;
1286                 pipe_conf = &hw->pipe_b_conf;
1287                 hs = &hw->hsync_b;
1288                 hb = &hw->hblank_b;
1289                 ht = &hw->htotal_b;
1290                 vs = &hw->vsync_b;
1291                 vb = &hw->vblank_b;
1292                 vt = &hw->vtotal_b;
1293                 ss = &hw->src_size_b;
1294                 dpll_reg = DPLL_B;
1295                 fp0_reg = FPB0;
1296                 fp1_reg = FPB1;
1297                 pipe_conf_reg = PIPEBCONF;
1298                 pipe_stat_reg = PIPEBSTAT;
1299                 hsync_reg = HSYNC_B;
1300                 htotal_reg = HTOTAL_B;
1301                 hblank_reg = HBLANK_B;
1302                 vsync_reg = VSYNC_B;
1303                 vtotal_reg = VTOTAL_B;
1304                 vblank_reg = VBLANK_B;
1305                 src_size_reg = SRC_SIZE_B;
1306         } else {
1307                 dpll = &hw->dpll_a;
1308                 fp0 = &hw->fpa0;
1309                 fp1 = &hw->fpa1;
1310                 pipe_conf = &hw->pipe_a_conf;
1311                 hs = &hw->hsync_a;
1312                 hb = &hw->hblank_a;
1313                 ht = &hw->htotal_a;
1314                 vs = &hw->vsync_a;
1315                 vb = &hw->vblank_a;
1316                 vt = &hw->vtotal_a;
1317                 ss = &hw->src_size_a;
1318                 dpll_reg = DPLL_A;
1319                 fp0_reg = FPA0;
1320                 fp1_reg = FPA1;
1321                 pipe_conf_reg = PIPEACONF;
1322                 pipe_stat_reg = PIPEASTAT;
1323                 hsync_reg = HSYNC_A;
1324                 htotal_reg = HTOTAL_A;
1325                 hblank_reg = HBLANK_A;
1326                 vsync_reg = VSYNC_A;
1327                 vtotal_reg = VTOTAL_A;
1328                 vblank_reg = VBLANK_A;
1329                 src_size_reg = SRC_SIZE_A;
1330         }
1331
1332         /* turn off pipe */
1333         tmp = INREG(pipe_conf_reg);
1334         tmp &= ~PIPECONF_ENABLE;
1335         OUTREG(pipe_conf_reg, tmp);
1336
1337         count = 0;
1338         do {
1339                 tmp_val[count % 3] = INREG(PIPEA_DSL);
1340                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1341                         break;
1342                 count++;
1343                 udelay(1);
1344                 if (count % 200 == 0) {
1345                         tmp = INREG(pipe_conf_reg);
1346                         tmp &= ~PIPECONF_ENABLE;
1347                         OUTREG(pipe_conf_reg, tmp);
1348                 }
1349         } while (count < 2000);
1350
1351         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1352
1353         /* Disable planes A and B. */
1354         tmp = INREG(DSPACNTR);
1355         tmp &= ~DISPPLANE_PLANE_ENABLE;
1356         OUTREG(DSPACNTR, tmp);
1357         tmp = INREG(DSPBCNTR);
1358         tmp &= ~DISPPLANE_PLANE_ENABLE;
1359         OUTREG(DSPBCNTR, tmp);
1360
1361         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1362         mdelay(20);
1363
1364         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1365         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1366         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1367
1368         /* Disable Sync */
1369         tmp = INREG(ADPA);
1370         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1371         tmp |= ADPA_DPMS_D3;
1372         OUTREG(ADPA, tmp);
1373
1374         /* do some funky magic - xyzzy */
1375         OUTREG(0x61204, 0xabcd0000);
1376
1377         /* turn off PLL */
1378         tmp = INREG(dpll_reg);
1379         tmp &= ~DPLL_VCO_ENABLE;
1380         OUTREG(dpll_reg, tmp);
1381
1382         /* Set PLL parameters */
1383         OUTREG(fp0_reg, *fp0);
1384         OUTREG(fp1_reg, *fp1);
1385
1386         /* Enable PLL */
1387         OUTREG(dpll_reg, *dpll);
1388
1389         /* Set DVOs B/C */
1390         OUTREG(DVOB, hw->dvob);
1391         OUTREG(DVOC, hw->dvoc);
1392
1393         /* undo funky magic */
1394         OUTREG(0x61204, 0x00000000);
1395
1396         /* Set ADPA */
1397         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1398         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1399
1400         /* Set pipe parameters */
1401         OUTREG(hsync_reg, *hs);
1402         OUTREG(hblank_reg, *hb);
1403         OUTREG(htotal_reg, *ht);
1404         OUTREG(vsync_reg, *vs);
1405         OUTREG(vblank_reg, *vb);
1406         OUTREG(vtotal_reg, *vt);
1407         OUTREG(src_size_reg, *ss);
1408
1409         switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1410                                           FB_VMODE_ODD_FLD_FIRST)) {
1411         case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST:
1412                 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN);
1413                 break;
1414         case FB_VMODE_INTERLACED: /* even lines first */
1415                 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN);
1416                 break;
1417         default:                /* non-interlaced */
1418                 OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */
1419         }
1420         /* Enable pipe */
1421         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1422
1423         /* Enable sync */
1424         tmp = INREG(ADPA);
1425         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1426         tmp |= ADPA_DPMS_D0;
1427         OUTREG(ADPA, tmp);
1428
1429         /* setup display plane */
1430         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1431                 /*
1432                  *      i830M errata: the display plane must be enabled
1433                  *      to allow writes to the other bits in the plane
1434                  *      control register.
1435                  */
1436                 tmp = INREG(DSPACNTR);
1437                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1438                         tmp |= DISPPLANE_PLANE_ENABLE;
1439                         OUTREG(DSPACNTR, tmp);
1440                         OUTREG(DSPACNTR,
1441                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1442                         mdelay(1);
1443                 }
1444         }
1445
1446         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1447         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1448         OUTREG(DSPABASE, hw->disp_a_base);
1449
1450         /* Enable plane */
1451         if (!blank) {
1452                 tmp = INREG(DSPACNTR);
1453                 tmp |= DISPPLANE_PLANE_ENABLE;
1454                 OUTREG(DSPACNTR, tmp);
1455                 OUTREG(DSPABASE, hw->disp_a_base);
1456         }
1457
1458         return 0;
1459 }
1460
1461 /* forward declarations */
1462 static void refresh_ring(struct intelfb_info *dinfo);
1463 static void reset_state(struct intelfb_info *dinfo);
1464 static void do_flush(struct intelfb_info *dinfo);
1465
1466 static  u32 get_ring_space(struct intelfb_info *dinfo)
1467 {
1468         u32 ring_space;
1469
1470         if (dinfo->ring_tail >= dinfo->ring_head)
1471                 ring_space = dinfo->ring.size -
1472                         (dinfo->ring_tail - dinfo->ring_head);
1473         else
1474                 ring_space = dinfo->ring_head - dinfo->ring_tail;
1475
1476         if (ring_space > RING_MIN_FREE)
1477                 ring_space -= RING_MIN_FREE;
1478         else
1479                 ring_space = 0;
1480
1481         return ring_space;
1482 }
1483
1484 static int wait_ring(struct intelfb_info *dinfo, int n)
1485 {
1486         int i = 0;
1487         unsigned long end;
1488         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1489
1490 #if VERBOSE > 0
1491         DBG_MSG("wait_ring: %d\n", n);
1492 #endif
1493
1494         end = jiffies + (HZ * 3);
1495         while (dinfo->ring_space < n) {
1496                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1497                 dinfo->ring_space = get_ring_space(dinfo);
1498
1499                 if (dinfo->ring_head != last_head) {
1500                         end = jiffies + (HZ * 3);
1501                         last_head = dinfo->ring_head;
1502                 }
1503                 i++;
1504                 if (time_before(end, jiffies)) {
1505                         if (!i) {
1506                                 /* Try again */
1507                                 reset_state(dinfo);
1508                                 refresh_ring(dinfo);
1509                                 do_flush(dinfo);
1510                                 end = jiffies + (HZ * 3);
1511                                 i = 1;
1512                         } else {
1513                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1514                                         dinfo->ring_space, n);
1515                                 WRN_MSG("lockup - turning off hardware "
1516                                         "acceleration\n");
1517                                 dinfo->ring_lockup = 1;
1518                                 break;
1519                         }
1520                 }
1521                 udelay(1);
1522         }
1523         return i;
1524 }
1525
1526 static void do_flush(struct intelfb_info *dinfo)
1527 {
1528         START_RING(2);
1529         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1530         OUT_RING(MI_NOOP);
1531         ADVANCE_RING();
1532 }
1533
1534 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1535 {
1536 #if VERBOSE > 0
1537         DBG_MSG("intelfbhw_do_sync\n");
1538 #endif
1539
1540         if (!dinfo->accel)
1541                 return;
1542
1543         /*
1544          * Send a flush, then wait until the ring is empty.  This is what
1545          * the XFree86 driver does, and actually it doesn't seem a lot worse
1546          * than the recommended method (both have problems).
1547          */
1548         do_flush(dinfo);
1549         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1550         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1551 }
1552
1553 static void refresh_ring(struct intelfb_info *dinfo)
1554 {
1555 #if VERBOSE > 0
1556         DBG_MSG("refresh_ring\n");
1557 #endif
1558
1559         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1560         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1561         dinfo->ring_space = get_ring_space(dinfo);
1562 }
1563
1564 static void reset_state(struct intelfb_info *dinfo)
1565 {
1566         int i;
1567         u32 tmp;
1568
1569 #if VERBOSE > 0
1570         DBG_MSG("reset_state\n");
1571 #endif
1572
1573         for (i = 0; i < FENCE_NUM; i++)
1574                 OUTREG(FENCE + (i << 2), 0);
1575
1576         /* Flush the ring buffer if it's enabled. */
1577         tmp = INREG(PRI_RING_LENGTH);
1578         if (tmp & RING_ENABLE) {
1579 #if VERBOSE > 0
1580                 DBG_MSG("reset_state: ring was enabled\n");
1581 #endif
1582                 refresh_ring(dinfo);
1583                 intelfbhw_do_sync(dinfo);
1584                 DO_RING_IDLE();
1585         }
1586
1587         OUTREG(PRI_RING_LENGTH, 0);
1588         OUTREG(PRI_RING_HEAD, 0);
1589         OUTREG(PRI_RING_TAIL, 0);
1590         OUTREG(PRI_RING_START, 0);
1591 }
1592
1593 /* Stop the 2D engine, and turn off the ring buffer. */
1594 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1595 {
1596 #if VERBOSE > 0
1597         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1598                 dinfo->accel, dinfo->ring_active);
1599 #endif
1600
1601         if (!dinfo->accel)
1602                 return;
1603
1604         dinfo->ring_active = 0;
1605         reset_state(dinfo);
1606 }
1607
1608 /*
1609  * Enable the ring buffer, and initialise the 2D engine.
1610  * It is assumed that the graphics engine has been stopped by previously
1611  * calling intelfb_2d_stop().
1612  */
1613 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1614 {
1615 #if VERBOSE > 0
1616         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1617                 dinfo->accel, dinfo->ring_active);
1618 #endif
1619
1620         if (!dinfo->accel)
1621                 return;
1622
1623         /* Initialise the primary ring buffer. */
1624         OUTREG(PRI_RING_LENGTH, 0);
1625         OUTREG(PRI_RING_TAIL, 0);
1626         OUTREG(PRI_RING_HEAD, 0);
1627
1628         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1629         OUTREG(PRI_RING_LENGTH,
1630                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1631                 RING_NO_REPORT | RING_ENABLE);
1632         refresh_ring(dinfo);
1633         dinfo->ring_active = 1;
1634 }
1635
1636 /* 2D fillrect (solid fill or invert) */
1637 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1638                            u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
1639 {
1640         u32 br00, br09, br13, br14, br16;
1641
1642 #if VERBOSE > 0
1643         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1644                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1645 #endif
1646
1647         br00 = COLOR_BLT_CMD;
1648         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1649         br13 = (rop << ROP_SHIFT) | pitch;
1650         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1651         br16 = color;
1652
1653         switch (bpp) {
1654         case 8:
1655                 br13 |= COLOR_DEPTH_8;
1656                 break;
1657         case 16:
1658                 br13 |= COLOR_DEPTH_16;
1659                 break;
1660         case 32:
1661                 br13 |= COLOR_DEPTH_32;
1662                 br00 |= WRITE_ALPHA | WRITE_RGB;
1663                 break;
1664         }
1665
1666         START_RING(6);
1667         OUT_RING(br00);
1668         OUT_RING(br13);
1669         OUT_RING(br14);
1670         OUT_RING(br09);
1671         OUT_RING(br16);
1672         OUT_RING(MI_NOOP);
1673         ADVANCE_RING();
1674
1675 #if VERBOSE > 0
1676         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1677                 dinfo->ring_tail, dinfo->ring_space);
1678 #endif
1679 }
1680
1681 void
1682 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1683                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1684 {
1685         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1686
1687 #if VERBOSE > 0
1688         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1689                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1690 #endif
1691
1692         br00 = XY_SRC_COPY_BLT_CMD;
1693         br09 = dinfo->fb_start;
1694         br11 = (pitch << PITCH_SHIFT);
1695         br12 = dinfo->fb_start;
1696         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1697         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1698         br23 = ((dstx + w) << WIDTH_SHIFT) |
1699                ((dsty + h) << HEIGHT_SHIFT);
1700         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1701
1702         switch (bpp) {
1703         case 8:
1704                 br13 |= COLOR_DEPTH_8;
1705                 break;
1706         case 16:
1707                 br13 |= COLOR_DEPTH_16;
1708                 break;
1709         case 32:
1710                 br13 |= COLOR_DEPTH_32;
1711                 br00 |= WRITE_ALPHA | WRITE_RGB;
1712                 break;
1713         }
1714
1715         START_RING(8);
1716         OUT_RING(br00);
1717         OUT_RING(br13);
1718         OUT_RING(br22);
1719         OUT_RING(br23);
1720         OUT_RING(br09);
1721         OUT_RING(br26);
1722         OUT_RING(br11);
1723         OUT_RING(br12);
1724         ADVANCE_RING();
1725 }
1726
1727 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1728                            u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
1729                            u32 bpp)
1730 {
1731         int nbytes, ndwords, pad, tmp;
1732         u32 br00, br09, br13, br18, br19, br22, br23;
1733         int dat, ix, iy, iw;
1734         int i, j;
1735
1736 #if VERBOSE > 0
1737         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1738 #endif
1739
1740         /* size in bytes of a padded scanline */
1741         nbytes = ROUND_UP_TO(w, 16) / 8;
1742
1743         /* Total bytes of padded scanline data to write out. */
1744         nbytes = nbytes * h;
1745
1746         /*
1747          * Check if the glyph data exceeds the immediate mode limit.
1748          * It would take a large font (1K pixels) to hit this limit.
1749          */
1750         if (nbytes > MAX_MONO_IMM_SIZE)
1751                 return 0;
1752
1753         /* Src data is packaged a dword (32-bit) at a time. */
1754         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1755
1756         /*
1757          * Ring has to be padded to a quad word. But because the command starts
1758            with 7 bytes, pad only if there is an even number of ndwords
1759          */
1760         pad = !(ndwords % 2);
1761
1762         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1763         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1764         br09 = dinfo->fb_start;
1765         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1766         br18 = bg;
1767         br19 = fg;
1768         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1769         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1770
1771         switch (bpp) {
1772         case 8:
1773                 br13 |= COLOR_DEPTH_8;
1774                 break;
1775         case 16:
1776                 br13 |= COLOR_DEPTH_16;
1777                 break;
1778         case 32:
1779                 br13 |= COLOR_DEPTH_32;
1780                 br00 |= WRITE_ALPHA | WRITE_RGB;
1781                 break;
1782         }
1783
1784         START_RING(8 + ndwords);
1785         OUT_RING(br00);
1786         OUT_RING(br13);
1787         OUT_RING(br22);
1788         OUT_RING(br23);
1789         OUT_RING(br09);
1790         OUT_RING(br18);
1791         OUT_RING(br19);
1792         ix = iy = 0;
1793         iw = ROUND_UP_TO(w, 8) / 8;
1794         while (ndwords--) {
1795                 dat = 0;
1796                 for (j = 0; j < 2; ++j) {
1797                         for (i = 0; i < 2; ++i) {
1798                                 if (ix != iw || i == 0)
1799                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1800                         }
1801                         if (ix == iw && iy != (h-1)) {
1802                                 ix = 0;
1803                                 ++iy;
1804                         }
1805                 }
1806                 OUT_RING(dat);
1807         }
1808         if (pad)
1809                 OUT_RING(MI_NOOP);
1810         ADVANCE_RING();
1811
1812         return 1;
1813 }
1814
1815 /* HW cursor functions. */
1816 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1817 {
1818         u32 tmp;
1819
1820 #if VERBOSE > 0
1821         DBG_MSG("intelfbhw_cursor_init\n");
1822 #endif
1823
1824         if (dinfo->mobile || IS_I9XX(dinfo)) {
1825                 if (!dinfo->cursor.physical)
1826                         return;
1827                 tmp = INREG(CURSOR_A_CONTROL);
1828                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1829                          CURSOR_MEM_TYPE_LOCAL |
1830                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1831                 tmp |= CURSOR_MODE_DISABLE;
1832                 OUTREG(CURSOR_A_CONTROL, tmp);
1833                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1834         } else {
1835                 tmp = INREG(CURSOR_CONTROL);
1836                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1837                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1838                 tmp = CURSOR_FORMAT_3C;
1839                 OUTREG(CURSOR_CONTROL, tmp);
1840                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1841                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1842                       (64 << CURSOR_SIZE_V_SHIFT);
1843                 OUTREG(CURSOR_SIZE, tmp);
1844         }
1845 }
1846
1847 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1848 {
1849         u32 tmp;
1850
1851 #if VERBOSE > 0
1852         DBG_MSG("intelfbhw_cursor_hide\n");
1853 #endif
1854
1855         dinfo->cursor_on = 0;
1856         if (dinfo->mobile || IS_I9XX(dinfo)) {
1857                 if (!dinfo->cursor.physical)
1858                         return;
1859                 tmp = INREG(CURSOR_A_CONTROL);
1860                 tmp &= ~CURSOR_MODE_MASK;
1861                 tmp |= CURSOR_MODE_DISABLE;
1862                 OUTREG(CURSOR_A_CONTROL, tmp);
1863                 /* Flush changes */
1864                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1865         } else {
1866                 tmp = INREG(CURSOR_CONTROL);
1867                 tmp &= ~CURSOR_ENABLE;
1868                 OUTREG(CURSOR_CONTROL, tmp);
1869         }
1870 }
1871
1872 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1873 {
1874         u32 tmp;
1875
1876 #if VERBOSE > 0
1877         DBG_MSG("intelfbhw_cursor_show\n");
1878 #endif
1879
1880         dinfo->cursor_on = 1;
1881
1882         if (dinfo->cursor_blanked)
1883                 return;
1884
1885         if (dinfo->mobile || IS_I9XX(dinfo)) {
1886                 if (!dinfo->cursor.physical)
1887                         return;
1888                 tmp = INREG(CURSOR_A_CONTROL);
1889                 tmp &= ~CURSOR_MODE_MASK;
1890                 tmp |= CURSOR_MODE_64_4C_AX;
1891                 OUTREG(CURSOR_A_CONTROL, tmp);
1892                 /* Flush changes */
1893                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1894         } else {
1895                 tmp = INREG(CURSOR_CONTROL);
1896                 tmp |= CURSOR_ENABLE;
1897                 OUTREG(CURSOR_CONTROL, tmp);
1898         }
1899 }
1900
1901 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1902 {
1903         u32 tmp;
1904
1905 #if VERBOSE > 0
1906         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1907 #endif
1908
1909         /*
1910          * Sets the position. The coordinates are assumed to already
1911          * have any offset adjusted. Assume that the cursor is never
1912          * completely off-screen, and that x, y are always >= 0.
1913          */
1914
1915         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1916               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1917         OUTREG(CURSOR_A_POSITION, tmp);
1918
1919         if (IS_I9XX(dinfo))
1920                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1921 }
1922
1923 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1924 {
1925 #if VERBOSE > 0
1926         DBG_MSG("intelfbhw_cursor_setcolor\n");
1927 #endif
1928
1929         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1930         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1931         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1932         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1933 }
1934
1935 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1936                            u8 *data)
1937 {
1938         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1939         int i, j, w = width / 8;
1940         int mod = width % 8, t_mask, d_mask;
1941
1942 #if VERBOSE > 0
1943         DBG_MSG("intelfbhw_cursor_load\n");
1944 #endif
1945
1946         if (!dinfo->cursor.virtual)
1947                 return;
1948
1949         t_mask = 0xff >> mod;
1950         d_mask = ~(0xff >> mod);
1951         for (i = height; i--; ) {
1952                 for (j = 0; j < w; j++) {
1953                         writeb(0x00, addr + j);
1954                         writeb(*(data++), addr + j+8);
1955                 }
1956                 if (mod) {
1957                         writeb(t_mask, addr + j);
1958                         writeb(*(data++) & d_mask, addr + j+8);
1959                 }
1960                 addr += 16;
1961         }
1962 }
1963
1964 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1965 {
1966         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1967         int i, j;
1968
1969 #if VERBOSE > 0
1970         DBG_MSG("intelfbhw_cursor_reset\n");
1971 #endif
1972
1973         if (!dinfo->cursor.virtual)
1974                 return;
1975
1976         for (i = 64; i--; ) {
1977                 for (j = 0; j < 8; j++) {
1978                         writeb(0xff, addr + j+0);
1979                         writeb(0x00, addr + j+8);
1980                 }
1981                 addr += 16;
1982         }
1983 }
1984
1985 static irqreturn_t intelfbhw_irq(int irq, void *dev_id)
1986 {
1987         u16 tmp;
1988         struct intelfb_info *dinfo = dev_id;
1989
1990         spin_lock(&dinfo->int_lock);
1991
1992         tmp = INREG16(IIR);
1993         if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
1994                 tmp &= PIPE_A_EVENT_INTERRUPT;
1995         else
1996                 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
1997
1998         if (tmp == 0) {
1999                 spin_unlock(&dinfo->int_lock);
2000                 return IRQ_RETVAL(0); /* not us */
2001         }
2002
2003         /* clear status bits 0-15 ASAP and don't touch bits 16-31 */
2004         OUTREG(PIPEASTAT, INREG(PIPEASTAT));
2005
2006         OUTREG16(IIR, tmp);
2007         if (dinfo->vsync.pan_display) {
2008                 dinfo->vsync.pan_display = 0;
2009                 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2010         }
2011
2012         dinfo->vsync.count++;
2013         wake_up_interruptible(&dinfo->vsync.wait);
2014
2015         spin_unlock(&dinfo->int_lock);
2016
2017         return IRQ_RETVAL(1);
2018 }
2019
2020 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2021 {
2022         u16 tmp;
2023         if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2024                 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2025                                 "intelfb", dinfo)) {
2026                         clear_bit(0, &dinfo->irq_flags);
2027                         return -EINVAL;
2028                 }
2029
2030                 spin_lock_irq(&dinfo->int_lock);
2031                 OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */
2032                 OUTREG16(IMR, 0);
2033         } else
2034                 spin_lock_irq(&dinfo->int_lock);
2035
2036         if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2037                 tmp = PIPE_A_EVENT_INTERRUPT;
2038         else
2039                 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2040         if (tmp != INREG16(IER)) {
2041                 DBG_MSG("changing IER to 0x%X\n", tmp);
2042                 OUTREG16(IER, tmp);
2043         }
2044
2045         spin_unlock_irq(&dinfo->int_lock);
2046         return 0;
2047 }
2048
2049 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2050 {
2051         if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2052                 if (dinfo->vsync.pan_display) {
2053                         dinfo->vsync.pan_display = 0;
2054                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2055                 }
2056                 spin_lock_irq(&dinfo->int_lock);
2057                 OUTREG16(HWSTAM, 0xffff);
2058                 OUTREG16(IMR, 0xffff);
2059                 OUTREG16(IER, 0x0);
2060
2061                 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2062                 spin_unlock_irq(&dinfo->int_lock);
2063
2064                 free_irq(dinfo->pdev->irq, dinfo);
2065         }
2066 }
2067
2068 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2069 {
2070         struct intelfb_vsync *vsync;
2071         unsigned int count;
2072         int ret;
2073
2074         switch (pipe) {
2075                 case 0:
2076                         vsync = &dinfo->vsync;
2077                         break;
2078                 default:
2079                         return -ENODEV;
2080         }
2081
2082         ret = intelfbhw_enable_irq(dinfo);
2083         if (ret)
2084                 return ret;
2085
2086         count = vsync->count;
2087         ret = wait_event_interruptible_timeout(vsync->wait,
2088                                                count != vsync->count, HZ / 10);
2089         if (ret < 0)
2090                 return ret;
2091         if (ret == 0) {
2092                 DBG_MSG("wait_for_vsync timed out!\n");
2093                 return -ETIMEDOUT;
2094         }
2095
2096         return 0;
2097 }