2 * linux/drivers/video/pxafb.c
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
10 * Based on acornfb.c Copyright (C) Russell King.
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
18 * Please direct your questions and comments on this driver to the following
21 * linux-arm-kernel@lists.arm.linux.org.uk
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/errno.h>
30 #include <linux/string.h>
31 #include <linux/interrupt.h>
32 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/platform_device.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/completion.h>
44 #include <linux/mutex.h>
45 #include <linux/kthread.h>
46 #include <linux/freezer.h>
48 #include <asm/hardware.h>
51 #include <asm/div64.h>
52 #include <asm/arch/pxa-regs.h>
53 #include <asm/arch/pxa2xx-gpio.h>
54 #include <asm/arch/bitfield.h>
55 #include <asm/arch/pxafb.h>
58 * Complain if VAR is out of range.
64 /* Bits which should not be set in machine configuration structures */
65 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
66 LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
67 LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
69 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\
70 LCCR3_PCD | LCCR3_BPP)
72 static void (*pxafb_backlight_power)(int);
73 static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
75 static int pxafb_activate_var(struct fb_var_screeninfo *var,
77 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
79 static inline unsigned long
80 lcd_readl(struct pxafb_info *fbi, unsigned int off)
82 return __raw_readl(fbi->mmio_base + off);
86 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
88 __raw_writel(val, fbi->mmio_base + off);
91 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
95 local_irq_save(flags);
97 * We need to handle two requests being made at the same time.
98 * There are two important cases:
99 * 1. When we are changing VT (C_REENABLE) while unblanking
100 * (C_ENABLE) We must perform the unblanking, which will
101 * do our REENABLE for us.
102 * 2. When we are blanking, but immediately unblank before
103 * we have blanked. We do the "REENABLE" thing here as
104 * well, just to be sure.
106 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
108 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
111 if (state != (u_int)-1) {
112 fbi->task_state = state;
113 schedule_work(&fbi->task);
115 local_irq_restore(flags);
118 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
121 chan >>= 16 - bf->length;
122 return chan << bf->offset;
126 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
127 u_int trans, struct fb_info *info)
129 struct pxafb_info *fbi = (struct pxafb_info *)info;
132 if (regno >= fbi->palette_size)
135 if (fbi->fb.var.grayscale) {
136 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
140 switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
141 case LCCR4_PAL_FOR_0:
142 val = ((red >> 0) & 0xf800);
143 val |= ((green >> 5) & 0x07e0);
144 val |= ((blue >> 11) & 0x001f);
145 fbi->palette_cpu[regno] = val;
147 case LCCR4_PAL_FOR_1:
148 val = ((red << 8) & 0x00f80000);
149 val |= ((green >> 0) & 0x0000fc00);
150 val |= ((blue >> 8) & 0x000000f8);
151 ((u32 *)(fbi->palette_cpu))[regno] = val;
153 case LCCR4_PAL_FOR_2:
154 val = ((red << 8) & 0x00fc0000);
155 val |= ((green >> 0) & 0x0000fc00);
156 val |= ((blue >> 8) & 0x000000fc);
157 ((u32 *)(fbi->palette_cpu))[regno] = val;
165 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
166 u_int trans, struct fb_info *info)
168 struct pxafb_info *fbi = (struct pxafb_info *)info;
173 * If inverse mode was selected, invert all the colours
174 * rather than the register number. The register number
175 * is what you poke into the framebuffer to produce the
176 * colour you requested.
178 if (fbi->cmap_inverse) {
180 green = 0xffff - green;
181 blue = 0xffff - blue;
185 * If greyscale is true, then we convert the RGB value
186 * to greyscale no matter what visual we are using.
188 if (fbi->fb.var.grayscale)
189 red = green = blue = (19595 * red + 38470 * green +
192 switch (fbi->fb.fix.visual) {
193 case FB_VISUAL_TRUECOLOR:
195 * 16-bit True Colour. We encode the RGB value
196 * according to the RGB bitfield information.
199 u32 *pal = fbi->fb.pseudo_palette;
201 val = chan_to_field(red, &fbi->fb.var.red);
202 val |= chan_to_field(green, &fbi->fb.var.green);
203 val |= chan_to_field(blue, &fbi->fb.var.blue);
210 case FB_VISUAL_STATIC_PSEUDOCOLOR:
211 case FB_VISUAL_PSEUDOCOLOR:
212 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
220 * pxafb_bpp_to_lccr3():
221 * Convert a bits per pixel value to the correct bit pattern for LCCR3
223 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
226 switch (var->bits_per_pixel) {
227 case 1: ret = LCCR3_1BPP; break;
228 case 2: ret = LCCR3_2BPP; break;
229 case 4: ret = LCCR3_4BPP; break;
230 case 8: ret = LCCR3_8BPP; break;
231 case 16: ret = LCCR3_16BPP; break;
233 switch (var->red.length + var->green.length +
234 var->blue.length + var->transp.length) {
235 case 18: ret = LCCR3_18BPP_P | LCCR3_PDFOR_3; break;
236 case 19: ret = LCCR3_19BPP_P; break;
240 switch (var->red.length + var->green.length +
241 var->blue.length + var->transp.length) {
242 case 18: ret = LCCR3_18BPP | LCCR3_PDFOR_3; break;
243 case 19: ret = LCCR3_19BPP; break;
244 case 24: ret = LCCR3_24BPP | LCCR3_PDFOR_3; break;
245 case 25: ret = LCCR3_25BPP; break;
252 #ifdef CONFIG_CPU_FREQ
254 * pxafb_display_dma_period()
255 * Calculate the minimum period (in picoseconds) between two DMA
256 * requests for the LCD controller. If we hit this, it means we're
257 * doing nothing but LCD DMA.
259 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
262 * Period = pixclock * bits_per_byte * bytes_per_transfer
263 * / memory_bits_per_pixel;
265 return var->pixclock * 8 * 16 / var->bits_per_pixel;
270 * Select the smallest mode that allows the desired resolution to be
271 * displayed. If desired parameters can be rounded up.
273 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
274 struct fb_var_screeninfo *var)
276 struct pxafb_mode_info *mode = NULL;
277 struct pxafb_mode_info *modelist = mach->modes;
278 unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
281 for (i = 0; i < mach->num_modes; i++) {
282 if (modelist[i].xres >= var->xres &&
283 modelist[i].yres >= var->yres &&
284 modelist[i].xres < best_x &&
285 modelist[i].yres < best_y &&
286 modelist[i].bpp >= var->bits_per_pixel) {
287 best_x = modelist[i].xres;
288 best_y = modelist[i].yres;
296 static void pxafb_setmode(struct fb_var_screeninfo *var,
297 struct pxafb_mode_info *mode)
299 var->xres = mode->xres;
300 var->yres = mode->yres;
301 var->bits_per_pixel = mode->bpp;
302 var->pixclock = mode->pixclock;
303 var->hsync_len = mode->hsync_len;
304 var->left_margin = mode->left_margin;
305 var->right_margin = mode->right_margin;
306 var->vsync_len = mode->vsync_len;
307 var->upper_margin = mode->upper_margin;
308 var->lower_margin = mode->lower_margin;
309 var->sync = mode->sync;
310 var->grayscale = mode->cmap_greyscale;
311 var->xres_virtual = var->xres;
312 var->yres_virtual = var->yres;
317 * Get the video params out of 'var'. If a value doesn't fit, round it up,
318 * if it's too big, return -EINVAL.
320 * Round up in the following order: bits_per_pixel, xres,
321 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
322 * bitfields, horizontal timing, vertical timing.
324 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
326 struct pxafb_info *fbi = (struct pxafb_info *)info;
327 struct pxafb_mach_info *inf = fbi->dev->platform_data;
329 if (var->xres < MIN_XRES)
330 var->xres = MIN_XRES;
331 if (var->yres < MIN_YRES)
332 var->yres = MIN_YRES;
334 if (inf->fixed_modes) {
335 struct pxafb_mode_info *mode;
337 mode = pxafb_getmode(inf, var);
340 pxafb_setmode(var, mode);
342 if (var->xres > inf->modes->xres)
344 if (var->yres > inf->modes->yres)
346 if (var->bits_per_pixel > inf->modes->bpp)
351 max(var->xres_virtual, var->xres);
353 max(var->yres_virtual, var->yres);
356 * Setup the RGB parameters for this display.
358 * The pixel packing format is described on page 7-11 of the
359 * PXA2XX Developer's Manual.
361 if (var->bits_per_pixel == 16) {
362 var->red.offset = 11; var->red.length = 5;
363 var->green.offset = 5; var->green.length = 6;
364 var->blue.offset = 0; var->blue.length = 5;
365 var->transp.offset = var->transp.length = 0;
366 } else if (var->bits_per_pixel > 16) {
367 struct pxafb_mode_info *mode;
369 mode = pxafb_getmode(inf, var);
373 switch (mode->depth) {
374 case 18: /* RGB666 */
375 var->transp.offset = var->transp.length = 0;
376 var->red.offset = 12; var->red.length = 6;
377 var->green.offset = 6; var->green.length = 6;
378 var->blue.offset = 0; var->blue.length = 6;
380 case 19: /* RGBT666 */
381 var->transp.offset = 18; var->transp.length = 1;
382 var->red.offset = 12; var->red.length = 6;
383 var->green.offset = 6; var->green.length = 6;
384 var->blue.offset = 0; var->blue.length = 6;
386 case 24: /* RGB888 */
387 var->transp.offset = var->transp.length = 0;
388 var->red.offset = 16; var->red.length = 8;
389 var->green.offset = 8; var->green.length = 8;
390 var->blue.offset = 0; var->blue.length = 8;
392 case 25: /* RGBT888 */
393 var->transp.offset = 24; var->transp.length = 1;
394 var->red.offset = 16; var->red.length = 8;
395 var->green.offset = 8; var->green.length = 8;
396 var->blue.offset = 0; var->blue.length = 8;
402 var->red.offset = var->green.offset = 0;
403 var->blue.offset = var->transp.offset = 0;
405 var->green.length = 8;
406 var->blue.length = 8;
407 var->transp.length = 0;
410 #ifdef CONFIG_CPU_FREQ
411 pr_debug("pxafb: dma period = %d ps\n",
412 pxafb_display_dma_period(var));
418 static inline void pxafb_set_truecolor(u_int is_true_color)
420 /* do your machine-specific setup if needed */
425 * Set the user defined part of the display for the specified console
427 static int pxafb_set_par(struct fb_info *info)
429 struct pxafb_info *fbi = (struct pxafb_info *)info;
430 struct fb_var_screeninfo *var = &info->var;
432 if (var->bits_per_pixel >= 16)
433 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
434 else if (!fbi->cmap_static)
435 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
438 * Some people have weird ideas about wanting static
439 * pseudocolor maps. I suspect their user space
440 * applications are broken.
442 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
445 fbi->fb.fix.line_length = var->xres_virtual *
446 var->bits_per_pixel / 8;
447 if (var->bits_per_pixel >= 16)
448 fbi->palette_size = 0;
450 fbi->palette_size = var->bits_per_pixel == 1 ?
451 4 : 1 << var->bits_per_pixel;
453 fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
456 * Set (any) board control register to handle new color depth
458 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
460 if (fbi->fb.var.bits_per_pixel >= 16)
461 fb_dealloc_cmap(&fbi->fb.cmap);
463 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
465 pxafb_activate_var(var, fbi);
472 * Blank the display by setting all palette values to zero. Note, the
473 * 16 bpp mode does not really use the palette, so this will not
474 * blank the display in all modes.
476 static int pxafb_blank(int blank, struct fb_info *info)
478 struct pxafb_info *fbi = (struct pxafb_info *)info;
482 case FB_BLANK_POWERDOWN:
483 case FB_BLANK_VSYNC_SUSPEND:
484 case FB_BLANK_HSYNC_SUSPEND:
485 case FB_BLANK_NORMAL:
486 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
487 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
488 for (i = 0; i < fbi->palette_size; i++)
489 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
491 pxafb_schedule_work(fbi, C_DISABLE);
492 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
495 case FB_BLANK_UNBLANK:
496 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
497 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
498 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
499 fb_set_cmap(&fbi->fb.cmap, info);
500 pxafb_schedule_work(fbi, C_ENABLE);
505 static int pxafb_mmap(struct fb_info *info,
506 struct vm_area_struct *vma)
508 struct pxafb_info *fbi = (struct pxafb_info *)info;
509 unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
511 if (off < info->fix.smem_len) {
512 vma->vm_pgoff += fbi->video_offset / PAGE_SIZE;
513 return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
514 fbi->map_dma, fbi->map_size);
519 static struct fb_ops pxafb_ops = {
520 .owner = THIS_MODULE,
521 .fb_check_var = pxafb_check_var,
522 .fb_set_par = pxafb_set_par,
523 .fb_setcolreg = pxafb_setcolreg,
524 .fb_fillrect = cfb_fillrect,
525 .fb_copyarea = cfb_copyarea,
526 .fb_imageblit = cfb_imageblit,
527 .fb_blank = pxafb_blank,
528 .fb_mmap = pxafb_mmap,
532 * Calculate the PCD value from the clock rate (in picoseconds).
533 * We take account of the PPCR clock setting.
534 * From PXA Developer's Manual:
545 * LCLK = LCD/Memory Clock
548 * PixelClock here is in Hz while the pixclock argument given is the
549 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
551 * The function get_lclk_frequency_10khz returns LCLK in units of
552 * 10khz. Calling the result of this function lclk gives us the
555 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
556 * -------------------------------------- - 1
559 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
561 static inline unsigned int get_pcd(struct pxafb_info *fbi,
562 unsigned int pixclock)
564 unsigned long long pcd;
566 /* FIXME: Need to take into account Double Pixel Clock mode
567 * (DPC) bit? or perhaps set it based on the various clock
569 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
571 do_div(pcd, 100000000 * 2);
572 /* no need for this, since we should subtract 1 anyway. they cancel */
573 /* pcd += 1; */ /* make up for integer math truncations */
574 return (unsigned int)pcd;
578 * Some touchscreens need hsync information from the video driver to
579 * function correctly. We export it here. Note that 'hsync_time' and
580 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
581 * of the hsync period in seconds.
583 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
587 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
592 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
594 fbi->hsync_time = htime;
597 unsigned long pxafb_get_hsync_time(struct device *dev)
599 struct pxafb_info *fbi = dev_get_drvdata(dev);
601 /* If display is blanked/suspended, hsync isn't active */
602 if (!fbi || (fbi->state != C_ENABLE))
605 return fbi->hsync_time;
607 EXPORT_SYMBOL(pxafb_get_hsync_time);
609 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
610 unsigned int offset, size_t size)
612 struct pxafb_dma_descriptor *dma_desc, *pal_desc;
613 unsigned int dma_desc_off, pal_desc_off;
615 if (dma < 0 || dma >= DMA_MAX)
618 dma_desc = &fbi->dma_buff->dma_desc[dma];
619 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
621 dma_desc->fsadr = fbi->screen_dma + offset;
623 dma_desc->ldcmd = size;
625 if (pal < 0 || pal >= PAL_MAX) {
626 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
627 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
629 pal_desc = &fbi->dma_buff->pal_desc[pal];
630 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
632 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
635 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
636 pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
638 pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
640 pal_desc->ldcmd |= LDCMD_PAL;
642 /* flip back and forth between palette and frame buffer */
643 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
644 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
645 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
651 #ifdef CONFIG_FB_PXA_SMARTPANEL
652 static int setup_smart_dma(struct pxafb_info *fbi)
654 struct pxafb_dma_descriptor *dma_desc;
655 unsigned long dma_desc_off, cmd_buff_off;
657 dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
658 dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
659 cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
661 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
662 dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
664 dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
666 fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
670 int pxafb_smart_flush(struct fb_info *info)
672 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
676 /* disable controller until all registers are set up */
677 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
679 /* 1. make it an even number of commands to align on 32-bit boundary
680 * 2. add the interrupt command to the end of the chain so we can
681 * keep track of the end of the transfer
684 while (fbi->n_smart_cmds & 1)
685 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
687 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
688 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
689 setup_smart_dma(fbi);
691 /* continue to execute next command */
692 prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
693 lcd_writel(fbi, PRSR, prsr);
695 /* stop the processor in case it executed "wait for sync" cmd */
696 lcd_writel(fbi, CMDCR, 0x0001);
698 /* don't send interrupts for fifo underruns on channel 6 */
699 lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
701 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
702 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
703 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
704 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
705 lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
708 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
710 if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
711 pr_warning("%s: timeout waiting for command done\n",
717 prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
718 lcd_writel(fbi, PRSR, prsr);
719 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
720 lcd_writel(fbi, FDADR6, 0);
721 fbi->n_smart_cmds = 0;
725 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
728 struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
730 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
731 for (i = 0; i < n_cmds; i++) {
732 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
733 pxafb_smart_flush(info);
735 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds++;
741 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
743 unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
744 return (t == 0) ? 1 : t;
747 static void setup_smart_timing(struct pxafb_info *fbi,
748 struct fb_var_screeninfo *var)
750 struct pxafb_mach_info *inf = fbi->dev->platform_data;
751 struct pxafb_mode_info *mode = &inf->modes[0];
752 unsigned long lclk = clk_get_rate(fbi->clk);
753 unsigned t1, t2, t3, t4;
755 t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
756 t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
757 t3 = mode->op_hold_time;
758 t4 = mode->cmd_inh_time;
761 LCCR1_DisWdth(var->xres) |
762 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
763 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
764 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
766 fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
767 fbi->reg_lccr3 = LCCR3_PixClkDiv(__smart_timing(t4, lclk));
769 /* FIXME: make this configurable */
773 static int pxafb_smart_thread(void *arg)
775 struct pxafb_info *fbi = arg;
776 struct pxafb_mach_info *inf = fbi->dev->platform_data;
778 if (!fbi || !inf->smart_update) {
779 pr_err("%s: not properly initialized, thread terminated\n",
784 pr_debug("%s(): task starting\n", __func__);
787 while (!kthread_should_stop()) {
792 if (fbi->state == C_ENABLE) {
793 inf->smart_update(&fbi->fb);
794 complete(&fbi->refresh_done);
797 set_current_state(TASK_INTERRUPTIBLE);
798 schedule_timeout(30 * HZ / 1000);
801 pr_debug("%s(): task ending\n", __func__);
805 static int pxafb_smart_init(struct pxafb_info *fbi)
807 fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
809 if (IS_ERR(fbi->smart_thread)) {
810 printk(KERN_ERR "%s: unable to create kernel thread\n",
812 return PTR_ERR(fbi->smart_thread);
817 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
822 int pxafb_smart_flush(struct fb_info *info)
826 #endif /* CONFIG_FB_SMART_PANEL */
828 static void setup_parallel_timing(struct pxafb_info *fbi,
829 struct fb_var_screeninfo *var)
831 unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
834 LCCR1_DisWdth(var->xres) +
835 LCCR1_HorSnchWdth(var->hsync_len) +
836 LCCR1_BegLnDel(var->left_margin) +
837 LCCR1_EndLnDel(var->right_margin);
840 * If we have a dual scan LCD, we need to halve
841 * the YRES parameter.
843 lines_per_panel = var->yres;
844 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
845 lines_per_panel /= 2;
848 LCCR2_DisHght(lines_per_panel) +
849 LCCR2_VrtSnchWdth(var->vsync_len) +
850 LCCR2_BegFrmDel(var->upper_margin) +
851 LCCR2_EndFrmDel(var->lower_margin);
853 fbi->reg_lccr3 = fbi->lccr3 |
854 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
855 LCCR3_HorSnchH : LCCR3_HorSnchL) |
856 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
857 LCCR3_VrtSnchH : LCCR3_VrtSnchL);
860 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
861 set_hsync_time(fbi, pcd);
866 * pxafb_activate_var():
867 * Configures LCD Controller based on entries in var parameter.
868 * Settings are only written to the controller if changes were made.
870 static int pxafb_activate_var(struct fb_var_screeninfo *var,
871 struct pxafb_info *fbi)
877 if (!(fbi->lccr0 & LCCR0_LCDT)) {
878 if (var->xres < 16 || var->xres > 1024)
879 printk(KERN_ERR "%s: invalid xres %d\n",
880 fbi->fb.fix.id, var->xres);
881 switch (var->bits_per_pixel) {
891 printk(KERN_ERR "%s: invalid bit depth %d\n",
892 fbi->fb.fix.id, var->bits_per_pixel);
896 if (var->hsync_len < 1 || var->hsync_len > 64)
897 printk(KERN_ERR "%s: invalid hsync_len %d\n",
898 fbi->fb.fix.id, var->hsync_len);
899 if (var->left_margin < 1 || var->left_margin > 255)
900 printk(KERN_ERR "%s: invalid left_margin %d\n",
901 fbi->fb.fix.id, var->left_margin);
902 if (var->right_margin < 1 || var->right_margin > 255)
903 printk(KERN_ERR "%s: invalid right_margin %d\n",
904 fbi->fb.fix.id, var->right_margin);
905 if (var->yres < 1 || var->yres > 1024)
906 printk(KERN_ERR "%s: invalid yres %d\n",
907 fbi->fb.fix.id, var->yres);
908 if (var->vsync_len < 1 || var->vsync_len > 64)
909 printk(KERN_ERR "%s: invalid vsync_len %d\n",
910 fbi->fb.fix.id, var->vsync_len);
911 if (var->upper_margin < 0 || var->upper_margin > 255)
912 printk(KERN_ERR "%s: invalid upper_margin %d\n",
913 fbi->fb.fix.id, var->upper_margin);
914 if (var->lower_margin < 0 || var->lower_margin > 255)
915 printk(KERN_ERR "%s: invalid lower_margin %d\n",
916 fbi->fb.fix.id, var->lower_margin);
919 /* Update shadow copy atomically */
920 local_irq_save(flags);
922 #ifdef CONFIG_FB_PXA_SMARTPANEL
923 if (fbi->lccr0 & LCCR0_LCDT)
924 setup_smart_timing(fbi, var);
927 setup_parallel_timing(fbi, var);
929 fbi->reg_lccr0 = fbi->lccr0 |
930 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
931 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
933 fbi->reg_lccr3 |= pxafb_bpp_to_lccr3(var);
935 nbytes = var->yres * fbi->fb.fix.line_length;
937 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) {
939 setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes);
942 if ((var->bits_per_pixel >= 16) || (fbi->lccr0 & LCCR0_LCDT))
943 setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes);
945 setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes);
947 fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
948 fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
949 local_irq_restore(flags);
952 * Only update the registers if the controller is enabled
953 * and something has changed.
955 if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
956 (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
957 (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
958 (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
959 (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
960 (lcd_readl(fbi, FDADR1) != fbi->fdadr[1]))
961 pxafb_schedule_work(fbi, C_REENABLE);
967 * NOTE! The following functions are purely helpers for set_ctrlr_state.
968 * Do not call them directly; set_ctrlr_state does the correct serialisation
969 * to ensure that things happen in the right way 100% of time time.
972 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
974 pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
976 if (pxafb_backlight_power)
977 pxafb_backlight_power(on);
980 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
982 pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
985 pxafb_lcd_power(on, &fbi->fb.var);
988 static void pxafb_setup_gpio(struct pxafb_info *fbi)
991 unsigned int lccr0 = fbi->lccr0;
994 * setup is based on type of panel supported
997 /* 4 bit interface */
998 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
999 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
1000 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
1003 /* 8 bit interface */
1004 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
1005 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1006 (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
1007 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1008 (lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1009 (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
1012 /* 16 bit interface */
1013 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
1014 ((lccr0 & LCCR0_SDS) == LCCR0_Dual ||
1015 (lccr0 & LCCR0_PAS) == LCCR0_Act))
1019 printk(KERN_ERR "pxafb_setup_gpio: unable to determine "
1020 "bits per pixel\n");
1024 for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
1025 pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
1026 /* 18 bit interface */
1027 if (fbi->fb.var.bits_per_pixel > 16) {
1028 pxa_gpio_mode(86 | GPIO_ALT_FN_2_OUT);
1029 pxa_gpio_mode(87 | GPIO_ALT_FN_2_OUT);
1031 pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
1032 pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
1033 pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
1034 pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
1037 static void pxafb_enable_controller(struct pxafb_info *fbi)
1039 pr_debug("pxafb: Enabling LCD controller\n");
1040 pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1041 pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1042 pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1043 pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1044 pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1045 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1047 /* enable LCD controller clock */
1048 clk_enable(fbi->clk);
1050 if (fbi->lccr0 & LCCR0_LCDT)
1053 /* Sequence from 11.7.10 */
1054 lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1055 lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1056 lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1057 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1059 lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1060 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1061 lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1064 static void pxafb_disable_controller(struct pxafb_info *fbi)
1068 #ifdef CONFIG_FB_PXA_SMARTPANEL
1069 if (fbi->lccr0 & LCCR0_LCDT) {
1070 wait_for_completion_timeout(&fbi->refresh_done,
1076 /* Clear LCD Status Register */
1077 lcd_writel(fbi, LCSR, 0xffffffff);
1079 lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1080 lcd_writel(fbi, LCCR0, lccr0);
1081 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1083 wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1085 /* disable LCD controller clock */
1086 clk_disable(fbi->clk);
1090 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1092 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1094 struct pxafb_info *fbi = dev_id;
1095 unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR);
1097 if (lcsr & LCSR_LDD) {
1098 lccr0 = lcd_readl(fbi, LCCR0);
1099 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1100 complete(&fbi->disable_done);
1103 #ifdef CONFIG_FB_PXA_SMARTPANEL
1104 if (lcsr & LCSR_CMD_INT)
1105 complete(&fbi->command_done);
1108 lcd_writel(fbi, LCSR, lcsr);
1113 * This function must be called from task context only, since it will
1114 * sleep when disabling the LCD controller, or if we get two contending
1115 * processes trying to alter state.
1117 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1121 mutex_lock(&fbi->ctrlr_lock);
1123 old_state = fbi->state;
1126 * Hack around fbcon initialisation.
1128 if (old_state == C_STARTUP && state == C_REENABLE)
1132 case C_DISABLE_CLKCHANGE:
1134 * Disable controller for clock change. If the
1135 * controller is already disabled, then do nothing.
1137 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1139 /* TODO __pxafb_lcd_power(fbi, 0); */
1140 pxafb_disable_controller(fbi);
1147 * Disable controller
1149 if (old_state != C_DISABLE) {
1151 __pxafb_backlight_power(fbi, 0);
1152 __pxafb_lcd_power(fbi, 0);
1153 if (old_state != C_DISABLE_CLKCHANGE)
1154 pxafb_disable_controller(fbi);
1158 case C_ENABLE_CLKCHANGE:
1160 * Enable the controller after clock change. Only
1161 * do this if we were disabled for the clock change.
1163 if (old_state == C_DISABLE_CLKCHANGE) {
1164 fbi->state = C_ENABLE;
1165 pxafb_enable_controller(fbi);
1166 /* TODO __pxafb_lcd_power(fbi, 1); */
1172 * Re-enable the controller only if it was already
1173 * enabled. This is so we reprogram the control
1176 if (old_state == C_ENABLE) {
1177 __pxafb_lcd_power(fbi, 0);
1178 pxafb_disable_controller(fbi);
1179 pxafb_setup_gpio(fbi);
1180 pxafb_enable_controller(fbi);
1181 __pxafb_lcd_power(fbi, 1);
1187 * Re-enable the controller after PM. This is not
1188 * perfect - think about the case where we were doing
1189 * a clock change, and we suspended half-way through.
1191 if (old_state != C_DISABLE_PM)
1197 * Power up the LCD screen, enable controller, and
1198 * turn on the backlight.
1200 if (old_state != C_ENABLE) {
1201 fbi->state = C_ENABLE;
1202 pxafb_setup_gpio(fbi);
1203 pxafb_enable_controller(fbi);
1204 __pxafb_lcd_power(fbi, 1);
1205 __pxafb_backlight_power(fbi, 1);
1209 mutex_unlock(&fbi->ctrlr_lock);
1213 * Our LCD controller task (which is called when we blank or unblank)
1216 static void pxafb_task(struct work_struct *work)
1218 struct pxafb_info *fbi =
1219 container_of(work, struct pxafb_info, task);
1220 u_int state = xchg(&fbi->task_state, -1);
1222 set_ctrlr_state(fbi, state);
1225 #ifdef CONFIG_CPU_FREQ
1227 * CPU clock speed change handler. We need to adjust the LCD timing
1228 * parameters when the CPU clock is adjusted by the power management
1231 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1234 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1236 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1237 /* TODO struct cpufreq_freqs *f = data; */
1241 case CPUFREQ_PRECHANGE:
1242 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1245 case CPUFREQ_POSTCHANGE:
1246 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1247 set_hsync_time(fbi, pcd);
1248 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1249 LCCR3_PixClkDiv(pcd);
1250 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1257 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1259 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1260 struct fb_var_screeninfo *var = &fbi->fb.var;
1261 struct cpufreq_policy *policy = data;
1264 case CPUFREQ_ADJUST:
1265 case CPUFREQ_INCOMPATIBLE:
1266 pr_debug("min dma period: %d ps, "
1267 "new clock %d kHz\n", pxafb_display_dma_period(var),
1269 /* TODO: fill in min/max values */
1278 * Power management hooks. Note that we won't be called from IRQ context,
1279 * unlike the blank functions above, so we may sleep.
1281 static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
1283 struct pxafb_info *fbi = platform_get_drvdata(dev);
1285 set_ctrlr_state(fbi, C_DISABLE_PM);
1289 static int pxafb_resume(struct platform_device *dev)
1291 struct pxafb_info *fbi = platform_get_drvdata(dev);
1293 set_ctrlr_state(fbi, C_ENABLE_PM);
1297 #define pxafb_suspend NULL
1298 #define pxafb_resume NULL
1302 * pxafb_map_video_memory():
1303 * Allocates the DRAM memory for the frame buffer. This buffer is
1304 * remapped into a non-cached, non-buffered, memory region to
1305 * allow palette and pixel writes to occur without flushing the
1306 * cache. Once this area is remapped, all virtual memory
1307 * access to the video memory should occur at the new region.
1309 static int __devinit pxafb_map_video_memory(struct pxafb_info *fbi)
1312 * We reserve one page for the palette, plus the size
1313 * of the framebuffer.
1315 fbi->video_offset = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
1316 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + fbi->video_offset);
1317 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
1318 &fbi->map_dma, GFP_KERNEL);
1321 /* prevent initial garbage on screen */
1322 memset(fbi->map_cpu, 0, fbi->map_size);
1323 fbi->fb.screen_base = fbi->map_cpu + fbi->video_offset;
1324 fbi->screen_dma = fbi->map_dma + fbi->video_offset;
1327 * FIXME: this is actually the wrong thing to place in
1328 * smem_start. But fbdev suffers from the problem that
1329 * it needs an API which doesn't exist (in this case,
1330 * dma_writecombine_mmap)
1332 fbi->fb.fix.smem_start = fbi->screen_dma;
1333 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1335 fbi->dma_buff = (void *) fbi->map_cpu;
1336 fbi->dma_buff_phys = fbi->map_dma;
1337 fbi->palette_cpu = (u16 *) fbi->dma_buff->palette;
1339 pr_debug("pxafb: palette_mem_size = 0x%08x\n", fbi->palette_size*sizeof(u16));
1341 #ifdef CONFIG_FB_PXA_SMARTPANEL
1342 fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1343 fbi->n_smart_cmds = 0;
1347 return fbi->map_cpu ? 0 : -ENOMEM;
1350 static void pxafb_decode_mode_info(struct pxafb_info *fbi,
1351 struct pxafb_mode_info *modes,
1352 unsigned int num_modes)
1354 unsigned int i, smemlen;
1356 pxafb_setmode(&fbi->fb.var, &modes[0]);
1358 for (i = 0; i < num_modes; i++) {
1359 smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8;
1360 if (smemlen > fbi->fb.fix.smem_len)
1361 fbi->fb.fix.smem_len = smemlen;
1365 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1366 struct pxafb_mach_info *inf)
1368 unsigned int lcd_conn = inf->lcd_conn;
1370 fbi->cmap_inverse = inf->cmap_inverse;
1371 fbi->cmap_static = inf->cmap_static;
1373 switch (lcd_conn & 0xf) {
1374 case LCD_TYPE_MONO_STN:
1375 fbi->lccr0 = LCCR0_CMS;
1377 case LCD_TYPE_MONO_DSTN:
1378 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1380 case LCD_TYPE_COLOR_STN:
1383 case LCD_TYPE_COLOR_DSTN:
1384 fbi->lccr0 = LCCR0_SDS;
1386 case LCD_TYPE_COLOR_TFT:
1387 fbi->lccr0 = LCCR0_PAS;
1389 case LCD_TYPE_SMART_PANEL:
1390 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1393 /* fall back to backward compatibility way */
1394 fbi->lccr0 = inf->lccr0;
1395 fbi->lccr3 = inf->lccr3;
1396 fbi->lccr4 = inf->lccr4;
1400 if (lcd_conn == LCD_MONO_STN_8BPP)
1401 fbi->lccr0 |= LCCR0_DPD;
1403 fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1404 fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1405 fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0;
1408 pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes);
1411 static struct pxafb_info * __devinit pxafb_init_fbinfo(struct device *dev)
1413 struct pxafb_info *fbi;
1415 struct pxafb_mach_info *inf = dev->platform_data;
1417 /* Alloc the pxafb_info and pseudo_palette in one step */
1418 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1422 memset(fbi, 0, sizeof(struct pxafb_info));
1425 fbi->clk = clk_get(dev, "LCDCLK");
1426 if (IS_ERR(fbi->clk)) {
1431 strcpy(fbi->fb.fix.id, PXA_NAME);
1433 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1434 fbi->fb.fix.type_aux = 0;
1435 fbi->fb.fix.xpanstep = 0;
1436 fbi->fb.fix.ypanstep = 0;
1437 fbi->fb.fix.ywrapstep = 0;
1438 fbi->fb.fix.accel = FB_ACCEL_NONE;
1440 fbi->fb.var.nonstd = 0;
1441 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1442 fbi->fb.var.height = -1;
1443 fbi->fb.var.width = -1;
1444 fbi->fb.var.accel_flags = 0;
1445 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1447 fbi->fb.fbops = &pxafb_ops;
1448 fbi->fb.flags = FBINFO_DEFAULT;
1452 addr = addr + sizeof(struct pxafb_info);
1453 fbi->fb.pseudo_palette = addr;
1455 fbi->state = C_STARTUP;
1456 fbi->task_state = (u_char)-1;
1458 pxafb_decode_mach_info(fbi, inf);
1460 init_waitqueue_head(&fbi->ctrlr_wait);
1461 INIT_WORK(&fbi->task, pxafb_task);
1462 mutex_init(&fbi->ctrlr_lock);
1463 init_completion(&fbi->disable_done);
1464 #ifdef CONFIG_FB_PXA_SMARTPANEL
1465 init_completion(&fbi->command_done);
1466 init_completion(&fbi->refresh_done);
1472 #ifdef CONFIG_FB_PXA_PARAMETERS
1473 static int __devinit parse_opt_mode(struct device *dev, const char *this_opt)
1475 struct pxafb_mach_info *inf = dev->platform_data;
1477 const char *name = this_opt+5;
1478 unsigned int namelen = strlen(name);
1479 int res_specified = 0, bpp_specified = 0;
1480 unsigned int xres = 0, yres = 0, bpp = 0;
1481 int yres_specified = 0;
1483 for (i = namelen-1; i >= 0; i--) {
1487 if (!bpp_specified && !yres_specified) {
1488 bpp = simple_strtoul(&name[i+1], NULL, 0);
1494 if (!yres_specified) {
1495 yres = simple_strtoul(&name[i+1], NULL, 0);
1506 if (i < 0 && yres_specified) {
1507 xres = simple_strtoul(name, NULL, 0);
1511 if (res_specified) {
1512 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1513 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1522 inf->modes[0].bpp = bpp;
1523 dev_info(dev, "overriding bit depth: %d\n", bpp);
1526 dev_err(dev, "Depth %d is not valid\n", bpp);
1532 static int __devinit parse_opt(struct device *dev, char *this_opt)
1534 struct pxafb_mach_info *inf = dev->platform_data;
1535 struct pxafb_mode_info *mode = &inf->modes[0];
1540 if (!strncmp(this_opt, "mode:", 5)) {
1541 return parse_opt_mode(dev, this_opt);
1542 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1543 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1544 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1545 } else if (!strncmp(this_opt, "left:", 5)) {
1546 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1547 sprintf(s, "left: %u\n", mode->left_margin);
1548 } else if (!strncmp(this_opt, "right:", 6)) {
1549 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1550 sprintf(s, "right: %u\n", mode->right_margin);
1551 } else if (!strncmp(this_opt, "upper:", 6)) {
1552 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1553 sprintf(s, "upper: %u\n", mode->upper_margin);
1554 } else if (!strncmp(this_opt, "lower:", 6)) {
1555 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1556 sprintf(s, "lower: %u\n", mode->lower_margin);
1557 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1558 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1559 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1560 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1561 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1562 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1563 } else if (!strncmp(this_opt, "hsync:", 6)) {
1564 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1565 sprintf(s, "hsync: Active Low\n");
1566 mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1568 sprintf(s, "hsync: Active High\n");
1569 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1571 } else if (!strncmp(this_opt, "vsync:", 6)) {
1572 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1573 sprintf(s, "vsync: Active Low\n");
1574 mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1576 sprintf(s, "vsync: Active High\n");
1577 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1579 } else if (!strncmp(this_opt, "dpc:", 4)) {
1580 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1581 sprintf(s, "double pixel clock: false\n");
1582 inf->lccr3 &= ~LCCR3_DPC;
1584 sprintf(s, "double pixel clock: true\n");
1585 inf->lccr3 |= LCCR3_DPC;
1587 } else if (!strncmp(this_opt, "outputen:", 9)) {
1588 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1589 sprintf(s, "output enable: active low\n");
1590 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1592 sprintf(s, "output enable: active high\n");
1593 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1595 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1596 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1597 sprintf(s, "pixel clock polarity: falling edge\n");
1598 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1600 sprintf(s, "pixel clock polarity: rising edge\n");
1601 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1603 } else if (!strncmp(this_opt, "color", 5)) {
1604 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1605 } else if (!strncmp(this_opt, "mono", 4)) {
1606 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1607 } else if (!strncmp(this_opt, "active", 6)) {
1608 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1609 } else if (!strncmp(this_opt, "passive", 7)) {
1610 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1611 } else if (!strncmp(this_opt, "single", 6)) {
1612 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1613 } else if (!strncmp(this_opt, "dual", 4)) {
1614 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1615 } else if (!strncmp(this_opt, "4pix", 4)) {
1616 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1617 } else if (!strncmp(this_opt, "8pix", 4)) {
1618 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1620 dev_err(dev, "unknown option: %s\n", this_opt);
1625 dev_info(dev, "override %s", s);
1630 static int __devinit pxafb_parse_options(struct device *dev, char *options)
1635 if (!options || !*options)
1638 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1640 /* could be made table driven or similar?... */
1641 while ((this_opt = strsep(&options, ",")) != NULL) {
1642 ret = parse_opt(dev, this_opt);
1649 static char g_options[256] __devinitdata = "";
1652 static int __init pxafb_setup_options(void)
1654 char *options = NULL;
1656 if (fb_get_options("pxafb", &options))
1660 strlcpy(g_options, options, sizeof(g_options));
1665 #define pxafb_setup_options() (0)
1667 module_param_string(options, g_options, sizeof(g_options), 0);
1668 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1672 #define pxafb_parse_options(...) (0)
1673 #define pxafb_setup_options() (0)
1676 static int __devinit pxafb_probe(struct platform_device *dev)
1678 struct pxafb_info *fbi;
1679 struct pxafb_mach_info *inf;
1683 dev_dbg(&dev->dev, "pxafb_probe\n");
1685 inf = dev->dev.platform_data;
1691 ret = pxafb_parse_options(&dev->dev, g_options);
1696 /* Check for various illegal bit-combinations. Currently only
1697 * a warning is given. */
1699 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1700 dev_warn(&dev->dev, "machine LCCR0 setting contains "
1701 "illegal bits: %08x\n",
1702 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1703 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1704 dev_warn(&dev->dev, "machine LCCR3 setting contains "
1705 "illegal bits: %08x\n",
1706 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1707 if (inf->lccr0 & LCCR0_DPD &&
1708 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1709 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1710 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1711 dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is "
1712 "only valid in passive mono"
1713 " single panel mode\n");
1714 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1715 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1716 dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
1717 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1718 (inf->modes->upper_margin || inf->modes->lower_margin))
1719 dev_warn(&dev->dev, "Upper and lower margins must be 0 in "
1723 dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
1727 if (inf->modes->xres == 0 ||
1728 inf->modes->yres == 0 ||
1729 inf->modes->bpp == 0) {
1730 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
1734 pxafb_backlight_power = inf->pxafb_backlight_power;
1735 pxafb_lcd_power = inf->pxafb_lcd_power;
1736 fbi = pxafb_init_fbinfo(&dev->dev);
1738 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
1739 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
1744 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1746 dev_err(&dev->dev, "no I/O memory resource defined\n");
1751 r = request_mem_region(r->start, r->end - r->start + 1, dev->name);
1753 dev_err(&dev->dev, "failed to request I/O memory\n");
1758 fbi->mmio_base = ioremap(r->start, r->end - r->start + 1);
1759 if (fbi->mmio_base == NULL) {
1760 dev_err(&dev->dev, "failed to map I/O memory\n");
1762 goto failed_free_res;
1765 /* Initialize video memory */
1766 ret = pxafb_map_video_memory(fbi);
1768 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
1770 goto failed_free_io;
1773 irq = platform_get_irq(dev, 0);
1775 dev_err(&dev->dev, "no IRQ defined\n");
1777 goto failed_free_mem;
1780 ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
1782 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
1784 goto failed_free_mem;
1787 #ifdef CONFIG_FB_PXA_SMARTPANEL
1788 ret = pxafb_smart_init(fbi);
1790 dev_err(&dev->dev, "failed to initialize smartpanel\n");
1791 goto failed_free_irq;
1795 * This makes sure that our colour bitfield
1796 * descriptors are correctly initialised.
1798 ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
1800 dev_err(&dev->dev, "failed to get suitable mode\n");
1801 goto failed_free_irq;
1804 ret = pxafb_set_par(&fbi->fb);
1806 dev_err(&dev->dev, "Failed to set parameters\n");
1807 goto failed_free_irq;
1810 platform_set_drvdata(dev, fbi);
1812 ret = register_framebuffer(&fbi->fb);
1815 "Failed to register framebuffer device: %d\n", ret);
1816 goto failed_free_cmap;
1819 #ifdef CONFIG_CPU_FREQ
1820 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1821 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1822 cpufreq_register_notifier(&fbi->freq_transition,
1823 CPUFREQ_TRANSITION_NOTIFIER);
1824 cpufreq_register_notifier(&fbi->freq_policy,
1825 CPUFREQ_POLICY_NOTIFIER);
1829 * Ok, now enable the LCD controller
1831 set_ctrlr_state(fbi, C_ENABLE);
1836 if (fbi->fb.cmap.len)
1837 fb_dealloc_cmap(&fbi->fb.cmap);
1841 dma_free_writecombine(&dev->dev, fbi->map_size,
1842 fbi->map_cpu, fbi->map_dma);
1844 iounmap(fbi->mmio_base);
1846 release_mem_region(r->start, r->end - r->start + 1);
1849 platform_set_drvdata(dev, NULL);
1855 static int __devexit pxafb_remove(struct platform_device *dev)
1857 struct pxafb_info *fbi = platform_get_drvdata(dev);
1860 struct fb_info *info;
1867 unregister_framebuffer(info);
1869 pxafb_disable_controller(fbi);
1871 if (fbi->fb.cmap.len)
1872 fb_dealloc_cmap(&fbi->fb.cmap);
1874 irq = platform_get_irq(dev, 0);
1877 dma_free_writecombine(&dev->dev, fbi->map_size,
1878 fbi->map_cpu, fbi->map_dma);
1880 iounmap(fbi->mmio_base);
1882 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
1883 release_mem_region(r->start, r->end - r->start + 1);
1891 static struct platform_driver pxafb_driver = {
1892 .probe = pxafb_probe,
1893 .remove = pxafb_remove,
1894 .suspend = pxafb_suspend,
1895 .resume = pxafb_resume,
1897 .owner = THIS_MODULE,
1898 .name = "pxa2xx-fb",
1902 static int __init pxafb_init(void)
1904 if (pxafb_setup_options())
1907 return platform_driver_register(&pxafb_driver);
1910 static void __exit pxafb_exit(void)
1912 platform_driver_unregister(&pxafb_driver);
1915 module_init(pxafb_init);
1916 module_exit(pxafb_exit);
1918 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1919 MODULE_LICENSE("GPL");