git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_cache_conf_rate(struct ath_softc *sc,
  63                                 struct ieee80211_conf *conf)
  64 {
  65         switch (conf->channel->band) {
  66         case IEEE80211_BAND_2GHZ:
  67                 if (conf_is_ht20(conf))
  68                         sc->cur_rate_table =
  69                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
  70                 else if (conf_is_ht40_minus(conf))
  71                         sc->cur_rate_table =
  72                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
  73                 else if (conf_is_ht40_plus(conf))
  74                         sc->cur_rate_table =
  75                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
  76                 else
  77                         sc->cur_rate_table =
  78                           sc->hw_rate_table[ATH9K_MODE_11G];
  79                 break;
  80         case IEEE80211_BAND_5GHZ:
  81                 if (conf_is_ht20(conf))
  82                         sc->cur_rate_table =
  83                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
  84                 else if (conf_is_ht40_minus(conf))
  85                         sc->cur_rate_table =
  86                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
  87                 else if (conf_is_ht40_plus(conf))
  88                         sc->cur_rate_table =
  89                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
  90                 else
  91                         sc->cur_rate_table =
  92                           sc->hw_rate_table[ATH9K_MODE_11A];
  93                 break;
  94         default:
  95                 BUG_ON(1);
  96                 break;
  97         }
  98 }
  99
 100 static void ath_update_txpow(struct ath_softc *sc)
 101 {
 102         struct ath_hal *ah = sc->sc_ah;
 103         u32 txpow;
 104
 105         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 106                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 107                 /* read back in case value is clamped */
 108                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 109                 sc->sc_curtxpow = txpow;
 110         }
 111 }
 112
 113 static u8 parse_mpdudensity(u8 mpdudensity)
 114 {
 115         /*
 116          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 117          *   0 for no restriction
 118          *   1 for 1/4 us
 119          *   2 for 1/2 us
 120          *   3 for 1 us
 121          *   4 for 2 us
 122          *   5 for 4 us
 123          *   6 for 8 us
 124          *   7 for 16 us
 125          */
 126         switch (mpdudensity) {
 127         case 0:
 128                 return 0;
 129         case 1:
 130         case 2:
 131         case 3:
 132                 /* Our lower layer calculations limit our precision to
 133                    1 microsecond */
 134                 return 1;
 135         case 4:
 136                 return 2;
 137         case 5:
 138                 return 4;
 139         case 6:
 140                 return 8;
 141         case 7:
 142                 return 16;
 143         default:
 144                 return 0;
 145         }
 146 }
 147
 148 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 149 {
 150         struct ath_rate_table *rate_table = NULL;
 151         struct ieee80211_supported_band *sband;
 152         struct ieee80211_rate *rate;
 153         int i, maxrates;
 154
 155         switch (band) {
 156         case IEEE80211_BAND_2GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 158                 break;
 159         case IEEE80211_BAND_5GHZ:
 160                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 161                 break;
 162         default:
 163                 break;
 164         }
 165
 166         if (rate_table == NULL)
 167                 return;
 168
 169         sband = &sc->sbands[band];
 170         rate = sc->rates[band];
 171
 172         if (rate_table->rate_cnt > ATH_RATE_MAX)
 173                 maxrates = ATH_RATE_MAX;
 174         else
 175                 maxrates = rate_table->rate_cnt;
 176
 177         for (i = 0; i < maxrates; i++) {
 178                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 179                 rate[i].hw_value = rate_table->info[i].ratecode;
 180                 sband->n_bitrates++;
 181                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 182                         rate[i].bitrate / 10, rate[i].hw_value);
 183         }
 184 }
 185
 186 static int ath_setup_channels(struct ath_softc *sc)
 187 {
 188         struct ath_hal *ah = sc->sc_ah;
 189         int nchan, i, a = 0, b = 0;
 190         u8 regclassids[ATH_REGCLASSIDS_MAX];
 191         u32 nregclass = 0;
 192         struct ieee80211_supported_band *band_2ghz;
 193         struct ieee80211_supported_band *band_5ghz;
 194         struct ieee80211_channel *chan_2ghz;
 195         struct ieee80211_channel *chan_5ghz;
 196         struct ath9k_channel *c;
 197
 198         /* Fill in ah->ah_channels */
 199         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 200                                       regclassids, ATH_REGCLASSIDS_MAX,
 201                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 202                 u32 rd = ah->ah_currentRD;
 203                 DPRINTF(sc, ATH_DBG_FATAL,
 204                         "Unable to collect channel list; "
 205                         "regdomain likely %u country code %u\n",
 206                         rd, CTRY_DEFAULT);
 207                 return -EINVAL;
 208         }
 209
 210         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 211         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 212         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 213         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 214
 215         for (i = 0; i < nchan; i++) {
 216                 c = &ah->ah_channels[i];
 217                 if (IS_CHAN_2GHZ(c)) {
 218                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 219                         chan_2ghz[a].center_freq = c->channel;
 220                         chan_2ghz[a].max_power = c->maxTxPower;
 221                         c->chan = &chan_2ghz[a];
 222
 223                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 224                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 225                         if (c->channelFlags & CHANNEL_PASSIVE)
 226                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 227
 228                         band_2ghz->n_channels = ++a;
 229
 230                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 231                                 "channelFlags: 0x%x\n",
 232                                 c->channel, c->channelFlags);
 233                 } else if (IS_CHAN_5GHZ(c)) {
 234                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 235                         chan_5ghz[b].center_freq = c->channel;
 236                         chan_5ghz[b].max_power = c->maxTxPower;
 237                         c->chan = &chan_5ghz[a];
 238
 239                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 240                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 241                         if (c->channelFlags & CHANNEL_PASSIVE)
 242                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 243
 244                         band_5ghz->n_channels = ++b;
 245
 246                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 247                                 "channelFlags: 0x%x\n",
 248                                 c->channel, c->channelFlags);
 249                 }
 250         }
 251
 252         return 0;
 253 }
 254
 255 /*
 256  * Set/change channels.  If the channel is really being changed, it's done
 257  * by reseting the chip.  To accomplish this we must first cleanup any pending
 258  * DMA, then restart stuff.
 259 */
 260 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 261 {
 262         struct ath_hal *ah = sc->sc_ah;
 263         bool fastcc = true, stopped;
 264         struct ieee80211_hw *hw = sc->hw;
 265         struct ieee80211_channel *channel = hw->conf.channel;
 266         int r;
 267
 268         if (sc->sc_flags & SC_OP_INVALID)
 269                 return -EIO;
 270
 271         /*
 272          * This is only performed if the channel settings have
 273          * actually changed.
 274          *
 275          * To switch channels clear any pending DMA operations;
 276          * wait long enough for the RX fifo to drain, reset the
 277          * hardware at the new frequency, and then re-enable
 278          * the relevant bits of the h/w.
 279          */
 280         ath9k_hw_set_interrupts(ah, 0);
 281         ath_draintxq(sc, false);
 282         stopped = ath_stoprecv(sc);
 283
 284         /* XXX: do not flush receive queue here. We don't want
 285          * to flush data frames already in queue because of
 286          * changing channel. */
 287
 288         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 289                 fastcc = false;
 290
 291         DPRINTF(sc, ATH_DBG_CONFIG,
 292                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 293                 sc->sc_ah->ah_curchan->channel,
 294                 channel->center_freq, sc->tx_chan_width);
 295
 296         spin_lock_bh(&sc->sc_resetlock);
 297
 298         r = ath9k_hw_reset(ah, hchan, fastcc);
 299         if (r) {
 300                 DPRINTF(sc, ATH_DBG_FATAL,
 301                         "Unable to reset channel (%u Mhz) "
 302                         "reset status %u\n",
 303                         channel->center_freq, r);
 304                 spin_unlock_bh(&sc->sc_resetlock);
 305                 return r;
 306         }
 307         spin_unlock_bh(&sc->sc_resetlock);
 308
 309         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 310         sc->sc_flags &= ~SC_OP_FULL_RESET;
 311
 312         if (ath_startrecv(sc) != 0) {
 313                 DPRINTF(sc, ATH_DBG_FATAL,
 314                         "Unable to restart recv logic\n");
 315                 return -EIO;
 316         }
 317
 318         ath_cache_conf_rate(sc, &hw->conf);
 319         ath_update_txpow(sc);
 320         ath9k_hw_set_interrupts(ah, sc->sc_imask);
 321         return 0;
 322 }
 323
 324 /*
 325  *  This routine performs the periodic noise floor calibration function
 326  *  that is used to adjust and optimize the chip performance.  This
 327  *  takes environmental changes (location, temperature) into account.
 328  *  When the task is complete, it reschedules itself depending on the
 329  *  appropriate interval that was calculated.
 330  */
 331 static void ath_ani_calibrate(unsigned long data)
 332 {
 333         struct ath_softc *sc;
 334         struct ath_hal *ah;
 335         bool longcal = false;
 336         bool shortcal = false;
 337         bool aniflag = false;
 338         unsigned int timestamp = jiffies_to_msecs(jiffies);
 339         u32 cal_interval;
 340
 341         sc = (struct ath_softc *)data;
 342         ah = sc->sc_ah;
 343
 344         /*
 345         * don't calibrate when we're scanning.
 346         * we are most likely not on our home channel.
 347         */
 348         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 349                 return;
 350
 351         /* Long calibration runs independently of short calibration. */
 352         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 353                 longcal = true;
 354                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 355                 sc->sc_ani.sc_longcal_timer = timestamp;
 356         }
 357
 358         /* Short calibration applies only while sc_caldone is false */
 359         if (!sc->sc_ani.sc_caldone) {
 360                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 361                     ATH_SHORT_CALINTERVAL) {
 362                         shortcal = true;
 363                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 364                         sc->sc_ani.sc_shortcal_timer = timestamp;
 365                         sc->sc_ani.sc_resetcal_timer = timestamp;
 366                 }
 367         } else {
 368                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 369                     ATH_RESTART_CALINTERVAL) {
 370                         sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
 371                         if (sc->sc_ani.sc_caldone)
 372                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 373                 }
 374         }
 375
 376         /* Verify whether we must check ANI */
 377         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 378            ATH_ANI_POLLINTERVAL) {
 379                 aniflag = true;
 380                 sc->sc_ani.sc_checkani_timer = timestamp;
 381         }
 382
 383         /* Skip all processing if there's nothing to do. */
 384         if (longcal || shortcal || aniflag) {
 385                 /* Call ANI routine if necessary */
 386                 if (aniflag)
 387                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 388                                              ah->ah_curchan);
 389
 390                 /* Perform calibration if necessary */
 391                 if (longcal || shortcal) {
 392                         bool iscaldone = false;
 393
 394                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 395                                                sc->sc_rx_chainmask, longcal,
 396                                                &iscaldone)) {
 397                                 if (longcal)
 398                                         sc->sc_ani.sc_noise_floor =
 399                                                 ath9k_hw_getchan_noise(ah,
 400                                                                ah->ah_curchan);
 401
 402                                 DPRINTF(sc, ATH_DBG_ANI,
 403                                         "calibrate chan %u/%x nf: %d\n",
 404                                         ah->ah_curchan->channel,
 405                                         ah->ah_curchan->channelFlags,
 406                                         sc->sc_ani.sc_noise_floor);
 407                         } else {
 408                                 DPRINTF(sc, ATH_DBG_ANY,
 409                                         "calibrate chan %u/%x failed\n",
 410                                         ah->ah_curchan->channel,
 411                                         ah->ah_curchan->channelFlags);
 412                         }
 413                         sc->sc_ani.sc_caldone = iscaldone;
 414                 }
 415         }
 416
 417         /*
 418         * Set timer interval based on previous results.
 419         * The interval must be the shortest necessary to satisfy ANI,
 420         * short calibration and long calibration.
 421         */
 422         cal_interval = ATH_LONG_CALINTERVAL;
 423         if (sc->sc_ah->ah_config.enable_ani)
 424                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 425         if (!sc->sc_ani.sc_caldone)
 426                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 427
 428         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 429 }
 430
 431 /*
 432  * Update tx/rx chainmask. For legacy association,
 433  * hard code chainmask to 1x1, for 11n association, use
 434  * the chainmask configuration, for bt coexistence, use
 435  * the chainmask configuration even in legacy mode.
 436  */
 437 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 438 {
 439         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 440         if (is_ht ||
 441             (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 442                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 443                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 444         } else {
 445                 sc->sc_tx_chainmask = 1;
 446                 sc->sc_rx_chainmask = 1;
 447         }
 448
 449         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 450                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 451 }
 452
 453 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 454 {
 455         struct ath_node *an;
 456
 457         an = (struct ath_node *)sta->drv_priv;
 458
 459         if (sc->sc_flags & SC_OP_TXAGGR)
 460                 ath_tx_node_init(sc, an);
 461
 462         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 463                              sta->ht_cap.ampdu_factor);
 464         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 465 }
 466
 467 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 468 {
 469         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 470
 471         if (sc->sc_flags & SC_OP_TXAGGR)
 472                 ath_tx_node_cleanup(sc, an);
 473 }
 474
 475 static void ath9k_tasklet(unsigned long data)
 476 {
 477         struct ath_softc *sc = (struct ath_softc *)data;
 478         u32 status = sc->sc_intrstatus;
 479
 480         if (status & ATH9K_INT_FATAL) {
 481                 /* need a chip reset */
 482                 ath_reset(sc, false);
 483                 return;
 484         } else {
 485
 486                 if (status &
 487                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 488                         spin_lock_bh(&sc->rx.rxflushlock);
 489                         ath_rx_tasklet(sc, 0);
 490                         spin_unlock_bh(&sc->rx.rxflushlock);
 491                 }
 492                 /* XXX: optimize this */
 493                 if (status & ATH9K_INT_TX)
 494                         ath_tx_tasklet(sc);
 495         }
 496
 497         /* re-enable hardware interrupt */
 498         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 499 }
 500
 501 static irqreturn_t ath_isr(int irq, void *dev)
 502 {
 503         struct ath_softc *sc = dev;
 504         struct ath_hal *ah = sc->sc_ah;
 505         enum ath9k_int status;
 506         bool sched = false;
 507
 508         do {
 509                 if (sc->sc_flags & SC_OP_INVALID) {
 510                         /*
 511                          * The hardware is not ready/present, don't
 512                          * touch anything. Note this can happen early
 513                          * on if the IRQ is shared.
 514                          */
 515                         return IRQ_NONE;
 516                 }
 517                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 518                         return IRQ_NONE;
 519                 }
 520
 521                 /*
 522                  * Figure out the reason(s) for the interrupt.  Note
 523                  * that the hal returns a pseudo-ISR that may include
 524                  * bits we haven't explicitly enabled so we mask the
 525                  * value to insure we only process bits we requested.
 526                  */
 527                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 528
 529                 status &= sc->sc_imask; /* discard unasked-for bits */
 530
 531                 /*
 532                  * If there are no status bits set, then this interrupt was not
 533                  * for me (should have been caught above).
 534                  */
 535                 if (!status)
 536                         return IRQ_NONE;
 537
 538                 sc->sc_intrstatus = status;
 539
 540                 if (status & ATH9K_INT_FATAL) {
 541                         /* need a chip reset */
 542                         sched = true;
 543                 } else if (status & ATH9K_INT_RXORN) {
 544                         /* need a chip reset */
 545                         sched = true;
 546                 } else {
 547                         if (status & ATH9K_INT_SWBA) {
 548                                 /* schedule a tasklet for beacon handling */
 549                                 tasklet_schedule(&sc->bcon_tasklet);
 550                         }
 551                         if (status & ATH9K_INT_RXEOL) {
 552                                 /*
 553                                  * NB: the hardware should re-read the link when
 554                                  *     RXE bit is written, but it doesn't work
 555                                  *     at least on older hardware revs.
 556                                  */
 557                                 sched = true;
 558                         }
 559
 560                         if (status & ATH9K_INT_TXURN)
 561                                 /* bump tx trigger level */
 562                                 ath9k_hw_updatetxtriglevel(ah, true);
 563                         /* XXX: optimize this */
 564                         if (status & ATH9K_INT_RX)
 565                                 sched = true;
 566                         if (status & ATH9K_INT_TX)
 567                                 sched = true;
 568                         if (status & ATH9K_INT_BMISS)
 569                                 sched = true;
 570                         /* carrier sense timeout */
 571                         if (status & ATH9K_INT_CST)
 572                                 sched = true;
 573                         if (status & ATH9K_INT_MIB) {
 574                                 /*
 575                                  * Disable interrupts until we service the MIB
 576                                  * interrupt; otherwise it will continue to
 577                                  * fire.
 578                                  */
 579                                 ath9k_hw_set_interrupts(ah, 0);
 580                                 /*
 581                                  * Let the hal handle the event. We assume
 582                                  * it will clear whatever condition caused
 583                                  * the interrupt.
 584                                  */
 585                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 586                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 587                         }
 588                         if (status & ATH9K_INT_TIM_TIMER) {
 589                                 if (!(ah->ah_caps.hw_caps &
 590                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 591                                         /* Clear RxAbort bit so that we can
 592                                          * receive frames */
 593                                         ath9k_hw_setrxabort(ah, 0);
 594                                         sched = true;
 595                                 }
 596                         }
 597                 }
 598         } while (0);
 599
 600         ath_debug_stat_interrupt(sc, status);
 601
 602         if (sched) {
 603                 /* turn off every interrupt except SWBA */
 604                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 605                 tasklet_schedule(&sc->intr_tq);
 606         }
 607
 608         return IRQ_HANDLED;
 609 }
 610
 611 static int ath_get_channel(struct ath_softc *sc,
 612                            struct ieee80211_channel *chan)
 613 {
 614         int i;
 615
 616         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 617                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 618                         return i;
 619         }
 620
 621         return -1;
 622 }
 623
 624 static u32 ath_get_extchanmode(struct ath_softc *sc,
 625                                struct ieee80211_channel *chan,
 626                                enum nl80211_channel_type channel_type)
 627 {
 628         u32 chanmode = 0;
 629
 630         switch (chan->band) {
 631         case IEEE80211_BAND_2GHZ:
 632                 switch(channel_type) {
 633                 case NL80211_CHAN_NO_HT:
 634                 case NL80211_CHAN_HT20:
 635                         chanmode = CHANNEL_G_HT20;
 636                         break;
 637                 case NL80211_CHAN_HT40PLUS:
 638                         chanmode = CHANNEL_G_HT40PLUS;
 639                         break;
 640                 case NL80211_CHAN_HT40MINUS:
 641                         chanmode = CHANNEL_G_HT40MINUS;
 642                         break;
 643                 }
 644                 break;
 645         case IEEE80211_BAND_5GHZ:
 646                 switch(channel_type) {
 647                 case NL80211_CHAN_NO_HT:
 648                 case NL80211_CHAN_HT20:
 649                         chanmode = CHANNEL_A_HT20;
 650                         break;
 651                 case NL80211_CHAN_HT40PLUS:
 652                         chanmode = CHANNEL_A_HT40PLUS;
 653                         break;
 654                 case NL80211_CHAN_HT40MINUS:
 655                         chanmode = CHANNEL_A_HT40MINUS;
 656                         break;
 657                 }
 658                 break;
 659         default:
 660                 break;
 661         }
 662
 663         return chanmode;
 664 }
 665
 666 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 667                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 668 {
 669         bool status;
 670
 671         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 672                 keyix, hk, mac, false);
 673
 674         return status != false;
 675 }
 676
 677 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 678                            struct ath9k_keyval *hk,
 679                            const u8 *addr)
 680 {
 681         const u8 *key_rxmic;
 682         const u8 *key_txmic;
 683
 684         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 685         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 686
 687         if (addr == NULL) {
 688                 /* Group key installation */
 689                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 690                 return ath_keyset(sc, keyix, hk, addr);
 691         }
 692         if (!sc->sc_splitmic) {
 693                 /*
 694                  * data key goes at first index,
 695                  * the hal handles the MIC keys at index+64.
 696                  */
 697                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 698                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 699                 return ath_keyset(sc, keyix, hk, addr);
 700         }
 701         /*
 702          * TX key goes at first index, RX key at +32.
 703          * The hal handles the MIC keys at index+64.
 704          */
 705         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 706         if (!ath_keyset(sc, keyix, hk, NULL)) {
 707                 /* Txmic entry failed. No need to proceed further */
 708                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 709                         "Setting TX MIC Key Failed\n");
 710                 return 0;
 711         }
 712
 713         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 714         /* XXX delete tx key on failure? */
 715         return ath_keyset(sc, keyix + 32, hk, addr);
 716 }
 717
 718 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 719 {
 720         int i;
 721
 722         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 723                 if (test_bit(i, sc->sc_keymap) ||
 724                     test_bit(i + 64, sc->sc_keymap))
 725                         continue; /* At least one part of TKIP key allocated */
 726                 if (sc->sc_splitmic &&
 727                     (test_bit(i + 32, sc->sc_keymap) ||
 728                      test_bit(i + 64 + 32, sc->sc_keymap)))
 729                         continue; /* At least one part of TKIP key allocated */
 730
 731                 /* Found a free slot for a TKIP key */
 732                 return i;
 733         }
 734         return -1;
 735 }
 736
 737 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 738 {
 739         int i;
 740
 741         /* First, try to find slots that would not be available for TKIP. */
 742         if (sc->sc_splitmic) {
 743                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
 744                         if (!test_bit(i, sc->sc_keymap) &&
 745                             (test_bit(i + 32, sc->sc_keymap) ||
 746                              test_bit(i + 64, sc->sc_keymap) ||
 747                              test_bit(i + 64 + 32, sc->sc_keymap)))
 748                                 return i;
 749                         if (!test_bit(i + 32, sc->sc_keymap) &&
 750                             (test_bit(i, sc->sc_keymap) ||
 751                              test_bit(i + 64, sc->sc_keymap) ||
 752                              test_bit(i + 64 + 32, sc->sc_keymap)))
 753                                 return i + 32;
 754                         if (!test_bit(i + 64, sc->sc_keymap) &&
 755                             (test_bit(i , sc->sc_keymap) ||
 756                              test_bit(i + 32, sc->sc_keymap) ||
 757                              test_bit(i + 64 + 32, sc->sc_keymap)))
 758                                 return i + 64;
 759                         if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
 760                             (test_bit(i, sc->sc_keymap) ||
 761                              test_bit(i + 32, sc->sc_keymap) ||
 762                              test_bit(i + 64, sc->sc_keymap)))
 763                                 return i + 64 + 32;
 764                 }
 765         } else {
 766                 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
 767                         if (!test_bit(i, sc->sc_keymap) &&
 768                             test_bit(i + 64, sc->sc_keymap))
 769                                 return i;
 770                         if (test_bit(i, sc->sc_keymap) &&
 771                             !test_bit(i + 64, sc->sc_keymap))
 772                                 return i + 64;
 773                 }
 774         }
 775
 776         /* No partially used TKIP slots, pick any available slot */
 777         for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
 778                 /* Do not allow slots that could be needed for TKIP group keys
 779                  * to be used. This limitation could be removed if we know that
 780                  * TKIP will not be used. */
 781                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 782                         continue;
 783                 if (sc->sc_splitmic) {
 784                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 785                                 continue;
 786                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 787                                 continue;
 788                 }
 789
 790                 if (!test_bit(i, sc->sc_keymap))
 791                         return i; /* Found a free slot for a key */
 792         }
 793
 794         /* No free slot found */
 795         return -1;
 796 }
 797
 798 static int ath_key_config(struct ath_softc *sc,
 799                           struct ieee80211_sta *sta,
 800                           struct ieee80211_key_conf *key)
 801 {
 802         struct ath9k_keyval hk;
 803         const u8 *mac = NULL;
 804         int ret = 0;
 805         int idx;
 806
 807         memset(&hk, 0, sizeof(hk));
 808
 809         switch (key->alg) {
 810         case ALG_WEP:
 811                 hk.kv_type = ATH9K_CIPHER_WEP;
 812                 break;
 813         case ALG_TKIP:
 814                 hk.kv_type = ATH9K_CIPHER_TKIP;
 815                 break;
 816         case ALG_CCMP:
 817                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 818                 break;
 819         default:
 820                 return -EINVAL;
 821         }
 822
 823         hk.kv_len = key->keylen;
 824         memcpy(hk.kv_val, key->key, key->keylen);
 825
 826         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 827                 /* For now, use the default keys for broadcast keys. This may
 828                  * need to change with virtual interfaces. */
 829                 idx = key->keyidx;
 830         } else if (key->keyidx) {
 831                 struct ieee80211_vif *vif;
 832
 833                 if (WARN_ON(!sta))
 834                         return -EOPNOTSUPP;
 835                 mac = sta->addr;
 836
 837                 vif = sc->sc_vaps[0];
 838                 if (vif->type != NL80211_IFTYPE_AP) {
 839                         /* Only keyidx 0 should be used with unicast key, but
 840                          * allow this for client mode for now. */
 841                         idx = key->keyidx;
 842                 } else
 843                         return -EIO;
 844         } else {
 845                 if (WARN_ON(!sta))
 846                         return -EOPNOTSUPP;
 847                 mac = sta->addr;
 848
 849                 if (key->alg == ALG_TKIP)
 850                         idx = ath_reserve_key_cache_slot_tkip(sc);
 851                 else
 852                         idx = ath_reserve_key_cache_slot(sc);
 853                 if (idx < 0)
 854                         return -EIO; /* no free key cache entries */
 855         }
 856
 857         if (key->alg == ALG_TKIP)
 858                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 859         else
 860                 ret = ath_keyset(sc, idx, &hk, mac);
 861
 862         if (!ret)
 863                 return -EIO;
 864
 865         set_bit(idx, sc->sc_keymap);
 866         if (key->alg == ALG_TKIP) {
 867                 set_bit(idx + 64, sc->sc_keymap);
 868                 if (sc->sc_splitmic) {
 869                         set_bit(idx + 32, sc->sc_keymap);
 870                         set_bit(idx + 64 + 32, sc->sc_keymap);
 871                 }
 872         }
 873
 874         return idx;
 875 }
 876
 877 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 878 {
 879         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 880         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 881                 return;
 882
 883         clear_bit(key->hw_key_idx, sc->sc_keymap);
 884         if (key->alg != ALG_TKIP)
 885                 return;
 886
 887         clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
 888         if (sc->sc_splitmic) {
 889                 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
 890                 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
 891         }
 892 }
 893
 894 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 895 {
 896 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 897 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 898
 899         ht_info->ht_supported = true;
 900         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 901                        IEEE80211_HT_CAP_SM_PS |
 902                        IEEE80211_HT_CAP_SGI_40 |
 903                        IEEE80211_HT_CAP_DSSSCCK40;
 904
 905         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 906         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 907         /* set up supported mcs set */
 908         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 909         ht_info->mcs.rx_mask[0] = 0xff;
 910         ht_info->mcs.rx_mask[1] = 0xff;
 911         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 912 }
 913
 914 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 915                                  struct ieee80211_vif *vif,
 916                                  struct ieee80211_bss_conf *bss_conf)
 917 {
 918         struct ath_vap *avp = (void *)vif->drv_priv;
 919
 920         if (bss_conf->assoc) {
 921                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 922                         bss_conf->aid, sc->sc_curbssid);
 923
 924                 /* New association, store aid */
 925                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 926                         sc->sc_curaid = bss_conf->aid;
 927                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 928                                                sc->sc_curaid);
 929                 }
 930
 931                 /* Configure the beacon */
 932                 ath_beacon_config(sc, 0);
 933                 sc->sc_flags |= SC_OP_BEACONS;
 934
 935                 /* Reset rssi stats */
 936                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 937                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 938                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 939                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 940
 941                 /* Start ANI */
 942                 mod_timer(&sc->sc_ani.timer,
 943                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 944
 945         } else {
 946                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 947                 sc->sc_curaid = 0;
 948         }
 949 }
 950
 951 /********************************/
 952 /*       LED functions          */
 953 /********************************/
 954
 955 static void ath_led_brightness(struct led_classdev *led_cdev,
 956                                enum led_brightness brightness)
 957 {
 958         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 959         struct ath_softc *sc = led->sc;
 960
 961         switch (brightness) {
 962         case LED_OFF:
 963                 if (led->led_type == ATH_LED_ASSOC ||
 964                     led->led_type == ATH_LED_RADIO)
 965                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 966                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 967                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 968                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 969                 break;
 970         case LED_FULL:
 971                 if (led->led_type == ATH_LED_ASSOC)
 972                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 973                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 974                 break;
 975         default:
 976                 break;
 977         }
 978 }
 979
 980 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 981                             char *trigger)
 982 {
 983         int ret;
 984
 985         led->sc = sc;
 986         led->led_cdev.name = led->name;
 987         led->led_cdev.default_trigger = trigger;
 988         led->led_cdev.brightness_set = ath_led_brightness;
 989
 990         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 991         if (ret)
 992                 DPRINTF(sc, ATH_DBG_FATAL,
 993                         "Failed to register led:%s", led->name);
 994         else
 995                 led->registered = 1;
 996         return ret;
 997 }
 998
 999 static void ath_unregister_led(struct ath_led *led)
1000 {
1001         if (led->registered) {
1002                 led_classdev_unregister(&led->led_cdev);
1003                 led->registered = 0;
1004         }
1005 }
1006
1007 static void ath_deinit_leds(struct ath_softc *sc)
1008 {
1009         ath_unregister_led(&sc->assoc_led);
1010         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1011         ath_unregister_led(&sc->tx_led);
1012         ath_unregister_led(&sc->rx_led);
1013         ath_unregister_led(&sc->radio_led);
1014         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1015 }
1016
1017 static void ath_init_leds(struct ath_softc *sc)
1018 {
1019         char *trigger;
1020         int ret;
1021
1022         /* Configure gpio 1 for output */
1023         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1024                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1025         /* LED off, active low */
1026         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1027
1028         trigger = ieee80211_get_radio_led_name(sc->hw);
1029         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1030                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1031         ret = ath_register_led(sc, &sc->radio_led, trigger);
1032         sc->radio_led.led_type = ATH_LED_RADIO;
1033         if (ret)
1034                 goto fail;
1035
1036         trigger = ieee80211_get_assoc_led_name(sc->hw);
1037         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1038                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1039         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1040         sc->assoc_led.led_type = ATH_LED_ASSOC;
1041         if (ret)
1042                 goto fail;
1043
1044         trigger = ieee80211_get_tx_led_name(sc->hw);
1045         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1046                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1047         ret = ath_register_led(sc, &sc->tx_led, trigger);
1048         sc->tx_led.led_type = ATH_LED_TX;
1049         if (ret)
1050                 goto fail;
1051
1052         trigger = ieee80211_get_rx_led_name(sc->hw);
1053         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1054                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1055         ret = ath_register_led(sc, &sc->rx_led, trigger);
1056         sc->rx_led.led_type = ATH_LED_RX;
1057         if (ret)
1058                 goto fail;
1059
1060         return;
1061
1062 fail:
1063         ath_deinit_leds(sc);
1064 }
1065
1066 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1067
1068 /*******************/
1069 /*      Rfkill     */
1070 /*******************/
1071
1072 static void ath_radio_enable(struct ath_softc *sc)
1073 {
1074         struct ath_hal *ah = sc->sc_ah;
1075         struct ieee80211_channel *channel = sc->hw->conf.channel;
1076         int r;
1077
1078         spin_lock_bh(&sc->sc_resetlock);
1079
1080         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1081
1082         if (r) {
1083                 DPRINTF(sc, ATH_DBG_FATAL,
1084                         "Unable to reset channel %u (%uMhz) ",
1085                         "reset status %u\n",
1086                         channel->center_freq, r);
1087         }
1088         spin_unlock_bh(&sc->sc_resetlock);
1089
1090         ath_update_txpow(sc);
1091         if (ath_startrecv(sc) != 0) {
1092                 DPRINTF(sc, ATH_DBG_FATAL,
1093                         "Unable to restart recv logic\n");
1094                 return;
1095         }
1096
1097         if (sc->sc_flags & SC_OP_BEACONS)
1098                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1099
1100         /* Re-Enable  interrupts */
1101         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1102
1103         /* Enable LED */
1104         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1105                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1106         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1107
1108         ieee80211_wake_queues(sc->hw);
1109 }
1110
1111 static void ath_radio_disable(struct ath_softc *sc)
1112 {
1113         struct ath_hal *ah = sc->sc_ah;
1114         struct ieee80211_channel *channel = sc->hw->conf.channel;
1115         int r;
1116
1117         ieee80211_stop_queues(sc->hw);
1118
1119         /* Disable LED */
1120         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1121         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1122
1123         /* Disable interrupts */
1124         ath9k_hw_set_interrupts(ah, 0);
1125
1126         ath_draintxq(sc, false);        /* clear pending tx frames */
1127         ath_stoprecv(sc);               /* turn off frame recv */
1128         ath_flushrecv(sc);              /* flush recv queue */
1129
1130         spin_lock_bh(&sc->sc_resetlock);
1131         r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1132         if (r) {
1133                 DPRINTF(sc, ATH_DBG_FATAL,
1134                         "Unable to reset channel %u (%uMhz) "
1135                         "reset status %u\n",
1136                         channel->center_freq, r);
1137         }
1138         spin_unlock_bh(&sc->sc_resetlock);
1139
1140         ath9k_hw_phy_disable(ah);
1141         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1142 }
1143
1144 static bool ath_is_rfkill_set(struct ath_softc *sc)
1145 {
1146         struct ath_hal *ah = sc->sc_ah;
1147
1148         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1149                                   ah->ah_rfkill_polarity;
1150 }
1151
1152 /* h/w rfkill poll function */
1153 static void ath_rfkill_poll(struct work_struct *work)
1154 {
1155         struct ath_softc *sc = container_of(work, struct ath_softc,
1156                                             rf_kill.rfkill_poll.work);
1157         bool radio_on;
1158
1159         if (sc->sc_flags & SC_OP_INVALID)
1160                 return;
1161
1162         radio_on = !ath_is_rfkill_set(sc);
1163
1164         /*
1165          * enable/disable radio only when there is a
1166          * state change in RF switch
1167          */
1168         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1169                 enum rfkill_state state;
1170
1171                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1172                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1173                                 : RFKILL_STATE_HARD_BLOCKED;
1174                 } else if (radio_on) {
1175                         ath_radio_enable(sc);
1176                         state = RFKILL_STATE_UNBLOCKED;
1177                 } else {
1178                         ath_radio_disable(sc);
1179                         state = RFKILL_STATE_HARD_BLOCKED;
1180                 }
1181
1182                 if (state == RFKILL_STATE_HARD_BLOCKED)
1183                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1184                 else
1185                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1186
1187                 rfkill_force_state(sc->rf_kill.rfkill, state);
1188         }
1189
1190         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1191                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1192 }
1193
1194 /* s/w rfkill handler */
1195 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1196 {
1197         struct ath_softc *sc = data;
1198
1199         switch (state) {
1200         case RFKILL_STATE_SOFT_BLOCKED:
1201                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1202                     SC_OP_RFKILL_SW_BLOCKED)))
1203                         ath_radio_disable(sc);
1204                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1205                 return 0;
1206         case RFKILL_STATE_UNBLOCKED:
1207                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1208                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1209                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1210                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1211                                         "radio as it is disabled by h/w\n");
1212                                 return -EPERM;
1213                         }
1214                         ath_radio_enable(sc);
1215                 }
1216                 return 0;
1217         default:
1218                 return -EINVAL;
1219         }
1220 }
1221
1222 /* Init s/w rfkill */
1223 static int ath_init_sw_rfkill(struct ath_softc *sc)
1224 {
1225         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1226                                              RFKILL_TYPE_WLAN);
1227         if (!sc->rf_kill.rfkill) {
1228                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1229                 return -ENOMEM;
1230         }
1231
1232         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1233                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1234         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1235         sc->rf_kill.rfkill->data = sc;
1236         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1237         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1238         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1239
1240         return 0;
1241 }
1242
1243 /* Deinitialize rfkill */
1244 static void ath_deinit_rfkill(struct ath_softc *sc)
1245 {
1246         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1247                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1248
1249         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1250                 rfkill_unregister(sc->rf_kill.rfkill);
1251                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1252                 sc->rf_kill.rfkill = NULL;
1253         }
1254 }
1255
1256 static int ath_start_rfkill_poll(struct ath_softc *sc)
1257 {
1258         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1259                 queue_delayed_work(sc->hw->workqueue,
1260                                    &sc->rf_kill.rfkill_poll, 0);
1261
1262         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1263                 if (rfkill_register(sc->rf_kill.rfkill)) {
1264                         DPRINTF(sc, ATH_DBG_FATAL,
1265                                 "Unable to register rfkill\n");
1266                         rfkill_free(sc->rf_kill.rfkill);
1267
1268                         /* Deinitialize the device */
1269                         ath_detach(sc);
1270                         if (sc->pdev->irq)
1271                                 free_irq(sc->pdev->irq, sc);
1272                         pci_iounmap(sc->pdev, sc->mem);
1273                         pci_release_region(sc->pdev, 0);
1274                         pci_disable_device(sc->pdev);
1275                         ieee80211_free_hw(sc->hw);
1276                         return -EIO;
1277                 } else {
1278                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1279                 }
1280         }
1281
1282         return 0;
1283 }
1284 #endif /* CONFIG_RFKILL */
1285
1286 static void ath_detach(struct ath_softc *sc)
1287 {
1288         struct ieee80211_hw *hw = sc->hw;
1289         int i = 0;
1290
1291         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1292
1293 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1294         ath_deinit_rfkill(sc);
1295 #endif
1296         ath_deinit_leds(sc);
1297
1298         ieee80211_unregister_hw(hw);
1299         ath_rx_cleanup(sc);
1300         ath_tx_cleanup(sc);
1301
1302         tasklet_kill(&sc->intr_tq);
1303         tasklet_kill(&sc->bcon_tasklet);
1304
1305         if (!(sc->sc_flags & SC_OP_INVALID))
1306                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1307
1308         /* cleanup tx queues */
1309         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1310                 if (ATH_TXQ_SETUP(sc, i))
1311                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1312
1313         ath9k_hw_detach(sc->sc_ah);
1314         ath9k_exit_debug(sc);
1315 }
1316
1317 static int ath_init(u16 devid, struct ath_softc *sc)
1318 {
1319         struct ath_hal *ah = NULL;
1320         int status;
1321         int error = 0, i;
1322         int csz = 0;
1323
1324         /* XXX: hardware will not be ready until ath_open() being called */
1325         sc->sc_flags |= SC_OP_INVALID;
1326
1327         if (ath9k_init_debug(sc) < 0)
1328                 printk(KERN_ERR "Unable to create debugfs files\n");
1329
1330         spin_lock_init(&sc->sc_resetlock);
1331         mutex_init(&sc->mutex);
1332         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1333         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1334                      (unsigned long)sc);
1335
1336         /*
1337          * Cache line size is used to size and align various
1338          * structures used to communicate with the hardware.
1339          */
1340         bus_read_cachesize(sc, &csz);
1341         /* XXX assert csz is non-zero */
1342         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1343
1344         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1345         if (ah == NULL) {
1346                 DPRINTF(sc, ATH_DBG_FATAL,
1347                         "Unable to attach hardware; HAL status %d\n", status);
1348                 error = -ENXIO;
1349                 goto bad;
1350         }
1351         sc->sc_ah = ah;
1352
1353         /* Get the hardware key cache size. */
1354         sc->sc_keymax = ah->ah_caps.keycache_size;
1355         if (sc->sc_keymax > ATH_KEYMAX) {
1356                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1357                         "Warning, using only %u entries in %u key cache\n",
1358                         ATH_KEYMAX, sc->sc_keymax);
1359                 sc->sc_keymax = ATH_KEYMAX;
1360         }
1361
1362         /*
1363          * Reset the key cache since some parts do not
1364          * reset the contents on initial power up.
1365          */
1366         for (i = 0; i < sc->sc_keymax; i++)
1367                 ath9k_hw_keyreset(ah, (u16) i);
1368
1369         /* Collect the channel list using the default country code */
1370
1371         error = ath_setup_channels(sc);
1372         if (error)
1373                 goto bad;
1374
1375         /* default to MONITOR mode */
1376         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1377
1378
1379         /* Setup rate tables */
1380
1381         ath_rate_attach(sc);
1382         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1383         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1384
1385         /*
1386          * Allocate hardware transmit queues: one queue for
1387          * beacon frames and one data queue for each QoS
1388          * priority.  Note that the hal handles reseting
1389          * these queues at the needed time.
1390          */
1391         sc->beacon.beaconq = ath_beaconq_setup(ah);
1392         if (sc->beacon.beaconq == -1) {
1393                 DPRINTF(sc, ATH_DBG_FATAL,
1394                         "Unable to setup a beacon xmit queue\n");
1395                 error = -EIO;
1396                 goto bad2;
1397         }
1398         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1399         if (sc->beacon.cabq == NULL) {
1400                 DPRINTF(sc, ATH_DBG_FATAL,
1401                         "Unable to setup CAB xmit queue\n");
1402                 error = -EIO;
1403                 goto bad2;
1404         }
1405
1406         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1407         ath_cabq_update(sc);
1408
1409         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1410                 sc->tx.hwq_map[i] = -1;
1411
1412         /* Setup data queues */
1413         /* NB: ensure BK queue is the lowest priority h/w queue */
1414         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1415                 DPRINTF(sc, ATH_DBG_FATAL,
1416                         "Unable to setup xmit queue for BK traffic\n");
1417                 error = -EIO;
1418                 goto bad2;
1419         }
1420
1421         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1422                 DPRINTF(sc, ATH_DBG_FATAL,
1423                         "Unable to setup xmit queue for BE traffic\n");
1424                 error = -EIO;
1425                 goto bad2;
1426         }
1427         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1428                 DPRINTF(sc, ATH_DBG_FATAL,
1429                         "Unable to setup xmit queue for VI traffic\n");
1430                 error = -EIO;
1431                 goto bad2;
1432         }
1433         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1434                 DPRINTF(sc, ATH_DBG_FATAL,
1435                         "Unable to setup xmit queue for VO traffic\n");
1436                 error = -EIO;
1437                 goto bad2;
1438         }
1439
1440         /* Initializes the noise floor to a reasonable default value.
1441          * Later on this will be updated during ANI processing. */
1442
1443         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1444         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1445
1446         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1447                                    ATH9K_CIPHER_TKIP, NULL)) {
1448                 /*
1449                  * Whether we should enable h/w TKIP MIC.
1450                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1451                  * report WMM capable, so it's always safe to turn on
1452                  * TKIP MIC in this case.
1453                  */
1454                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1455                                        0, 1, NULL);
1456         }
1457
1458         /*
1459          * Check whether the separate key cache entries
1460          * are required to handle both tx+rx MIC keys.
1461          * With split mic keys the number of stations is limited
1462          * to 27 otherwise 59.
1463          */
1464         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465                                    ATH9K_CIPHER_TKIP, NULL)
1466             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1467                                       ATH9K_CIPHER_MIC, NULL)
1468             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1469                                       0, NULL))
1470                 sc->sc_splitmic = 1;
1471
1472         /* turn on mcast key search if possible */
1473         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1474                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1475                                              1, NULL);
1476
1477         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1478         sc->sc_config.txpowlimit_override = 0;
1479
1480         /* 11n Capabilities */
1481         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1482                 sc->sc_flags |= SC_OP_TXAGGR;
1483                 sc->sc_flags |= SC_OP_RXAGGR;
1484         }
1485
1486         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1487         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1488
1489         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1490         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1491
1492         ath9k_hw_getmac(ah, sc->sc_myaddr);
1493         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1494                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1495                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1496                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1497         }
1498
1499         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1500
1501         /* initialize beacon slots */
1502         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1503                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1504
1505         /* save MISC configurations */
1506         sc->sc_config.swBeaconProcess = 1;
1507
1508         /* setup channels and rates */
1509
1510         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1511                 sc->channels[IEEE80211_BAND_2GHZ];
1512         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1513                 sc->rates[IEEE80211_BAND_2GHZ];
1514         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1515
1516         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1517                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1518                         sc->channels[IEEE80211_BAND_5GHZ];
1519                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1520                         sc->rates[IEEE80211_BAND_5GHZ];
1521                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1522         }
1523
1524         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1525                 ath9k_hw_btcoex_enable(sc->sc_ah);
1526
1527         return 0;
1528 bad2:
1529         /* cleanup tx queues */
1530         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1531                 if (ATH_TXQ_SETUP(sc, i))
1532                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1533 bad:
1534         if (ah)
1535                 ath9k_hw_detach(ah);
1536
1537         return error;
1538 }
1539
1540 static int ath_attach(u16 devid, struct ath_softc *sc)
1541 {
1542         struct ieee80211_hw *hw = sc->hw;
1543         int error = 0;
1544
1545         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1546
1547         error = ath_init(devid, sc);
1548         if (error != 0)
1549                 return error;
1550
1551         /* get mac address from hardware and set in mac80211 */
1552
1553         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1554
1555         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1556                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1557                 IEEE80211_HW_SIGNAL_DBM |
1558                 IEEE80211_HW_AMPDU_AGGREGATION;
1559
1560         hw->wiphy->interface_modes =
1561                 BIT(NL80211_IFTYPE_AP) |
1562                 BIT(NL80211_IFTYPE_STATION) |
1563                 BIT(NL80211_IFTYPE_ADHOC);
1564
1565         hw->queues = 4;
1566         hw->max_rates = 4;
1567         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1568         hw->sta_data_size = sizeof(struct ath_node);
1569         hw->vif_data_size = sizeof(struct ath_vap);
1570
1571         hw->rate_control_algorithm = "ath9k_rate_control";
1572
1573         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1574                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1575                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1576                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1577         }
1578
1579         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1580         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1581                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1582                         &sc->sbands[IEEE80211_BAND_5GHZ];
1583
1584         /* initialize tx/rx engine */
1585         error = ath_tx_init(sc, ATH_TXBUF);
1586         if (error != 0)
1587                 goto detach;
1588
1589         error = ath_rx_init(sc, ATH_RXBUF);
1590         if (error != 0)
1591                 goto detach;
1592
1593 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1594         /* Initialze h/w Rfkill */
1595         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1596                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1597
1598         /* Initialize s/w rfkill */
1599         if (ath_init_sw_rfkill(sc))
1600                 goto detach;
1601 #endif
1602
1603         error = ieee80211_register_hw(hw);
1604
1605         /* Initialize LED control */
1606         ath_init_leds(sc);
1607
1608         return 0;
1609 detach:
1610         ath_detach(sc);
1611         return error;
1612 }
1613
1614 int ath_reset(struct ath_softc *sc, bool retry_tx)
1615 {
1616         struct ath_hal *ah = sc->sc_ah;
1617         struct ieee80211_hw *hw = sc->hw;
1618         int r;
1619
1620         ath9k_hw_set_interrupts(ah, 0);
1621         ath_draintxq(sc, retry_tx);
1622         ath_stoprecv(sc);
1623         ath_flushrecv(sc);
1624
1625         spin_lock_bh(&sc->sc_resetlock);
1626         r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1627         if (r)
1628                 DPRINTF(sc, ATH_DBG_FATAL,
1629                         "Unable to reset hardware; reset status %u\n", r);
1630         spin_unlock_bh(&sc->sc_resetlock);
1631
1632         if (ath_startrecv(sc) != 0)
1633                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1634
1635         /*
1636          * We may be doing a reset in response to a request
1637          * that changes the channel so update any state that
1638          * might change as a result.
1639          */
1640         ath_cache_conf_rate(sc, &hw->conf);
1641
1642         ath_update_txpow(sc);
1643
1644         if (sc->sc_flags & SC_OP_BEACONS)
1645                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1646
1647         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1648
1649         if (retry_tx) {
1650                 int i;
1651                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1652                         if (ATH_TXQ_SETUP(sc, i)) {
1653                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1654                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1655                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1656                         }
1657                 }
1658         }
1659
1660         return r;
1661 }
1662
1663 /*
1664  *  This function will allocate both the DMA descriptor structure, and the
1665  *  buffers it contains.  These are used to contain the descriptors used
1666  *  by the system.
1667 */
1668 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1669                       struct list_head *head, const char *name,
1670                       int nbuf, int ndesc)
1671 {
1672 #define DS2PHYS(_dd, _ds)                                               \
1673         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1674 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1675 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1676
1677         struct ath_desc *ds;
1678         struct ath_buf *bf;
1679         int i, bsize, error;
1680
1681         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1682                 name, nbuf, ndesc);
1683
1684         /* ath_desc must be a multiple of DWORDs */
1685         if ((sizeof(struct ath_desc) % 4) != 0) {
1686                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1687                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1688                 error = -ENOMEM;
1689                 goto fail;
1690         }
1691
1692         dd->dd_name = name;
1693         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1694
1695         /*
1696          * Need additional DMA memory because we can't use
1697          * descriptors that cross the 4K page boundary. Assume
1698          * one skipped descriptor per 4K page.
1699          */
1700         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1701                 u32 ndesc_skipped =
1702                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1703                 u32 dma_len;
1704
1705                 while (ndesc_skipped) {
1706                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1707                         dd->dd_desc_len += dma_len;
1708
1709                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1710                 };
1711         }
1712
1713         /* allocate descriptors */
1714         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1715                               dd->dd_desc_len,
1716                               &dd->dd_desc_paddr);
1717         if (dd->dd_desc == NULL) {
1718                 error = -ENOMEM;
1719                 goto fail;
1720         }
1721         ds = dd->dd_desc;
1722         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1723                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1724                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1725
1726         /* allocate buffers */
1727         bsize = sizeof(struct ath_buf) * nbuf;
1728         bf = kmalloc(bsize, GFP_KERNEL);
1729         if (bf == NULL) {
1730                 error = -ENOMEM;
1731                 goto fail2;
1732         }
1733         memset(bf, 0, bsize);
1734         dd->dd_bufptr = bf;
1735
1736         INIT_LIST_HEAD(head);
1737         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1738                 bf->bf_desc = ds;
1739                 bf->bf_daddr = DS2PHYS(dd, ds);
1740
1741                 if (!(sc->sc_ah->ah_caps.hw_caps &
1742                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1743                         /*
1744                          * Skip descriptor addresses which can cause 4KB
1745                          * boundary crossing (addr + length) with a 32 dword
1746                          * descriptor fetch.
1747                          */
1748                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1749                                 ASSERT((caddr_t) bf->bf_desc <
1750                                        ((caddr_t) dd->dd_desc +
1751                                         dd->dd_desc_len));
1752
1753                                 ds += ndesc;
1754                                 bf->bf_desc = ds;
1755                                 bf->bf_daddr = DS2PHYS(dd, ds);
1756                         }
1757                 }
1758                 list_add_tail(&bf->list, head);
1759         }
1760         return 0;
1761 fail2:
1762         pci_free_consistent(sc->pdev,
1763                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1764 fail:
1765         memset(dd, 0, sizeof(*dd));
1766         return error;
1767 #undef ATH_DESC_4KB_BOUND_CHECK
1768 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1769 #undef DS2PHYS
1770 }
1771
1772 void ath_descdma_cleanup(struct ath_softc *sc,
1773                          struct ath_descdma *dd,
1774                          struct list_head *head)
1775 {
1776         pci_free_consistent(sc->pdev,
1777                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1778
1779         INIT_LIST_HEAD(head);
1780         kfree(dd->dd_bufptr);
1781         memset(dd, 0, sizeof(*dd));
1782 }
1783
1784 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1785 {
1786         int qnum;
1787
1788         switch (queue) {
1789         case 0:
1790                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1791                 break;
1792         case 1:
1793                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1794                 break;
1795         case 2:
1796                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1797                 break;
1798         case 3:
1799                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1800                 break;
1801         default:
1802                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1803                 break;
1804         }
1805
1806         return qnum;
1807 }
1808
1809 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1810 {
1811         int qnum;
1812
1813         switch (queue) {
1814         case ATH9K_WME_AC_VO:
1815                 qnum = 0;
1816                 break;
1817         case ATH9K_WME_AC_VI:
1818                 qnum = 1;
1819                 break;
1820         case ATH9K_WME_AC_BE:
1821                 qnum = 2;
1822                 break;
1823         case ATH9K_WME_AC_BK:
1824                 qnum = 3;
1825                 break;
1826         default:
1827                 qnum = -1;
1828                 break;
1829         }
1830
1831         return qnum;
1832 }
1833
1834 /**********************/
1835 /* mac80211 callbacks */
1836 /**********************/
1837
1838 static int ath9k_start(struct ieee80211_hw *hw)
1839 {
1840         struct ath_softc *sc = hw->priv;
1841         struct ieee80211_channel *curchan = hw->conf.channel;
1842         struct ath9k_channel *init_channel;
1843         int r, pos;
1844
1845         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1846                 "initial channel: %d MHz\n", curchan->center_freq);
1847
1848         /* setup initial channel */
1849
1850         pos = ath_get_channel(sc, curchan);
1851         if (pos == -1) {
1852                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1853                 return -EINVAL;
1854         }
1855
1856         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1857         sc->sc_ah->ah_channels[pos].chanmode =
1858                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1859         init_channel = &sc->sc_ah->ah_channels[pos];
1860
1861         /* Reset SERDES registers */
1862         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1863
1864         /*
1865          * The basic interface to setting the hardware in a good
1866          * state is ``reset''.  On return the hardware is known to
1867          * be powered up and with interrupts disabled.  This must
1868          * be followed by initialization of the appropriate bits
1869          * and then setup of the interrupt mask.
1870          */
1871         spin_lock_bh(&sc->sc_resetlock);
1872         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1873         if (r) {
1874                 DPRINTF(sc, ATH_DBG_FATAL,
1875                         "Unable to reset hardware; reset status %u "
1876                         "(freq %u MHz)\n", r,
1877                         curchan->center_freq);
1878                 spin_unlock_bh(&sc->sc_resetlock);
1879                 return r;
1880         }
1881         spin_unlock_bh(&sc->sc_resetlock);
1882
1883         /*
1884          * This is needed only to setup initial state
1885          * but it's best done after a reset.
1886          */
1887         ath_update_txpow(sc);
1888
1889         /*
1890          * Setup the hardware after reset:
1891          * The receive engine is set going.
1892          * Frame transmit is handled entirely
1893          * in the frame output path; there's nothing to do
1894          * here except setup the interrupt mask.
1895          */
1896         if (ath_startrecv(sc) != 0) {
1897                 DPRINTF(sc, ATH_DBG_FATAL,
1898                         "Unable to start recv logic\n");
1899                 return -EIO;
1900         }
1901
1902         /* Setup our intr mask. */
1903         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1904                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1905                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1906
1907         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1908                 sc->sc_imask |= ATH9K_INT_GTT;
1909
1910         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1911                 sc->sc_imask |= ATH9K_INT_CST;
1912
1913         /*
1914          * Enable MIB interrupts when there are hardware phy counters.
1915          * Note we only do this (at the moment) for station mode.
1916          */
1917         if (ath9k_hw_phycounters(sc->sc_ah) &&
1918             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1919              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1920                 sc->sc_imask |= ATH9K_INT_MIB;
1921         /*
1922          * Some hardware processes the TIM IE and fires an
1923          * interrupt when the TIM bit is set.  For hardware
1924          * that does, if not overridden by configuration,
1925          * enable the TIM interrupt when operating as station.
1926          */
1927         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1928             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1929             !sc->sc_config.swBeaconProcess)
1930                 sc->sc_imask |= ATH9K_INT_TIM;
1931
1932         ath_cache_conf_rate(sc, &hw->conf);
1933
1934         sc->sc_flags &= ~SC_OP_INVALID;
1935
1936         /* Disable BMISS interrupt when we're not associated */
1937         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1938         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1939
1940         ieee80211_wake_queues(sc->hw);
1941
1942 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1943         r = ath_start_rfkill_poll(sc);
1944 #endif
1945         return r;
1946 }
1947
1948 static int ath9k_tx(struct ieee80211_hw *hw,
1949                     struct sk_buff *skb)
1950 {
1951         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1952         struct ath_softc *sc = hw->priv;
1953         struct ath_tx_control txctl;
1954         int hdrlen, padsize;
1955
1956         memset(&txctl, 0, sizeof(struct ath_tx_control));
1957
1958         /*
1959          * As a temporary workaround, assign seq# here; this will likely need
1960          * to be cleaned up to work better with Beacon transmission and virtual
1961          * BSSes.
1962          */
1963         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1964                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1965                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1966                         sc->tx.seq_no += 0x10;
1967                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1968                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1969         }
1970
1971         /* Add the padding after the header if this is not already done */
1972         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1973         if (hdrlen & 3) {
1974                 padsize = hdrlen % 4;
1975                 if (skb_headroom(skb) < padsize)
1976                         return -1;
1977                 skb_push(skb, padsize);
1978                 memmove(skb->data, skb->data + padsize, hdrlen);
1979         }
1980
1981         /* Check if a tx queue is available */
1982
1983         txctl.txq = ath_test_get_txq(sc, skb);
1984         if (!txctl.txq)
1985                 goto exit;
1986
1987         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1988
1989         if (ath_tx_start(sc, skb, &txctl) != 0) {
1990                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1991                 goto exit;
1992         }
1993
1994         return 0;
1995 exit:
1996         dev_kfree_skb_any(skb);
1997         return 0;
1998 }
1999
2000 static void ath9k_stop(struct ieee80211_hw *hw)
2001 {
2002         struct ath_softc *sc = hw->priv;
2003
2004         if (sc->sc_flags & SC_OP_INVALID) {
2005                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2006                 return;
2007         }
2008
2009         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2010
2011         ieee80211_stop_queues(sc->hw);
2012
2013         /* make sure h/w will not generate any interrupt
2014          * before setting the invalid flag. */
2015         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2016
2017         if (!(sc->sc_flags & SC_OP_INVALID)) {
2018                 ath_draintxq(sc, false);
2019                 ath_stoprecv(sc);
2020                 ath9k_hw_phy_disable(sc->sc_ah);
2021         } else
2022                 sc->rx.rxlink = NULL;
2023
2024 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2025         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2026                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2027 #endif
2028         /* disable HAL and put h/w to sleep */
2029         ath9k_hw_disable(sc->sc_ah);
2030         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2031
2032         sc->sc_flags |= SC_OP_INVALID;
2033
2034         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2035 }
2036
2037 static int ath9k_add_interface(struct ieee80211_hw *hw,
2038                                struct ieee80211_if_init_conf *conf)
2039 {
2040         struct ath_softc *sc = hw->priv;
2041         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2042         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2043
2044         /* Support only vap for now */
2045
2046         if (sc->sc_nvaps)
2047                 return -ENOBUFS;
2048
2049         switch (conf->type) {
2050         case NL80211_IFTYPE_STATION:
2051                 ic_opmode = NL80211_IFTYPE_STATION;
2052                 break;
2053         case NL80211_IFTYPE_ADHOC:
2054                 ic_opmode = NL80211_IFTYPE_ADHOC;
2055                 break;
2056         case NL80211_IFTYPE_AP:
2057                 ic_opmode = NL80211_IFTYPE_AP;
2058                 break;
2059         default:
2060                 DPRINTF(sc, ATH_DBG_FATAL,
2061                         "Interface type %d not yet supported\n", conf->type);
2062                 return -EOPNOTSUPP;
2063         }
2064
2065         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2066
2067         /* Set the VAP opmode */
2068         avp->av_opmode = ic_opmode;
2069         avp->av_bslot = -1;
2070
2071         if (ic_opmode == NL80211_IFTYPE_AP)
2072                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2073
2074         sc->sc_vaps[0] = conf->vif;
2075         sc->sc_nvaps++;
2076
2077         /* Set the device opmode */
2078         sc->sc_ah->ah_opmode = ic_opmode;
2079
2080         if (conf->type == NL80211_IFTYPE_AP) {
2081                 /* TODO: is this a suitable place to start ANI for AP mode? */
2082                 /* Start ANI */
2083                 mod_timer(&sc->sc_ani.timer,
2084                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2085         }
2086
2087         return 0;
2088 }
2089
2090 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2091                                    struct ieee80211_if_init_conf *conf)
2092 {
2093         struct ath_softc *sc = hw->priv;
2094         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2095
2096         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2097
2098         /* Stop ANI */
2099         del_timer_sync(&sc->sc_ani.timer);
2100
2101         /* Reclaim beacon resources */
2102         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2103             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2104                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2105                 ath_beacon_return(sc, avp);
2106         }
2107
2108         sc->sc_flags &= ~SC_OP_BEACONS;
2109
2110         sc->sc_vaps[0] = NULL;
2111         sc->sc_nvaps--;
2112 }
2113
2114 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2115 {
2116         struct ath_softc *sc = hw->priv;
2117         struct ieee80211_conf *conf = &hw->conf;
2118
2119         mutex_lock(&sc->mutex);
2120         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2121                 struct ieee80211_channel *curchan = hw->conf.channel;
2122                 int pos;
2123
2124                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2125                         curchan->center_freq);
2126
2127                 pos = ath_get_channel(sc, curchan);
2128                 if (pos == -1) {
2129                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2130                                 curchan->center_freq);
2131                         mutex_unlock(&sc->mutex);
2132                         return -EINVAL;
2133                 }
2134
2135                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2136                 sc->sc_ah->ah_channels[pos].chanmode =
2137                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2138                         CHANNEL_G : CHANNEL_A;
2139
2140                 if (conf_is_ht(conf)) {
2141                         if (conf_is_ht40(conf))
2142                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2143
2144                         sc->sc_ah->ah_channels[pos].chanmode =
2145                                 ath_get_extchanmode(sc, curchan,
2146                                                     conf->channel_type);
2147                 }
2148
2149                 ath_update_chainmask(sc, conf_is_ht(conf));
2150
2151                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2152                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2153                         mutex_unlock(&sc->mutex);
2154                         return -EINVAL;
2155                 }
2156         }
2157
2158         if (changed & IEEE80211_CONF_CHANGE_POWER)
2159                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2160
2161         mutex_unlock(&sc->mutex);
2162         return 0;
2163 }
2164
2165 static int ath9k_config_interface(struct ieee80211_hw *hw,
2166                                   struct ieee80211_vif *vif,
2167                                   struct ieee80211_if_conf *conf)
2168 {
2169         struct ath_softc *sc = hw->priv;
2170         struct ath_hal *ah = sc->sc_ah;
2171         struct ath_vap *avp = (void *)vif->drv_priv;
2172         u32 rfilt = 0;
2173         int error, i;
2174
2175         /* TODO: Need to decide which hw opmode to use for multi-interface
2176          * cases */
2177         if (vif->type == NL80211_IFTYPE_AP &&
2178             ah->ah_opmode != NL80211_IFTYPE_AP) {
2179                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2180                 ath9k_hw_setopmode(ah);
2181                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2182                 /* Request full reset to get hw opmode changed properly */
2183                 sc->sc_flags |= SC_OP_FULL_RESET;
2184         }
2185
2186         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2187             !is_zero_ether_addr(conf->bssid)) {
2188                 switch (vif->type) {
2189                 case NL80211_IFTYPE_STATION:
2190                 case NL80211_IFTYPE_ADHOC:
2191                         /* Set BSSID */
2192                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2193                         sc->sc_curaid = 0;
2194                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2195                                                sc->sc_curaid);
2196
2197                         /* Set aggregation protection mode parameters */
2198                         sc->sc_config.ath_aggr_prot = 0;
2199
2200                         DPRINTF(sc, ATH_DBG_CONFIG,
2201                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2202                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2203
2204                         /* need to reconfigure the beacon */
2205                         sc->sc_flags &= ~SC_OP_BEACONS ;
2206
2207                         break;
2208                 default:
2209                         break;
2210                 }
2211         }
2212
2213         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2214             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2215              (vif->type == NL80211_IFTYPE_AP))) {
2216                 /*
2217                  * Allocate and setup the beacon frame.
2218                  *
2219                  * Stop any previous beacon DMA.  This may be
2220                  * necessary, for example, when an ibss merge
2221                  * causes reconfiguration; we may be called
2222                  * with beacon transmission active.
2223                  */
2224                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2225
2226                 error = ath_beacon_alloc(sc, 0);
2227                 if (error != 0)
2228                         return error;
2229
2230                 ath_beacon_sync(sc, 0);
2231         }
2232
2233         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2234         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2235                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2236                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2237                                 ath9k_hw_keysetmac(sc->sc_ah,
2238                                                    (u16)i,
2239                                                    sc->sc_curbssid);
2240         }
2241
2242         /* Only legacy IBSS for now */
2243         if (vif->type == NL80211_IFTYPE_ADHOC)
2244                 ath_update_chainmask(sc, 0);
2245
2246         return 0;
2247 }
2248
2249 #define SUPPORTED_FILTERS                       \
2250         (FIF_PROMISC_IN_BSS |                   \
2251         FIF_ALLMULTI |                          \
2252         FIF_CONTROL |                           \
2253         FIF_OTHER_BSS |                         \
2254         FIF_BCN_PRBRESP_PROMISC |               \
2255         FIF_FCSFAIL)
2256
2257 /* FIXME: sc->sc_full_reset ? */
2258 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2259                                    unsigned int changed_flags,
2260                                    unsigned int *total_flags,
2261                                    int mc_count,
2262                                    struct dev_mc_list *mclist)
2263 {
2264         struct ath_softc *sc = hw->priv;
2265         u32 rfilt;
2266
2267         changed_flags &= SUPPORTED_FILTERS;
2268         *total_flags &= SUPPORTED_FILTERS;
2269
2270         sc->rx.rxfilter = *total_flags;
2271         rfilt = ath_calcrxfilter(sc);
2272         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2273
2274         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2275                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2276                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2277         }
2278
2279         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2280 }
2281
2282 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2283                              struct ieee80211_vif *vif,
2284                              enum sta_notify_cmd cmd,
2285                              struct ieee80211_sta *sta)
2286 {
2287         struct ath_softc *sc = hw->priv;
2288
2289         switch (cmd) {
2290         case STA_NOTIFY_ADD:
2291                 ath_node_attach(sc, sta);
2292                 break;
2293         case STA_NOTIFY_REMOVE:
2294                 ath_node_detach(sc, sta);
2295                 break;
2296         default:
2297                 break;
2298         }
2299 }
2300
2301 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2302                          u16 queue,
2303                          const struct ieee80211_tx_queue_params *params)
2304 {
2305         struct ath_softc *sc = hw->priv;
2306         struct ath9k_tx_queue_info qi;
2307         int ret = 0, qnum;
2308
2309         if (queue >= WME_NUM_AC)
2310                 return 0;
2311
2312         qi.tqi_aifs = params->aifs;
2313         qi.tqi_cwmin = params->cw_min;
2314         qi.tqi_cwmax = params->cw_max;
2315         qi.tqi_burstTime = params->txop;
2316         qnum = ath_get_hal_qnum(queue, sc);
2317
2318         DPRINTF(sc, ATH_DBG_CONFIG,
2319                 "Configure tx [queue/halq] [%d/%d],  "
2320                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2321                 queue, qnum, params->aifs, params->cw_min,
2322                 params->cw_max, params->txop);
2323
2324         ret = ath_txq_update(sc, qnum, &qi);
2325         if (ret)
2326                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2327
2328         return ret;
2329 }
2330
2331 static int ath9k_set_key(struct ieee80211_hw *hw,
2332                          enum set_key_cmd cmd,
2333                          struct ieee80211_vif *vif,
2334                          struct ieee80211_sta *sta,
2335                          struct ieee80211_key_conf *key)
2336 {
2337         struct ath_softc *sc = hw->priv;
2338         int ret = 0;
2339
2340         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2341
2342         switch (cmd) {
2343         case SET_KEY:
2344                 ret = ath_key_config(sc, sta, key);
2345                 if (ret >= 0) {
2346                         key->hw_key_idx = ret;
2347                         /* push IV and Michael MIC generation to stack */
2348                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2349                         if (key->alg == ALG_TKIP)
2350                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2351                         ret = 0;
2352                 }
2353                 break;
2354         case DISABLE_KEY:
2355                 ath_key_delete(sc, key);
2356                 break;
2357         default:
2358                 ret = -EINVAL;
2359         }
2360
2361         return ret;
2362 }
2363
2364 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2365                                    struct ieee80211_vif *vif,
2366                                    struct ieee80211_bss_conf *bss_conf,
2367                                    u32 changed)
2368 {
2369         struct ath_softc *sc = hw->priv;
2370
2371         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2372                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2373                         bss_conf->use_short_preamble);
2374                 if (bss_conf->use_short_preamble)
2375                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2376                 else
2377                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2378         }
2379
2380         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2381                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2382                         bss_conf->use_cts_prot);
2383                 if (bss_conf->use_cts_prot &&
2384                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2385                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2386                 else
2387                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2388         }
2389
2390         if (changed & BSS_CHANGED_ASSOC) {
2391                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2392                         bss_conf->assoc);
2393                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2394         }
2395 }
2396
2397 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2398 {
2399         u64 tsf;
2400         struct ath_softc *sc = hw->priv;
2401         struct ath_hal *ah = sc->sc_ah;
2402
2403         tsf = ath9k_hw_gettsf64(ah);
2404
2405         return tsf;
2406 }
2407
2408 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2409 {
2410         struct ath_softc *sc = hw->priv;
2411         struct ath_hal *ah = sc->sc_ah;
2412
2413         ath9k_hw_reset_tsf(ah);
2414 }
2415
2416 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2417                        enum ieee80211_ampdu_mlme_action action,
2418                        struct ieee80211_sta *sta,
2419                        u16 tid, u16 *ssn)
2420 {
2421         struct ath_softc *sc = hw->priv;
2422         int ret = 0;
2423
2424         switch (action) {
2425         case IEEE80211_AMPDU_RX_START:
2426                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2427                         ret = -ENOTSUPP;
2428                 break;
2429         case IEEE80211_AMPDU_RX_STOP:
2430                 break;
2431         case IEEE80211_AMPDU_TX_START:
2432                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2433                 if (ret < 0)
2434                         DPRINTF(sc, ATH_DBG_FATAL,
2435                                 "Unable to start TX aggregation\n");
2436                 else
2437                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2438                 break;
2439         case IEEE80211_AMPDU_TX_STOP:
2440                 ret = ath_tx_aggr_stop(sc, sta, tid);
2441                 if (ret < 0)
2442                         DPRINTF(sc, ATH_DBG_FATAL,
2443                                 "Unable to stop TX aggregation\n");
2444
2445                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2446                 break;
2447         case IEEE80211_AMPDU_TX_RESUME:
2448                 ath_tx_aggr_resume(sc, sta, tid);
2449                 break;
2450         default:
2451                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2452         }
2453
2454         return ret;
2455 }
2456
2457 static struct ieee80211_ops ath9k_ops = {
2458         .tx                 = ath9k_tx,
2459         .start              = ath9k_start,
2460         .stop               = ath9k_stop,
2461         .add_interface      = ath9k_add_interface,
2462         .remove_interface   = ath9k_remove_interface,
2463         .config             = ath9k_config,
2464         .config_interface   = ath9k_config_interface,
2465         .configure_filter   = ath9k_configure_filter,
2466         .sta_notify         = ath9k_sta_notify,
2467         .conf_tx            = ath9k_conf_tx,
2468         .bss_info_changed   = ath9k_bss_info_changed,
2469         .set_key            = ath9k_set_key,
2470         .get_tsf            = ath9k_get_tsf,
2471         .reset_tsf          = ath9k_reset_tsf,
2472         .ampdu_action       = ath9k_ampdu_action,
2473 };
2474
2475 static struct {
2476         u32 version;
2477         const char * name;
2478 } ath_mac_bb_names[] = {
2479         { AR_SREV_VERSION_5416_PCI,     "5416" },
2480         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2481         { AR_SREV_VERSION_9100,         "9100" },
2482         { AR_SREV_VERSION_9160,         "9160" },
2483         { AR_SREV_VERSION_9280,         "9280" },
2484         { AR_SREV_VERSION_9285,         "9285" }
2485 };
2486
2487 static struct {
2488         u16 version;
2489         const char * name;
2490 } ath_rf_names[] = {
2491         { 0,                            "5133" },
2492         { AR_RAD5133_SREV_MAJOR,        "5133" },
2493         { AR_RAD5122_SREV_MAJOR,        "5122" },
2494         { AR_RAD2133_SREV_MAJOR,        "2133" },
2495         { AR_RAD2122_SREV_MAJOR,        "2122" }
2496 };
2497
2498 /*
2499  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2500  */
2501 static const char *
2502 ath_mac_bb_name(u32 mac_bb_version)
2503 {
2504         int i;
2505
2506         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2507                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2508                         return ath_mac_bb_names[i].name;
2509                 }
2510         }
2511
2512         return "????";
2513 }
2514
2515 /*
2516  * Return the RF name. "????" is returned if the RF is unknown.
2517  */
2518 static const char *
2519 ath_rf_name(u16 rf_version)
2520 {
2521         int i;
2522
2523         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2524                 if (ath_rf_names[i].version == rf_version) {
2525                         return ath_rf_names[i].name;
2526                 }
2527         }
2528
2529         return "????";
2530 }
2531
2532 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2533 {
2534         void __iomem *mem;
2535         struct ath_softc *sc;
2536         struct ieee80211_hw *hw;
2537         u8 csz;
2538         u32 val;
2539         int ret = 0;
2540         struct ath_hal *ah;
2541
2542         if (pci_enable_device(pdev))
2543                 return -EIO;
2544
2545         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2546
2547         if (ret) {
2548                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2549                 goto bad;
2550         }
2551
2552         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2553
2554         if (ret) {
2555                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2556                         "DMA enable failed\n");
2557                 goto bad;
2558         }
2559
2560         /*
2561          * Cache line size is used to size and align various
2562          * structures used to communicate with the hardware.
2563          */
2564         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2565         if (csz == 0) {
2566                 /*
2567                  * Linux 2.4.18 (at least) writes the cache line size
2568                  * register as a 16-bit wide register which is wrong.
2569                  * We must have this setup properly for rx buffer
2570                  * DMA to work so force a reasonable value here if it
2571                  * comes up zero.
2572                  */
2573                 csz = L1_CACHE_BYTES / sizeof(u32);
2574                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2575         }
2576         /*
2577          * The default setting of latency timer yields poor results,
2578          * set it to the value used by other systems. It may be worth
2579          * tweaking this setting more.
2580          */
2581         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2582
2583         pci_set_master(pdev);
2584
2585         /*
2586          * Disable the RETRY_TIMEOUT register (0x41) to keep
2587          * PCI Tx retries from interfering with C3 CPU state.
2588          */
2589         pci_read_config_dword(pdev, 0x40, &val);
2590         if ((val & 0x0000ff00) != 0)
2591                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2592
2593         ret = pci_request_region(pdev, 0, "ath9k");
2594         if (ret) {
2595                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2596                 ret = -ENODEV;
2597                 goto bad;
2598         }
2599
2600         mem = pci_iomap(pdev, 0, 0);
2601         if (!mem) {
2602                 printk(KERN_ERR "PCI memory map error\n") ;
2603                 ret = -EIO;
2604                 goto bad1;
2605         }
2606
2607         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2608         if (hw == NULL) {
2609                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2610                 goto bad2;
2611         }
2612
2613         SET_IEEE80211_DEV(hw, &pdev->dev);
2614         pci_set_drvdata(pdev, hw);
2615
2616         sc = hw->priv;
2617         sc->hw = hw;
2618         sc->pdev = pdev;
2619         sc->mem = mem;
2620
2621         if (ath_attach(id->device, sc) != 0) {
2622                 ret = -ENODEV;
2623                 goto bad3;
2624         }
2625
2626         /* setup interrupt service routine */
2627
2628         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2629                 printk(KERN_ERR "%s: request_irq failed\n",
2630                         wiphy_name(hw->wiphy));
2631                 ret = -EIO;
2632                 goto bad4;
2633         }
2634
2635         ah = sc->sc_ah;
2636         printk(KERN_INFO
2637                "%s: Atheros AR%s MAC/BB Rev:%x "
2638                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2639                wiphy_name(hw->wiphy),
2640                ath_mac_bb_name(ah->ah_macVersion),
2641                ah->ah_macRev,
2642                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2643                ah->ah_phyRev,
2644                (unsigned long)mem, pdev->irq);
2645
2646         return 0;
2647 bad4:
2648         ath_detach(sc);
2649 bad3:
2650         ieee80211_free_hw(hw);
2651 bad2:
2652         pci_iounmap(pdev, mem);
2653 bad1:
2654         pci_release_region(pdev, 0);
2655 bad:
2656         pci_disable_device(pdev);
2657         return ret;
2658 }
2659
2660 static void ath_pci_remove(struct pci_dev *pdev)
2661 {
2662         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2663         struct ath_softc *sc = hw->priv;
2664
2665         ath_detach(sc);
2666         if (pdev->irq)
2667                 free_irq(pdev->irq, sc);
2668         pci_iounmap(pdev, sc->mem);
2669         pci_release_region(pdev, 0);
2670         pci_disable_device(pdev);
2671         ieee80211_free_hw(hw);
2672 }
2673
2674 #ifdef CONFIG_PM
2675
2676 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2677 {
2678         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2679         struct ath_softc *sc = hw->priv;
2680
2681         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2682
2683 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2684         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2685                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2686 #endif
2687
2688         pci_save_state(pdev);
2689         pci_disable_device(pdev);
2690         pci_set_power_state(pdev, 3);
2691
2692         return 0;
2693 }
2694
2695 static int ath_pci_resume(struct pci_dev *pdev)
2696 {
2697         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2698         struct ath_softc *sc = hw->priv;
2699         u32 val;
2700         int err;
2701
2702         err = pci_enable_device(pdev);
2703         if (err)
2704                 return err;
2705         pci_restore_state(pdev);
2706         /*
2707          * Suspend/Resume resets the PCI configuration space, so we have to
2708          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2709          * PCI Tx retries from interfering with C3 CPU state
2710          */
2711         pci_read_config_dword(pdev, 0x40, &val);
2712         if ((val & 0x0000ff00) != 0)
2713                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2714
2715         /* Enable LED */
2716         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2717                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2718         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2719
2720 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2721         /*
2722          * check the h/w rfkill state on resume
2723          * and start the rfkill poll timer
2724          */
2725         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2726                 queue_delayed_work(sc->hw->workqueue,
2727                                    &sc->rf_kill.rfkill_poll, 0);
2728 #endif
2729
2730         return 0;
2731 }
2732
2733 #endif /* CONFIG_PM */
2734
2735 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2736
2737 static struct pci_driver ath_pci_driver = {
2738         .name       = "ath9k",
2739         .id_table   = ath_pci_id_table,
2740         .probe      = ath_pci_probe,
2741         .remove     = ath_pci_remove,
2742 #ifdef CONFIG_PM
2743         .suspend    = ath_pci_suspend,
2744         .resume     = ath_pci_resume,
2745 #endif /* CONFIG_PM */
2746 };
2747
2748 static int __init init_ath_pci(void)
2749 {
2750         int error;
2751
2752         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2753
2754         /* Register rate control algorithm */
2755         error = ath_rate_control_register();
2756         if (error != 0) {
2757                 printk(KERN_ERR
2758                         "Unable to register rate control algorithm: %d\n",
2759                         error);
2760                 ath_rate_control_unregister();
2761                 return error;
2762         }
2763
2764         if (pci_register_driver(&ath_pci_driver) < 0) {
2765                 printk(KERN_ERR
2766                         "ath_pci: No devices found, driver not installed.\n");
2767                 ath_rate_control_unregister();
2768                 pci_unregister_driver(&ath_pci_driver);
2769                 return -ENODEV;
2770         }
2771
2772         return 0;
2773 }
2774 module_init(init_ath_pci);
2775
2776 static void __exit exit_ath_pci(void)
2777 {
2778         ath_rate_control_unregister();
2779         pci_unregister_driver(&ath_pci_driver);
2780         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2781 }
2782 module_exit(exit_ath_pci);