1 /* Linker script for the sim85e2c simulator, which is a verilog simulation of
2 the V850E2 NA85E2C cpu core (CONFIG_V850E2_SIM85E2C). */
5 /* 1MB of `instruction RAM', starting at 0.
6 Instruction fetches are much faster from IRAM than from DRAM. */
7 IRAM : ORIGIN = IRAM_ADDR, LENGTH = IRAM_SIZE
9 /* 1MB of `data RAM', below and contiguous with the I/O space.
10 Data fetches are much faster from DRAM than from IRAM. */
11 DRAM : ORIGIN = DRAM_ADDR, LENGTH = DRAM_SIZE
13 /* `external ram' (CS1 area), comes after IRAM. */
14 ERAM : ORIGIN = ERAM_ADDR, LENGTH = ERAM_SIZE
16 /* Dynamic RAM; uses memory controller. */
17 SDRAM : ORIGIN = SDRAM_ADDR, LENGTH = SDRAM_SIZE
23 *arch/v850/kernel/head.o
29 _memcons_output_end = . ;
32 /* We stick console output into a buffer here. */