git.oblomov.eu Git - linux-2.6/blob - drivers/staging/pata_rdc/pata_rdc.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/module.h>
   4
   5 #include <linux/pci.h>
   6 #include <linux/device.h>
   7
   8 #include <scsi/scsi_host.h>
   9 #include <linux/libata.h>
  10
  11 #include "pata_rdc.h"
  12
  13 /* #define DBGPRINTF */
  14
  15 #ifdef DBGPRINTF
  16
  17     #define dbgprintf(format, arg...) printk(KERN_INFO format, ## arg)
  18
  19 #else
  20
  21     #define dbgprintf(...)
  22
  23 #endif
  24
  25 /* Driver Info. */
  26 #define DRIVER_NAME         "pata_rdc"  /* sata_rdc for SATA */
  27 #define DRIVER_VERSION      "2.6.28"    /* based on kernel version. */
  28                                         /* because each kernel main version has
  29                                          * its libata, we follow kernel to
  30                                          * determine the last libata version.
  31                                          */
  32
  33
  34 static const struct pci_device_id rdc_pata_id_table[] = {
  35         { 0x17F3, 0x1011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31011},
  36         { 0x17F3, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RDC_17F31012},
  37         { }     /* terminate list */
  38 };
  39
  40 MODULE_LICENSE("GPL");
  41 MODULE_AUTHOR("this version author is RDC");    /* replace "RDC" with the last maintainer. */
  42 MODULE_DESCRIPTION("RDC PCI IDE Driver");
  43 MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
  44 MODULE_VERSION(DRIVER_VERSION);
  45
  46 /* a pci driver */
  47 static struct pci_driver rdc_pata_driver = {
  48         .name           = DRIVER_NAME,
  49         .id_table       = rdc_pata_id_table,
  50         .probe          = rdc_init_one,
  51         .remove         = ata_pci_remove_one,
  52 #ifdef CONFIG_PM
  53         .suspend        = ata_pci_device_suspend,
  54         .resume         = ata_pci_device_resume,
  55 #endif
  56 };
  57
  58 static unsigned int in_module_init = 1; /* hotplugging check??? */
  59 static int __init pata_rdc_init(void)
  60 {
  61         int rc;
  62
  63         dbgprintf("pata_rdc_init\n");
  64         rc = pci_register_driver(&rdc_pata_driver);
  65         if (rc) {
  66                 dbgprintf("pata_rdc_init faile\n");
  67                 return rc;
  68         }
  69
  70         in_module_init = 0;
  71
  72         return 0;
  73 }
  74
  75 static void __exit pata_rdc_exit(void)
  76 {
  77         dbgprintf("pata_rdc_exit\n");
  78         pci_unregister_driver(&rdc_pata_driver);
  79 }
  80
  81 module_init(pata_rdc_init);
  82 module_exit(pata_rdc_exit);
  83
  84 /* ata device data */
  85
  86 /* see ATA Host Adapters Standards. */
  87 static struct pci_bits ATA_Decode_Enable_Bits[] = {
  88         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 0 */
  89         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 1 */
  90 };
  91
  92 /* pata host template */
  93 static struct scsi_host_template rdc_pata_sht = {
  94         ATA_BMDMA_SHT(DRIVER_NAME),
  95 };
  96
  97 static const struct ata_port_operations rdc_pata_ops = {
  98         .inherits       = &ata_bmdma_port_ops,
  99
 100         .port_start     = rdc_pata_port_start,
 101         .port_stop      = rdc_pata_port_stop,
 102         .prereset       = rdc_pata_prereset,
 103         .cable_detect   = rdc_pata_cable_detect,
 104         .set_piomode    = rdc_pata_set_piomode,
 105         .set_dmamode    = rdc_pata_set_dmamode,
 106 };
 107
 108 static struct ata_port_info rdc_pata_port_info[] = {
 109         [RDC_17F31011] = {
 110         .flags          = ATA_FLAG_SLAVE_POSS,
 111         .pio_mask       = 0x1f,         /* pio0-4 */
 112         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 113         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 114         .port_ops       = &rdc_pata_ops,
 115         },
 116
 117         [RDC_17F31012] = {
 118         .flags          = ATA_FLAG_SLAVE_POSS,
 119         .pio_mask       = 0x1f,         /* pio0-4 */
 120         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 121         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 122         .port_ops       = &rdc_pata_ops,
 123         },
 124 };
 125
 126
 127
 128
 129 /* callback function for pci_driver */
 130
 131 /**
 132  *    Register ATA PCI device with kernel services
 133  *    @pdev: PCI device to register
 134  *    @ent: Entry in sch_pci_tbl matching with @pdev
 135  *
 136  *    LOCKING:
 137  *    Inherited from PCI layer (may sleep).
 138  *
 139  *    RETURNS:
 140  *    Zero on success, or -ERRNO value.
 141  */
 142 static int __devinit rdc_init_one(struct pci_dev *pdev,
 143                                   const struct pci_device_id *ent)
 144 {
 145         /*struct device *dev = &pdev->dev; */
 146         struct ata_port_info port_info[2];
 147         const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
 148
 149         int rc;
 150
 151         dbgprintf("rdc_init_one\n");
 152
 153         /* no hotplugging support (FIXME) */ /* why??? */
 154         if (!in_module_init) {
 155                 dbgprintf("rdc_init_one in_module_init == 0 failed \n");
 156                 return -ENODEV;
 157         }
 158         port_info[0] = rdc_pata_port_info[ent->driver_data];
 159         port_info[1] = rdc_pata_port_info[ent->driver_data];
 160
 161         /* enable device and prepare host */
 162         rc = pci_enable_device(pdev);
 163         if (rc) {
 164                 dbgprintf("rdc_init_one pci_enable_device failed \n");
 165                 return rc;
 166         }
 167         /* initialize controller */
 168
 169         pci_intx(pdev, 1);  /* enable interrupt */
 170
 171         return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
 172 }
 173
 174 /* callback function for ata_port */
 175
 176 /**
 177  *    Set port up for dma.
 178  *    @ap: Port to initialize
 179  *
 180  *    Called just after data structures for each port are
 181  *    initialized.  Allocates space for PRD table if the device
 182  *    is DMA capable SFF.
 183
 184     Some drivers also use this entry point as a chance to allocate driverprivate
 185     memory for ap->private_data.
 186
 187  *
 188  *    May be used as the port_start() entry in ata_port_operations.
 189  *
 190  *    LOCKING:
 191  *    Inherited from caller.
 192  */
 193 static int rdc_pata_port_start(struct ata_port *ap)
 194 {
 195         uint    Channel;
 196
 197         Channel = ap->port_no;
 198         dbgprintf("rdc_pata_port_start Channel: %u \n", Channel);
 199         if (ap->ioaddr.bmdma_addr) {
 200                 return ata_port_start(ap);
 201         } else {
 202                 dbgprintf("rdc_pata_port_start return 0 !!!\n");
 203                 return 0;
 204         }
 205 }
 206
 207 static void rdc_pata_port_stop(struct ata_port *ap)
 208 {
 209         uint    Channel;
 210
 211         Channel = ap->port_no;
 212
 213         dbgprintf("rdc_pata_port_stop Channel: %u \n", Channel);
 214 }
 215
 216 /**
 217  *    prereset for PATA host controller
 218  *    @link: Target link
 219  *    @deadline: deadline jiffies for the operation
 220  *
 221  *    LOCKING:
 222  *    None (inherited from caller).
 223  */
 224 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
 225 {
 226         struct pci_dev *pdev;
 227         struct ata_port *ap;
 228         uint Channel;
 229
 230         dbgprintf("rdc_pata_prereset\n");
 231
 232         ap = link->ap;
 233         pdev = to_pci_dev(ap->host->dev);
 234
 235         Channel = ap->port_no;
 236
 237         /* test ATA Decode Enable Bits, should be enable. */
 238         if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
 239                 dbgprintf("rdc_pata_prereset Channel: %u, Decode Disable\n", Channel);
 240                 return -ENOENT;
 241         } else {
 242                 dbgprintf("rdc_pata_prereset Channel: %u, Decode Enable\n", Channel);
 243                 return ata_std_prereset(link, deadline);
 244         }
 245 }
 246
 247 /**
 248  *    Probe host controller cable detect info
 249  *    @ap: Port for which cable detect info is desired
 250  *
 251  *    Read cable indicator from ATA PCI device's PCI config
 252  *    register.  This register is normally set by firmware (BIOS).
 253  *
 254  *    LOCKING:
 255  *    None (inherited from caller).
 256  */
 257 static int rdc_pata_cable_detect(struct ata_port *ap)
 258 {
 259         struct pci_dev *pdev;
 260         uint Channel;
 261         uint Mask;
 262         u32 u32Value;
 263
 264         dbgprintf("rdc_pata_cable_detect\n");
 265
 266         pdev = to_pci_dev(ap->host->dev);
 267
 268         Channel = ap->port_no;
 269
 270         if (Channel == 0)
 271                 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
 272         else
 273                 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
 274
 275         /* check BIOS cable detect results */
 276         pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
 277
 278         if ((u32Value & Mask) == 0) {
 279                 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA40 \n", Channel);
 280                 return ATA_CBL_PATA40;
 281         } else {
 282                 dbgprintf("rdc_pata_cable_detect Channel: %u, PATA80 \n", Channel);
 283                 return ATA_CBL_PATA80;
 284         }
 285 }
 286
 287 /**
 288  *    Initialize host controller PATA PIO timings
 289  *    @ap: Port whose timings we are configuring
 290  *    @adev: um
 291  *
 292  *    Set PIO mode for device, in host controller PCI config space.
 293  *
 294  *    LOCKING:
 295  *    None (inherited from caller).
 296  */
 297 static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
 298 {
 299         struct pci_dev *pdev;
 300         uint    Channel;
 301         uint    DeviceID;
 302         uint    PIOTimingMode;
 303         uint    PrefetchPostingEnable;
 304
 305         dbgprintf("rdc_pata_set_piomode\n");
 306
 307         pdev = to_pci_dev(ap->host->dev);
 308
 309         Channel = ap->port_no;
 310         DeviceID = adev->devno;
 311         /*
 312          * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
 313          * XFER_PIO_2, XFER_PIO_3...
 314          */
 315         PIOTimingMode = adev->pio_mode - XFER_PIO_0;
 316
 317         if (adev->class == ATA_DEV_ATA) {
 318                 PrefetchPostingEnable = TRUE;
 319         } else {
 320                 /* ATAPI, CD DVD Rom */
 321                 PrefetchPostingEnable = FALSE;
 322         }
 323
 324         /* PIO configuration clears DTE unconditionally.  It will be
 325          * programmed in set_dmamode which is guaranteed to be called
 326          * after set_piomode if any DMA mode is available.
 327          */
 328
 329         /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
 330          * selected */
 331
 332         if (Channel == 0) {
 333                 ATAHostAdapter_SetPrimaryPIO(
 334                     pdev,
 335                     DeviceID,
 336                     PIOTimingMode,
 337                     TRUE,/* DMAEnable, */
 338                     PrefetchPostingEnable
 339                     );
 340
 341                 ATAHostAdapter_SetPrimaryUDMA(
 342                     pdev,
 343                     DeviceID,
 344                     FALSE,/* UDMAEnable, */
 345                     UDMA0
 346                     );
 347         } else {
 348                 ATAHostAdapter_SetSecondaryPIO(
 349                     pdev,
 350                     DeviceID,
 351                     PIOTimingMode,
 352                     TRUE,/* DMAEnable, */
 353                     PrefetchPostingEnable
 354                     );
 355
 356                 ATAHostAdapter_SetSecondaryUDMA(
 357                     pdev,
 358                     DeviceID,
 359                     FALSE,/* UDMAEnable, */
 360                     UDMA0
 361                     );
 362         }
 363         dbgprintf("rdc_pata_set_piomode Channel: %u, DeviceID: %u, PIO: %d \n", Channel, DeviceID, PIOTimingMode);
 364 }
 365
 366 /**
 367  *    Initialize host controller PATA DMA timings
 368  *    @ap: Port whose timings we are configuring
 369  *    @adev: um
 370  *
 371  *    Set MW/UDMA mode for device, in host controller PCI config space.
 372  *
 373  *    LOCKING:
 374  *    None (inherited from caller).
 375  */
 376 static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 377 {
 378         struct pci_dev *pdev;
 379         uint    Channel;
 380         uint    DeviceID;
 381         uint    PIOTimingMode;
 382         uint    PrefetchPostingEnable;
 383         uint    DMATimingMode;
 384         uint    UDMAEnable;
 385
 386         dbgprintf("rdc_pata_set_dmamode\n");
 387
 388         pdev = to_pci_dev(ap->host->dev);
 389
 390         Channel = ap->port_no;
 391         DeviceID = adev->devno;
 392         PIOTimingMode = adev->pio_mode - XFER_PIO_0;  /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
 393         DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
 394
 395         if (adev->class == ATA_DEV_ATA) {
 396                 PrefetchPostingEnable = TRUE;
 397         } else {
 398                 /* ATAPI, CD DVD Rom */
 399                 PrefetchPostingEnable = FALSE;
 400         }
 401
 402         if (ap->udma_mask == 0) {
 403                 /* ata_port dont support udma. depend on hardware spec. */
 404                 UDMAEnable = FALSE;
 405         } else {
 406                 UDMAEnable = TRUE;
 407         }
 408
 409         /*if (ap->mdma_mask == 0) {
 410         }*/
 411
 412         if (Channel == 0) {
 413                 if (DMATimingMode >= XFER_UDMA_0) {
 414                         /* UDMA */
 415                         ATAHostAdapter_SetPrimaryPIO(pdev,
 416                                 DeviceID,
 417                                 PIOTimingMode,
 418                                 TRUE,/*DMAEnable,*/
 419                                 PrefetchPostingEnable);
 420
 421                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 422                                 DeviceID,
 423                                 UDMAEnable,
 424                                 DMATimingMode - XFER_UDMA_0);
 425                         dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
 426                 } else {
 427                         /* MDMA */
 428                         ATAHostAdapter_SetPrimaryPIO(pdev,
 429                                 DeviceID,
 430                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 431                                 TRUE,/*DMAEnable,*/
 432                                 PrefetchPostingEnable);
 433
 434                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 435                                 DeviceID,
 436                                 FALSE,/*UDMAEnable,*/
 437                                 UDMA0);
 438                         dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
 439                 }
 440         } else {
 441                 if (DMATimingMode >= XFER_UDMA_0) {
 442                         /* UDMA */
 443                         ATAHostAdapter_SetSecondaryPIO(pdev,
 444                                 DeviceID,
 445                                 PIOTimingMode,
 446                                 TRUE,/*DMAEnable,*/
 447                                 PrefetchPostingEnable);
 448
 449                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 450                                 DeviceID,
 451                                 UDMAEnable,
 452                                 DMATimingMode - XFER_UDMA_0);
 453                         dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, UDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_UDMA_0));
 454                 } else {
 455                         /* MDMA */
 456                         ATAHostAdapter_SetSecondaryPIO(pdev,
 457                                 DeviceID,
 458                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 459                                 TRUE,/*DMAEnable,*/
 460                                 PrefetchPostingEnable);
 461
 462                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 463                                 DeviceID,
 464                                 FALSE,/*UDMAEnable,*/
 465                                 UDMA0);
 466                         dbgprintf("rdc_pata_set_dmamode Channel: %u, DeviceID: %u, MDMA: %u \n", Channel, DeviceID, (uint)(DMATimingMode - XFER_MW_DMA_0));
 467                 }
 468         }
 469 }
 470
 471 /* modified PCIDeviceIO code. */
 472
 473 static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
 474 {
 475         uint funcresult;
 476         unchar *pchar;
 477         uint i;
 478
 479         funcresult = TRUE;
 480
 481         pchar = pBuffer;
 482
 483         for (i = 0; i < Length; i++) {
 484                 pci_read_config_byte(pdev, Offset, pchar);
 485                 Offset++;
 486                 pchar++;
 487         }
 488
 489         funcresult = TRUE;
 490
 491         goto funcexit;
 492 funcexit:
 493
 494         return funcresult;
 495 }
 496
 497 static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
 498 {
 499         uint funcresult;
 500         unchar *pchar;
 501         uint i;
 502
 503         funcresult = TRUE;
 504
 505         pchar = pBuffer;
 506
 507         for (i = 0; i < Length; i++) {
 508                 pci_write_config_byte(pdev, Offset, *pchar);
 509                 Offset++;
 510                 pchar++;
 511         }
 512
 513         funcresult = TRUE;
 514
 515         goto funcexit;
 516 funcexit:
 517
 518         return funcresult;
 519 }
 520
 521 /* modified ATAHostAdapter code. */
 522 static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
 523                                          uint PIOTimingMode, uint DMAEnable,
 524                                          uint PrefetchPostingEnable)
 525 {
 526         uint funcresult;
 527         uint result;
 528         uint ATATimingRegister;
 529         uint Device1TimingRegister;
 530
 531         funcresult = TRUE;
 532
 533         ATATimingRegister = 0;
 534         Device1TimingRegister = 0;
 535
 536         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 537                                                  ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
 538                                                  ATAConfiguration_ID_PrimaryTiming_Size,
 539                                                  &ATATimingRegister);
 540         if (result == FALSE) {
 541                 funcresult = FALSE;
 542                 goto funcexit;
 543         }
 544
 545         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 546                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 547                                                   ATAConfiguration_ID_Device1Timing_Size,
 548                                                   &Device1TimingRegister);
 549         if (result == FALSE) {
 550                 funcresult = FALSE;
 551                 goto funcexit;
 552         }
 553
 554         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 555
 556         switch (DeviceID) {
 557         case 0:
 558                 /* mask clear */
 559                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 560                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 561                                       ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 562                                       ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 563                                       ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 564                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 565
 566                 if (PIOTimingMode > PIO0)
 567                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 568
 569                 if (PIOTimingMode >= PIO3)
 570                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 571
 572                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 573                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 574
 575                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 576                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 577
 578                 if (PIOTimingMode <= PIO2)
 579                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 580                 else if (PIOTimingMode == PIO3)
 581                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 582                 else if (PIOTimingMode == PIO4)
 583                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 584
 585                 if (PIOTimingMode <= PIO1)
 586                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 587                 else if (PIOTimingMode == PIO2)
 588                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 589                 else if (PIOTimingMode <= PIO4)
 590                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 591                 break;
 592         case 1:
 593                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 594                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 595                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 596                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 597
 598                 if (PIOTimingMode > PIO0)
 599                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 600
 601                 if (PIOTimingMode >= PIO3)
 602                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 603
 604                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 605                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 606
 607                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 608                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 609
 610                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode |
 611                                            ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
 612
 613                 if (PIOTimingMode <= PIO2)
 614                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
 615                 else if (PIOTimingMode == PIO3)
 616                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
 617                 else if (PIOTimingMode == PIO4)
 618                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
 619
 620                 if (PIOTimingMode <= PIO1)
 621                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
 622                 else if (PIOTimingMode == PIO2)
 623                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
 624                 else if (PIOTimingMode <= PIO4)
 625                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
 626                 break;
 627         default:
 628                 funcresult = FALSE;
 629                 goto funcexit;
 630                 break;
 631         }
 632
 633         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 634                                                    ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
 635                                                    ATAConfiguration_ID_PrimaryTiming_Size,
 636                                                    &ATATimingRegister);
 637         if (result == FALSE) {
 638                 funcresult = FALSE;
 639                 goto funcexit;
 640         }
 641
 642         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 643                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 644                                                    ATAConfiguration_ID_Device1Timing_Size,
 645                                                    &Device1TimingRegister);
 646         if (result == FALSE) {
 647                 funcresult = FALSE;
 648                 goto funcexit;
 649         }
 650
 651         goto funcexit;
 652 funcexit:
 653
 654         return funcresult;
 655 }
 656
 657 static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID,
 658                                            uint PIOTimingMode, uint DMAEnable,
 659                                            uint PrefetchPostingEnable)
 660 {
 661         uint funcresult;
 662         uint result;
 663         uint ATATimingRegister;
 664         uint Device1TimingRegister;
 665
 666         funcresult = TRUE;
 667
 668         ATATimingRegister = 0;
 669         Device1TimingRegister = 0;
 670
 671         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 672                                                   ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 673                                                   ATAConfiguration_ID_SecondaryTiming_Size,
 674                                                   &ATATimingRegister);
 675         if (result == FALSE) {
 676                 funcresult = FALSE;
 677                 goto funcexit;
 678         }
 679
 680         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 681                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 682                                                   ATAConfiguration_ID_Device1Timing_Size,
 683                                                   &Device1TimingRegister);
 684         if (result == FALSE) {
 685                 funcresult = FALSE;
 686                 goto funcexit;
 687         }
 688
 689         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 690
 691         switch (DeviceID) {
 692         case 0:
 693                 /* mask clear */
 694                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 695                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 696                                        ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 697                                        ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 698                                        ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 699                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 700
 701                 if (PIOTimingMode > PIO0)
 702                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 703
 704                 if (PIOTimingMode >= PIO3)
 705                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 706
 707                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 708                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 709
 710                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 711                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 712
 713                 if (PIOTimingMode <= PIO2)
 714                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 715                 else if (PIOTimingMode == PIO3)
 716                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 717                 else if (PIOTimingMode == PIO4)
 718                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 719
 720                 if (PIOTimingMode <= PIO1)
 721                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 722                 else if (PIOTimingMode == PIO2)
 723                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 724                 else if (PIOTimingMode <= PIO4)
 725                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 726                 break;
 727         case 1:
 728                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 729                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 730                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 731                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 732
 733                 if (PIOTimingMode > PIO0)
 734                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 735
 736                 if (PIOTimingMode >= PIO3)
 737                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 738
 739                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 740                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 741
 742                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 743                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 744
 745                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode |
 746                                            ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
 747
 748                 if (PIOTimingMode <= PIO2)
 749                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
 750                 else if (PIOTimingMode == PIO3)
 751                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
 752                 else if (PIOTimingMode == PIO4)
 753                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
 754
 755                 if (PIOTimingMode <= PIO1)
 756                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
 757                 else if (PIOTimingMode == PIO2)
 758                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
 759                 else if (PIOTimingMode <= PIO4)
 760                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
 761                 break;
 762         default:
 763                 funcresult = FALSE;
 764                 goto funcexit;
 765                 break;
 766         }
 767
 768         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 769                                                    ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 770                                                    ATAConfiguration_ID_SecondaryTiming_Size,
 771                                                    &ATATimingRegister);
 772         if (result == FALSE) {
 773                 funcresult = FALSE;
 774                 goto funcexit;
 775         }
 776
 777         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 778                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 779                                                    ATAConfiguration_ID_Device1Timing_Size,
 780                                                    &Device1TimingRegister);
 781         if (result == FALSE) {
 782                 funcresult = FALSE;
 783                 goto funcexit;
 784         }
 785
 786         goto funcexit;
 787 funcexit:
 788         return funcresult;
 789 }
 790
 791 static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID,
 792                                           uint UDMAEnable, uint UDMATimingMode)
 793 {
 794         uint funcresult;
 795         uint result;
 796         uint UDMAControlRegister;
 797         uint UDMATimingRegister;
 798         ulong IDEIOConfigurationRegister;
 799
 800         funcresult = TRUE;
 801         UDMAControlRegister = 0;
 802         UDMATimingRegister = 0;
 803         IDEIOConfigurationRegister = 0;
 804
 805         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 806                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 807                                                   ATAConfiguration_ID_UDMAControl_Size,
 808                                                   &UDMAControlRegister);
 809         if (result == FALSE) {
 810                 funcresult = FALSE;
 811                 goto funcexit;
 812         }
 813
 814         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 815                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 816                                                   ATAConfiguration_ID_UDMATiming_Size,
 817                                                   &UDMATimingRegister);
 818         if (result == FALSE) {
 819                 funcresult = FALSE;
 820                 goto funcexit;
 821         }
 822
 823         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 824                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 825                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 826                                                   &IDEIOConfigurationRegister);
 827         if (result == FALSE) {
 828                 funcresult = FALSE;
 829                 goto funcexit;
 830         }
 831
 832         /*Rom Code will determine the device cable type and ATA 100.*/
 833         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
 834         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
 835
 836         switch (DeviceID) {
 837         case 0:
 838                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
 839                 if (UDMAEnable == TRUE)
 840                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable;
 841
 842                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable |
 843                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable);
 844
 845                 if (UDMATimingMode >= UDMA5)
 846                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable;
 847                 else if (UDMATimingMode >= UDMA3)
 848                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
 849
 850                 /* if 80 cable report */
 851                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime);
 852
 853                 if (UDMATimingMode == UDMA0) {
 854                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0;
 855                 } else if (UDMATimingMode == UDMA1 ||
 856                            UDMATimingMode == UDMA3 ||
 857                            UDMATimingMode == UDMA5) {
 858                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1;
 859                 } else if (UDMATimingMode == UDMA2 ||
 860                            UDMATimingMode == UDMA4) {
 861                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2;
 862                 }
 863                 break;
 864         case 1:
 865                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable);
 866                 if (UDMAEnable == TRUE)
 867                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable;
 868
 869                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable |
 870                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable);
 871
 872                 if (UDMATimingMode >= UDMA5)
 873                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable;
 874                 else if (UDMATimingMode >= UDMA3)
 875                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable;
 876
 877                 /* if 80 cable report */
 878                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime);
 879
 880                 if (UDMATimingMode == UDMA0) {
 881                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0;
 882                 } else if (UDMATimingMode == UDMA1 ||
 883                            UDMATimingMode == UDMA3 ||
 884                            UDMATimingMode == UDMA5) {
 885                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1;
 886                 } else if (UDMATimingMode == UDMA2 ||
 887                            UDMATimingMode == UDMA4) {
 888                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2;
 889                 }
 890                 break;
 891         default:
 892                 funcresult = FALSE;
 893                 goto funcexit;
 894                 break;
 895         }
 896
 897         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 898                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 899                                                    ATAConfiguration_ID_UDMAControl_Size,
 900                                                    &UDMAControlRegister);
 901         if (result == FALSE) {
 902                 funcresult = FALSE;
 903                 goto funcexit;
 904         }
 905
 906         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 907                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 908                                                    ATAConfiguration_ID_UDMATiming_Size,
 909                                                    &UDMATimingRegister);
 910         if (result == FALSE) {
 911                 funcresult = FALSE;
 912                 goto funcexit;
 913         }
 914
 915         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 916                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 917                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
 918                                                    &IDEIOConfigurationRegister);
 919         if (result == FALSE) {
 920                 funcresult = FALSE;
 921                 goto funcexit;
 922         }
 923
 924         goto funcexit;
 925 funcexit:
 926         return funcresult;
 927 }
 928
 929 static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
 930                                             uint UDMAEnable, uint UDMATimingMode)
 931 {
 932         uint funcresult;
 933         uint result;
 934         uint UDMAControlRegister;
 935         uint UDMATimingRegister;
 936         ulong IDEIOConfigurationRegister;
 937
 938         funcresult = TRUE;
 939
 940         UDMAControlRegister = 0;
 941         UDMATimingRegister = 0;
 942         IDEIOConfigurationRegister = 0;
 943
 944         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 945                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 946                                                   ATAConfiguration_ID_UDMAControl_Size,
 947                                                   &UDMAControlRegister);
 948         if (result == FALSE) {
 949                 funcresult = FALSE;
 950                 goto funcexit;
 951         }
 952
 953         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 954                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 955                                                   ATAConfiguration_ID_UDMATiming_Size,
 956                                                   &UDMATimingRegister);
 957         if (result == FALSE) {
 958                 funcresult = FALSE;
 959                 goto funcexit;
 960         }
 961
 962         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 963                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 964                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 965                                                   &IDEIOConfigurationRegister);
 966         if (result == FALSE) {
 967                 funcresult = FALSE;
 968                 goto funcexit;
 969         }
 970
 971         /* Rom Code will determine the device cable type and ATA 100. */
 972         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
 973         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
 974
 975         switch (DeviceID) {
 976         case 0:
 977                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable);
 978                 if (UDMAEnable == TRUE)
 979                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable;
 980
 981                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable |
 982                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable);
 983
 984                 if (UDMATimingMode >= UDMA5)
 985                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable;
 986                 else if (UDMATimingMode >= UDMA3)
 987                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable;
 988
 989                 /* if 80 cable report */
 990                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime);
 991
 992                 if (UDMATimingMode == UDMA0) {
 993                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
 994                 } else if (UDMATimingMode == UDMA1 ||
 995                            UDMATimingMode == UDMA3 ||
 996                            UDMATimingMode == UDMA5) {
 997                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1;
 998                 } else if (UDMATimingMode == UDMA2 ||
 999                            UDMATimingMode == UDMA4) {
1000                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2;
1001                 }
1002                 break;
1003         case 1:
1004                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable);
1005                 if (UDMAEnable == TRUE)
1006                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable;
1007
1008                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable |
1009                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable);
1010
1011                 if (UDMATimingMode >= UDMA5)
1012                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable;
1013                 else if (UDMATimingMode >= UDMA3)
1014                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable;
1015
1016                 /* if 80 cable report */
1017                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime);
1018
1019                 if (UDMATimingMode == UDMA0) {
1020                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0;
1021                 } else if (UDMATimingMode == UDMA1 ||
1022                            UDMATimingMode == UDMA3 ||
1023                            UDMATimingMode == UDMA5) {
1024                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1;
1025                 } else if (UDMATimingMode == UDMA2 ||
1026                            UDMATimingMode == UDMA4) {
1027                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
1028                 }
1029                 break;
1030         default:
1031                 funcresult = FALSE;
1032                 goto funcexit;
1033                 break;
1034         }
1035
1036         result = PCIDeviceIO_WritePCIConfiguration(pdev,
1037                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
1038                                                    ATAConfiguration_ID_UDMAControl_Size,
1039                                                    &UDMAControlRegister);
1040         if (result == FALSE) {
1041                 funcresult = FALSE;
1042                 goto funcexit;
1043         }
1044
1045         result = PCIDeviceIO_WritePCIConfiguration(pdev,
1046                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
1047                                                    ATAConfiguration_ID_UDMATiming_Size,
1048                                                    &UDMATimingRegister);
1049         if (result == FALSE) {
1050                 funcresult = FALSE;
1051                 goto funcexit;
1052         }
1053
1054         result = PCIDeviceIO_WritePCIConfiguration(pdev,
1055                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
1056                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
1057                                                    &IDEIOConfigurationRegister);
1058         if (result == FALSE) {
1059                 funcresult = FALSE;
1060                 goto funcexit;
1061         }
1062
1063         goto funcexit;
1064 funcexit:
1065         return funcresult;
1066 }