git.oblomov.eu Git - linux-2.6/blob - drivers/char/synclink_gt.c

   1 /*
   2  * Device driver for Microgate SyncLink GT serial adapters.
   3  *
   4  * written by Paul Fulghum for Microgate Corporation
   5  * paulkf@microgate.com
   6  *
   7  * Microgate and SyncLink are trademarks of Microgate Corporation
   8  *
   9  * This code is released under the GNU General Public License (GPL)
  10  *
  11  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  12  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  13  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  14  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  15  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  16  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  17  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  18  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  19  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  20  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  21  * OF THE POSSIBILITY OF SUCH DAMAGE.
  22  */
  23
  24 /*
  25  * DEBUG OUTPUT DEFINITIONS
  26  *
  27  * uncomment lines below to enable specific types of debug output
  28  *
  29  * DBGINFO   information - most verbose output
  30  * DBGERR    serious errors
  31  * DBGBH     bottom half service routine debugging
  32  * DBGISR    interrupt service routine debugging
  33  * DBGDATA   output receive and transmit data
  34  * DBGTBUF   output transmit DMA buffers and registers
  35  * DBGRBUF   output receive DMA buffers and registers
  36  */
  37
  38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
  39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
  40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
  41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
  42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
  43 //#define DBGTBUF(info) dump_tbufs(info)
  44 //#define DBGRBUF(info) dump_rbufs(info)
  45
  46
  47 #include <linux/module.h>
  48 #include <linux/errno.h>
  49 #include <linux/signal.h>
  50 #include <linux/sched.h>
  51 #include <linux/timer.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/tty.h>
  55 #include <linux/tty_flip.h>
  56 #include <linux/serial.h>
  57 #include <linux/major.h>
  58 #include <linux/string.h>
  59 #include <linux/fcntl.h>
  60 #include <linux/ptrace.h>
  61 #include <linux/ioport.h>
  62 #include <linux/mm.h>
  63 #include <linux/seq_file.h>
  64 #include <linux/slab.h>
  65 #include <linux/netdevice.h>
  66 #include <linux/vmalloc.h>
  67 #include <linux/init.h>
  68 #include <linux/delay.h>
  69 #include <linux/ioctl.h>
  70 #include <linux/termios.h>
  71 #include <linux/bitops.h>
  72 #include <linux/workqueue.h>
  73 #include <linux/hdlc.h>
  74 #include <linux/synclink.h>
  75
  76 #include <asm/system.h>
  77 #include <asm/io.h>
  78 #include <asm/irq.h>
  79 #include <asm/dma.h>
  80 #include <asm/types.h>
  81 #include <asm/uaccess.h>
  82
  83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
  84 #define SYNCLINK_GENERIC_HDLC 1
  85 #else
  86 #define SYNCLINK_GENERIC_HDLC 0
  87 #endif
  88
  89 /*
  90  * module identification
  91  */
  92 static char *driver_name     = "SyncLink GT";
  93 static char *tty_driver_name = "synclink_gt";
  94 static char *tty_dev_prefix  = "ttySLG";
  95 MODULE_LICENSE("GPL");
  96 #define MGSL_MAGIC 0x5401
  97 #define MAX_DEVICES 32
  98
  99 static struct pci_device_id pci_table[] = {
 100         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 101         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 102         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 103         {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
 104         {0,}, /* terminate list */
 105 };
 106 MODULE_DEVICE_TABLE(pci, pci_table);
 107
 108 static int  init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 109 static void remove_one(struct pci_dev *dev);
 110 static struct pci_driver pci_driver = {
 111         .name           = "synclink_gt",
 112         .id_table       = pci_table,
 113         .probe          = init_one,
 114         .remove         = __devexit_p(remove_one),
 115 };
 116
 117 static bool pci_registered;
 118
 119 /*
 120  * module configuration and status
 121  */
 122 static struct slgt_info *slgt_device_list;
 123 static int slgt_device_count;
 124
 125 static int ttymajor;
 126 static int debug_level;
 127 static int maxframe[MAX_DEVICES];
 128
 129 module_param(ttymajor, int, 0);
 130 module_param(debug_level, int, 0);
 131 module_param_array(maxframe, int, NULL, 0);
 132
 133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
 134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
 135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
 136
 137 /*
 138  * tty support and callbacks
 139  */
 140 static struct tty_driver *serial_driver;
 141
 142 static int  open(struct tty_struct *tty, struct file * filp);
 143 static void close(struct tty_struct *tty, struct file * filp);
 144 static void hangup(struct tty_struct *tty);
 145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
 146
 147 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 148 static int put_char(struct tty_struct *tty, unsigned char ch);
 149 static void send_xchar(struct tty_struct *tty, char ch);
 150 static void wait_until_sent(struct tty_struct *tty, int timeout);
 151 static int  write_room(struct tty_struct *tty);
 152 static void flush_chars(struct tty_struct *tty);
 153 static void flush_buffer(struct tty_struct *tty);
 154 static void tx_hold(struct tty_struct *tty);
 155 static void tx_release(struct tty_struct *tty);
 156
 157 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 158 static int  chars_in_buffer(struct tty_struct *tty);
 159 static void throttle(struct tty_struct * tty);
 160 static void unthrottle(struct tty_struct * tty);
 161 static int set_break(struct tty_struct *tty, int break_state);
 162
 163 /*
 164  * generic HDLC support and callbacks
 165  */
 166 #if SYNCLINK_GENERIC_HDLC
 167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 168 static void hdlcdev_tx_done(struct slgt_info *info);
 169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
 170 static int  hdlcdev_init(struct slgt_info *info);
 171 static void hdlcdev_exit(struct slgt_info *info);
 172 #endif
 173
 174
 175 /*
 176  * device specific structures, macros and functions
 177  */
 178
 179 #define SLGT_MAX_PORTS 4
 180 #define SLGT_REG_SIZE  256
 181
 182 /*
 183  * conditional wait facility
 184  */
 185 struct cond_wait {
 186         struct cond_wait *next;
 187         wait_queue_head_t q;
 188         wait_queue_t wait;
 189         unsigned int data;
 190 };
 191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
 192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
 193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
 194 static void flush_cond_wait(struct cond_wait **head);
 195
 196 /*
 197  * DMA buffer descriptor and access macros
 198  */
 199 struct slgt_desc
 200 {
 201         __le16 count;
 202         __le16 status;
 203         __le32 pbuf;  /* physical address of data buffer */
 204         __le32 next;  /* physical address of next descriptor */
 205
 206         /* driver book keeping */
 207         char *buf;          /* virtual  address of data buffer */
 208         unsigned int pdesc; /* physical address of this descriptor */
 209         dma_addr_t buf_dma_addr;
 210         unsigned short buf_count;
 211 };
 212
 213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
 214 #define set_desc_next(a,b) (a).next   = cpu_to_le32((unsigned int)(b))
 215 #define set_desc_count(a,b)(a).count  = cpu_to_le16((unsigned short)(b))
 216 #define set_desc_eof(a,b)  (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
 217 #define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
 218 #define desc_count(a)      (le16_to_cpu((a).count))
 219 #define desc_status(a)     (le16_to_cpu((a).status))
 220 #define desc_complete(a)   (le16_to_cpu((a).status) & BIT15)
 221 #define desc_eof(a)        (le16_to_cpu((a).status) & BIT2)
 222 #define desc_crc_error(a)  (le16_to_cpu((a).status) & BIT1)
 223 #define desc_abort(a)      (le16_to_cpu((a).status) & BIT0)
 224 #define desc_residue(a)    ((le16_to_cpu((a).status) & 0x38) >> 3)
 225
 226 struct _input_signal_events {
 227         int ri_up;
 228         int ri_down;
 229         int dsr_up;
 230         int dsr_down;
 231         int dcd_up;
 232         int dcd_down;
 233         int cts_up;
 234         int cts_down;
 235 };
 236
 237 /*
 238  * device instance data structure
 239  */
 240 struct slgt_info {
 241         void *if_ptr;           /* General purpose pointer (used by SPPP) */
 242         struct tty_port port;
 243
 244         struct slgt_info *next_device;  /* device list link */
 245
 246         int magic;
 247
 248         char device_name[25];
 249         struct pci_dev *pdev;
 250
 251         int port_count;  /* count of ports on adapter */
 252         int adapter_num; /* adapter instance number */
 253         int port_num;    /* port instance number */
 254
 255         /* array of pointers to port contexts on this adapter */
 256         struct slgt_info *port_array[SLGT_MAX_PORTS];
 257
 258         int                     line;           /* tty line instance number */
 259
 260         struct mgsl_icount      icount;
 261
 262         int                     timeout;
 263         int                     x_char;         /* xon/xoff character */
 264         unsigned int            read_status_mask;
 265         unsigned int            ignore_status_mask;
 266
 267         wait_queue_head_t       status_event_wait_q;
 268         wait_queue_head_t       event_wait_q;
 269         struct timer_list       tx_timer;
 270         struct timer_list       rx_timer;
 271
 272         unsigned int            gpio_present;
 273         struct cond_wait        *gpio_wait_q;
 274
 275         spinlock_t lock;        /* spinlock for synchronizing with ISR */
 276
 277         struct work_struct task;
 278         u32 pending_bh;
 279         bool bh_requested;
 280         bool bh_running;
 281
 282         int isr_overflow;
 283         bool irq_requested;     /* true if IRQ requested */
 284         bool irq_occurred;      /* for diagnostics use */
 285
 286         /* device configuration */
 287
 288         unsigned int bus_type;
 289         unsigned int irq_level;
 290         unsigned long irq_flags;
 291
 292         unsigned char __iomem * reg_addr;  /* memory mapped registers address */
 293         u32 phys_reg_addr;
 294         bool reg_addr_requested;
 295
 296         MGSL_PARAMS params;       /* communications parameters */
 297         u32 idle_mode;
 298         u32 max_frame_size;       /* as set by device config */
 299
 300         unsigned int rbuf_fill_level;
 301         unsigned int rx_pio;
 302         unsigned int if_mode;
 303         unsigned int base_clock;
 304
 305         /* device status */
 306
 307         bool rx_enabled;
 308         bool rx_restart;
 309
 310         bool tx_enabled;
 311         bool tx_active;
 312
 313         unsigned char signals;    /* serial signal states */
 314         int init_error;  /* initialization error */
 315
 316         unsigned char *tx_buf;
 317         int tx_count;
 318
 319         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 320         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 321         bool drop_rts_on_tx_done;
 322         struct  _input_signal_events    input_signal_events;
 323
 324         int dcd_chkcount;       /* check counts to prevent */
 325         int cts_chkcount;       /* too many IRQs if a signal */
 326         int dsr_chkcount;       /* is floating */
 327         int ri_chkcount;
 328
 329         char *bufs;             /* virtual address of DMA buffer lists */
 330         dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
 331
 332         unsigned int rbuf_count;
 333         struct slgt_desc *rbufs;
 334         unsigned int rbuf_current;
 335         unsigned int rbuf_index;
 336         unsigned int rbuf_fill_index;
 337         unsigned short rbuf_fill_count;
 338
 339         unsigned int tbuf_count;
 340         struct slgt_desc *tbufs;
 341         unsigned int tbuf_current;
 342         unsigned int tbuf_start;
 343
 344         unsigned char *tmp_rbuf;
 345         unsigned int tmp_rbuf_count;
 346
 347         /* SPPP/Cisco HDLC device parts */
 348
 349         int netcount;
 350         spinlock_t netlock;
 351 #if SYNCLINK_GENERIC_HDLC
 352         struct net_device *netdev;
 353 #endif
 354
 355 };
 356
 357 static MGSL_PARAMS default_params = {
 358         .mode            = MGSL_MODE_HDLC,
 359         .loopback        = 0,
 360         .flags           = HDLC_FLAG_UNDERRUN_ABORT15,
 361         .encoding        = HDLC_ENCODING_NRZI_SPACE,
 362         .clock_speed     = 0,
 363         .addr_filter     = 0xff,
 364         .crc_type        = HDLC_CRC_16_CCITT,
 365         .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
 366         .preamble        = HDLC_PREAMBLE_PATTERN_NONE,
 367         .data_rate       = 9600,
 368         .data_bits       = 8,
 369         .stop_bits       = 1,
 370         .parity          = ASYNC_PARITY_NONE
 371 };
 372
 373
 374 #define BH_RECEIVE  1
 375 #define BH_TRANSMIT 2
 376 #define BH_STATUS   4
 377 #define IO_PIN_SHUTDOWN_LIMIT 100
 378
 379 #define DMABUFSIZE 256
 380 #define DESC_LIST_SIZE 4096
 381
 382 #define MASK_PARITY  BIT1
 383 #define MASK_FRAMING BIT0
 384 #define MASK_BREAK   BIT14
 385 #define MASK_OVERRUN BIT4
 386
 387 #define GSR   0x00 /* global status */
 388 #define JCR   0x04 /* JTAG control */
 389 #define IODR  0x08 /* GPIO direction */
 390 #define IOER  0x0c /* GPIO interrupt enable */
 391 #define IOVR  0x10 /* GPIO value */
 392 #define IOSR  0x14 /* GPIO interrupt status */
 393 #define TDR   0x80 /* tx data */
 394 #define RDR   0x80 /* rx data */
 395 #define TCR   0x82 /* tx control */
 396 #define TIR   0x84 /* tx idle */
 397 #define TPR   0x85 /* tx preamble */
 398 #define RCR   0x86 /* rx control */
 399 #define VCR   0x88 /* V.24 control */
 400 #define CCR   0x89 /* clock control */
 401 #define BDR   0x8a /* baud divisor */
 402 #define SCR   0x8c /* serial control */
 403 #define SSR   0x8e /* serial status */
 404 #define RDCSR 0x90 /* rx DMA control/status */
 405 #define TDCSR 0x94 /* tx DMA control/status */
 406 #define RDDAR 0x98 /* rx DMA descriptor address */
 407 #define TDDAR 0x9c /* tx DMA descriptor address */
 408
 409 #define RXIDLE      BIT14
 410 #define RXBREAK     BIT14
 411 #define IRQ_TXDATA  BIT13
 412 #define IRQ_TXIDLE  BIT12
 413 #define IRQ_TXUNDER BIT11 /* HDLC */
 414 #define IRQ_RXDATA  BIT10
 415 #define IRQ_RXIDLE  BIT9  /* HDLC */
 416 #define IRQ_RXBREAK BIT9  /* async */
 417 #define IRQ_RXOVER  BIT8
 418 #define IRQ_DSR     BIT7
 419 #define IRQ_CTS     BIT6
 420 #define IRQ_DCD     BIT5
 421 #define IRQ_RI      BIT4
 422 #define IRQ_ALL     0x3ff0
 423 #define IRQ_MASTER  BIT0
 424
 425 #define slgt_irq_on(info, mask) \
 426         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
 427 #define slgt_irq_off(info, mask) \
 428         wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
 429
 430 static __u8  rd_reg8(struct slgt_info *info, unsigned int addr);
 431 static void  wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
 432 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
 433 static void  wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
 434 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
 435 static void  wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
 436
 437 static void  msc_set_vcr(struct slgt_info *info);
 438
 439 static int  startup(struct slgt_info *info);
 440 static int  block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
 441 static void shutdown(struct slgt_info *info);
 442 static void program_hw(struct slgt_info *info);
 443 static void change_params(struct slgt_info *info);
 444
 445 static int  register_test(struct slgt_info *info);
 446 static int  irq_test(struct slgt_info *info);
 447 static int  loopback_test(struct slgt_info *info);
 448 static int  adapter_test(struct slgt_info *info);
 449
 450 static void reset_adapter(struct slgt_info *info);
 451 static void reset_port(struct slgt_info *info);
 452 static void async_mode(struct slgt_info *info);
 453 static void sync_mode(struct slgt_info *info);
 454
 455 static void rx_stop(struct slgt_info *info);
 456 static void rx_start(struct slgt_info *info);
 457 static void reset_rbufs(struct slgt_info *info);
 458 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
 459 static void rdma_reset(struct slgt_info *info);
 460 static bool rx_get_frame(struct slgt_info *info);
 461 static bool rx_get_buf(struct slgt_info *info);
 462
 463 static void tx_start(struct slgt_info *info);
 464 static void tx_stop(struct slgt_info *info);
 465 static void tx_set_idle(struct slgt_info *info);
 466 static unsigned int free_tbuf_count(struct slgt_info *info);
 467 static unsigned int tbuf_bytes(struct slgt_info *info);
 468 static void reset_tbufs(struct slgt_info *info);
 469 static void tdma_reset(struct slgt_info *info);
 470 static void tdma_start(struct slgt_info *info);
 471 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
 472
 473 static void get_signals(struct slgt_info *info);
 474 static void set_signals(struct slgt_info *info);
 475 static void enable_loopback(struct slgt_info *info);
 476 static void set_rate(struct slgt_info *info, u32 data_rate);
 477
 478 static int  bh_action(struct slgt_info *info);
 479 static void bh_handler(struct work_struct *work);
 480 static void bh_transmit(struct slgt_info *info);
 481 static void isr_serial(struct slgt_info *info);
 482 static void isr_rdma(struct slgt_info *info);
 483 static void isr_txeom(struct slgt_info *info, unsigned short status);
 484 static void isr_tdma(struct slgt_info *info);
 485
 486 static int  alloc_dma_bufs(struct slgt_info *info);
 487 static void free_dma_bufs(struct slgt_info *info);
 488 static int  alloc_desc(struct slgt_info *info);
 489 static void free_desc(struct slgt_info *info);
 490 static int  alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 491 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
 492
 493 static int  alloc_tmp_rbuf(struct slgt_info *info);
 494 static void free_tmp_rbuf(struct slgt_info *info);
 495
 496 static void tx_timeout(unsigned long context);
 497 static void rx_timeout(unsigned long context);
 498
 499 /*
 500  * ioctl handlers
 501  */
 502 static int  get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
 503 static int  get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 504 static int  set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
 505 static int  get_txidle(struct slgt_info *info, int __user *idle_mode);
 506 static int  set_txidle(struct slgt_info *info, int idle_mode);
 507 static int  tx_enable(struct slgt_info *info, int enable);
 508 static int  tx_abort(struct slgt_info *info);
 509 static int  rx_enable(struct slgt_info *info, int enable);
 510 static int  modem_input_wait(struct slgt_info *info,int arg);
 511 static int  wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
 512 static int  tiocmget(struct tty_struct *tty, struct file *file);
 513 static int  tiocmset(struct tty_struct *tty, struct file *file,
 514                      unsigned int set, unsigned int clear);
 515 static int set_break(struct tty_struct *tty, int break_state);
 516 static int  get_interface(struct slgt_info *info, int __user *if_mode);
 517 static int  set_interface(struct slgt_info *info, int if_mode);
 518 static int  set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 519 static int  get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 520 static int  wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
 521
 522 /*
 523  * driver functions
 524  */
 525 static void add_device(struct slgt_info *info);
 526 static void device_init(int adapter_num, struct pci_dev *pdev);
 527 static int  claim_resources(struct slgt_info *info);
 528 static void release_resources(struct slgt_info *info);
 529
 530 /*
 531  * DEBUG OUTPUT CODE
 532  */
 533 #ifndef DBGINFO
 534 #define DBGINFO(fmt)
 535 #endif
 536 #ifndef DBGERR
 537 #define DBGERR(fmt)
 538 #endif
 539 #ifndef DBGBH
 540 #define DBGBH(fmt)
 541 #endif
 542 #ifndef DBGISR
 543 #define DBGISR(fmt)
 544 #endif
 545
 546 #ifdef DBGDATA
 547 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
 548 {
 549         int i;
 550         int linecount;
 551         printk("%s %s data:\n",info->device_name, label);
 552         while(count) {
 553                 linecount = (count > 16) ? 16 : count;
 554                 for(i=0; i < linecount; i++)
 555                         printk("%02X ",(unsigned char)data[i]);
 556                 for(;i<17;i++)
 557                         printk("   ");
 558                 for(i=0;i<linecount;i++) {
 559                         if (data[i]>=040 && data[i]<=0176)
 560                                 printk("%c",data[i]);
 561                         else
 562                                 printk(".");
 563                 }
 564                 printk("\n");
 565                 data  += linecount;
 566                 count -= linecount;
 567         }
 568 }
 569 #else
 570 #define DBGDATA(info, buf, size, label)
 571 #endif
 572
 573 #ifdef DBGTBUF
 574 static void dump_tbufs(struct slgt_info *info)
 575 {
 576         int i;
 577         printk("tbuf_current=%d\n", info->tbuf_current);
 578         for (i=0 ; i < info->tbuf_count ; i++) {
 579                 printk("%d: count=%04X status=%04X\n",
 580                         i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
 581         }
 582 }
 583 #else
 584 #define DBGTBUF(info)
 585 #endif
 586
 587 #ifdef DBGRBUF
 588 static void dump_rbufs(struct slgt_info *info)
 589 {
 590         int i;
 591         printk("rbuf_current=%d\n", info->rbuf_current);
 592         for (i=0 ; i < info->rbuf_count ; i++) {
 593                 printk("%d: count=%04X status=%04X\n",
 594                         i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
 595         }
 596 }
 597 #else
 598 #define DBGRBUF(info)
 599 #endif
 600
 601 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
 602 {
 603 #ifdef SANITY_CHECK
 604         if (!info) {
 605                 printk("null struct slgt_info for (%s) in %s\n", devname, name);
 606                 return 1;
 607         }
 608         if (info->magic != MGSL_MAGIC) {
 609                 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
 610                 return 1;
 611         }
 612 #else
 613         if (!info)
 614                 return 1;
 615 #endif
 616         return 0;
 617 }
 618
 619 /**
 620  * line discipline callback wrappers
 621  *
 622  * The wrappers maintain line discipline references
 623  * while calling into the line discipline.
 624  *
 625  * ldisc_receive_buf  - pass receive data to line discipline
 626  */
 627 static void ldisc_receive_buf(struct tty_struct *tty,
 628                               const __u8 *data, char *flags, int count)
 629 {
 630         struct tty_ldisc *ld;
 631         if (!tty)
 632                 return;
 633         ld = tty_ldisc_ref(tty);
 634         if (ld) {
 635                 if (ld->ops->receive_buf)
 636                         ld->ops->receive_buf(tty, data, flags, count);
 637                 tty_ldisc_deref(ld);
 638         }
 639 }
 640
 641 /* tty callbacks */
 642
 643 static int open(struct tty_struct *tty, struct file *filp)
 644 {
 645         struct slgt_info *info;
 646         int retval, line;
 647         unsigned long flags;
 648
 649         line = tty->index;
 650         if ((line < 0) || (line >= slgt_device_count)) {
 651                 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
 652                 return -ENODEV;
 653         }
 654
 655         info = slgt_device_list;
 656         while(info && info->line != line)
 657                 info = info->next_device;
 658         if (sanity_check(info, tty->name, "open"))
 659                 return -ENODEV;
 660         if (info->init_error) {
 661                 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
 662                 return -ENODEV;
 663         }
 664
 665         tty->driver_data = info;
 666         info->port.tty = tty;
 667
 668         DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
 669
 670         /* If port is closing, signal caller to try again */
 671         if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
 672                 if (info->port.flags & ASYNC_CLOSING)
 673                         interruptible_sleep_on(&info->port.close_wait);
 674                 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
 675                         -EAGAIN : -ERESTARTSYS);
 676                 goto cleanup;
 677         }
 678
 679         info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 680
 681         spin_lock_irqsave(&info->netlock, flags);
 682         if (info->netcount) {
 683                 retval = -EBUSY;
 684                 spin_unlock_irqrestore(&info->netlock, flags);
 685                 goto cleanup;
 686         }
 687         info->port.count++;
 688         spin_unlock_irqrestore(&info->netlock, flags);
 689
 690         if (info->port.count == 1) {
 691                 /* 1st open on this device, init hardware */
 692                 retval = startup(info);
 693                 if (retval < 0)
 694                         goto cleanup;
 695         }
 696
 697         retval = block_til_ready(tty, filp, info);
 698         if (retval) {
 699                 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
 700                 goto cleanup;
 701         }
 702
 703         retval = 0;
 704
 705 cleanup:
 706         if (retval) {
 707                 if (tty->count == 1)
 708                         info->port.tty = NULL; /* tty layer will release tty struct */
 709                 if(info->port.count)
 710                         info->port.count--;
 711         }
 712
 713         DBGINFO(("%s open rc=%d\n", info->device_name, retval));
 714         return retval;
 715 }
 716
 717 static void close(struct tty_struct *tty, struct file *filp)
 718 {
 719         struct slgt_info *info = tty->driver_data;
 720
 721         if (sanity_check(info, tty->name, "close"))
 722                 return;
 723         DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
 724
 725         if (tty_port_close_start(&info->port, tty, filp) == 0)
 726                 goto cleanup;
 727
 728         if (info->port.flags & ASYNC_INITIALIZED)
 729                 wait_until_sent(tty, info->timeout);
 730         flush_buffer(tty);
 731         tty_ldisc_flush(tty);
 732
 733         shutdown(info);
 734
 735         tty_port_close_end(&info->port, tty);
 736         info->port.tty = NULL;
 737 cleanup:
 738         DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
 739 }
 740
 741 static void hangup(struct tty_struct *tty)
 742 {
 743         struct slgt_info *info = tty->driver_data;
 744
 745         if (sanity_check(info, tty->name, "hangup"))
 746                 return;
 747         DBGINFO(("%s hangup\n", info->device_name));
 748
 749         flush_buffer(tty);
 750         shutdown(info);
 751
 752         info->port.count = 0;
 753         info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
 754         info->port.tty = NULL;
 755
 756         wake_up_interruptible(&info->port.open_wait);
 757 }
 758
 759 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
 760 {
 761         struct slgt_info *info = tty->driver_data;
 762         unsigned long flags;
 763
 764         DBGINFO(("%s set_termios\n", tty->driver->name));
 765
 766         change_params(info);
 767
 768         /* Handle transition to B0 status */
 769         if (old_termios->c_cflag & CBAUD &&
 770             !(tty->termios->c_cflag & CBAUD)) {
 771                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 772                 spin_lock_irqsave(&info->lock,flags);
 773                 set_signals(info);
 774                 spin_unlock_irqrestore(&info->lock,flags);
 775         }
 776
 777         /* Handle transition away from B0 status */
 778         if (!(old_termios->c_cflag & CBAUD) &&
 779             tty->termios->c_cflag & CBAUD) {
 780                 info->signals |= SerialSignal_DTR;
 781                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 782                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 783                         info->signals |= SerialSignal_RTS;
 784                 }
 785                 spin_lock_irqsave(&info->lock,flags);
 786                 set_signals(info);
 787                 spin_unlock_irqrestore(&info->lock,flags);
 788         }
 789
 790         /* Handle turning off CRTSCTS */
 791         if (old_termios->c_cflag & CRTSCTS &&
 792             !(tty->termios->c_cflag & CRTSCTS)) {
 793                 tty->hw_stopped = 0;
 794                 tx_release(tty);
 795         }
 796 }
 797
 798 static int write(struct tty_struct *tty,
 799                  const unsigned char *buf, int count)
 800 {
 801         int ret = 0;
 802         struct slgt_info *info = tty->driver_data;
 803         unsigned long flags;
 804         unsigned int bufs_needed;
 805
 806         if (sanity_check(info, tty->name, "write"))
 807                 goto cleanup;
 808         DBGINFO(("%s write count=%d\n", info->device_name, count));
 809
 810         if (!info->tx_buf)
 811                 goto cleanup;
 812
 813         if (count > info->max_frame_size) {
 814                 ret = -EIO;
 815                 goto cleanup;
 816         }
 817
 818         if (!count)
 819                 goto cleanup;
 820
 821         if (!info->tx_active && info->tx_count) {
 822                 /* send accumulated data from send_char() */
 823                 tx_load(info, info->tx_buf, info->tx_count);
 824                 goto start;
 825         }
 826         bufs_needed = (count/DMABUFSIZE);
 827         if (count % DMABUFSIZE)
 828                 ++bufs_needed;
 829         if (bufs_needed > free_tbuf_count(info))
 830                 goto cleanup;
 831
 832         ret = info->tx_count = count;
 833         tx_load(info, buf, count);
 834         goto start;
 835
 836 start:
 837         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
 838                 spin_lock_irqsave(&info->lock,flags);
 839                 if (!info->tx_active)
 840                         tx_start(info);
 841                 else
 842                         tdma_start(info);
 843                 spin_unlock_irqrestore(&info->lock,flags);
 844         }
 845
 846 cleanup:
 847         DBGINFO(("%s write rc=%d\n", info->device_name, ret));
 848         return ret;
 849 }
 850
 851 static int put_char(struct tty_struct *tty, unsigned char ch)
 852 {
 853         struct slgt_info *info = tty->driver_data;
 854         unsigned long flags;
 855         int ret = 0;
 856
 857         if (sanity_check(info, tty->name, "put_char"))
 858                 return 0;
 859         DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
 860         if (!info->tx_buf)
 861                 return 0;
 862         spin_lock_irqsave(&info->lock,flags);
 863         if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
 864                 info->tx_buf[info->tx_count++] = ch;
 865                 ret = 1;
 866         }
 867         spin_unlock_irqrestore(&info->lock,flags);
 868         return ret;
 869 }
 870
 871 static void send_xchar(struct tty_struct *tty, char ch)
 872 {
 873         struct slgt_info *info = tty->driver_data;
 874         unsigned long flags;
 875
 876         if (sanity_check(info, tty->name, "send_xchar"))
 877                 return;
 878         DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
 879         info->x_char = ch;
 880         if (ch) {
 881                 spin_lock_irqsave(&info->lock,flags);
 882                 if (!info->tx_enabled)
 883                         tx_start(info);
 884                 spin_unlock_irqrestore(&info->lock,flags);
 885         }
 886 }
 887
 888 static void wait_until_sent(struct tty_struct *tty, int timeout)
 889 {
 890         struct slgt_info *info = tty->driver_data;
 891         unsigned long orig_jiffies, char_time;
 892
 893         if (!info )
 894                 return;
 895         if (sanity_check(info, tty->name, "wait_until_sent"))
 896                 return;
 897         DBGINFO(("%s wait_until_sent entry\n", info->device_name));
 898         if (!(info->port.flags & ASYNC_INITIALIZED))
 899                 goto exit;
 900
 901         orig_jiffies = jiffies;
 902
 903         /* Set check interval to 1/5 of estimated time to
 904          * send a character, and make it at least 1. The check
 905          * interval should also be less than the timeout.
 906          * Note: use tight timings here to satisfy the NIST-PCTS.
 907          */
 908
 909         lock_kernel();
 910
 911         if (info->params.data_rate) {
 912                 char_time = info->timeout/(32 * 5);
 913                 if (!char_time)
 914                         char_time++;
 915         } else
 916                 char_time = 1;
 917
 918         if (timeout)
 919                 char_time = min_t(unsigned long, char_time, timeout);
 920
 921         while (info->tx_active) {
 922                 msleep_interruptible(jiffies_to_msecs(char_time));
 923                 if (signal_pending(current))
 924                         break;
 925                 if (timeout && time_after(jiffies, orig_jiffies + timeout))
 926                         break;
 927         }
 928         unlock_kernel();
 929
 930 exit:
 931         DBGINFO(("%s wait_until_sent exit\n", info->device_name));
 932 }
 933
 934 static int write_room(struct tty_struct *tty)
 935 {
 936         struct slgt_info *info = tty->driver_data;
 937         int ret;
 938
 939         if (sanity_check(info, tty->name, "write_room"))
 940                 return 0;
 941         ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
 942         DBGINFO(("%s write_room=%d\n", info->device_name, ret));
 943         return ret;
 944 }
 945
 946 static void flush_chars(struct tty_struct *tty)
 947 {
 948         struct slgt_info *info = tty->driver_data;
 949         unsigned long flags;
 950
 951         if (sanity_check(info, tty->name, "flush_chars"))
 952                 return;
 953         DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
 954
 955         if (info->tx_count <= 0 || tty->stopped ||
 956             tty->hw_stopped || !info->tx_buf)
 957                 return;
 958
 959         DBGINFO(("%s flush_chars start transmit\n", info->device_name));
 960
 961         spin_lock_irqsave(&info->lock,flags);
 962         if (!info->tx_active && info->tx_count) {
 963                 tx_load(info, info->tx_buf,info->tx_count);
 964                 tx_start(info);
 965         }
 966         spin_unlock_irqrestore(&info->lock,flags);
 967 }
 968
 969 static void flush_buffer(struct tty_struct *tty)
 970 {
 971         struct slgt_info *info = tty->driver_data;
 972         unsigned long flags;
 973
 974         if (sanity_check(info, tty->name, "flush_buffer"))
 975                 return;
 976         DBGINFO(("%s flush_buffer\n", info->device_name));
 977
 978         spin_lock_irqsave(&info->lock,flags);
 979         if (!info->tx_active)
 980                 info->tx_count = 0;
 981         spin_unlock_irqrestore(&info->lock,flags);
 982
 983         tty_wakeup(tty);
 984 }
 985
 986 /*
 987  * throttle (stop) transmitter
 988  */
 989 static void tx_hold(struct tty_struct *tty)
 990 {
 991         struct slgt_info *info = tty->driver_data;
 992         unsigned long flags;
 993
 994         if (sanity_check(info, tty->name, "tx_hold"))
 995                 return;
 996         DBGINFO(("%s tx_hold\n", info->device_name));
 997         spin_lock_irqsave(&info->lock,flags);
 998         if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
 999                 tx_stop(info);
1000         spin_unlock_irqrestore(&info->lock,flags);
1001 }
1002
1003 /*
1004  * release (start) transmitter
1005  */
1006 static void tx_release(struct tty_struct *tty)
1007 {
1008         struct slgt_info *info = tty->driver_data;
1009         unsigned long flags;
1010
1011         if (sanity_check(info, tty->name, "tx_release"))
1012                 return;
1013         DBGINFO(("%s tx_release\n", info->device_name));
1014         spin_lock_irqsave(&info->lock,flags);
1015         if (!info->tx_active && info->tx_count) {
1016                 tx_load(info, info->tx_buf, info->tx_count);
1017                 tx_start(info);
1018         }
1019         spin_unlock_irqrestore(&info->lock,flags);
1020 }
1021
1022 /*
1023  * Service an IOCTL request
1024  *
1025  * Arguments
1026  *
1027  *      tty     pointer to tty instance data
1028  *      file    pointer to associated file object for device
1029  *      cmd     IOCTL command code
1030  *      arg     command argument/context
1031  *
1032  * Return 0 if success, otherwise error code
1033  */
1034 static int ioctl(struct tty_struct *tty, struct file *file,
1035                  unsigned int cmd, unsigned long arg)
1036 {
1037         struct slgt_info *info = tty->driver_data;
1038         struct mgsl_icount cnow;        /* kernel counter temps */
1039         struct serial_icounter_struct __user *p_cuser;  /* user space */
1040         unsigned long flags;
1041         void __user *argp = (void __user *)arg;
1042         int ret;
1043
1044         if (sanity_check(info, tty->name, "ioctl"))
1045                 return -ENODEV;
1046         DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1047
1048         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1049             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1050                 if (tty->flags & (1 << TTY_IO_ERROR))
1051                     return -EIO;
1052         }
1053
1054         lock_kernel();
1055
1056         switch (cmd) {
1057         case MGSL_IOCGPARAMS:
1058                 ret = get_params(info, argp);
1059                 break;
1060         case MGSL_IOCSPARAMS:
1061                 ret = set_params(info, argp);
1062                 break;
1063         case MGSL_IOCGTXIDLE:
1064                 ret = get_txidle(info, argp);
1065                 break;
1066         case MGSL_IOCSTXIDLE:
1067                 ret = set_txidle(info, (int)arg);
1068                 break;
1069         case MGSL_IOCTXENABLE:
1070                 ret = tx_enable(info, (int)arg);
1071                 break;
1072         case MGSL_IOCRXENABLE:
1073                 ret = rx_enable(info, (int)arg);
1074                 break;
1075         case MGSL_IOCTXABORT:
1076                 ret = tx_abort(info);
1077                 break;
1078         case MGSL_IOCGSTATS:
1079                 ret = get_stats(info, argp);
1080                 break;
1081         case MGSL_IOCWAITEVENT:
1082                 ret = wait_mgsl_event(info, argp);
1083                 break;
1084         case TIOCMIWAIT:
1085                 ret = modem_input_wait(info,(int)arg);
1086                 break;
1087         case MGSL_IOCGIF:
1088                 ret = get_interface(info, argp);
1089                 break;
1090         case MGSL_IOCSIF:
1091                 ret = set_interface(info,(int)arg);
1092                 break;
1093         case MGSL_IOCSGPIO:
1094                 ret = set_gpio(info, argp);
1095                 break;
1096         case MGSL_IOCGGPIO:
1097                 ret = get_gpio(info, argp);
1098                 break;
1099         case MGSL_IOCWAITGPIO:
1100                 ret = wait_gpio(info, argp);
1101                 break;
1102         case TIOCGICOUNT:
1103                 spin_lock_irqsave(&info->lock,flags);
1104                 cnow = info->icount;
1105                 spin_unlock_irqrestore(&info->lock,flags);
1106                 p_cuser = argp;
1107                 if (put_user(cnow.cts, &p_cuser->cts) ||
1108                     put_user(cnow.dsr, &p_cuser->dsr) ||
1109                     put_user(cnow.rng, &p_cuser->rng) ||
1110                     put_user(cnow.dcd, &p_cuser->dcd) ||
1111                     put_user(cnow.rx, &p_cuser->rx) ||
1112                     put_user(cnow.tx, &p_cuser->tx) ||
1113                     put_user(cnow.frame, &p_cuser->frame) ||
1114                     put_user(cnow.overrun, &p_cuser->overrun) ||
1115                     put_user(cnow.parity, &p_cuser->parity) ||
1116                     put_user(cnow.brk, &p_cuser->brk) ||
1117                     put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1118                         ret = -EFAULT;
1119                 ret = 0;
1120                 break;
1121         default:
1122                 ret = -ENOIOCTLCMD;
1123         }
1124         unlock_kernel();
1125         return ret;
1126 }
1127
1128 /*
1129  * support for 32 bit ioctl calls on 64 bit systems
1130  */
1131 #ifdef CONFIG_COMPAT
1132 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1133 {
1134         struct MGSL_PARAMS32 tmp_params;
1135
1136         DBGINFO(("%s get_params32\n", info->device_name));
1137         tmp_params.mode            = (compat_ulong_t)info->params.mode;
1138         tmp_params.loopback        = info->params.loopback;
1139         tmp_params.flags           = info->params.flags;
1140         tmp_params.encoding        = info->params.encoding;
1141         tmp_params.clock_speed     = (compat_ulong_t)info->params.clock_speed;
1142         tmp_params.addr_filter     = info->params.addr_filter;
1143         tmp_params.crc_type        = info->params.crc_type;
1144         tmp_params.preamble_length = info->params.preamble_length;
1145         tmp_params.preamble        = info->params.preamble;
1146         tmp_params.data_rate       = (compat_ulong_t)info->params.data_rate;
1147         tmp_params.data_bits       = info->params.data_bits;
1148         tmp_params.stop_bits       = info->params.stop_bits;
1149         tmp_params.parity          = info->params.parity;
1150         if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1151                 return -EFAULT;
1152         return 0;
1153 }
1154
1155 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1156 {
1157         struct MGSL_PARAMS32 tmp_params;
1158
1159         DBGINFO(("%s set_params32\n", info->device_name));
1160         if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1161                 return -EFAULT;
1162
1163         spin_lock(&info->lock);
1164         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1165                 info->base_clock = tmp_params.clock_speed;
1166         } else {
1167                 info->params.mode            = tmp_params.mode;
1168                 info->params.loopback        = tmp_params.loopback;
1169                 info->params.flags           = tmp_params.flags;
1170                 info->params.encoding        = tmp_params.encoding;
1171                 info->params.clock_speed     = tmp_params.clock_speed;
1172                 info->params.addr_filter     = tmp_params.addr_filter;
1173                 info->params.crc_type        = tmp_params.crc_type;
1174                 info->params.preamble_length = tmp_params.preamble_length;
1175                 info->params.preamble        = tmp_params.preamble;
1176                 info->params.data_rate       = tmp_params.data_rate;
1177                 info->params.data_bits       = tmp_params.data_bits;
1178                 info->params.stop_bits       = tmp_params.stop_bits;
1179                 info->params.parity          = tmp_params.parity;
1180         }
1181         spin_unlock(&info->lock);
1182
1183         program_hw(info);
1184
1185         return 0;
1186 }
1187
1188 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1189                          unsigned int cmd, unsigned long arg)
1190 {
1191         struct slgt_info *info = tty->driver_data;
1192         int rc = -ENOIOCTLCMD;
1193
1194         if (sanity_check(info, tty->name, "compat_ioctl"))
1195                 return -ENODEV;
1196         DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1197
1198         switch (cmd) {
1199
1200         case MGSL_IOCSPARAMS32:
1201                 rc = set_params32(info, compat_ptr(arg));
1202                 break;
1203
1204         case MGSL_IOCGPARAMS32:
1205                 rc = get_params32(info, compat_ptr(arg));
1206                 break;
1207
1208         case MGSL_IOCGPARAMS:
1209         case MGSL_IOCSPARAMS:
1210         case MGSL_IOCGTXIDLE:
1211         case MGSL_IOCGSTATS:
1212         case MGSL_IOCWAITEVENT:
1213         case MGSL_IOCGIF:
1214         case MGSL_IOCSGPIO:
1215         case MGSL_IOCGGPIO:
1216         case MGSL_IOCWAITGPIO:
1217         case TIOCGICOUNT:
1218                 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1219                 break;
1220
1221         case MGSL_IOCSTXIDLE:
1222         case MGSL_IOCTXENABLE:
1223         case MGSL_IOCRXENABLE:
1224         case MGSL_IOCTXABORT:
1225         case TIOCMIWAIT:
1226         case MGSL_IOCSIF:
1227                 rc = ioctl(tty, file, cmd, arg);
1228                 break;
1229         }
1230
1231         DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1232         return rc;
1233 }
1234 #else
1235 #define slgt_compat_ioctl NULL
1236 #endif /* ifdef CONFIG_COMPAT */
1237
1238 /*
1239  * proc fs support
1240  */
1241 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1242 {
1243         char stat_buf[30];
1244         unsigned long flags;
1245
1246         seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1247                       info->device_name, info->phys_reg_addr,
1248                       info->irq_level, info->max_frame_size);
1249
1250         /* output current serial signal states */
1251         spin_lock_irqsave(&info->lock,flags);
1252         get_signals(info);
1253         spin_unlock_irqrestore(&info->lock,flags);
1254
1255         stat_buf[0] = 0;
1256         stat_buf[1] = 0;
1257         if (info->signals & SerialSignal_RTS)
1258                 strcat(stat_buf, "|RTS");
1259         if (info->signals & SerialSignal_CTS)
1260                 strcat(stat_buf, "|CTS");
1261         if (info->signals & SerialSignal_DTR)
1262                 strcat(stat_buf, "|DTR");
1263         if (info->signals & SerialSignal_DSR)
1264                 strcat(stat_buf, "|DSR");
1265         if (info->signals & SerialSignal_DCD)
1266                 strcat(stat_buf, "|CD");
1267         if (info->signals & SerialSignal_RI)
1268                 strcat(stat_buf, "|RI");
1269
1270         if (info->params.mode != MGSL_MODE_ASYNC) {
1271                 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1272                                info->icount.txok, info->icount.rxok);
1273                 if (info->icount.txunder)
1274                         seq_printf(m, " txunder:%d", info->icount.txunder);
1275                 if (info->icount.txabort)
1276                         seq_printf(m, " txabort:%d", info->icount.txabort);
1277                 if (info->icount.rxshort)
1278                         seq_printf(m, " rxshort:%d", info->icount.rxshort);
1279                 if (info->icount.rxlong)
1280                         seq_printf(m, " rxlong:%d", info->icount.rxlong);
1281                 if (info->icount.rxover)
1282                         seq_printf(m, " rxover:%d", info->icount.rxover);
1283                 if (info->icount.rxcrc)
1284                         seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1285         } else {
1286                 seq_printf(m, "\tASYNC tx:%d rx:%d",
1287                                info->icount.tx, info->icount.rx);
1288                 if (info->icount.frame)
1289                         seq_printf(m, " fe:%d", info->icount.frame);
1290                 if (info->icount.parity)
1291                         seq_printf(m, " pe:%d", info->icount.parity);
1292                 if (info->icount.brk)
1293                         seq_printf(m, " brk:%d", info->icount.brk);
1294                 if (info->icount.overrun)
1295                         seq_printf(m, " oe:%d", info->icount.overrun);
1296         }
1297
1298         /* Append serial signal status to end */
1299         seq_printf(m, " %s\n", stat_buf+1);
1300
1301         seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1302                        info->tx_active,info->bh_requested,info->bh_running,
1303                        info->pending_bh);
1304 }
1305
1306 /* Called to print information about devices
1307  */
1308 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1309 {
1310         struct slgt_info *info;
1311
1312         seq_puts(m, "synclink_gt driver\n");
1313
1314         info = slgt_device_list;
1315         while( info ) {
1316                 line_info(m, info);
1317                 info = info->next_device;
1318         }
1319         return 0;
1320 }
1321
1322 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1323 {
1324         return single_open(file, synclink_gt_proc_show, NULL);
1325 }
1326
1327 static const struct file_operations synclink_gt_proc_fops = {
1328         .owner          = THIS_MODULE,
1329         .open           = synclink_gt_proc_open,
1330         .read           = seq_read,
1331         .llseek         = seq_lseek,
1332         .release        = single_release,
1333 };
1334
1335 /*
1336  * return count of bytes in transmit buffer
1337  */
1338 static int chars_in_buffer(struct tty_struct *tty)
1339 {
1340         struct slgt_info *info = tty->driver_data;
1341         int count;
1342         if (sanity_check(info, tty->name, "chars_in_buffer"))
1343                 return 0;
1344         count = tbuf_bytes(info);
1345         DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1346         return count;
1347 }
1348
1349 /*
1350  * signal remote device to throttle send data (our receive data)
1351  */
1352 static void throttle(struct tty_struct * tty)
1353 {
1354         struct slgt_info *info = tty->driver_data;
1355         unsigned long flags;
1356
1357         if (sanity_check(info, tty->name, "throttle"))
1358                 return;
1359         DBGINFO(("%s throttle\n", info->device_name));
1360         if (I_IXOFF(tty))
1361                 send_xchar(tty, STOP_CHAR(tty));
1362         if (tty->termios->c_cflag & CRTSCTS) {
1363                 spin_lock_irqsave(&info->lock,flags);
1364                 info->signals &= ~SerialSignal_RTS;
1365                 set_signals(info);
1366                 spin_unlock_irqrestore(&info->lock,flags);
1367         }
1368 }
1369
1370 /*
1371  * signal remote device to stop throttling send data (our receive data)
1372  */
1373 static void unthrottle(struct tty_struct * tty)
1374 {
1375         struct slgt_info *info = tty->driver_data;
1376         unsigned long flags;
1377
1378         if (sanity_check(info, tty->name, "unthrottle"))
1379                 return;
1380         DBGINFO(("%s unthrottle\n", info->device_name));
1381         if (I_IXOFF(tty)) {
1382                 if (info->x_char)
1383                         info->x_char = 0;
1384                 else
1385                         send_xchar(tty, START_CHAR(tty));
1386         }
1387         if (tty->termios->c_cflag & CRTSCTS) {
1388                 spin_lock_irqsave(&info->lock,flags);
1389                 info->signals |= SerialSignal_RTS;
1390                 set_signals(info);
1391                 spin_unlock_irqrestore(&info->lock,flags);
1392         }
1393 }
1394
1395 /*
1396  * set or clear transmit break condition
1397  * break_state  -1=set break condition, 0=clear
1398  */
1399 static int set_break(struct tty_struct *tty, int break_state)
1400 {
1401         struct slgt_info *info = tty->driver_data;
1402         unsigned short value;
1403         unsigned long flags;
1404
1405         if (sanity_check(info, tty->name, "set_break"))
1406                 return -EINVAL;
1407         DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1408
1409         spin_lock_irqsave(&info->lock,flags);
1410         value = rd_reg16(info, TCR);
1411         if (break_state == -1)
1412                 value |= BIT6;
1413         else
1414                 value &= ~BIT6;
1415         wr_reg16(info, TCR, value);
1416         spin_unlock_irqrestore(&info->lock,flags);
1417         return 0;
1418 }
1419
1420 #if SYNCLINK_GENERIC_HDLC
1421
1422 /**
1423  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1424  * set encoding and frame check sequence (FCS) options
1425  *
1426  * dev       pointer to network device structure
1427  * encoding  serial encoding setting
1428  * parity    FCS setting
1429  *
1430  * returns 0 if success, otherwise error code
1431  */
1432 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1433                           unsigned short parity)
1434 {
1435         struct slgt_info *info = dev_to_port(dev);
1436         unsigned char  new_encoding;
1437         unsigned short new_crctype;
1438
1439         /* return error if TTY interface open */
1440         if (info->port.count)
1441                 return -EBUSY;
1442
1443         DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1444
1445         switch (encoding)
1446         {
1447         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1448         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1449         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1450         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1451         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1452         default: return -EINVAL;
1453         }
1454
1455         switch (parity)
1456         {
1457         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1458         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1459         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1460         default: return -EINVAL;
1461         }
1462
1463         info->params.encoding = new_encoding;
1464         info->params.crc_type = new_crctype;
1465
1466         /* if network interface up, reprogram hardware */
1467         if (info->netcount)
1468                 program_hw(info);
1469
1470         return 0;
1471 }
1472
1473 /**
1474  * called by generic HDLC layer to send frame
1475  *
1476  * skb  socket buffer containing HDLC frame
1477  * dev  pointer to network device structure
1478  *
1479  * returns 0 if success, otherwise error code
1480  */
1481 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1482 {
1483         struct slgt_info *info = dev_to_port(dev);
1484         unsigned long flags;
1485
1486         DBGINFO(("%s hdlc_xmit\n", dev->name));
1487
1488         /* stop sending until this frame completes */
1489         netif_stop_queue(dev);
1490
1491         /* copy data to device buffers */
1492         info->tx_count = skb->len;
1493         tx_load(info, skb->data, skb->len);
1494
1495         /* update network statistics */
1496         dev->stats.tx_packets++;
1497         dev->stats.tx_bytes += skb->len;
1498
1499         /* done with socket buffer, so free it */
1500         dev_kfree_skb(skb);
1501
1502         /* save start time for transmit timeout detection */
1503         dev->trans_start = jiffies;
1504
1505         /* start hardware transmitter if necessary */
1506         spin_lock_irqsave(&info->lock,flags);
1507         if (!info->tx_active)
1508                 tx_start(info);
1509         spin_unlock_irqrestore(&info->lock,flags);
1510
1511         return 0;
1512 }
1513
1514 /**
1515  * called by network layer when interface enabled
1516  * claim resources and initialize hardware
1517  *
1518  * dev  pointer to network device structure
1519  *
1520  * returns 0 if success, otherwise error code
1521  */
1522 static int hdlcdev_open(struct net_device *dev)
1523 {
1524         struct slgt_info *info = dev_to_port(dev);
1525         int rc;
1526         unsigned long flags;
1527
1528         if (!try_module_get(THIS_MODULE))
1529                 return -EBUSY;
1530
1531         DBGINFO(("%s hdlcdev_open\n", dev->name));
1532
1533         /* generic HDLC layer open processing */
1534         if ((rc = hdlc_open(dev)))
1535                 return rc;
1536
1537         /* arbitrate between network and tty opens */
1538         spin_lock_irqsave(&info->netlock, flags);
1539         if (info->port.count != 0 || info->netcount != 0) {
1540                 DBGINFO(("%s hdlc_open busy\n", dev->name));
1541                 spin_unlock_irqrestore(&info->netlock, flags);
1542                 return -EBUSY;
1543         }
1544         info->netcount=1;
1545         spin_unlock_irqrestore(&info->netlock, flags);
1546
1547         /* claim resources and init adapter */
1548         if ((rc = startup(info)) != 0) {
1549                 spin_lock_irqsave(&info->netlock, flags);
1550                 info->netcount=0;
1551                 spin_unlock_irqrestore(&info->netlock, flags);
1552                 return rc;
1553         }
1554
1555         /* assert DTR and RTS, apply hardware settings */
1556         info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1557         program_hw(info);
1558
1559         /* enable network layer transmit */
1560         dev->trans_start = jiffies;
1561         netif_start_queue(dev);
1562
1563         /* inform generic HDLC layer of current DCD status */
1564         spin_lock_irqsave(&info->lock, flags);
1565         get_signals(info);
1566         spin_unlock_irqrestore(&info->lock, flags);
1567         if (info->signals & SerialSignal_DCD)
1568                 netif_carrier_on(dev);
1569         else
1570                 netif_carrier_off(dev);
1571         return 0;
1572 }
1573
1574 /**
1575  * called by network layer when interface is disabled
1576  * shutdown hardware and release resources
1577  *
1578  * dev  pointer to network device structure
1579  *
1580  * returns 0 if success, otherwise error code
1581  */
1582 static int hdlcdev_close(struct net_device *dev)
1583 {
1584         struct slgt_info *info = dev_to_port(dev);
1585         unsigned long flags;
1586
1587         DBGINFO(("%s hdlcdev_close\n", dev->name));
1588
1589         netif_stop_queue(dev);
1590
1591         /* shutdown adapter and release resources */
1592         shutdown(info);
1593
1594         hdlc_close(dev);
1595
1596         spin_lock_irqsave(&info->netlock, flags);
1597         info->netcount=0;
1598         spin_unlock_irqrestore(&info->netlock, flags);
1599
1600         module_put(THIS_MODULE);
1601         return 0;
1602 }
1603
1604 /**
1605  * called by network layer to process IOCTL call to network device
1606  *
1607  * dev  pointer to network device structure
1608  * ifr  pointer to network interface request structure
1609  * cmd  IOCTL command code
1610  *
1611  * returns 0 if success, otherwise error code
1612  */
1613 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1614 {
1615         const size_t size = sizeof(sync_serial_settings);
1616         sync_serial_settings new_line;
1617         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1618         struct slgt_info *info = dev_to_port(dev);
1619         unsigned int flags;
1620
1621         DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1622
1623         /* return error if TTY interface open */
1624         if (info->port.count)
1625                 return -EBUSY;
1626
1627         if (cmd != SIOCWANDEV)
1628                 return hdlc_ioctl(dev, ifr, cmd);
1629
1630         switch(ifr->ifr_settings.type) {
1631         case IF_GET_IFACE: /* return current sync_serial_settings */
1632
1633                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1634                 if (ifr->ifr_settings.size < size) {
1635                         ifr->ifr_settings.size = size; /* data size wanted */
1636                         return -ENOBUFS;
1637                 }
1638
1639                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1640                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1641                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1642                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1643
1644                 switch (flags){
1645                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1646                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1647                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1648                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1649                 default: new_line.clock_type = CLOCK_DEFAULT;
1650                 }
1651
1652                 new_line.clock_rate = info->params.clock_speed;
1653                 new_line.loopback   = info->params.loopback ? 1:0;
1654
1655                 if (copy_to_user(line, &new_line, size))
1656                         return -EFAULT;
1657                 return 0;
1658
1659         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1660
1661                 if(!capable(CAP_NET_ADMIN))
1662                         return -EPERM;
1663                 if (copy_from_user(&new_line, line, size))
1664                         return -EFAULT;
1665
1666                 switch (new_line.clock_type)
1667                 {
1668                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1669                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1670                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1671                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1672                 case CLOCK_DEFAULT:  flags = info->params.flags &
1673                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1674                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1675                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1676                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1677                 default: return -EINVAL;
1678                 }
1679
1680                 if (new_line.loopback != 0 && new_line.loopback != 1)
1681                         return -EINVAL;
1682
1683                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1684                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1685                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1686                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1687                 info->params.flags |= flags;
1688
1689                 info->params.loopback = new_line.loopback;
1690
1691                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1692                         info->params.clock_speed = new_line.clock_rate;
1693                 else
1694                         info->params.clock_speed = 0;
1695
1696                 /* if network interface up, reprogram hardware */
1697                 if (info->netcount)
1698                         program_hw(info);
1699                 return 0;
1700
1701         default:
1702                 return hdlc_ioctl(dev, ifr, cmd);
1703         }
1704 }
1705
1706 /**
1707  * called by network layer when transmit timeout is detected
1708  *
1709  * dev  pointer to network device structure
1710  */
1711 static void hdlcdev_tx_timeout(struct net_device *dev)
1712 {
1713         struct slgt_info *info = dev_to_port(dev);
1714         unsigned long flags;
1715
1716         DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1717
1718         dev->stats.tx_errors++;
1719         dev->stats.tx_aborted_errors++;
1720
1721         spin_lock_irqsave(&info->lock,flags);
1722         tx_stop(info);
1723         spin_unlock_irqrestore(&info->lock,flags);
1724
1725         netif_wake_queue(dev);
1726 }
1727
1728 /**
1729  * called by device driver when transmit completes
1730  * reenable network layer transmit if stopped
1731  *
1732  * info  pointer to device instance information
1733  */
1734 static void hdlcdev_tx_done(struct slgt_info *info)
1735 {
1736         if (netif_queue_stopped(info->netdev))
1737                 netif_wake_queue(info->netdev);
1738 }
1739
1740 /**
1741  * called by device driver when frame received
1742  * pass frame to network layer
1743  *
1744  * info  pointer to device instance information
1745  * buf   pointer to buffer contianing frame data
1746  * size  count of data bytes in buf
1747  */
1748 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1749 {
1750         struct sk_buff *skb = dev_alloc_skb(size);
1751         struct net_device *dev = info->netdev;
1752
1753         DBGINFO(("%s hdlcdev_rx\n", dev->name));
1754
1755         if (skb == NULL) {
1756                 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1757                 dev->stats.rx_dropped++;
1758                 return;
1759         }
1760
1761         memcpy(skb_put(skb, size), buf, size);
1762
1763         skb->protocol = hdlc_type_trans(skb, dev);
1764
1765         dev->stats.rx_packets++;
1766         dev->stats.rx_bytes += size;
1767
1768         netif_rx(skb);
1769 }
1770
1771 static const struct net_device_ops hdlcdev_ops = {
1772         .ndo_open       = hdlcdev_open,
1773         .ndo_stop       = hdlcdev_close,
1774         .ndo_change_mtu = hdlc_change_mtu,
1775         .ndo_start_xmit = hdlc_start_xmit,
1776         .ndo_do_ioctl   = hdlcdev_ioctl,
1777         .ndo_tx_timeout = hdlcdev_tx_timeout,
1778 };
1779
1780 /**
1781  * called by device driver when adding device instance
1782  * do generic HDLC initialization
1783  *
1784  * info  pointer to device instance information
1785  *
1786  * returns 0 if success, otherwise error code
1787  */
1788 static int hdlcdev_init(struct slgt_info *info)
1789 {
1790         int rc;
1791         struct net_device *dev;
1792         hdlc_device *hdlc;
1793
1794         /* allocate and initialize network and HDLC layer objects */
1795
1796         if (!(dev = alloc_hdlcdev(info))) {
1797                 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1798                 return -ENOMEM;
1799         }
1800
1801         /* for network layer reporting purposes only */
1802         dev->mem_start = info->phys_reg_addr;
1803         dev->mem_end   = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1804         dev->irq       = info->irq_level;
1805
1806         /* network layer callbacks and settings */
1807         dev->netdev_ops     = &hdlcdev_ops;
1808         dev->watchdog_timeo = 10 * HZ;
1809         dev->tx_queue_len   = 50;
1810
1811         /* generic HDLC layer callbacks and settings */
1812         hdlc         = dev_to_hdlc(dev);
1813         hdlc->attach = hdlcdev_attach;
1814         hdlc->xmit   = hdlcdev_xmit;
1815
1816         /* register objects with HDLC layer */
1817         if ((rc = register_hdlc_device(dev))) {
1818                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1819                 free_netdev(dev);
1820                 return rc;
1821         }
1822
1823         info->netdev = dev;
1824         return 0;
1825 }
1826
1827 /**
1828  * called by device driver when removing device instance
1829  * do generic HDLC cleanup
1830  *
1831  * info  pointer to device instance information
1832  */
1833 static void hdlcdev_exit(struct slgt_info *info)
1834 {
1835         unregister_hdlc_device(info->netdev);
1836         free_netdev(info->netdev);
1837         info->netdev = NULL;
1838 }
1839
1840 #endif /* ifdef CONFIG_HDLC */
1841
1842 /*
1843  * get async data from rx DMA buffers
1844  */
1845 static void rx_async(struct slgt_info *info)
1846 {
1847         struct tty_struct *tty = info->port.tty;
1848         struct mgsl_icount *icount = &info->icount;
1849         unsigned int start, end;
1850         unsigned char *p;
1851         unsigned char status;
1852         struct slgt_desc *bufs = info->rbufs;
1853         int i, count;
1854         int chars = 0;
1855         int stat;
1856         unsigned char ch;
1857
1858         start = end = info->rbuf_current;
1859
1860         while(desc_complete(bufs[end])) {
1861                 count = desc_count(bufs[end]) - info->rbuf_index;
1862                 p     = bufs[end].buf + info->rbuf_index;
1863
1864                 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1865                 DBGDATA(info, p, count, "rx");
1866
1867                 for(i=0 ; i < count; i+=2, p+=2) {
1868                         ch = *p;
1869                         icount->rx++;
1870
1871                         stat = 0;
1872
1873                         if ((status = *(p+1) & (BIT1 + BIT0))) {
1874                                 if (status & BIT1)
1875                                         icount->parity++;
1876                                 else if (status & BIT0)
1877                                         icount->frame++;
1878                                 /* discard char if tty control flags say so */
1879                                 if (status & info->ignore_status_mask)
1880                                         continue;
1881                                 if (status & BIT1)
1882                                         stat = TTY_PARITY;
1883                                 else if (status & BIT0)
1884                                         stat = TTY_FRAME;
1885                         }
1886                         if (tty) {
1887                                 tty_insert_flip_char(tty, ch, stat);
1888                                 chars++;
1889                         }
1890                 }
1891
1892                 if (i < count) {
1893                         /* receive buffer not completed */
1894                         info->rbuf_index += i;
1895                         mod_timer(&info->rx_timer, jiffies + 1);
1896                         break;
1897                 }
1898
1899                 info->rbuf_index = 0;
1900                 free_rbufs(info, end, end);
1901
1902                 if (++end == info->rbuf_count)
1903                         end = 0;
1904
1905                 /* if entire list searched then no frame available */
1906                 if (end == start)
1907                         break;
1908         }
1909
1910         if (tty && chars)
1911                 tty_flip_buffer_push(tty);
1912 }
1913
1914 /*
1915  * return next bottom half action to perform
1916  */
1917 static int bh_action(struct slgt_info *info)
1918 {
1919         unsigned long flags;
1920         int rc;
1921
1922         spin_lock_irqsave(&info->lock,flags);
1923
1924         if (info->pending_bh & BH_RECEIVE) {
1925                 info->pending_bh &= ~BH_RECEIVE;
1926                 rc = BH_RECEIVE;
1927         } else if (info->pending_bh & BH_TRANSMIT) {
1928                 info->pending_bh &= ~BH_TRANSMIT;
1929                 rc = BH_TRANSMIT;
1930         } else if (info->pending_bh & BH_STATUS) {
1931                 info->pending_bh &= ~BH_STATUS;
1932                 rc = BH_STATUS;
1933         } else {
1934                 /* Mark BH routine as complete */
1935                 info->bh_running = false;
1936                 info->bh_requested = false;
1937                 rc = 0;
1938         }
1939
1940         spin_unlock_irqrestore(&info->lock,flags);
1941
1942         return rc;
1943 }
1944
1945 /*
1946  * perform bottom half processing
1947  */
1948 static void bh_handler(struct work_struct *work)
1949 {
1950         struct slgt_info *info = container_of(work, struct slgt_info, task);
1951         int action;
1952
1953         if (!info)
1954                 return;
1955         info->bh_running = true;
1956
1957         while((action = bh_action(info))) {
1958                 switch (action) {
1959                 case BH_RECEIVE:
1960                         DBGBH(("%s bh receive\n", info->device_name));
1961                         switch(info->params.mode) {
1962                         case MGSL_MODE_ASYNC:
1963                                 rx_async(info);
1964                                 break;
1965                         case MGSL_MODE_HDLC:
1966                                 while(rx_get_frame(info));
1967                                 break;
1968                         case MGSL_MODE_RAW:
1969                         case MGSL_MODE_MONOSYNC:
1970                         case MGSL_MODE_BISYNC:
1971                                 while(rx_get_buf(info));
1972                                 break;
1973                         }
1974                         /* restart receiver if rx DMA buffers exhausted */
1975                         if (info->rx_restart)
1976                                 rx_start(info);
1977                         break;
1978                 case BH_TRANSMIT:
1979                         bh_transmit(info);
1980                         break;
1981                 case BH_STATUS:
1982                         DBGBH(("%s bh status\n", info->device_name));
1983                         info->ri_chkcount = 0;
1984                         info->dsr_chkcount = 0;
1985                         info->dcd_chkcount = 0;
1986                         info->cts_chkcount = 0;
1987                         break;
1988                 default:
1989                         DBGBH(("%s unknown action\n", info->device_name));
1990                         break;
1991                 }
1992         }
1993         DBGBH(("%s bh_handler exit\n", info->device_name));
1994 }
1995
1996 static void bh_transmit(struct slgt_info *info)
1997 {
1998         struct tty_struct *tty = info->port.tty;
1999
2000         DBGBH(("%s bh_transmit\n", info->device_name));
2001         if (tty)
2002                 tty_wakeup(tty);
2003 }
2004
2005 static void dsr_change(struct slgt_info *info, unsigned short status)
2006 {
2007         if (status & BIT3) {
2008                 info->signals |= SerialSignal_DSR;
2009                 info->input_signal_events.dsr_up++;
2010         } else {
2011                 info->signals &= ~SerialSignal_DSR;
2012                 info->input_signal_events.dsr_down++;
2013         }
2014         DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2015         if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2016                 slgt_irq_off(info, IRQ_DSR);
2017                 return;
2018         }
2019         info->icount.dsr++;
2020         wake_up_interruptible(&info->status_event_wait_q);
2021         wake_up_interruptible(&info->event_wait_q);
2022         info->pending_bh |= BH_STATUS;
2023 }
2024
2025 static void cts_change(struct slgt_info *info, unsigned short status)
2026 {
2027         if (status & BIT2) {
2028                 info->signals |= SerialSignal_CTS;
2029                 info->input_signal_events.cts_up++;
2030         } else {
2031                 info->signals &= ~SerialSignal_CTS;
2032                 info->input_signal_events.cts_down++;
2033         }
2034         DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2035         if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2036                 slgt_irq_off(info, IRQ_CTS);
2037                 return;
2038         }
2039         info->icount.cts++;
2040         wake_up_interruptible(&info->status_event_wait_q);
2041         wake_up_interruptible(&info->event_wait_q);
2042         info->pending_bh |= BH_STATUS;
2043
2044         if (info->port.flags & ASYNC_CTS_FLOW) {
2045                 if (info->port.tty) {
2046                         if (info->port.tty->hw_stopped) {
2047                                 if (info->signals & SerialSignal_CTS) {
2048                                         info->port.tty->hw_stopped = 0;
2049                                         info->pending_bh |= BH_TRANSMIT;
2050                                         return;
2051                                 }
2052                         } else {
2053                                 if (!(info->signals & SerialSignal_CTS))
2054                                         info->port.tty->hw_stopped = 1;
2055                         }
2056                 }
2057         }
2058 }
2059
2060 static void dcd_change(struct slgt_info *info, unsigned short status)
2061 {
2062         if (status & BIT1) {
2063                 info->signals |= SerialSignal_DCD;
2064                 info->input_signal_events.dcd_up++;
2065         } else {
2066                 info->signals &= ~SerialSignal_DCD;
2067                 info->input_signal_events.dcd_down++;
2068         }
2069         DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2070         if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2071                 slgt_irq_off(info, IRQ_DCD);
2072                 return;
2073         }
2074         info->icount.dcd++;
2075 #if SYNCLINK_GENERIC_HDLC
2076         if (info->netcount) {
2077                 if (info->signals & SerialSignal_DCD)
2078                         netif_carrier_on(info->netdev);
2079                 else
2080                         netif_carrier_off(info->netdev);
2081         }
2082 #endif
2083         wake_up_interruptible(&info->status_event_wait_q);
2084         wake_up_interruptible(&info->event_wait_q);
2085         info->pending_bh |= BH_STATUS;
2086
2087         if (info->port.flags & ASYNC_CHECK_CD) {
2088                 if (info->signals & SerialSignal_DCD)
2089                         wake_up_interruptible(&info->port.open_wait);
2090                 else {
2091                         if (info->port.tty)
2092                                 tty_hangup(info->port.tty);
2093                 }
2094         }
2095 }
2096
2097 static void ri_change(struct slgt_info *info, unsigned short status)
2098 {
2099         if (status & BIT0) {
2100                 info->signals |= SerialSignal_RI;
2101                 info->input_signal_events.ri_up++;
2102         } else {
2103                 info->signals &= ~SerialSignal_RI;
2104                 info->input_signal_events.ri_down++;
2105         }
2106         DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2107         if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2108                 slgt_irq_off(info, IRQ_RI);
2109                 return;
2110         }
2111         info->icount.rng++;
2112         wake_up_interruptible(&info->status_event_wait_q);
2113         wake_up_interruptible(&info->event_wait_q);
2114         info->pending_bh |= BH_STATUS;
2115 }
2116
2117 static void isr_rxdata(struct slgt_info *info)
2118 {
2119         unsigned int count = info->rbuf_fill_count;
2120         unsigned int i = info->rbuf_fill_index;
2121         unsigned short reg;
2122
2123         while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2124                 reg = rd_reg16(info, RDR);
2125                 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2126                 if (desc_complete(info->rbufs[i])) {
2127                         /* all buffers full */
2128                         rx_stop(info);
2129                         info->rx_restart = 1;
2130                         continue;
2131                 }
2132                 info->rbufs[i].buf[count++] = (unsigned char)reg;
2133                 /* async mode saves status byte to buffer for each data byte */
2134                 if (info->params.mode == MGSL_MODE_ASYNC)
2135                         info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2136                 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2137                         /* buffer full or end of frame */
2138                         set_desc_count(info->rbufs[i], count);
2139                         set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2140                         info->rbuf_fill_count = count = 0;
2141                         if (++i == info->rbuf_count)
2142                                 i = 0;
2143                         info->pending_bh |= BH_RECEIVE;
2144                 }
2145         }
2146
2147         info->rbuf_fill_index = i;
2148         info->rbuf_fill_count = count;
2149 }
2150
2151 static void isr_serial(struct slgt_info *info)
2152 {
2153         unsigned short status = rd_reg16(info, SSR);
2154
2155         DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2156
2157         wr_reg16(info, SSR, status); /* clear pending */
2158
2159         info->irq_occurred = true;
2160
2161         if (info->params.mode == MGSL_MODE_ASYNC) {
2162                 if (status & IRQ_TXIDLE) {
2163                         if (info->tx_count)
2164                                 isr_txeom(info, status);
2165                 }
2166                 if (info->rx_pio && (status & IRQ_RXDATA))
2167                         isr_rxdata(info);
2168                 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2169                         info->icount.brk++;
2170                         /* process break detection if tty control allows */
2171                         if (info->port.tty) {
2172                                 if (!(status & info->ignore_status_mask)) {
2173                                         if (info->read_status_mask & MASK_BREAK) {
2174                                                 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2175                                                 if (info->port.flags & ASYNC_SAK)
2176                                                         do_SAK(info->port.tty);
2177                                         }
2178                                 }
2179                         }
2180                 }
2181         } else {
2182                 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2183                         isr_txeom(info, status);
2184                 if (info->rx_pio && (status & IRQ_RXDATA))
2185                         isr_rxdata(info);
2186                 if (status & IRQ_RXIDLE) {
2187                         if (status & RXIDLE)
2188                                 info->icount.rxidle++;
2189                         else
2190                                 info->icount.exithunt++;
2191                         wake_up_interruptible(&info->event_wait_q);
2192                 }
2193
2194                 if (status & IRQ_RXOVER)
2195                         rx_start(info);
2196         }
2197
2198         if (status & IRQ_DSR)
2199                 dsr_change(info, status);
2200         if (status & IRQ_CTS)
2201                 cts_change(info, status);
2202         if (status & IRQ_DCD)
2203                 dcd_change(info, status);
2204         if (status & IRQ_RI)
2205                 ri_change(info, status);
2206 }
2207
2208 static void isr_rdma(struct slgt_info *info)
2209 {
2210         unsigned int status = rd_reg32(info, RDCSR);
2211
2212         DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2213
2214         /* RDCSR (rx DMA control/status)
2215          *
2216          * 31..07  reserved
2217          * 06      save status byte to DMA buffer
2218          * 05      error
2219          * 04      eol (end of list)
2220          * 03      eob (end of buffer)
2221          * 02      IRQ enable
2222          * 01      reset
2223          * 00      enable
2224          */
2225         wr_reg32(info, RDCSR, status);  /* clear pending */
2226
2227         if (status & (BIT5 + BIT4)) {
2228                 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2229                 info->rx_restart = true;
2230         }
2231         info->pending_bh |= BH_RECEIVE;
2232 }
2233
2234 static void isr_tdma(struct slgt_info *info)
2235 {
2236         unsigned int status = rd_reg32(info, TDCSR);
2237
2238         DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2239
2240         /* TDCSR (tx DMA control/status)
2241          *
2242          * 31..06  reserved
2243          * 05      error
2244          * 04      eol (end of list)
2245          * 03      eob (end of buffer)
2246          * 02      IRQ enable
2247          * 01      reset
2248          * 00      enable
2249          */
2250         wr_reg32(info, TDCSR, status);  /* clear pending */
2251
2252         if (status & (BIT5 + BIT4 + BIT3)) {
2253                 // another transmit buffer has completed
2254                 // run bottom half to get more send data from user
2255                 info->pending_bh |= BH_TRANSMIT;
2256         }
2257 }
2258
2259 static void isr_txeom(struct slgt_info *info, unsigned short status)
2260 {
2261         DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2262
2263         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2264         tdma_reset(info);
2265         reset_tbufs(info);
2266         if (status & IRQ_TXUNDER) {
2267                 unsigned short val = rd_reg16(info, TCR);
2268                 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2269                 wr_reg16(info, TCR, val); /* clear reset bit */
2270         }
2271
2272         if (info->tx_active) {
2273                 if (info->params.mode != MGSL_MODE_ASYNC) {
2274                         if (status & IRQ_TXUNDER)
2275                                 info->icount.txunder++;
2276                         else if (status & IRQ_TXIDLE)
2277                                 info->icount.txok++;
2278                 }
2279
2280                 info->tx_active = false;
2281                 info->tx_count = 0;
2282
2283                 del_timer(&info->tx_timer);
2284
2285                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2286                         info->signals &= ~SerialSignal_RTS;
2287                         info->drop_rts_on_tx_done = false;
2288                         set_signals(info);
2289                 }
2290
2291 #if SYNCLINK_GENERIC_HDLC
2292                 if (info->netcount)
2293                         hdlcdev_tx_done(info);
2294                 else
2295 #endif
2296                 {
2297                         if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2298                                 tx_stop(info);
2299                                 return;
2300                         }
2301                         info->pending_bh |= BH_TRANSMIT;
2302                 }
2303         }
2304 }
2305
2306 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2307 {
2308         struct cond_wait *w, *prev;
2309
2310         /* wake processes waiting for specific transitions */
2311         for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2312                 if (w->data & changed) {
2313                         w->data = state;
2314                         wake_up_interruptible(&w->q);
2315                         if (prev != NULL)
2316                                 prev->next = w->next;
2317                         else
2318                                 info->gpio_wait_q = w->next;
2319                 } else
2320                         prev = w;
2321         }
2322 }
2323
2324 /* interrupt service routine
2325  *
2326  *      irq     interrupt number
2327  *      dev_id  device ID supplied during interrupt registration
2328  */
2329 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2330 {
2331         struct slgt_info *info = dev_id;
2332         unsigned int gsr;
2333         unsigned int i;
2334
2335         DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2336
2337         spin_lock(&info->lock);
2338
2339         while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2340                 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2341                 info->irq_occurred = true;
2342                 for(i=0; i < info->port_count ; i++) {
2343                         if (info->port_array[i] == NULL)
2344                                 continue;
2345                         if (gsr & (BIT8 << i))
2346                                 isr_serial(info->port_array[i]);
2347                         if (gsr & (BIT16 << (i*2)))
2348                                 isr_rdma(info->port_array[i]);
2349                         if (gsr & (BIT17 << (i*2)))
2350                                 isr_tdma(info->port_array[i]);
2351                 }
2352         }
2353
2354         if (info->gpio_present) {
2355                 unsigned int state;
2356                 unsigned int changed;
2357                 while ((changed = rd_reg32(info, IOSR)) != 0) {
2358                         DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2359                         /* read latched state of GPIO signals */
2360                         state = rd_reg32(info, IOVR);
2361                         /* clear pending GPIO interrupt bits */
2362                         wr_reg32(info, IOSR, changed);
2363                         for (i=0 ; i < info->port_count ; i++) {
2364                                 if (info->port_array[i] != NULL)
2365                                         isr_gpio(info->port_array[i], changed, state);
2366                         }
2367                 }
2368         }
2369
2370         for(i=0; i < info->port_count ; i++) {
2371                 struct slgt_info *port = info->port_array[i];
2372
2373                 if (port && (port->port.count || port->netcount) &&
2374                     port->pending_bh && !port->bh_running &&
2375                     !port->bh_requested) {
2376                         DBGISR(("%s bh queued\n", port->device_name));
2377                         schedule_work(&port->task);
2378                         port->bh_requested = true;
2379                 }
2380         }
2381
2382         spin_unlock(&info->lock);
2383
2384         DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2385         return IRQ_HANDLED;
2386 }
2387
2388 static int startup(struct slgt_info *info)
2389 {
2390         DBGINFO(("%s startup\n", info->device_name));
2391
2392         if (info->port.flags & ASYNC_INITIALIZED)
2393                 return 0;
2394
2395         if (!info->tx_buf) {
2396                 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2397                 if (!info->tx_buf) {
2398                         DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2399                         return -ENOMEM;
2400                 }
2401         }
2402
2403         info->pending_bh = 0;
2404
2405         memset(&info->icount, 0, sizeof(info->icount));
2406
2407         /* program hardware for current parameters */
2408         change_params(info);
2409
2410         if (info->port.tty)
2411                 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2412
2413         info->port.flags |= ASYNC_INITIALIZED;
2414
2415         return 0;
2416 }
2417
2418 /*
2419  *  called by close() and hangup() to shutdown hardware
2420  */
2421 static void shutdown(struct slgt_info *info)
2422 {
2423         unsigned long flags;
2424
2425         if (!(info->port.flags & ASYNC_INITIALIZED))
2426                 return;
2427
2428         DBGINFO(("%s shutdown\n", info->device_name));
2429
2430         /* clear status wait queue because status changes */
2431         /* can't happen after shutting down the hardware */
2432         wake_up_interruptible(&info->status_event_wait_q);
2433         wake_up_interruptible(&info->event_wait_q);
2434
2435         del_timer_sync(&info->tx_timer);
2436         del_timer_sync(&info->rx_timer);
2437
2438         kfree(info->tx_buf);
2439         info->tx_buf = NULL;
2440
2441         spin_lock_irqsave(&info->lock,flags);
2442
2443         tx_stop(info);
2444         rx_stop(info);
2445
2446         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2447
2448         if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2449                 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2450                 set_signals(info);
2451         }
2452
2453         flush_cond_wait(&info->gpio_wait_q);
2454
2455         spin_unlock_irqrestore(&info->lock,flags);
2456
2457         if (info->port.tty)
2458                 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2459
2460         info->port.flags &= ~ASYNC_INITIALIZED;
2461 }
2462
2463 static void program_hw(struct slgt_info *info)
2464 {
2465         unsigned long flags;
2466
2467         spin_lock_irqsave(&info->lock,flags);
2468
2469         rx_stop(info);
2470         tx_stop(info);
2471
2472         if (info->params.mode != MGSL_MODE_ASYNC ||
2473             info->netcount)
2474                 sync_mode(info);
2475         else
2476                 async_mode(info);
2477
2478         set_signals(info);
2479
2480         info->dcd_chkcount = 0;
2481         info->cts_chkcount = 0;
2482         info->ri_chkcount = 0;
2483         info->dsr_chkcount = 0;
2484
2485         slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2486         get_signals(info);
2487
2488         if (info->netcount ||
2489             (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2490                 rx_start(info);
2491
2492         spin_unlock_irqrestore(&info->lock,flags);
2493 }
2494
2495 /*
2496  * reconfigure adapter based on new parameters
2497  */
2498 static void change_params(struct slgt_info *info)
2499 {
2500         unsigned cflag;
2501         int bits_per_char;
2502
2503         if (!info->port.tty || !info->port.tty->termios)
2504                 return;
2505         DBGINFO(("%s change_params\n", info->device_name));
2506
2507         cflag = info->port.tty->termios->c_cflag;
2508
2509         /* if B0 rate (hangup) specified then negate DTR and RTS */
2510         /* otherwise assert DTR and RTS */
2511         if (cflag & CBAUD)
2512                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2513         else
2514                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2515
2516         /* byte size and parity */
2517
2518         switch (cflag & CSIZE) {
2519         case CS5: info->params.data_bits = 5; break;
2520         case CS6: info->params.data_bits = 6; break;
2521         case CS7: info->params.data_bits = 7; break;
2522         case CS8: info->params.data_bits = 8; break;
2523         default:  info->params.data_bits = 7; break;
2524         }
2525
2526         info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2527
2528         if (cflag & PARENB)
2529                 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2530         else
2531                 info->params.parity = ASYNC_PARITY_NONE;
2532
2533         /* calculate number of jiffies to transmit a full
2534          * FIFO (32 bytes) at specified data rate
2535          */
2536         bits_per_char = info->params.data_bits +
2537                         info->params.stop_bits + 1;
2538
2539         info->params.data_rate = tty_get_baud_rate(info->port.tty);
2540
2541         if (info->params.data_rate) {
2542                 info->timeout = (32*HZ*bits_per_char) /
2543                                 info->params.data_rate;
2544         }
2545         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2546
2547         if (cflag & CRTSCTS)
2548                 info->port.flags |= ASYNC_CTS_FLOW;
2549         else
2550                 info->port.flags &= ~ASYNC_CTS_FLOW;
2551
2552         if (cflag & CLOCAL)
2553                 info->port.flags &= ~ASYNC_CHECK_CD;
2554         else
2555                 info->port.flags |= ASYNC_CHECK_CD;
2556
2557         /* process tty input control flags */
2558
2559         info->read_status_mask = IRQ_RXOVER;
2560         if (I_INPCK(info->port.tty))
2561                 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2562         if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2563                 info->read_status_mask |= MASK_BREAK;
2564         if (I_IGNPAR(info->port.tty))
2565                 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2566         if (I_IGNBRK(info->port.tty)) {
2567                 info->ignore_status_mask |= MASK_BREAK;
2568                 /* If ignoring parity and break indicators, ignore
2569                  * overruns too.  (For real raw support).
2570                  */
2571                 if (I_IGNPAR(info->port.tty))
2572                         info->ignore_status_mask |= MASK_OVERRUN;
2573         }
2574
2575         program_hw(info);
2576 }
2577
2578 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2579 {
2580         DBGINFO(("%s get_stats\n",  info->device_name));
2581         if (!user_icount) {
2582                 memset(&info->icount, 0, sizeof(info->icount));
2583         } else {
2584                 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2585                         return -EFAULT;
2586         }
2587         return 0;
2588 }
2589
2590 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2591 {
2592         DBGINFO(("%s get_params\n", info->device_name));
2593         if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2594                 return -EFAULT;
2595         return 0;
2596 }
2597
2598 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2599 {
2600         unsigned long flags;
2601         MGSL_PARAMS tmp_params;
2602
2603         DBGINFO(("%s set_params\n", info->device_name));
2604         if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2605                 return -EFAULT;
2606
2607         spin_lock_irqsave(&info->lock, flags);
2608         if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2609                 info->base_clock = tmp_params.clock_speed;
2610         else
2611                 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2612         spin_unlock_irqrestore(&info->lock, flags);
2613
2614         program_hw(info);
2615
2616         return 0;
2617 }
2618
2619 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2620 {
2621         DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2622         if (put_user(info->idle_mode, idle_mode))
2623                 return -EFAULT;
2624         return 0;
2625 }
2626
2627 static int set_txidle(struct slgt_info *info, int idle_mode)
2628 {
2629         unsigned long flags;
2630         DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2631         spin_lock_irqsave(&info->lock,flags);
2632         info->idle_mode = idle_mode;
2633         if (info->params.mode != MGSL_MODE_ASYNC)
2634                 tx_set_idle(info);
2635         spin_unlock_irqrestore(&info->lock,flags);
2636         return 0;
2637 }
2638
2639 static int tx_enable(struct slgt_info *info, int enable)
2640 {
2641         unsigned long flags;
2642         DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2643         spin_lock_irqsave(&info->lock,flags);
2644         if (enable) {
2645                 if (!info->tx_enabled)
2646                         tx_start(info);
2647         } else {
2648                 if (info->tx_enabled)
2649                         tx_stop(info);
2650         }
2651         spin_unlock_irqrestore(&info->lock,flags);
2652         return 0;
2653 }
2654
2655 /*
2656  * abort transmit HDLC frame
2657  */
2658 static int tx_abort(struct slgt_info *info)
2659 {
2660         unsigned long flags;
2661         DBGINFO(("%s tx_abort\n", info->device_name));
2662         spin_lock_irqsave(&info->lock,flags);
2663         tdma_reset(info);
2664         spin_unlock_irqrestore(&info->lock,flags);
2665         return 0;
2666 }
2667
2668 static int rx_enable(struct slgt_info *info, int enable)
2669 {
2670         unsigned long flags;
2671         unsigned int rbuf_fill_level;
2672         DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2673         spin_lock_irqsave(&info->lock,flags);
2674         /*
2675          * enable[31..16] = receive DMA buffer fill level
2676          * 0 = noop (leave fill level unchanged)
2677          * fill level must be multiple of 4 and <= buffer size
2678          */
2679         rbuf_fill_level = ((unsigned int)enable) >> 16;
2680         if (rbuf_fill_level) {
2681                 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2682                         spin_unlock_irqrestore(&info->lock, flags);
2683                         return -EINVAL;
2684                 }
2685                 info->rbuf_fill_level = rbuf_fill_level;
2686                 if (rbuf_fill_level < 128)
2687                         info->rx_pio = 1; /* PIO mode */
2688                 else
2689                         info->rx_pio = 0; /* DMA mode */
2690                 rx_stop(info); /* restart receiver to use new fill level */
2691         }
2692
2693         /*
2694          * enable[1..0] = receiver enable command
2695          * 0 = disable
2696          * 1 = enable
2697          * 2 = enable or force hunt mode if already enabled
2698          */
2699         enable &= 3;
2700         if (enable) {
2701                 if (!info->rx_enabled)
2702                         rx_start(info);
2703                 else if (enable == 2) {
2704                         /* force hunt mode (write 1 to RCR[3]) */
2705                         wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2706                 }
2707         } else {
2708                 if (info->rx_enabled)
2709                         rx_stop(info);
2710         }
2711         spin_unlock_irqrestore(&info->lock,flags);
2712         return 0;
2713 }
2714
2715 /*
2716  *  wait for specified event to occur
2717  */
2718 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2719 {
2720         unsigned long flags;
2721         int s;
2722         int rc=0;
2723         struct mgsl_icount cprev, cnow;
2724         int events;
2725         int mask;
2726         struct  _input_signal_events oldsigs, newsigs;
2727         DECLARE_WAITQUEUE(wait, current);
2728
2729         if (get_user(mask, mask_ptr))
2730                 return -EFAULT;
2731
2732         DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2733
2734         spin_lock_irqsave(&info->lock,flags);
2735
2736         /* return immediately if state matches requested events */
2737         get_signals(info);
2738         s = info->signals;
2739
2740         events = mask &
2741                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2742                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2743                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2744                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2745         if (events) {
2746                 spin_unlock_irqrestore(&info->lock,flags);
2747                 goto exit;
2748         }
2749
2750         /* save current irq counts */
2751         cprev = info->icount;
2752         oldsigs = info->input_signal_events;
2753
2754         /* enable hunt and idle irqs if needed */
2755         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2756                 unsigned short val = rd_reg16(info, SCR);
2757                 if (!(val & IRQ_RXIDLE))
2758                         wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2759         }
2760
2761         set_current_state(TASK_INTERRUPTIBLE);
2762         add_wait_queue(&info->event_wait_q, &wait);
2763
2764         spin_unlock_irqrestore(&info->lock,flags);
2765
2766         for(;;) {
2767                 schedule();
2768                 if (signal_pending(current)) {
2769                         rc = -ERESTARTSYS;
2770                         break;
2771                 }
2772
2773                 /* get current irq counts */
2774                 spin_lock_irqsave(&info->lock,flags);
2775                 cnow = info->icount;
2776                 newsigs = info->input_signal_events;
2777                 set_current_state(TASK_INTERRUPTIBLE);
2778                 spin_unlock_irqrestore(&info->lock,flags);
2779
2780                 /* if no change, wait aborted for some reason */
2781                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
2782                     newsigs.dsr_down == oldsigs.dsr_down &&
2783                     newsigs.dcd_up   == oldsigs.dcd_up   &&
2784                     newsigs.dcd_down == oldsigs.dcd_down &&
2785                     newsigs.cts_up   == oldsigs.cts_up   &&
2786                     newsigs.cts_down == oldsigs.cts_down &&
2787                     newsigs.ri_up    == oldsigs.ri_up    &&
2788                     newsigs.ri_down  == oldsigs.ri_down  &&
2789                     cnow.exithunt    == cprev.exithunt   &&
2790                     cnow.rxidle      == cprev.rxidle) {
2791                         rc = -EIO;
2792                         break;
2793                 }
2794
2795                 events = mask &
2796                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
2797                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2798                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
2799                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2800                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
2801                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2802                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
2803                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
2804                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
2805                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
2806                 if (events)
2807                         break;
2808
2809                 cprev = cnow;
2810                 oldsigs = newsigs;
2811         }
2812
2813         remove_wait_queue(&info->event_wait_q, &wait);
2814         set_current_state(TASK_RUNNING);
2815
2816
2817         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2818                 spin_lock_irqsave(&info->lock,flags);
2819                 if (!waitqueue_active(&info->event_wait_q)) {
2820                         /* disable enable exit hunt mode/idle rcvd IRQs */
2821                         wr_reg16(info, SCR,
2822                                 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2823                 }
2824                 spin_unlock_irqrestore(&info->lock,flags);
2825         }
2826 exit:
2827         if (rc == 0)
2828                 rc = put_user(events, mask_ptr);
2829         return rc;
2830 }
2831
2832 static int get_interface(struct slgt_info *info, int __user *if_mode)
2833 {
2834         DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2835         if (put_user(info->if_mode, if_mode))
2836                 return -EFAULT;
2837         return 0;
2838 }
2839
2840 static int set_interface(struct slgt_info *info, int if_mode)
2841 {
2842         unsigned long flags;
2843         unsigned short val;
2844
2845         DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2846         spin_lock_irqsave(&info->lock,flags);
2847         info->if_mode = if_mode;
2848
2849         msc_set_vcr(info);
2850
2851         /* TCR (tx control) 07  1=RTS driver control */
2852         val = rd_reg16(info, TCR);
2853         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2854                 val |= BIT7;
2855         else
2856                 val &= ~BIT7;
2857         wr_reg16(info, TCR, val);
2858
2859         spin_unlock_irqrestore(&info->lock,flags);
2860         return 0;
2861 }
2862
2863 /*
2864  * set general purpose IO pin state and direction
2865  *
2866  * user_gpio fields:
2867  * state   each bit indicates a pin state
2868  * smask   set bit indicates pin state to set
2869  * dir     each bit indicates a pin direction (0=input, 1=output)
2870  * dmask   set bit indicates pin direction to set
2871  */
2872 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2873 {
2874         unsigned long flags;
2875         struct gpio_desc gpio;
2876         __u32 data;
2877
2878         if (!info->gpio_present)
2879                 return -EINVAL;
2880         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2881                 return -EFAULT;
2882         DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2883                  info->device_name, gpio.state, gpio.smask,
2884                  gpio.dir, gpio.dmask));
2885
2886         spin_lock_irqsave(&info->lock,flags);
2887         if (gpio.dmask) {
2888                 data = rd_reg32(info, IODR);
2889                 data |= gpio.dmask & gpio.dir;
2890                 data &= ~(gpio.dmask & ~gpio.dir);
2891                 wr_reg32(info, IODR, data);
2892         }
2893         if (gpio.smask) {
2894                 data = rd_reg32(info, IOVR);
2895                 data |= gpio.smask & gpio.state;
2896                 data &= ~(gpio.smask & ~gpio.state);
2897                 wr_reg32(info, IOVR, data);
2898         }
2899         spin_unlock_irqrestore(&info->lock,flags);
2900
2901         return 0;
2902 }
2903
2904 /*
2905  * get general purpose IO pin state and direction
2906  */
2907 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2908 {
2909         struct gpio_desc gpio;
2910         if (!info->gpio_present)
2911                 return -EINVAL;
2912         gpio.state = rd_reg32(info, IOVR);
2913         gpio.smask = 0xffffffff;
2914         gpio.dir   = rd_reg32(info, IODR);
2915         gpio.dmask = 0xffffffff;
2916         if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2917                 return -EFAULT;
2918         DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2919                  info->device_name, gpio.state, gpio.dir));
2920         return 0;
2921 }
2922
2923 /*
2924  * conditional wait facility
2925  */
2926 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2927 {
2928         init_waitqueue_head(&w->q);
2929         init_waitqueue_entry(&w->wait, current);
2930         w->data = data;
2931 }
2932
2933 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2934 {
2935         set_current_state(TASK_INTERRUPTIBLE);
2936         add_wait_queue(&w->q, &w->wait);
2937         w->next = *head;
2938         *head = w;
2939 }
2940
2941 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2942 {
2943         struct cond_wait *w, *prev;
2944         remove_wait_queue(&cw->q, &cw->wait);
2945         set_current_state(TASK_RUNNING);
2946         for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2947                 if (w == cw) {
2948                         if (prev != NULL)
2949                                 prev->next = w->next;
2950                         else
2951                                 *head = w->next;
2952                         break;
2953                 }
2954         }
2955 }
2956
2957 static void flush_cond_wait(struct cond_wait **head)
2958 {
2959         while (*head != NULL) {
2960                 wake_up_interruptible(&(*head)->q);
2961                 *head = (*head)->next;
2962         }
2963 }
2964
2965 /*
2966  * wait for general purpose I/O pin(s) to enter specified state
2967  *
2968  * user_gpio fields:
2969  * state - bit indicates target pin state
2970  * smask - set bit indicates watched pin
2971  *
2972  * The wait ends when at least one watched pin enters the specified
2973  * state. When 0 (no error) is returned, user_gpio->state is set to the
2974  * state of all GPIO pins when the wait ends.
2975  *
2976  * Note: Each pin may be a dedicated input, dedicated output, or
2977  * configurable input/output. The number and configuration of pins
2978  * varies with the specific adapter model. Only input pins (dedicated
2979  * or configured) can be monitored with this function.
2980  */
2981 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2982 {
2983         unsigned long flags;
2984         int rc = 0;
2985         struct gpio_desc gpio;
2986         struct cond_wait wait;
2987         u32 state;
2988
2989         if (!info->gpio_present)
2990                 return -EINVAL;
2991         if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2992                 return -EFAULT;
2993         DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2994                  info->device_name, gpio.state, gpio.smask));
2995         /* ignore output pins identified by set IODR bit */
2996         if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2997                 return -EINVAL;
2998         init_cond_wait(&wait, gpio.smask);
2999
3000         spin_lock_irqsave(&info->lock, flags);
3001         /* enable interrupts for watched pins */
3002         wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3003         /* get current pin states */
3004         state = rd_reg32(info, IOVR);
3005
3006         if (gpio.smask & ~(state ^ gpio.state)) {
3007                 /* already in target state */
3008                 gpio.state = state;
3009         } else {
3010                 /* wait for target state */
3011                 add_cond_wait(&info->gpio_wait_q, &wait);
3012                 spin_unlock_irqrestore(&info->lock, flags);
3013                 schedule();
3014                 if (signal_pending(current))
3015                         rc = -ERESTARTSYS;
3016                 else
3017                         gpio.state = wait.data;
3018                 spin_lock_irqsave(&info->lock, flags);
3019                 remove_cond_wait(&info->gpio_wait_q, &wait);
3020         }
3021
3022         /* disable all GPIO interrupts if no waiting processes */
3023         if (info->gpio_wait_q == NULL)
3024                 wr_reg32(info, IOER, 0);
3025         spin_unlock_irqrestore(&info->lock,flags);
3026
3027         if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3028                 rc = -EFAULT;
3029         return rc;
3030 }
3031
3032 static int modem_input_wait(struct slgt_info *info,int arg)
3033 {
3034         unsigned long flags;
3035         int rc;
3036         struct mgsl_icount cprev, cnow;
3037         DECLARE_WAITQUEUE(wait, current);
3038
3039         /* save current irq counts */
3040         spin_lock_irqsave(&info->lock,flags);
3041         cprev = info->icount;
3042         add_wait_queue(&info->status_event_wait_q, &wait);
3043         set_current_state(TASK_INTERRUPTIBLE);
3044         spin_unlock_irqrestore(&info->lock,flags);
3045
3046         for(;;) {
3047                 schedule();
3048                 if (signal_pending(current)) {
3049                         rc = -ERESTARTSYS;
3050                         break;
3051                 }
3052
3053                 /* get new irq counts */
3054                 spin_lock_irqsave(&info->lock,flags);
3055                 cnow = info->icount;
3056                 set_current_state(TASK_INTERRUPTIBLE);
3057                 spin_unlock_irqrestore(&info->lock,flags);
3058
3059                 /* if no change, wait aborted for some reason */
3060                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3061                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3062                         rc = -EIO;
3063                         break;
3064                 }
3065
3066                 /* check for change in caller specified modem input */
3067                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3068                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3069                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3070                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3071                         rc = 0;
3072                         break;
3073                 }
3074
3075                 cprev = cnow;
3076         }
3077         remove_wait_queue(&info->status_event_wait_q, &wait);
3078         set_current_state(TASK_RUNNING);
3079         return rc;
3080 }
3081
3082 /*
3083  *  return state of serial control and status signals
3084  */
3085 static int tiocmget(struct tty_struct *tty, struct file *file)
3086 {
3087         struct slgt_info *info = tty->driver_data;
3088         unsigned int result;
3089         unsigned long flags;
3090
3091         spin_lock_irqsave(&info->lock,flags);
3092         get_signals(info);
3093         spin_unlock_irqrestore(&info->lock,flags);
3094
3095         result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3096                 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3097                 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3098                 ((info->signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3099                 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3100                 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3101
3102         DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3103         return result;
3104 }
3105
3106 /*
3107  * set modem control signals (DTR/RTS)
3108  *
3109  *      cmd     signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3110  *              TIOCMSET = set/clear signal values
3111  *      value   bit mask for command
3112  */
3113 static int tiocmset(struct tty_struct *tty, struct file *file,
3114                     unsigned int set, unsigned int clear)
3115 {
3116         struct slgt_info *info = tty->driver_data;
3117         unsigned long flags;
3118
3119         DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3120
3121         if (set & TIOCM_RTS)
3122                 info->signals |= SerialSignal_RTS;
3123         if (set & TIOCM_DTR)
3124                 info->signals |= SerialSignal_DTR;
3125         if (clear & TIOCM_RTS)
3126                 info->signals &= ~SerialSignal_RTS;
3127         if (clear & TIOCM_DTR)
3128                 info->signals &= ~SerialSignal_DTR;
3129
3130         spin_lock_irqsave(&info->lock,flags);
3131         set_signals(info);
3132         spin_unlock_irqrestore(&info->lock,flags);
3133         return 0;
3134 }
3135
3136 static int carrier_raised(struct tty_port *port)
3137 {
3138         unsigned long flags;
3139         struct slgt_info *info = container_of(port, struct slgt_info, port);
3140
3141         spin_lock_irqsave(&info->lock,flags);
3142         get_signals(info);
3143         spin_unlock_irqrestore(&info->lock,flags);
3144         return (info->signals & SerialSignal_DCD) ? 1 : 0;
3145 }
3146
3147 static void dtr_rts(struct tty_port *port, int on)
3148 {
3149         unsigned long flags;
3150         struct slgt_info *info = container_of(port, struct slgt_info, port);
3151
3152         spin_lock_irqsave(&info->lock,flags);
3153         if (on)
3154                 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3155         else
3156                 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3157         set_signals(info);
3158         spin_unlock_irqrestore(&info->lock,flags);
3159 }
3160
3161
3162 /*
3163  *  block current process until the device is ready to open
3164  */
3165 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3166                            struct slgt_info *info)
3167 {
3168         DECLARE_WAITQUEUE(wait, current);
3169         int             retval;
3170         bool            do_clocal = false;
3171         bool            extra_count = false;
3172         unsigned long   flags;
3173         int             cd;
3174         struct tty_port *port = &info->port;
3175
3176         DBGINFO(("%s block_til_ready\n", tty->driver->name));
3177
3178         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3179                 /* nonblock mode is set or port is not enabled */
3180                 port->flags |= ASYNC_NORMAL_ACTIVE;
3181                 return 0;
3182         }
3183
3184         if (tty->termios->c_cflag & CLOCAL)
3185                 do_clocal = true;
3186
3187         /* Wait for carrier detect and the line to become
3188          * free (i.e., not in use by the callout).  While we are in
3189          * this loop, port->count is dropped by one, so that
3190          * close() knows when to free things.  We restore it upon
3191          * exit, either normal or abnormal.
3192          */
3193
3194         retval = 0;
3195         add_wait_queue(&port->open_wait, &wait);
3196
3197         spin_lock_irqsave(&info->lock, flags);
3198         if (!tty_hung_up_p(filp)) {
3199                 extra_count = true;
3200                 port->count--;
3201         }
3202         spin_unlock_irqrestore(&info->lock, flags);
3203         port->blocked_open++;
3204
3205         while (1) {
3206                 if ((tty->termios->c_cflag & CBAUD))
3207                         tty_port_raise_dtr_rts(port);
3208
3209                 set_current_state(TASK_INTERRUPTIBLE);
3210
3211                 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3212                         retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3213                                         -EAGAIN : -ERESTARTSYS;
3214                         break;
3215                 }
3216
3217                 cd = tty_port_carrier_raised(port);
3218
3219                 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3220                         break;
3221
3222                 if (signal_pending(current)) {
3223                         retval = -ERESTARTSYS;
3224                         break;
3225                 }
3226
3227                 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3228                 schedule();
3229         }
3230
3231         set_current_state(TASK_RUNNING);
3232         remove_wait_queue(&port->open_wait, &wait);
3233
3234         if (extra_count)
3235                 port->count++;
3236         port->blocked_open--;
3237
3238         if (!retval)
3239                 port->flags |= ASYNC_NORMAL_ACTIVE;
3240
3241         DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3242         return retval;
3243 }
3244
3245 static int alloc_tmp_rbuf(struct slgt_info *info)
3246 {
3247         info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3248         if (info->tmp_rbuf == NULL)
3249                 return -ENOMEM;
3250         return 0;
3251 }
3252
3253 static void free_tmp_rbuf(struct slgt_info *info)
3254 {
3255         kfree(info->tmp_rbuf);
3256         info->tmp_rbuf = NULL;
3257 }
3258
3259 /*
3260  * allocate DMA descriptor lists.
3261  */
3262 static int alloc_desc(struct slgt_info *info)
3263 {
3264         unsigned int i;
3265         unsigned int pbufs;
3266
3267         /* allocate memory to hold descriptor lists */
3268         info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3269         if (info->bufs == NULL)
3270                 return -ENOMEM;
3271
3272         memset(info->bufs, 0, DESC_LIST_SIZE);
3273
3274         info->rbufs = (struct slgt_desc*)info->bufs;
3275         info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3276
3277         pbufs = (unsigned int)info->bufs_dma_addr;
3278
3279         /*
3280          * Build circular lists of descriptors
3281          */
3282
3283         for (i=0; i < info->rbuf_count; i++) {
3284                 /* physical address of this descriptor */
3285                 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3286
3287                 /* physical address of next descriptor */
3288                 if (i == info->rbuf_count - 1)
3289                         info->rbufs[i].next = cpu_to_le32(pbufs);
3290                 else
3291                         info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3292                 set_desc_count(info->rbufs[i], DMABUFSIZE);
3293         }
3294
3295         for (i=0; i < info->tbuf_count; i++) {
3296                 /* physical address of this descriptor */
3297                 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3298
3299                 /* physical address of next descriptor */
3300                 if (i == info->tbuf_count - 1)
3301                         info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3302                 else
3303                         info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3304         }
3305
3306         return 0;
3307 }
3308
3309 static void free_desc(struct slgt_info *info)
3310 {
3311         if (info->bufs != NULL) {
3312                 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3313                 info->bufs  = NULL;
3314                 info->rbufs = NULL;
3315                 info->tbufs = NULL;
3316         }
3317 }
3318
3319 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3320 {
3321         int i;
3322         for (i=0; i < count; i++) {
3323                 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3324                         return -ENOMEM;
3325                 bufs[i].pbuf  = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3326         }
3327         return 0;
3328 }
3329
3330 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3331 {
3332         int i;
3333         for (i=0; i < count; i++) {
3334                 if (bufs[i].buf == NULL)
3335                         continue;
3336                 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3337                 bufs[i].buf = NULL;
3338         }
3339 }
3340
3341 static int alloc_dma_bufs(struct slgt_info *info)
3342 {
3343         info->rbuf_count = 32;
3344         info->tbuf_count = 32;
3345
3346         if (alloc_desc(info) < 0 ||
3347             alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3348             alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3349             alloc_tmp_rbuf(info) < 0) {
3350                 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3351                 return -ENOMEM;
3352         }
3353         reset_rbufs(info);
3354         return 0;
3355 }
3356
3357 static void free_dma_bufs(struct slgt_info *info)
3358 {
3359         if (info->bufs) {
3360                 free_bufs(info, info->rbufs, info->rbuf_count);
3361                 free_bufs(info, info->tbufs, info->tbuf_count);
3362                 free_desc(info);
3363         }
3364         free_tmp_rbuf(info);
3365 }
3366
3367 static int claim_resources(struct slgt_info *info)
3368 {
3369         if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3370                 DBGERR(("%s reg addr conflict, addr=%08X\n",
3371                         info->device_name, info->phys_reg_addr));
3372                 info->init_error = DiagStatus_AddressConflict;
3373                 goto errout;
3374         }
3375         else
3376                 info->reg_addr_requested = true;
3377
3378         info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3379         if (!info->reg_addr) {
3380                 DBGERR(("%s cant map device registers, addr=%08X\n",
3381                         info->device_name, info->phys_reg_addr));
3382                 info->init_error = DiagStatus_CantAssignPciResources;
3383                 goto errout;
3384         }
3385         return 0;
3386
3387 errout:
3388         release_resources(info);
3389         return -ENODEV;
3390 }
3391
3392 static void release_resources(struct slgt_info *info)
3393 {
3394         if (info->irq_requested) {
3395                 free_irq(info->irq_level, info);
3396                 info->irq_requested = false;
3397         }
3398
3399         if (info->reg_addr_requested) {
3400                 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3401                 info->reg_addr_requested = false;
3402         }
3403
3404         if (info->reg_addr) {
3405                 iounmap(info->reg_addr);
3406                 info->reg_addr = NULL;
3407         }
3408 }
3409
3410 /* Add the specified device instance data structure to the
3411  * global linked list of devices and increment the device count.
3412  */
3413 static void add_device(struct slgt_info *info)
3414 {
3415         char *devstr;
3416
3417         info->next_device = NULL;
3418         info->line = slgt_device_count;
3419         sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3420
3421         if (info->line < MAX_DEVICES) {
3422                 if (maxframe[info->line])
3423                         info->max_frame_size = maxframe[info->line];
3424         }
3425
3426         slgt_device_count++;
3427
3428         if (!slgt_device_list)
3429                 slgt_device_list = info;
3430         else {
3431                 struct slgt_info *current_dev = slgt_device_list;
3432                 while(current_dev->next_device)
3433                         current_dev = current_dev->next_device;
3434                 current_dev->next_device = info;
3435         }
3436
3437         if (info->max_frame_size < 4096)
3438                 info->max_frame_size = 4096;
3439         else if (info->max_frame_size > 65535)
3440                 info->max_frame_size = 65535;
3441
3442         switch(info->pdev->device) {
3443         case SYNCLINK_GT_DEVICE_ID:
3444                 devstr = "GT";
3445                 break;
3446         case SYNCLINK_GT2_DEVICE_ID:
3447                 devstr = "GT2";
3448                 break;
3449         case SYNCLINK_GT4_DEVICE_ID:
3450                 devstr = "GT4";
3451                 break;
3452         case SYNCLINK_AC_DEVICE_ID:
3453                 devstr = "AC";
3454                 info->params.mode = MGSL_MODE_ASYNC;
3455                 break;
3456         default:
3457                 devstr = "(unknown model)";
3458         }
3459         printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3460                 devstr, info->device_name, info->phys_reg_addr,
3461                 info->irq_level, info->max_frame_size);
3462
3463 #if SYNCLINK_GENERIC_HDLC
3464         hdlcdev_init(info);
3465 #endif
3466 }
3467
3468 static const struct tty_port_operations slgt_port_ops = {
3469         .carrier_raised = carrier_raised,
3470         .dtr_rts = dtr_rts,
3471 };
3472
3473 /*
3474  *  allocate device instance structure, return NULL on failure
3475  */
3476 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3477 {
3478         struct slgt_info *info;
3479
3480         info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3481
3482         if (!info) {
3483                 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3484                         driver_name, adapter_num, port_num));
3485         } else {
3486                 tty_port_init(&info->port);
3487                 info->port.ops = &slgt_port_ops;
3488                 info->magic = MGSL_MAGIC;
3489                 INIT_WORK(&info->task, bh_handler);
3490                 info->max_frame_size = 4096;
3491                 info->base_clock = 14745600;
3492                 info->rbuf_fill_level = DMABUFSIZE;
3493                 info->port.close_delay = 5*HZ/10;
3494                 info->port.closing_wait = 30*HZ;
3495                 init_waitqueue_head(&info->status_event_wait_q);
3496                 init_waitqueue_head(&info->event_wait_q);
3497                 spin_lock_init(&info->netlock);
3498                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3499                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3500                 info->adapter_num = adapter_num;
3501                 info->port_num = port_num;
3502
3503                 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3504                 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3505
3506                 /* Copy configuration info to device instance data */
3507                 info->pdev = pdev;
3508                 info->irq_level = pdev->irq;
3509                 info->phys_reg_addr = pci_resource_start(pdev,0);
3510
3511                 info->bus_type = MGSL_BUS_TYPE_PCI;
3512                 info->irq_flags = IRQF_SHARED;
3513
3514                 info->init_error = -1; /* assume error, set to 0 on successful init */
3515         }
3516
3517         return info;
3518 }
3519
3520 static void device_init(int adapter_num, struct pci_dev *pdev)
3521 {
3522         struct slgt_info *port_array[SLGT_MAX_PORTS];
3523         int i;
3524         int port_count = 1;
3525
3526         if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3527                 port_count = 2;
3528         else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3529                 port_count = 4;
3530
3531         /* allocate device instances for all ports */
3532         for (i=0; i < port_count; ++i) {
3533                 port_array[i] = alloc_dev(adapter_num, i, pdev);
3534                 if (port_array[i] == NULL) {
3535                         for (--i; i >= 0; --i)
3536                                 kfree(port_array[i]);
3537                         return;
3538                 }
3539         }
3540
3541         /* give copy of port_array to all ports and add to device list  */
3542         for (i=0; i < port_count; ++i) {
3543                 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3544                 add_device(port_array[i]);
3545                 port_array[i]->port_count = port_count;
3546                 spin_lock_init(&port_array[i]->lock);
3547         }
3548
3549         /* Allocate and claim adapter resources */
3550         if (!claim_resources(port_array[0])) {
3551
3552                 alloc_dma_bufs(port_array[0]);
3553
3554                 /* copy resource information from first port to others */
3555                 for (i = 1; i < port_count; ++i) {
3556                         port_array[i]->lock      = port_array[0]->lock;
3557                         port_array[i]->irq_level = port_array[0]->irq_level;
3558                         port_array[i]->reg_addr  = port_array[0]->reg_addr;
3559                         alloc_dma_bufs(port_array[i]);
3560                 }
3561
3562                 if (request_irq(port_array[0]->irq_level,
3563                                         slgt_interrupt,
3564                                         port_array[0]->irq_flags,
3565                                         port_array[0]->device_name,
3566                                         port_array[0]) < 0) {
3567                         DBGERR(("%s request_irq failed IRQ=%d\n",
3568                                 port_array[0]->device_name,
3569                                 port_array[0]->irq_level));
3570                 } else {
3571                         port_array[0]->irq_requested = true;
3572                         adapter_test(port_array[0]);
3573                         for (i=1 ; i < port_count ; i++) {
3574                                 port_array[i]->init_error = port_array[0]->init_error;
3575                                 port_array[i]->gpio_present = port_array[0]->gpio_present;
3576                         }
3577                 }
3578         }
3579
3580         for (i=0; i < port_count; ++i)
3581                 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3582 }
3583
3584 static int __devinit init_one(struct pci_dev *dev,
3585                               const struct pci_device_id *ent)
3586 {
3587         if (pci_enable_device(dev)) {
3588                 printk("error enabling pci device %p\n", dev);
3589                 return -EIO;
3590         }
3591         pci_set_master(dev);
3592         device_init(slgt_device_count, dev);
3593         return 0;
3594 }
3595
3596 static void __devexit remove_one(struct pci_dev *dev)
3597 {
3598 }
3599
3600 static const struct tty_operations ops = {
3601         .open = open,
3602         .close = close,
3603         .write = write,
3604         .put_char = put_char,
3605         .flush_chars = flush_chars,
3606         .write_room = write_room,
3607         .chars_in_buffer = chars_in_buffer,
3608         .flush_buffer = flush_buffer,
3609         .ioctl = ioctl,
3610         .compat_ioctl = slgt_compat_ioctl,
3611         .throttle = throttle,
3612         .unthrottle = unthrottle,
3613         .send_xchar = send_xchar,
3614         .break_ctl = set_break,
3615         .wait_until_sent = wait_until_sent,
3616         .set_termios = set_termios,
3617         .stop = tx_hold,
3618         .start = tx_release,
3619         .hangup = hangup,
3620         .tiocmget = tiocmget,
3621         .tiocmset = tiocmset,
3622         .proc_fops = &synclink_gt_proc_fops,
3623 };
3624
3625 static void slgt_cleanup(void)
3626 {
3627         int rc;
3628         struct slgt_info *info;
3629         struct slgt_info *tmp;
3630
3631         printk(KERN_INFO "unload %s\n", driver_name);
3632
3633         if (serial_driver) {
3634                 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3635                         tty_unregister_device(serial_driver, info->line);
3636                 if ((rc = tty_unregister_driver(serial_driver)))
3637                         DBGERR(("tty_unregister_driver error=%d\n", rc));
3638                 put_tty_driver(serial_driver);
3639         }
3640
3641         /* reset devices */
3642         info = slgt_device_list;
3643         while(info) {
3644                 reset_port(info);
3645                 info = info->next_device;
3646         }
3647
3648         /* release devices */
3649         info = slgt_device_list;
3650         while(info) {
3651 #if SYNCLINK_GENERIC_HDLC
3652                 hdlcdev_exit(info);
3653 #endif
3654                 free_dma_bufs(info);
3655                 free_tmp_rbuf(info);
3656                 if (info->port_num == 0)
3657                         release_resources(info);
3658                 tmp = info;
3659                 info = info->next_device;
3660                 kfree(tmp);
3661         }
3662
3663         if (pci_registered)
3664                 pci_unregister_driver(&pci_driver);
3665 }
3666
3667 /*
3668  *  Driver initialization entry point.
3669  */
3670 static int __init slgt_init(void)
3671 {
3672         int rc;
3673
3674         printk(KERN_INFO "%s\n", driver_name);
3675
3676         serial_driver = alloc_tty_driver(MAX_DEVICES);
3677         if (!serial_driver) {
3678                 printk("%s can't allocate tty driver\n", driver_name);
3679                 return -ENOMEM;
3680         }
3681
3682         /* Initialize the tty_driver structure */
3683
3684         serial_driver->owner = THIS_MODULE;
3685         serial_driver->driver_name = tty_driver_name;
3686         serial_driver->name = tty_dev_prefix;
3687         serial_driver->major = ttymajor;
3688         serial_driver->minor_start = 64;
3689         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3690         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3691         serial_driver->init_termios = tty_std_termios;
3692         serial_driver->init_termios.c_cflag =
3693                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3694         serial_driver->init_termios.c_ispeed = 9600;
3695         serial_driver->init_termios.c_ospeed = 9600;
3696         serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3697         tty_set_operations(serial_driver, &ops);
3698         if ((rc = tty_register_driver(serial_driver)) < 0) {
3699                 DBGERR(("%s can't register serial driver\n", driver_name));
3700                 put_tty_driver(serial_driver);
3701                 serial_driver = NULL;
3702                 goto error;
3703         }
3704
3705         printk(KERN_INFO "%s, tty major#%d\n",
3706                driver_name, serial_driver->major);
3707
3708         slgt_device_count = 0;
3709         if ((rc = pci_register_driver(&pci_driver)) < 0) {
3710                 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3711                 goto error;
3712         }
3713         pci_registered = true;
3714
3715         if (!slgt_device_list)
3716                 printk("%s no devices found\n",driver_name);
3717
3718         return 0;
3719
3720 error:
3721         slgt_cleanup();
3722         return rc;
3723 }
3724
3725 static void __exit slgt_exit(void)
3726 {
3727         slgt_cleanup();
3728 }
3729
3730 module_init(slgt_init);
3731 module_exit(slgt_exit);
3732
3733 /*
3734  * register access routines
3735  */
3736
3737 #define CALC_REGADDR() \
3738         unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3739         if (addr >= 0x80) \
3740                 reg_addr += (info->port_num) * 32;
3741
3742 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3743 {
3744         CALC_REGADDR();
3745         return readb((void __iomem *)reg_addr);
3746 }
3747
3748 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3749 {
3750         CALC_REGADDR();
3751         writeb(value, (void __iomem *)reg_addr);
3752 }
3753
3754 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3755 {
3756         CALC_REGADDR();
3757         return readw((void __iomem *)reg_addr);
3758 }
3759
3760 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3761 {
3762         CALC_REGADDR();
3763         writew(value, (void __iomem *)reg_addr);
3764 }
3765
3766 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3767 {
3768         CALC_REGADDR();
3769         return readl((void __iomem *)reg_addr);
3770 }
3771
3772 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3773 {
3774         CALC_REGADDR();
3775         writel(value, (void __iomem *)reg_addr);
3776 }
3777
3778 static void rdma_reset(struct slgt_info *info)
3779 {
3780         unsigned int i;
3781
3782         /* set reset bit */
3783         wr_reg32(info, RDCSR, BIT1);
3784
3785         /* wait for enable bit cleared */
3786         for(i=0 ; i < 1000 ; i++)
3787                 if (!(rd_reg32(info, RDCSR) & BIT0))
3788                         break;
3789 }
3790
3791 static void tdma_reset(struct slgt_info *info)
3792 {
3793         unsigned int i;
3794
3795         /* set reset bit */
3796         wr_reg32(info, TDCSR, BIT1);
3797
3798         /* wait for enable bit cleared */
3799         for(i=0 ; i < 1000 ; i++)
3800                 if (!(rd_reg32(info, TDCSR) & BIT0))
3801                         break;
3802 }
3803
3804 /*
3805  * enable internal loopback
3806  * TxCLK and RxCLK are generated from BRG
3807  * and TxD is looped back to RxD internally.
3808  */
3809 static void enable_loopback(struct slgt_info *info)
3810 {
3811         /* SCR (serial control) BIT2=looopback enable */
3812         wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3813
3814         if (info->params.mode != MGSL_MODE_ASYNC) {
3815                 /* CCR (clock control)
3816                  * 07..05  tx clock source (010 = BRG)
3817                  * 04..02  rx clock source (010 = BRG)
3818                  * 01      auxclk enable   (0 = disable)
3819                  * 00      BRG enable      (1 = enable)
3820                  *
3821                  * 0100 1001
3822                  */
3823                 wr_reg8(info, CCR, 0x49);
3824
3825                 /* set speed if available, otherwise use default */
3826                 if (info->params.clock_speed)
3827                         set_rate(info, info->params.clock_speed);
3828                 else
3829                         set_rate(info, 3686400);
3830         }
3831 }
3832
3833 /*
3834  *  set baud rate generator to specified rate
3835  */
3836 static void set_rate(struct slgt_info *info, u32 rate)
3837 {
3838         unsigned int div;
3839         unsigned int osc = info->base_clock;
3840
3841         /* div = osc/rate - 1
3842          *
3843          * Round div up if osc/rate is not integer to
3844          * force to next slowest rate.
3845          */
3846
3847         if (rate) {
3848                 div = osc/rate;
3849                 if (!(osc % rate) && div)
3850                         div--;
3851                 wr_reg16(info, BDR, (unsigned short)div);
3852         }
3853 }
3854
3855 static void rx_stop(struct slgt_info *info)
3856 {
3857         unsigned short val;
3858
3859         /* disable and reset receiver */
3860         val = rd_reg16(info, RCR) & ~BIT1;          /* clear enable bit */
3861         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3862         wr_reg16(info, RCR, val);                  /* clear reset bit */
3863
3864         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3865
3866         /* clear pending rx interrupts */
3867         wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3868
3869         rdma_reset(info);
3870
3871         info->rx_enabled = false;
3872         info->rx_restart = false;
3873 }
3874
3875 static void rx_start(struct slgt_info *info)
3876 {
3877         unsigned short val;
3878
3879         slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3880
3881         /* clear pending rx overrun IRQ */
3882         wr_reg16(info, SSR, IRQ_RXOVER);
3883
3884         /* reset and disable receiver */
3885         val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3886         wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3887         wr_reg16(info, RCR, val);                  /* clear reset bit */
3888
3889         rdma_reset(info);
3890         reset_rbufs(info);
3891
3892         if (info->rx_pio) {
3893                 /* rx request when rx FIFO not empty */
3894                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3895                 slgt_irq_on(info, IRQ_RXDATA);
3896                 if (info->params.mode == MGSL_MODE_ASYNC) {
3897                         /* enable saving of rx status */
3898                         wr_reg32(info, RDCSR, BIT6);
3899                 }
3900         } else {
3901                 /* rx request when rx FIFO half full */
3902                 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3903                 /* set 1st descriptor address */
3904                 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3905
3906                 if (info->params.mode != MGSL_MODE_ASYNC) {
3907                         /* enable rx DMA and DMA interrupt */
3908                         wr_reg32(info, RDCSR, (BIT2 + BIT0));
3909                 } else {
3910                         /* enable saving of rx status, rx DMA and DMA interrupt */
3911                         wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3912                 }
3913         }
3914
3915         slgt_irq_on(info, IRQ_RXOVER);
3916
3917         /* enable receiver */
3918         wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3919
3920         info->rx_restart = false;
3921         info->rx_enabled = true;
3922 }
3923
3924 static void tx_start(struct slgt_info *info)
3925 {
3926         if (!info->tx_enabled) {
3927                 wr_reg16(info, TCR,
3928                          (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3929                 info->tx_enabled = true;
3930         }
3931
3932         if (info->tx_count) {
3933                 info->drop_rts_on_tx_done = false;
3934
3935                 if (info->params.mode != MGSL_MODE_ASYNC) {
3936                         if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3937                                 get_signals(info);
3938                                 if (!(info->signals & SerialSignal_RTS)) {
3939                                         info->signals |= SerialSignal_RTS;
3940                                         set_signals(info);
3941                                         info->drop_rts_on_tx_done = true;
3942                                 }
3943                         }
3944
3945                         slgt_irq_off(info, IRQ_TXDATA);
3946                         slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3947                         /* clear tx idle and underrun status bits */
3948                         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3949                         if (info->params.mode == MGSL_MODE_HDLC)
3950                                 mod_timer(&info->tx_timer, jiffies +
3951                                                 msecs_to_jiffies(5000));
3952                 } else {
3953                         slgt_irq_off(info, IRQ_TXDATA);
3954                         slgt_irq_on(info, IRQ_TXIDLE);
3955                         /* clear tx idle status bit */
3956                         wr_reg16(info, SSR, IRQ_TXIDLE);
3957                 }
3958                 tdma_start(info);
3959                 info->tx_active = true;
3960         }
3961 }
3962
3963 /*
3964  * start transmit DMA if inactive and there are unsent buffers
3965  */
3966 static void tdma_start(struct slgt_info *info)
3967 {
3968         unsigned int i;
3969
3970         if (rd_reg32(info, TDCSR) & BIT0)
3971                 return;
3972
3973         /* transmit DMA inactive, check for unsent buffers */
3974         i = info->tbuf_start;
3975         while (!desc_count(info->tbufs[i])) {
3976                 if (++i == info->tbuf_count)
3977                         i = 0;
3978                 if (i == info->tbuf_current)
3979                         return;
3980         }
3981         info->tbuf_start = i;
3982
3983         /* there are unsent buffers, start transmit DMA */
3984
3985         /* reset needed if previous error condition */
3986         tdma_reset(info);
3987
3988         /* set 1st descriptor address */
3989         wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3990         wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3991 }
3992
3993 static void tx_stop(struct slgt_info *info)
3994 {
3995         unsigned short val;
3996
3997         del_timer(&info->tx_timer);
3998
3999         tdma_reset(info);
4000
4001         /* reset and disable transmitter */
4002         val = rd_reg16(info, TCR) & ~BIT1;          /* clear enable bit */
4003         wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4004
4005         slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4006
4007         /* clear tx idle and underrun status bit */
4008         wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4009
4010         reset_tbufs(info);
4011
4012         info->tx_enabled = false;
4013         info->tx_active = false;
4014 }
4015
4016 static void reset_port(struct slgt_info *info)
4017 {
4018         if (!info->reg_addr)
4019                 return;
4020
4021         tx_stop(info);
4022         rx_stop(info);
4023
4024         info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4025         set_signals(info);
4026
4027         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4028 }
4029
4030 static void reset_adapter(struct slgt_info *info)
4031 {
4032         int i;
4033         for (i=0; i < info->port_count; ++i) {
4034                 if (info->port_array[i])
4035                         reset_port(info->port_array[i]);
4036         }
4037 }
4038
4039 static void async_mode(struct slgt_info *info)
4040 {
4041         unsigned short val;
4042
4043         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4044         tx_stop(info);
4045         rx_stop(info);
4046
4047         /* TCR (tx control)
4048          *
4049          * 15..13  mode, 010=async
4050          * 12..10  encoding, 000=NRZ
4051          * 09      parity enable
4052          * 08      1=odd parity, 0=even parity
4053          * 07      1=RTS driver control
4054          * 06      1=break enable
4055          * 05..04  character length
4056          *         00=5 bits
4057          *         01=6 bits
4058          *         10=7 bits
4059          *         11=8 bits
4060          * 03      0=1 stop bit, 1=2 stop bits
4061          * 02      reset
4062          * 01      enable
4063          * 00      auto-CTS enable
4064          */
4065         val = 0x4000;
4066
4067         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4068                 val |= BIT7;
4069
4070         if (info->params.parity != ASYNC_PARITY_NONE) {
4071                 val |= BIT9;
4072                 if (info->params.parity == ASYNC_PARITY_ODD)
4073                         val |= BIT8;
4074         }
4075
4076         switch (info->params.data_bits)
4077         {
4078         case 6: val |= BIT4; break;
4079         case 7: val |= BIT5; break;
4080         case 8: val |= BIT5 + BIT4; break;
4081         }
4082
4083         if (info->params.stop_bits != 1)
4084                 val |= BIT3;
4085
4086         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4087                 val |= BIT0;
4088
4089         wr_reg16(info, TCR, val);
4090
4091         /* RCR (rx control)
4092          *
4093          * 15..13  mode, 010=async
4094          * 12..10  encoding, 000=NRZ
4095          * 09      parity enable
4096          * 08      1=odd parity, 0=even parity
4097          * 07..06  reserved, must be 0
4098          * 05..04  character length
4099          *         00=5 bits
4100          *         01=6 bits
4101          *         10=7 bits
4102          *         11=8 bits
4103          * 03      reserved, must be zero
4104          * 02      reset
4105          * 01      enable
4106          * 00      auto-DCD enable
4107          */
4108         val = 0x4000;
4109
4110         if (info->params.parity != ASYNC_PARITY_NONE) {
4111                 val |= BIT9;
4112                 if (info->params.parity == ASYNC_PARITY_ODD)
4113                         val |= BIT8;
4114         }
4115
4116         switch (info->params.data_bits)
4117         {
4118         case 6: val |= BIT4; break;
4119         case 7: val |= BIT5; break;
4120         case 8: val |= BIT5 + BIT4; break;
4121         }
4122
4123         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4124                 val |= BIT0;
4125
4126         wr_reg16(info, RCR, val);
4127
4128         /* CCR (clock control)
4129          *
4130          * 07..05  011 = tx clock source is BRG/16
4131          * 04..02  010 = rx clock source is BRG
4132          * 01      0 = auxclk disabled
4133          * 00      1 = BRG enabled
4134          *
4135          * 0110 1001
4136          */
4137         wr_reg8(info, CCR, 0x69);
4138
4139         msc_set_vcr(info);
4140
4141         /* SCR (serial control)
4142          *
4143          * 15  1=tx req on FIFO half empty
4144          * 14  1=rx req on FIFO half full
4145          * 13  tx data  IRQ enable
4146          * 12  tx idle  IRQ enable
4147          * 11  rx break on IRQ enable
4148          * 10  rx data  IRQ enable
4149          * 09  rx break off IRQ enable
4150          * 08  overrun  IRQ enable
4151          * 07  DSR      IRQ enable
4152          * 06  CTS      IRQ enable
4153          * 05  DCD      IRQ enable
4154          * 04  RI       IRQ enable
4155          * 03  0=16x sampling, 1=8x sampling
4156          * 02  1=txd->rxd internal loopback enable
4157          * 01  reserved, must be zero
4158          * 00  1=master IRQ enable
4159          */
4160         val = BIT15 + BIT14 + BIT0;
4161         /* JCR[8] : 1 = x8 async mode feature available */
4162         if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4163             ((info->base_clock < (info->params.data_rate * 16)) ||
4164              (info->base_clock % (info->params.data_rate * 16)))) {
4165                 /* use 8x sampling */
4166                 val |= BIT3;
4167                 set_rate(info, info->params.data_rate * 8);
4168         } else {
4169                 /* use 16x sampling */
4170                 set_rate(info, info->params.data_rate * 16);
4171         }
4172         wr_reg16(info, SCR, val);
4173
4174         slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4175
4176         if (info->params.loopback)
4177                 enable_loopback(info);
4178 }
4179
4180 static void sync_mode(struct slgt_info *info)
4181 {
4182         unsigned short val;
4183
4184         slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4185         tx_stop(info);
4186         rx_stop(info);
4187
4188         /* TCR (tx control)
4189          *
4190          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4191          * 12..10  encoding
4192          * 09      CRC enable
4193          * 08      CRC32
4194          * 07      1=RTS driver control
4195          * 06      preamble enable
4196          * 05..04  preamble length
4197          * 03      share open/close flag
4198          * 02      reset
4199          * 01      enable
4200          * 00      auto-CTS enable
4201          */
4202         val = BIT2;
4203
4204         switch(info->params.mode) {
4205         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4206         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4207         case MGSL_MODE_RAW:      val |= BIT13; break;
4208         }
4209         if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4210                 val |= BIT7;
4211
4212         switch(info->params.encoding)
4213         {
4214         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4215         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4216         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4217         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4218         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4219         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4220         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4221         }
4222
4223         switch (info->params.crc_type & HDLC_CRC_MASK)
4224         {
4225         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4226         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4227         }
4228
4229         if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4230                 val |= BIT6;
4231
4232         switch (info->params.preamble_length)
4233         {
4234         case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4235         case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4236         case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4237         }
4238
4239         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4240                 val |= BIT0;
4241
4242         wr_reg16(info, TCR, val);
4243
4244         /* TPR (transmit preamble) */
4245
4246         switch (info->params.preamble)
4247         {
4248         case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4249         case HDLC_PREAMBLE_PATTERN_ONES:  val = 0xff; break;
4250         case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4251         case HDLC_PREAMBLE_PATTERN_10:    val = 0x55; break;
4252         case HDLC_PREAMBLE_PATTERN_01:    val = 0xaa; break;
4253         default:                          val = 0x7e; break;
4254         }
4255         wr_reg8(info, TPR, (unsigned char)val);
4256
4257         /* RCR (rx control)
4258          *
4259          * 15..13  mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4260          * 12..10  encoding
4261          * 09      CRC enable
4262          * 08      CRC32
4263          * 07..03  reserved, must be 0
4264          * 02      reset
4265          * 01      enable
4266          * 00      auto-DCD enable
4267          */
4268         val = 0;
4269
4270         switch(info->params.mode) {
4271         case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4272         case MGSL_MODE_BISYNC:   val |= BIT15; break;
4273         case MGSL_MODE_RAW:      val |= BIT13; break;
4274         }
4275
4276         switch(info->params.encoding)
4277         {
4278         case HDLC_ENCODING_NRZB:          val |= BIT10; break;
4279         case HDLC_ENCODING_NRZI_MARK:     val |= BIT11; break;
4280         case HDLC_ENCODING_NRZI:          val |= BIT11 + BIT10; break;
4281         case HDLC_ENCODING_BIPHASE_MARK:  val |= BIT12; break;
4282         case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4283         case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4284         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4285         }
4286
4287         switch (info->params.crc_type & HDLC_CRC_MASK)
4288         {
4289         case HDLC_CRC_16_CCITT: val |= BIT9; break;
4290         case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4291         }
4292
4293         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4294                 val |= BIT0;
4295
4296         wr_reg16(info, RCR, val);
4297
4298         /* CCR (clock control)
4299          *
4300          * 07..05  tx clock source
4301          * 04..02  rx clock source
4302          * 01      auxclk enable
4303          * 00      BRG enable
4304          */
4305         val = 0;
4306
4307         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4308         {
4309                 // when RxC source is DPLL, BRG generates 16X DPLL
4310                 // reference clock, so take TxC from BRG/16 to get
4311                 // transmit clock at actual data rate
4312                 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4313                         val |= BIT6 + BIT5;     /* 011, txclk = BRG/16 */
4314                 else
4315                         val |= BIT6;    /* 010, txclk = BRG */
4316         }
4317         else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4318                 val |= BIT7;    /* 100, txclk = DPLL Input */
4319         else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4320                 val |= BIT5;    /* 001, txclk = RXC Input */
4321
4322         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4323                 val |= BIT3;    /* 010, rxclk = BRG */
4324         else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4325                 val |= BIT4;    /* 100, rxclk = DPLL */
4326         else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4327                 val |= BIT2;    /* 001, rxclk = TXC Input */
4328
4329         if (info->params.clock_speed)
4330                 val |= BIT1 + BIT0;
4331
4332         wr_reg8(info, CCR, (unsigned char)val);
4333
4334         if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4335         {
4336                 // program DPLL mode
4337                 switch(info->params.encoding)
4338                 {
4339                 case HDLC_ENCODING_BIPHASE_MARK:
4340                 case HDLC_ENCODING_BIPHASE_SPACE:
4341                         val = BIT7; break;
4342                 case HDLC_ENCODING_BIPHASE_LEVEL:
4343                 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4344                         val = BIT7 + BIT6; break;
4345                 default: val = BIT6;    // NRZ encodings
4346                 }
4347                 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4348
4349                 // DPLL requires a 16X reference clock from BRG
4350                 set_rate(info, info->params.clock_speed * 16);
4351         }
4352         else
4353                 set_rate(info, info->params.clock_speed);
4354
4355         tx_set_idle(info);
4356
4357         msc_set_vcr(info);
4358
4359         /* SCR (serial control)
4360          *
4361          * 15  1=tx req on FIFO half empty
4362          * 14  1=rx req on FIFO half full
4363          * 13  tx data  IRQ enable
4364          * 12  tx idle  IRQ enable
4365          * 11  underrun IRQ enable
4366          * 10  rx data  IRQ enable
4367          * 09  rx idle  IRQ enable
4368          * 08  overrun  IRQ enable
4369          * 07  DSR      IRQ enable
4370          * 06  CTS      IRQ enable
4371          * 05  DCD      IRQ enable
4372          * 04  RI       IRQ enable
4373          * 03  reserved, must be zero
4374          * 02  1=txd->rxd internal loopback enable
4375          * 01  reserved, must be zero
4376          * 00  1=master IRQ enable
4377          */
4378         wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4379
4380         if (info->params.loopback)
4381                 enable_loopback(info);
4382 }
4383
4384 /*
4385  *  set transmit idle mode
4386  */
4387 static void tx_set_idle(struct slgt_info *info)
4388 {
4389         unsigned char val;
4390         unsigned short tcr;
4391
4392         /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4393          * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4394          */
4395         tcr = rd_reg16(info, TCR);
4396         if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4397                 /* disable preamble, set idle size to 16 bits */
4398                 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4399                 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4400                 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4401         } else if (!(tcr & BIT6)) {
4402                 /* preamble is disabled, set idle size to 8 bits */
4403                 tcr &= ~(BIT5 + BIT4);
4404         }
4405         wr_reg16(info, TCR, tcr);
4406
4407         if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4408                 /* LSB of custom tx idle specified in tx idle register */
4409                 val = (unsigned char)(info->idle_mode & 0xff);
4410         } else {
4411                 /* standard 8 bit idle patterns */
4412                 switch(info->idle_mode)
4413                 {
4414                 case HDLC_TXIDLE_FLAGS:          val = 0x7e; break;
4415                 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4416                 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4417                 case HDLC_TXIDLE_ZEROS:
4418                 case HDLC_TXIDLE_SPACE:          val = 0x00; break;
4419                 default:                         val = 0xff;
4420                 }
4421         }
4422
4423         wr_reg8(info, TIR, val);
4424 }
4425
4426 /*
4427  * get state of V24 status (input) signals
4428  */
4429 static void get_signals(struct slgt_info *info)
4430 {
4431         unsigned short status = rd_reg16(info, SSR);
4432
4433         /* clear all serial signals except DTR and RTS */
4434         info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4435
4436         if (status & BIT3)
4437                 info->signals |= SerialSignal_DSR;
4438         if (status & BIT2)
4439                 info->signals |= SerialSignal_CTS;
4440         if (status & BIT1)
4441                 info->signals |= SerialSignal_DCD;
4442         if (status & BIT0)
4443                 info->signals |= SerialSignal_RI;
4444 }
4445
4446 /*
4447  * set V.24 Control Register based on current configuration
4448  */
4449 static void msc_set_vcr(struct slgt_info *info)
4450 {
4451         unsigned char val = 0;
4452
4453         /* VCR (V.24 control)
4454          *
4455          * 07..04  serial IF select
4456          * 03      DTR
4457          * 02      RTS
4458          * 01      LL
4459          * 00      RL
4460          */
4461
4462         switch(info->if_mode & MGSL_INTERFACE_MASK)
4463         {
4464         case MGSL_INTERFACE_RS232:
4465                 val |= BIT5; /* 0010 */
4466                 break;
4467         case MGSL_INTERFACE_V35:
4468                 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4469                 break;
4470         case MGSL_INTERFACE_RS422:
4471                 val |= BIT6; /* 0100 */
4472                 break;
4473         }
4474
4475         if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4476                 val |= BIT4;
4477         if (info->signals & SerialSignal_DTR)
4478                 val |= BIT3;
4479         if (info->signals & SerialSignal_RTS)
4480                 val |= BIT2;
4481         if (info->if_mode & MGSL_INTERFACE_LL)
4482                 val |= BIT1;
4483         if (info->if_mode & MGSL_INTERFACE_RL)
4484                 val |= BIT0;
4485         wr_reg8(info, VCR, val);
4486 }
4487
4488 /*
4489  * set state of V24 control (output) signals
4490  */
4491 static void set_signals(struct slgt_info *info)
4492 {
4493         unsigned char val = rd_reg8(info, VCR);
4494         if (info->signals & SerialSignal_DTR)
4495                 val |= BIT3;
4496         else
4497                 val &= ~BIT3;
4498         if (info->signals & SerialSignal_RTS)
4499                 val |= BIT2;
4500         else
4501                 val &= ~BIT2;
4502         wr_reg8(info, VCR, val);
4503 }
4504
4505 /*
4506  * free range of receive DMA buffers (i to last)
4507  */
4508 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4509 {
4510         int done = 0;
4511
4512         while(!done) {
4513                 /* reset current buffer for reuse */
4514                 info->rbufs[i].status = 0;
4515                 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4516                 if (i == last)
4517                         done = 1;
4518                 if (++i == info->rbuf_count)
4519                         i = 0;
4520         }
4521         info->rbuf_current = i;
4522 }
4523
4524 /*
4525  * mark all receive DMA buffers as free
4526  */
4527 static void reset_rbufs(struct slgt_info *info)
4528 {
4529         free_rbufs(info, 0, info->rbuf_count - 1);
4530         info->rbuf_fill_index = 0;
4531         info->rbuf_fill_count = 0;
4532 }
4533
4534 /*
4535  * pass receive HDLC frame to upper layer
4536  *
4537  * return true if frame available, otherwise false
4538  */
4539 static bool rx_get_frame(struct slgt_info *info)
4540 {
4541         unsigned int start, end;
4542         unsigned short status;
4543         unsigned int framesize = 0;
4544         unsigned long flags;
4545         struct tty_struct *tty = info->port.tty;
4546         unsigned char addr_field = 0xff;
4547         unsigned int crc_size = 0;
4548
4549         switch (info->params.crc_type & HDLC_CRC_MASK) {
4550         case HDLC_CRC_16_CCITT: crc_size = 2; break;
4551         case HDLC_CRC_32_CCITT: crc_size = 4; break;
4552         }
4553
4554 check_again:
4555
4556         framesize = 0;
4557         addr_field = 0xff;
4558         start = end = info->rbuf_current;
4559
4560         for (;;) {
4561                 if (!desc_complete(info->rbufs[end]))
4562                         goto cleanup;
4563
4564                 if (framesize == 0 && info->params.addr_filter != 0xff)
4565                         addr_field = info->rbufs[end].buf[0];
4566
4567                 framesize += desc_count(info->rbufs[end]);
4568
4569                 if (desc_eof(info->rbufs[end]))
4570                         break;
4571
4572                 if (++end == info->rbuf_count)
4573                         end = 0;
4574
4575                 if (end == info->rbuf_current) {
4576                         if (info->rx_enabled){
4577                                 spin_lock_irqsave(&info->lock,flags);
4578                                 rx_start(info);
4579                                 spin_unlock_irqrestore(&info->lock,flags);
4580                         }
4581                         goto cleanup;
4582                 }
4583         }
4584
4585         /* status
4586          *
4587          * 15      buffer complete
4588          * 14..06  reserved
4589          * 05..04  residue
4590          * 02      eof (end of frame)
4591          * 01      CRC error
4592          * 00      abort
4593          */
4594         status = desc_status(info->rbufs[end]);
4595
4596         /* ignore CRC bit if not using CRC (bit is undefined) */
4597         if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4598                 status &= ~BIT1;
4599
4600         if (framesize == 0 ||
4601                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4602                 free_rbufs(info, start, end);
4603                 goto check_again;
4604         }
4605
4606         if (framesize < (2 + crc_size) || status & BIT0) {
4607                 info->icount.rxshort++;
4608                 framesize = 0;
4609         } else if (status & BIT1) {
4610                 info->icount.rxcrc++;
4611                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4612                         framesize = 0;
4613         }
4614
4615 #if SYNCLINK_GENERIC_HDLC
4616         if (framesize == 0) {
4617                 info->netdev->stats.rx_errors++;
4618                 info->netdev->stats.rx_frame_errors++;
4619         }
4620 #endif
4621
4622         DBGBH(("%s rx frame status=%04X size=%d\n",
4623                 info->device_name, status, framesize));
4624         DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4625
4626         if (framesize) {
4627                 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4628                         framesize -= crc_size;
4629                         crc_size = 0;
4630                 }
4631
4632                 if (framesize > info->max_frame_size + crc_size)
4633                         info->icount.rxlong++;
4634                 else {
4635                         /* copy dma buffer(s) to contiguous temp buffer */
4636                         int copy_count = framesize;
4637                         int i = start;
4638                         unsigned char *p = info->tmp_rbuf;
4639                         info->tmp_rbuf_count = framesize;
4640
4641                         info->icount.rxok++;
4642
4643                         while(copy_count) {
4644                                 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4645                                 memcpy(p, info->rbufs[i].buf, partial_count);
4646                                 p += partial_count;
4647                                 copy_count -= partial_count;
4648                                 if (++i == info->rbuf_count)
4649                                         i = 0;
4650                         }
4651
4652                         if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4653                                 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4654                                 framesize++;
4655                         }
4656
4657 #if SYNCLINK_GENERIC_HDLC
4658                         if (info->netcount)
4659                                 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4660                         else
4661 #endif
4662                                 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4663                 }
4664         }
4665         free_rbufs(info, start, end);
4666         return true;
4667
4668 cleanup:
4669         return false;
4670 }
4671
4672 /*
4673  * pass receive buffer (RAW synchronous mode) to tty layer
4674  * return true if buffer available, otherwise false
4675  */
4676 static bool rx_get_buf(struct slgt_info *info)
4677 {
4678         unsigned int i = info->rbuf_current;
4679         unsigned int count;
4680
4681         if (!desc_complete(info->rbufs[i]))
4682                 return false;
4683         count = desc_count(info->rbufs[i]);
4684         switch(info->params.mode) {
4685         case MGSL_MODE_MONOSYNC:
4686         case MGSL_MODE_BISYNC:
4687                 /* ignore residue in byte synchronous modes */
4688                 if (desc_residue(info->rbufs[i]))
4689                         count--;
4690                 break;
4691         }
4692         DBGDATA(info, info->rbufs[i].buf, count, "rx");
4693         DBGINFO(("rx_get_buf size=%d\n", count));
4694         if (count)
4695                 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4696                                   info->flag_buf, count);
4697         free_rbufs(info, i, i);
4698         return true;
4699 }
4700
4701 static void reset_tbufs(struct slgt_info *info)
4702 {
4703         unsigned int i;
4704         info->tbuf_current = 0;
4705         for (i=0 ; i < info->tbuf_count ; i++) {
4706                 info->tbufs[i].status = 0;
4707                 info->tbufs[i].count  = 0;
4708         }
4709 }
4710
4711 /*
4712  * return number of free transmit DMA buffers
4713  */
4714 static unsigned int free_tbuf_count(struct slgt_info *info)
4715 {
4716         unsigned int count = 0;
4717         unsigned int i = info->tbuf_current;
4718
4719         do
4720         {
4721                 if (desc_count(info->tbufs[i]))
4722                         break; /* buffer in use */
4723                 ++count;
4724                 if (++i == info->tbuf_count)
4725                         i=0;
4726         } while (i != info->tbuf_current);
4727
4728         /* if tx DMA active, last zero count buffer is in use */
4729         if (count && (rd_reg32(info, TDCSR) & BIT0))
4730                 --count;
4731
4732         return count;
4733 }
4734
4735 /*
4736  * return number of bytes in unsent transmit DMA buffers
4737  * and the serial controller tx FIFO
4738  */
4739 static unsigned int tbuf_bytes(struct slgt_info *info)
4740 {
4741         unsigned int total_count = 0;
4742         unsigned int i = info->tbuf_current;
4743         unsigned int reg_value;
4744         unsigned int count;
4745         unsigned int active_buf_count = 0;
4746
4747         /*
4748          * Add descriptor counts for all tx DMA buffers.
4749          * If count is zero (cleared by DMA controller after read),
4750          * the buffer is complete or is actively being read from.
4751          *
4752          * Record buf_count of last buffer with zero count starting
4753          * from current ring position. buf_count is mirror
4754          * copy of count and is not cleared by serial controller.
4755          * If DMA controller is active, that buffer is actively
4756          * being read so add to total.
4757          */
4758         do {
4759                 count = desc_count(info->tbufs[i]);
4760                 if (count)
4761                         total_count += count;
4762                 else if (!total_count)
4763                         active_buf_count = info->tbufs[i].buf_count;
4764                 if (++i == info->tbuf_count)
4765                         i = 0;
4766         } while (i != info->tbuf_current);
4767
4768         /* read tx DMA status register */
4769         reg_value = rd_reg32(info, TDCSR);
4770
4771         /* if tx DMA active, last zero count buffer is in use */
4772         if (reg_value & BIT0)
4773                 total_count += active_buf_count;
4774
4775         /* add tx FIFO count = reg_value[15..8] */
4776         total_count += (reg_value >> 8) & 0xff;
4777
4778         /* if transmitter active add one byte for shift register */
4779         if (info->tx_active)
4780                 total_count++;
4781
4782         return total_count;
4783 }
4784
4785 /*
4786  * load transmit DMA buffer(s) with data
4787  */
4788 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4789 {
4790         unsigned short count;
4791         unsigned int i;
4792         struct slgt_desc *d;
4793
4794         if (size == 0)
4795                 return;
4796
4797         DBGDATA(info, buf, size, "tx");
4798
4799         info->tbuf_start = i = info->tbuf_current;
4800
4801         while (size) {
4802                 d = &info->tbufs[i];
4803                 if (++i == info->tbuf_count)
4804                         i = 0;
4805
4806                 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4807                 memcpy(d->buf, buf, count);
4808
4809                 size -= count;
4810                 buf  += count;
4811
4812                 /*
4813                  * set EOF bit for last buffer of HDLC frame or
4814                  * for every buffer in raw mode
4815                  */
4816                 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4817                     info->params.mode == MGSL_MODE_RAW)
4818                         set_desc_eof(*d, 1);
4819                 else
4820                         set_desc_eof(*d, 0);
4821
4822                 set_desc_count(*d, count);
4823                 d->buf_count = count;
4824         }
4825
4826         info->tbuf_current = i;
4827 }
4828
4829 static int register_test(struct slgt_info *info)
4830 {
4831         static unsigned short patterns[] =
4832                 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4833         static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4834         unsigned int i;
4835         int rc = 0;
4836
4837         for (i=0 ; i < count ; i++) {
4838                 wr_reg16(info, TIR, patterns[i]);
4839                 wr_reg16(info, BDR, patterns[(i+1)%count]);
4840                 if ((rd_reg16(info, TIR) != patterns[i]) ||
4841                     (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4842                         rc = -ENODEV;
4843                         break;
4844                 }
4845         }
4846         info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4847         info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4848         return rc;
4849 }
4850
4851 static int irq_test(struct slgt_info *info)
4852 {
4853         unsigned long timeout;
4854         unsigned long flags;
4855         struct tty_struct *oldtty = info->port.tty;
4856         u32 speed = info->params.data_rate;
4857
4858         info->params.data_rate = 921600;
4859         info->port.tty = NULL;
4860
4861         spin_lock_irqsave(&info->lock, flags);
4862         async_mode(info);
4863         slgt_irq_on(info, IRQ_TXIDLE);
4864
4865         /* enable transmitter */
4866         wr_reg16(info, TCR,
4867                 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4868
4869         /* write one byte and wait for tx idle */
4870         wr_reg16(info, TDR, 0);
4871
4872         /* assume failure */
4873         info->init_error = DiagStatus_IrqFailure;
4874         info->irq_occurred = false;
4875
4876         spin_unlock_irqrestore(&info->lock, flags);
4877
4878         timeout=100;
4879         while(timeout-- && !info->irq_occurred)
4880                 msleep_interruptible(10);
4881
4882         spin_lock_irqsave(&info->lock,flags);
4883         reset_port(info);
4884         spin_unlock_irqrestore(&info->lock,flags);
4885
4886         info->params.data_rate = speed;
4887         info->port.tty = oldtty;
4888
4889         info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4890         return info->irq_occurred ? 0 : -ENODEV;
4891 }
4892
4893 static int loopback_test_rx(struct slgt_info *info)
4894 {
4895         unsigned char *src, *dest;
4896         int count;
4897
4898         if (desc_complete(info->rbufs[0])) {
4899                 count = desc_count(info->rbufs[0]);
4900                 src   = info->rbufs[0].buf;
4901                 dest  = info->tmp_rbuf;
4902
4903                 for( ; count ; count-=2, src+=2) {
4904                         /* src=data byte (src+1)=status byte */
4905                         if (!(*(src+1) & (BIT9 + BIT8))) {
4906                                 *dest = *src;
4907                                 dest++;
4908                                 info->tmp_rbuf_count++;
4909                         }
4910                 }
4911                 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4912                 return 1;
4913         }
4914         return 0;
4915 }
4916
4917 static int loopback_test(struct slgt_info *info)
4918 {
4919 #define TESTFRAMESIZE 20
4920
4921         unsigned long timeout;
4922         u16 count = TESTFRAMESIZE;
4923         unsigned char buf[TESTFRAMESIZE];
4924         int rc = -ENODEV;
4925         unsigned long flags;
4926
4927         struct tty_struct *oldtty = info->port.tty;
4928         MGSL_PARAMS params;
4929
4930         memcpy(&params, &info->params, sizeof(params));
4931
4932         info->params.mode = MGSL_MODE_ASYNC;
4933         info->params.data_rate = 921600;
4934         info->params.loopback = 1;
4935         info->port.tty = NULL;
4936
4937         /* build and send transmit frame */
4938         for (count = 0; count < TESTFRAMESIZE; ++count)
4939                 buf[count] = (unsigned char)count;
4940
4941         info->tmp_rbuf_count = 0;
4942         memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4943
4944         /* program hardware for HDLC and enabled receiver */
4945         spin_lock_irqsave(&info->lock,flags);
4946         async_mode(info);
4947         rx_start(info);
4948         info->tx_count = count;
4949         tx_load(info, buf, count);
4950         tx_start(info);
4951         spin_unlock_irqrestore(&info->lock, flags);
4952
4953         /* wait for receive complete */
4954         for (timeout = 100; timeout; --timeout) {
4955                 msleep_interruptible(10);
4956                 if (loopback_test_rx(info)) {
4957                         rc = 0;
4958                         break;
4959                 }
4960         }
4961
4962         /* verify received frame length and contents */
4963         if (!rc && (info->tmp_rbuf_count != count ||
4964                   memcmp(buf, info->tmp_rbuf, count))) {
4965                 rc = -ENODEV;
4966         }
4967
4968         spin_lock_irqsave(&info->lock,flags);
4969         reset_adapter(info);
4970         spin_unlock_irqrestore(&info->lock,flags);
4971
4972         memcpy(&info->params, &params, sizeof(info->params));
4973         info->port.tty = oldtty;
4974
4975         info->init_error = rc ? DiagStatus_DmaFailure : 0;
4976         return rc;
4977 }
4978
4979 static int adapter_test(struct slgt_info *info)
4980 {
4981         DBGINFO(("testing %s\n", info->device_name));
4982         if (register_test(info) < 0) {
4983                 printk("register test failure %s addr=%08X\n",
4984                         info->device_name, info->phys_reg_addr);
4985         } else if (irq_test(info) < 0) {
4986                 printk("IRQ test failure %s IRQ=%d\n",
4987                         info->device_name, info->irq_level);
4988         } else if (loopback_test(info) < 0) {
4989                 printk("loopback test failure %s\n", info->device_name);
4990         }
4991         return info->init_error;
4992 }
4993
4994 /*
4995  * transmit timeout handler
4996  */
4997 static void tx_timeout(unsigned long context)
4998 {
4999         struct slgt_info *info = (struct slgt_info*)context;
5000         unsigned long flags;
5001
5002         DBGINFO(("%s tx_timeout\n", info->device_name));
5003         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5004                 info->icount.txtimeout++;
5005         }
5006         spin_lock_irqsave(&info->lock,flags);
5007         info->tx_active = false;
5008         info->tx_count = 0;
5009         spin_unlock_irqrestore(&info->lock,flags);
5010
5011 #if SYNCLINK_GENERIC_HDLC
5012         if (info->netcount)
5013                 hdlcdev_tx_done(info);
5014         else
5015 #endif
5016                 bh_transmit(info);
5017 }
5018
5019 /*
5020  * receive buffer polling timer
5021  */
5022 static void rx_timeout(unsigned long context)
5023 {
5024         struct slgt_info *info = (struct slgt_info*)context;
5025         unsigned long flags;
5026
5027         DBGINFO(("%s rx_timeout\n", info->device_name));
5028         spin_lock_irqsave(&info->lock, flags);
5029         info->pending_bh |= BH_RECEIVE;
5030         spin_unlock_irqrestore(&info->lock, flags);
5031         bh_handler(&info->task);
5032 }
5033