2 * Architecture-specific setup.
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
45 #include <linux/cpufreq.h>
46 #include <linux/kexec.h>
47 #include <linux/crash_dump.h>
50 #include <asm/machvec.h>
52 #include <asm/meminit.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
58 #include <asm/sections.h>
59 #include <asm/setup.h>
61 #include <asm/system.h>
62 #include <asm/tlbflush.h>
63 #include <asm/unistd.h>
64 #include <asm/hpsim.h>
66 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
67 # error "struct cpuinfo_ia64 too big!"
71 unsigned long __per_cpu_offset[NR_CPUS];
72 EXPORT_SYMBOL(__per_cpu_offset);
75 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
76 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
77 unsigned long ia64_cycles_per_usec;
78 struct ia64_boot_param *ia64_boot_param;
79 struct screen_info screen_info;
80 unsigned long vga_console_iobase;
81 unsigned long vga_console_membase;
83 static struct resource data_resource = {
84 .name = "Kernel data",
85 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
88 static struct resource code_resource = {
89 .name = "Kernel code",
90 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
93 static struct resource bss_resource = {
95 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
98 unsigned long ia64_max_cacheline_size;
100 int dma_get_cache_alignment(void)
102 return ia64_max_cacheline_size;
104 EXPORT_SYMBOL(dma_get_cache_alignment);
106 unsigned long ia64_iobase; /* virtual address for I/O accesses */
107 EXPORT_SYMBOL(ia64_iobase);
108 struct io_space io_space[MAX_IO_SPACES];
109 EXPORT_SYMBOL(io_space);
110 unsigned int num_io_spaces;
113 * "flush_icache_range()" needs to know what processor dependent stride size to use
114 * when it makes i-cache(s) coherent with d-caches.
116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
117 unsigned long ia64_i_cache_stride_shift = ~0;
120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
123 * address of the second buffer must be aligned to (merge_mask+1) in order to be
124 * mergeable). By default, we assume there is no I/O MMU which can merge physically
125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
128 unsigned long ia64_max_iommu_merge_mask = ~0UL;
129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
132 * We use a special marker for the end of memory and it uses the extra (+1) slot
134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
135 int num_rsvd_regions __initdata;
139 * Filter incoming memory segments based on the primitive map created from the boot
140 * parameters. Segments contained in the map are removed from the memory ranges. A
141 * caller-specified function is called with the memory ranges that remain after filtering.
142 * This routine does not assume the incoming segments are sorted.
145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
147 unsigned long range_start, range_end, prev_start;
148 void (*func)(unsigned long, unsigned long, int);
152 if (start == PAGE_OFFSET) {
153 printk(KERN_WARNING "warning: skipping physical page 0\n");
155 if (start >= end) return 0;
159 * lowest possible address(walker uses virtual)
161 prev_start = PAGE_OFFSET;
164 for (i = 0; i < num_rsvd_regions; ++i) {
165 range_start = max(start, prev_start);
166 range_end = min(end, rsvd_region[i].start);
168 if (range_start < range_end)
169 call_pernode_memory(__pa(range_start), range_end - range_start, func);
171 /* nothing more available in this segment */
172 if (range_end == end) return 0;
174 prev_start = rsvd_region[i].end;
176 /* end of memory marker allows full processing inside loop body */
181 * Similar to "filter_rsvd_memory()", but the reserved memory ranges
182 * are not filtered out.
185 filter_memory(unsigned long start, unsigned long end, void *arg)
187 void (*func)(unsigned long, unsigned long, int);
190 if (start == PAGE_OFFSET) {
191 printk(KERN_WARNING "warning: skipping physical page 0\n");
199 call_pernode_memory(__pa(start), end - start, func);
204 sort_regions (struct rsvd_region *rsvd_region, int max)
208 /* simple bubble sorting */
210 for (j = 0; j < max; ++j) {
211 if (rsvd_region[j].start > rsvd_region[j+1].start) {
212 struct rsvd_region tmp;
213 tmp = rsvd_region[j];
214 rsvd_region[j] = rsvd_region[j + 1];
215 rsvd_region[j + 1] = tmp;
222 * Request address space for all standard resources
224 static int __init register_memory(void)
226 code_resource.start = ia64_tpa(_text);
227 code_resource.end = ia64_tpa(_etext) - 1;
228 data_resource.start = ia64_tpa(_etext);
229 data_resource.end = ia64_tpa(_edata) - 1;
230 bss_resource.start = ia64_tpa(__bss_start);
231 bss_resource.end = ia64_tpa(_end) - 1;
232 efi_initialize_iomem_resources(&code_resource, &data_resource,
238 __initcall(register_memory);
244 * This function checks if the reserved crashkernel is allowed on the specific
245 * IA64 machine flavour. Machines without an IO TLB use swiotlb and require
246 * some memory below 4 GB (i.e. in 32 bit area), see the implementation of
247 * lib/swiotlb.c. The hpzx1 architecture has an IO TLB but cannot use that
248 * in kdump case. See the comment in sba_init() in sba_iommu.c.
250 * So, the only machvec that really supports loading the kdump kernel
251 * over 4 GB is "sn2".
253 static int __init check_crashkernel_memory(unsigned long pbase, size_t size)
255 if (ia64_platform_is("sn2") || ia64_platform_is("uv"))
258 return pbase < (1UL << 32);
261 static void __init setup_crashkernel(unsigned long total, int *n)
263 unsigned long long base = 0, size = 0;
266 ret = parse_crashkernel(boot_command_line, total,
268 if (ret == 0 && size > 0) {
270 sort_regions(rsvd_region, *n);
271 base = kdump_find_rsvd_region(size,
275 if (!check_crashkernel_memory(base, size)) {
276 pr_warning("crashkernel: There would be kdump memory "
277 "at %ld GB but this is unusable because it "
278 "must\nbe below 4 GB. Change the memory "
279 "configuration of the machine.\n",
280 (unsigned long)(base >> 30));
285 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
286 "for crashkernel (System RAM: %ldMB)\n",
287 (unsigned long)(size >> 20),
288 (unsigned long)(base >> 20),
289 (unsigned long)(total >> 20));
290 rsvd_region[*n].start =
291 (unsigned long)__va(base);
292 rsvd_region[*n].end =
293 (unsigned long)__va(base + size);
295 crashk_res.start = base;
296 crashk_res.end = base + size - 1;
299 efi_memmap_res.start = ia64_boot_param->efi_memmap;
300 efi_memmap_res.end = efi_memmap_res.start +
301 ia64_boot_param->efi_memmap_size;
302 boot_param_res.start = __pa(ia64_boot_param);
303 boot_param_res.end = boot_param_res.start +
304 sizeof(*ia64_boot_param);
307 static inline void __init setup_crashkernel(unsigned long total, int *n)
312 * reserve_memory - setup reserved memory areas
314 * Setup the reserved memory areas set aside for the boot parameters,
315 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
316 * see include/asm-ia64/meminit.h if you need to define more.
319 reserve_memory (void)
322 unsigned long total_memory;
325 * none of the entries in this table overlap
327 rsvd_region[n].start = (unsigned long) ia64_boot_param;
328 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
331 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
332 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
335 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
336 rsvd_region[n].end = (rsvd_region[n].start
337 + strlen(__va(ia64_boot_param->command_line)) + 1);
340 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
341 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
344 #ifdef CONFIG_BLK_DEV_INITRD
345 if (ia64_boot_param->initrd_start) {
346 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
347 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
352 #ifdef CONFIG_PROC_VMCORE
353 if (reserve_elfcorehdr(&rsvd_region[n].start,
354 &rsvd_region[n].end) == 0)
358 total_memory = efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
361 setup_crashkernel(total_memory, &n);
363 /* end of memory marker */
364 rsvd_region[n].start = ~0UL;
365 rsvd_region[n].end = ~0UL;
368 num_rsvd_regions = n;
369 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
371 sort_regions(rsvd_region, num_rsvd_regions);
376 * find_initrd - get initrd parameters from the boot parameter structure
378 * Grab the initrd start and end from the boot parameter struct given us by
384 #ifdef CONFIG_BLK_DEV_INITRD
385 if (ia64_boot_param->initrd_start) {
386 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
387 initrd_end = initrd_start+ia64_boot_param->initrd_size;
389 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
390 initrd_start, ia64_boot_param->initrd_size);
398 unsigned long phys_iobase;
401 * Set `iobase' based on the EFI memory map or, failing that, the
402 * value firmware left in ar.k0.
404 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
405 * the port's virtual address, so ia32_load_state() loads it with a
406 * user virtual address. But in ia64 mode, glibc uses the
407 * *physical* address in ar.k0 to mmap the appropriate area from
408 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
409 * cases, user-mode can only use the legacy 0-64K I/O port space.
411 * ar.k0 is not involved in kernel I/O port accesses, which can use
412 * any of the I/O port spaces and are done via MMIO using the
413 * virtual mmio_base from the appropriate io_space[].
415 phys_iobase = efi_get_iobase();
417 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
418 printk(KERN_INFO "No I/O port range found in EFI memory map, "
419 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
421 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
422 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
424 /* setup legacy IO port space */
425 io_space[0].mmio_base = ia64_iobase;
426 io_space[0].sparse = 1;
431 * early_console_setup - setup debugging console
433 * Consoles started here require little enough setup that we can start using
434 * them very early in the boot process, either right after the machine
435 * vector initialization, or even before if the drivers can detect their hw.
437 * Returns non-zero if a console couldn't be setup.
439 static inline int __init
440 early_console_setup (char *cmdline)
444 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
446 extern int sn_serial_console_early_setup(void);
447 if (!sn_serial_console_early_setup())
451 #ifdef CONFIG_EFI_PCDP
452 if (!efi_setup_pcdp_console(cmdline))
455 if (!simcons_register())
458 return (earlycons) ? 0 : -1;
462 mark_bsp_online (void)
465 /* If we register an early console, allow CPU 0 to printk */
466 cpu_set(smp_processor_id(), cpu_online_map);
470 static __initdata int nomca;
471 static __init int setup_nomca(char *s)
476 early_param("nomca", setup_nomca);
478 #ifdef CONFIG_PROC_VMCORE
479 /* elfcorehdr= specifies the location of elf core header
480 * stored by the crashed kernel.
482 static int __init parse_elfcorehdr(char *arg)
487 elfcorehdr_addr = memparse(arg, &arg);
490 early_param("elfcorehdr", parse_elfcorehdr);
492 int __init reserve_elfcorehdr(unsigned long *start, unsigned long *end)
494 unsigned long length;
496 /* We get the address using the kernel command line,
497 * but the size is extracted from the EFI tables.
498 * Both address and size are required for reservation
502 if (elfcorehdr_addr >= ELFCORE_ADDR_MAX)
505 if ((length = vmcore_find_descriptor_size(elfcorehdr_addr)) == 0) {
506 elfcorehdr_addr = ELFCORE_ADDR_MAX;
510 *start = (unsigned long)__va(elfcorehdr_addr);
511 *end = *start + length;
515 #endif /* CONFIG_PROC_VMCORE */
518 setup_arch (char **cmdline_p)
522 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
524 *cmdline_p = __va(ia64_boot_param->command_line);
525 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
530 #ifdef CONFIG_IA64_GENERIC
531 /* machvec needs to be parsed from the command line
532 * before parse_early_param() is called to ensure
533 * that ia64_mv is initialised before any command line
534 * settings may cause console setup to occur
536 machvec_init_from_cmdline(*cmdline_p);
541 if (early_console_setup(*cmdline_p) == 0)
545 /* Initialize the ACPI boot-time table parser */
547 # ifdef CONFIG_ACPI_NUMA
549 per_cpu_scan_finalize((cpus_weight(early_cpu_possible_map) == 0 ?
550 32 : cpus_weight(early_cpu_possible_map)), additional_cpus);
554 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
556 #endif /* CONFIG_APCI_BOOT */
560 /* process SAL system table: */
561 ia64_sal_init(__va(efi.sal_systab));
563 #ifdef CONFIG_ITANIUM
564 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
567 u64 num_phys_stacked;
569 if (ia64_pal_rse_info(&num_phys_stacked, 0) == 0 && num_phys_stacked > 96)
570 ia64_patch_rse((u64) __start___rse_patchlist, (u64) __end___rse_patchlist);
575 cpu_physical_id(0) = hard_smp_processor_id();
578 cpu_init(); /* initialize the bootstrap CPU */
579 mmu_context_init(); /* initialize context_id bitmap */
587 # if defined(CONFIG_DUMMY_CONSOLE)
588 conswitchp = &dummy_con;
590 # if defined(CONFIG_VGA_CONSOLE)
592 * Non-legacy systems may route legacy VGA MMIO range to system
593 * memory. vga_con probes the MMIO hole, so memory looks like
594 * a VGA device to it. The EFI memory map can tell us if it's
595 * memory so we can avoid this problem.
597 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
598 conswitchp = &vga_con;
603 /* enable IA-64 Machine Check Abort Handling unless disabled */
607 platform_setup(cmdline_p);
608 check_sal_cache_flush();
613 * Display cpu info for all CPUs.
616 show_cpuinfo (struct seq_file *m, void *v)
619 # define lpj c->loops_per_jiffy
620 # define cpunum c->cpu
622 # define lpj loops_per_jiffy
627 const char *feature_name;
629 { 1UL << 0, "branchlong" },
630 { 1UL << 1, "spontaneous deferral"},
631 { 1UL << 2, "16-byte atomic ops" }
633 char features[128], *cp, *sep;
634 struct cpuinfo_ia64 *c = v;
636 unsigned long proc_freq;
641 /* build the feature string: */
642 memcpy(features, "standard", 9);
644 size = sizeof(features);
646 for (i = 0; i < ARRAY_SIZE(feature_bits) && size > 1; ++i) {
647 if (mask & feature_bits[i].mask) {
648 cp += snprintf(cp, size, "%s%s", sep,
649 feature_bits[i].feature_name),
651 mask &= ~feature_bits[i].mask;
652 size = sizeof(features) - (cp - features);
655 if (mask && size > 1) {
656 /* print unknown features as a hex value */
657 snprintf(cp, size, "%s0x%lx", sep, mask);
660 proc_freq = cpufreq_quick_get(cpunum);
662 proc_freq = c->proc_freq / 1000;
676 "cpu MHz : %lu.%03lu\n"
677 "itc MHz : %lu.%06lu\n"
678 "BogoMIPS : %lu.%02lu\n",
679 cpunum, c->vendor, c->family, c->model,
680 c->model_name, c->revision, c->archrev,
681 features, c->ppn, c->number,
682 proc_freq / 1000, proc_freq % 1000,
683 c->itc_freq / 1000000, c->itc_freq % 1000000,
684 lpj*HZ/500000, (lpj*HZ/5000) % 100);
686 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
687 if (c->socket_id != -1)
688 seq_printf(m, "physical id: %u\n", c->socket_id);
689 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
693 c->core_id, c->thread_id);
701 c_start (struct seq_file *m, loff_t *pos)
704 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
707 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
711 c_next (struct seq_file *m, void *v, loff_t *pos)
714 return c_start(m, pos);
718 c_stop (struct seq_file *m, void *v)
722 const struct seq_operations cpuinfo_op = {
730 static char brandname[MAX_BRANDS][128];
732 static char * __cpuinit
733 get_model_name(__u8 family, __u8 model)
739 memcpy(brand, "Unknown", 8);
740 if (ia64_pal_get_brand_info(brand)) {
742 memcpy(brand, "Merced", 7);
743 else if (family == 0x1f) switch (model) {
744 case 0: memcpy(brand, "McKinley", 9); break;
745 case 1: memcpy(brand, "Madison", 8); break;
746 case 2: memcpy(brand, "Madison up to 9M cache", 23); break;
749 for (i = 0; i < MAX_BRANDS; i++)
750 if (strcmp(brandname[i], brand) == 0)
752 for (i = 0; i < MAX_BRANDS; i++)
753 if (brandname[i][0] == '\0')
754 return strcpy(brandname[i], brand);
757 "%s: Table overflow. Some processor model information will be missing\n",
762 static void __cpuinit
763 identify_cpu (struct cpuinfo_ia64 *c)
766 unsigned long bits[5];
772 u64 ppn; /* processor serial number */
776 unsigned revision : 8;
779 unsigned archrev : 8;
780 unsigned reserved : 24;
786 pal_vm_info_1_u_t vm1;
787 pal_vm_info_2_u_t vm2;
789 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
791 for (i = 0; i < 5; ++i)
792 cpuid.bits[i] = ia64_get_cpuid(i);
794 memcpy(c->vendor, cpuid.field.vendor, 16);
796 c->cpu = smp_processor_id();
798 /* below default values will be overwritten by identify_siblings()
799 * for Multi-Threading/Multi-Core capable CPUs
801 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
804 identify_siblings(c);
806 if (c->threads_per_core > smp_num_siblings)
807 smp_num_siblings = c->threads_per_core;
809 c->ppn = cpuid.field.ppn;
810 c->number = cpuid.field.number;
811 c->revision = cpuid.field.revision;
812 c->model = cpuid.field.model;
813 c->family = cpuid.field.family;
814 c->archrev = cpuid.field.archrev;
815 c->features = cpuid.field.features;
816 c->model_name = get_model_name(c->family, c->model);
818 status = ia64_pal_vm_summary(&vm1, &vm2);
819 if (status == PAL_STATUS_SUCCESS) {
820 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
821 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
823 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
824 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
828 setup_per_cpu_areas (void)
830 /* start_kernel() requires this... */
831 #ifdef CONFIG_ACPI_HOTPLUG_CPU
832 prefill_possible_map();
837 * Calculate the max. cache line size.
839 * In addition, the minimum of the i-cache stride sizes is calculated for
840 * "flush_icache_range()".
842 static void __cpuinit
843 get_max_cacheline_size (void)
845 unsigned long line_size, max = 1;
846 u64 l, levels, unique_caches;
847 pal_cache_config_info_t cci;
850 status = ia64_pal_cache_summary(&levels, &unique_caches);
852 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
854 max = SMP_CACHE_BYTES;
855 /* Safest setup for "flush_icache_range()" */
856 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
860 for (l = 0; l < levels; ++l) {
861 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
865 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
866 __func__, l, status);
867 max = SMP_CACHE_BYTES;
868 /* The safest setup for "flush_icache_range()" */
869 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
870 cci.pcci_unified = 1;
872 line_size = 1 << cci.pcci_line_size;
875 if (!cci.pcci_unified) {
876 status = ia64_pal_cache_config_info(l,
877 /* cache_type (instruction)= */ 1,
881 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
882 __func__, l, status);
883 /* The safest setup for "flush_icache_range()" */
884 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
887 if (cci.pcci_stride < ia64_i_cache_stride_shift)
888 ia64_i_cache_stride_shift = cci.pcci_stride;
891 if (max > ia64_max_cacheline_size)
892 ia64_max_cacheline_size = max;
896 * cpu_init() initializes state that is per-CPU. This function acts
897 * as a 'CPU state barrier', nothing should get across.
902 extern void __cpuinit ia64_mmu_init (void *);
903 static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
904 unsigned long num_phys_stacked;
905 pal_vm_info_2_u_t vmi;
906 unsigned int max_ctx;
907 struct cpuinfo_ia64 *cpu_info;
910 cpu_data = per_cpu_init();
913 * insert boot cpu into sibling and core mapes
914 * (must be done after per_cpu area is setup)
916 if (smp_processor_id() == 0) {
917 cpu_set(0, per_cpu(cpu_sibling_map, 0));
918 cpu_set(0, cpu_core_map[0]);
923 * We set ar.k3 so that assembly code in MCA handler can compute
924 * physical addresses of per cpu variables with a simple:
925 * phys = ar.k3 + &per_cpu_var
927 ia64_set_kr(IA64_KR_PER_CPU_DATA,
928 ia64_tpa(cpu_data) - (long) __per_cpu_start);
930 get_max_cacheline_size();
933 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
934 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
935 * depends on the data returned by identify_cpu(). We break the dependency by
936 * accessing cpu_data() through the canonical per-CPU address.
938 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
939 identify_cpu(cpu_info);
941 #ifdef CONFIG_MCKINLEY
943 # define FEATURE_SET 16
944 struct ia64_pal_retval iprv;
946 if (cpu_info->family == 0x1f) {
947 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
948 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
949 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
950 (iprv.v1 | 0x80), FEATURE_SET, 0);
955 /* Clear the stack memory reserved for pt_regs: */
956 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
958 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
961 * Initialize the page-table base register to a global
962 * directory with all zeroes. This ensure that we can handle
963 * TLB-misses to user address-space even before we created the
964 * first user address-space. This may happen, e.g., due to
965 * aggressive use of lfetch.fault.
967 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
970 * Initialize default control register to defer speculative faults except
971 * for those arising from TLB misses, which are not deferred. The
972 * kernel MUST NOT depend on a particular setting of these bits (in other words,
973 * the kernel must have recovery code for all speculative accesses). Turn on
974 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
975 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
978 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
979 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
980 atomic_inc(&init_mm.mm_count);
981 current->active_mm = &init_mm;
985 ia64_mmu_init(ia64_imva(cpu_data));
986 ia64_mca_cpu_init(ia64_imva(cpu_data));
988 #ifdef CONFIG_IA32_SUPPORT
992 /* Clear ITC to eliminate sched_clock() overflows in human time. */
995 /* disable all local interrupt sources: */
996 ia64_set_itv(1 << 16);
997 ia64_set_lrr0(1 << 16);
998 ia64_set_lrr1(1 << 16);
999 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
1000 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
1002 /* clear TPR & XTP to enable all interrupt classes: */
1003 ia64_setreg(_IA64_REG_CR_TPR, 0);
1005 /* Clear any pending interrupts left by SAL/EFI */
1006 while (ia64_get_ivr() != IA64_SPURIOUS_INT_VECTOR)
1013 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
1014 if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
1015 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
1016 setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, NPTCG_FROM_PAL);
1018 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
1019 max_ctx = (1U << 15) - 1; /* use architected minimum */
1021 while (max_ctx < ia64_ctx.max_ctx) {
1022 unsigned int old = ia64_ctx.max_ctx;
1023 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
1027 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
1028 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
1030 num_phys_stacked = 96;
1032 /* size of physical stacked register partition plus 8 bytes: */
1033 if (num_phys_stacked > max_num_phys_stacked) {
1034 ia64_patch_phys_stack_reg(num_phys_stacked*8 + 8);
1035 max_num_phys_stacked = num_phys_stacked;
1037 platform_cpu_init();
1038 pm_idle = default_idle;
1044 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1045 (unsigned long) __end___mckinley_e9_bundles);
1048 static int __init run_dmi_scan(void)
1053 core_initcall(run_dmi_scan);