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   1 /*
   2  * PCI autoconfiguration library
   3  *
   4  * Author: Matt Porter <mporter@mvista.com>
   5  *
   6  * Copyright 2000, 2001 MontaVista Software Inc.
   7  * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
   8  * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 /*
  17  * Modified for MIPS by Jun Sun, jsun@mvista.com
  18  *
  19  * . Simplify the interface between pci_auto and the rest: a single function.
  20  * . Assign resources from low address to upper address.
  21  * . change most int to u32.
  22  *
  23  * Further modified to include it as mips generic code, ppopov@mvista.com.
  24  *
  25  * 2001-10-26  Bradley D. LaRonde <brad@ltc.com>
  26  * - Add a top_bus argument to the "early config" functions so that
  27  *   they can set a fake parent bus pointer to convince the underlying
  28  *   pci ops to use type 1 configuration for sub busses.
  29  * - Set bridge base and limit registers correctly.
  30  * - Align io and memory base properly before and after bridge setup.
  31  * - Don't fall through to pci_setup_bars for bridge.
  32  * - Reformat the debug output to look more like lspci's output.
  33  *
  34  * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
  35  *
  36  * 2003-08-05  Paul Mundt <lethal@linux-sh.org>
  37  * - Don't update the BAR values on systems that already have valid addresses
  38  *   and don't want these updated for whatever reason, by way of a new config
  39  *   option check. However, we still read in the old BAR values so that they
  40  *   can still be reported through the debug output.
  41  */
  42
  43 #include <linux/kernel.h>
  44 #include <linux/init.h>
  45 #include <linux/types.h>
  46 #include <linux/pci.h>
  47
  48 #define DEBUG
  49 #ifdef  DEBUG
  50 #define DBG(x...)       printk(x)
  51 #else
  52 #define DBG(x...)
  53 #endif
  54
  55 /*
  56  * These functions are used early on before PCI scanning is done
  57  * and all of the pci_dev and pci_bus structures have been created.
  58  */
  59 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
  60         int top_bus, int busnr, int devfn)
  61 {
  62         static struct pci_dev dev;
  63         static struct pci_bus bus;
  64
  65         dev.bus = &bus;
  66         dev.sysdata = hose;
  67         dev.devfn = devfn;
  68         bus.number = busnr;
  69         bus.ops = hose->pci_ops;
  70         bus.sysdata = hose;
  71
  72         if(busnr != top_bus)
  73                 /* Fake a parent bus structure. */
  74                 bus.parent = &bus;
  75         else
  76                 bus.parent = NULL;
  77
  78         return &dev;
  79 }
  80
  81 #define EARLY_PCI_OP(rw, size, type)                                    \
  82 static int early_##rw##_config_##size(struct pci_channel *hose,         \
  83         int top_bus, int bus, int devfn, int offset, type value)        \
  84 {                                                                       \
  85         return pci_##rw##_config_##size(                                \
  86                 fake_pci_dev(hose, top_bus, bus, devfn),                \
  87                 offset, value);                                         \
  88 }
  89
  90 EARLY_PCI_OP(read, byte, u8 *)
  91 EARLY_PCI_OP(read, word, u16 *)
  92 EARLY_PCI_OP(read, dword, u32 *)
  93 EARLY_PCI_OP(write, byte, u8)
  94 EARLY_PCI_OP(write, word, u16)
  95 EARLY_PCI_OP(write, dword, u32)
  96
  97 static struct resource *io_resource_inuse;
  98 static struct resource *mem_resource_inuse;
  99
 100 static u32 pciauto_lower_iospc;
 101 static u32 pciauto_upper_iospc;
 102
 103 static u32 pciauto_lower_memspc;
 104 static u32 pciauto_upper_memspc;
 105
 106 static void __init
 107 pciauto_setup_bars(struct pci_channel *hose,
 108                    int top_bus,
 109                    int current_bus,
 110                    int pci_devfn,
 111                    int bar_limit)
 112 {
 113         u32 bar_response, bar_size, bar_value;
 114         u32 bar, addr_mask, bar_nr = 0;
 115         u32 * upper_limit;
 116         u32 * lower_limit;
 117         int found_mem64 = 0;
 118
 119         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
 120                 u32 bar_addr;
 121
 122                 /* Read the old BAR value */
 123                 early_read_config_dword(hose, top_bus,
 124                                         current_bus,
 125                                         pci_devfn,
 126                                         bar,
 127                                         &bar_addr);
 128
 129                 /* Tickle the BAR and get the response */
 130                 early_write_config_dword(hose, top_bus,
 131                                          current_bus,
 132                                          pci_devfn,
 133                                          bar,
 134                                          0xffffffff);
 135
 136                 early_read_config_dword(hose, top_bus,
 137                                         current_bus,
 138                                         pci_devfn,
 139                                         bar,
 140                                         &bar_response);
 141
 142                 /*
 143                  * Write the old BAR value back out, only update the BAR
 144                  * if we implicitly want resources to be updated, which
 145                  * is done by the generic code further down. -- PFM.
 146                  */
 147                 early_write_config_dword(hose, top_bus,
 148                                          current_bus,
 149                                          pci_devfn,
 150                                          bar,
 151                                          bar_addr);
 152
 153                 /* If BAR is not implemented go to the next BAR */
 154                 if (!bar_response)
 155                         continue;
 156
 157                 /*
 158                  * Workaround for a BAR that doesn't use its upper word,
 159                  * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
 160                  * bdl <brad@ltc.com>
 161                  */
 162                 if (!(bar_response & 0xffff0000))
 163                         bar_response |= 0xffff0000;
 164
 165 retry:
 166                 /* Check the BAR type and set our address mask */
 167                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 168                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
 169                         upper_limit = &pciauto_upper_iospc;
 170                         lower_limit = &pciauto_lower_iospc;
 171                         DBG("        I/O");
 172                 } else {
 173                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 174                             PCI_BASE_ADDRESS_MEM_TYPE_64)
 175                                 found_mem64 = 1;
 176
 177                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
 178                         upper_limit = &pciauto_upper_memspc;
 179                         lower_limit = &pciauto_lower_memspc;
 180                         DBG("        Mem");
 181                 }
 182
 183
 184                 /* Calculate requested size */
 185                 bar_size = ~(bar_response & addr_mask) + 1;
 186
 187                 /* Allocate a base address */
 188                 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
 189
 190                 if ((bar_value + bar_size) > *upper_limit) {
 191                         if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 192                                 if (io_resource_inuse->child) {
 193                                         io_resource_inuse =
 194                                                 io_resource_inuse->child;
 195                                         pciauto_lower_iospc =
 196                                                 io_resource_inuse->start;
 197                                         pciauto_upper_iospc =
 198                                                 io_resource_inuse->end + 1;
 199                                         goto retry;
 200                                 }
 201
 202                         } else {
 203                                 if (mem_resource_inuse->child) {
 204                                         mem_resource_inuse =
 205                                                 mem_resource_inuse->child;
 206                                         pciauto_lower_memspc =
 207                                                 mem_resource_inuse->start;
 208                                         pciauto_upper_memspc =
 209                                                 mem_resource_inuse->end + 1;
 210                                         goto retry;
 211                                 }
 212                         }
 213                         DBG(" unavailable -- skipping, value %x size %x\n",
 214                                         bar_value, bar_size);
 215                         continue;
 216                 }
 217
 218                 if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {
 219                         DBG(" unavailable -- skipping, value %x size %x\n",
 220                                         bar_value, bar_size);
 221                         continue;
 222                 }
 223
 224 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
 225                 /* Write it out and update our limit */
 226                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 227                                          bar, bar_value);
 228 #endif
 229
 230                 *lower_limit = bar_value + bar_size;
 231
 232                 /*
 233                  * If we are a 64-bit decoder then increment to the
 234                  * upper 32 bits of the bar and force it to locate
 235                  * in the lower 4GB of memory.
 236                  */
 237                 if (found_mem64) {
 238                         bar += 4;
 239                         early_write_config_dword(hose, top_bus,
 240                                                  current_bus,
 241                                                  pci_devfn,
 242                                                  bar,
 243                                                  0x00000000);
 244                 }
 245
 246                 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
 247
 248                 bar_nr++;
 249         }
 250
 251 }
 252
 253 static void __init
 254 pciauto_prescan_setup_bridge(struct pci_channel *hose,
 255                              int top_bus,
 256                              int current_bus,
 257                              int pci_devfn,
 258                              int sub_bus)
 259 {
 260         /* Configure bus number registers */
 261         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 262                                 PCI_PRIMARY_BUS, current_bus);
 263         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 264                                 PCI_SECONDARY_BUS, sub_bus + 1);
 265         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 266                                 PCI_SUBORDINATE_BUS, 0xff);
 267
 268         /* Align memory and I/O to 1MB and 4KB boundaries. */
 269         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 270                 & ~(0x100000 - 1);
 271         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 272                 & ~(0x1000 - 1);
 273
 274         /* Set base (lower limit) of address range behind bridge. */
 275         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 276                 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
 277         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 278                 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
 279         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 280                 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
 281
 282         /* We don't support prefetchable memory for now, so disable */
 283         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 284                                 PCI_PREF_MEMORY_BASE, 0);
 285         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 286                                 PCI_PREF_MEMORY_LIMIT, 0);
 287 }
 288
 289 static void __init
 290 pciauto_postscan_setup_bridge(struct pci_channel *hose,
 291                               int top_bus,
 292                               int current_bus,
 293                               int pci_devfn,
 294                               int sub_bus)
 295 {
 296         u32 temp;
 297
 298         /*
 299          * [jsun] we always bump up baselines a little, so that if there
 300          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 301          * spaces.
 302          */
 303         pciauto_lower_memspc += 1;
 304         pciauto_lower_iospc += 1;
 305
 306         /* Configure bus number registers */
 307         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 308                                 PCI_SUBORDINATE_BUS, sub_bus);
 309
 310         /* Set upper limit of address range behind bridge. */
 311         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 312                 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
 313         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 314                 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
 315         early_write_config_word(hose, top_bus, current_bus, pci_devfn,
 316                 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
 317
 318         /* Align memory and I/O to 1MB and 4KB boundaries. */
 319         pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
 320                 & ~(0x100000 - 1);
 321         pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
 322                 & ~(0x1000 - 1);
 323
 324         /* Enable memory and I/O accesses, enable bus master */
 325         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 326                 PCI_COMMAND, &temp);
 327         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 328                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
 329                 | PCI_COMMAND_MASTER);
 330 }
 331
 332 static void __init
 333 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
 334                         int top_bus,
 335                         int current_bus,
 336                         int pci_devfn,
 337                         int sub_bus)
 338 {
 339         /* Configure bus number registers */
 340         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 341                                 PCI_PRIMARY_BUS, current_bus);
 342         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 343                                 PCI_SECONDARY_BUS, sub_bus + 1);
 344         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 345                                 PCI_SUBORDINATE_BUS, 0xff);
 346
 347         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 348         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 349                 & ~(0x1000 - 1);
 350         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 351                 & ~(0x4 - 1);
 352
 353         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 354                 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
 355         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 356                 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
 357 }
 358
 359 static void __init
 360 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
 361                         int top_bus,
 362                         int current_bus,
 363                         int pci_devfn,
 364                         int sub_bus)
 365 {
 366         u32 temp;
 367
 368         /*
 369          * [jsun] we always bump up baselines a little, so that if there
 370          * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
 371          * spaces.
 372          */
 373         pciauto_lower_memspc += 1;
 374         pciauto_lower_iospc += 1;
 375
 376         /*
 377          * Configure subordinate bus number.  The PCI subsystem
 378          * bus scan will renumber buses (reserving three additional
 379          * for this PCI<->CardBus bridge for the case where a CardBus
 380          * adapter contains a P2P or CB2CB bridge.
 381          */
 382
 383         early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 384                                 PCI_SUBORDINATE_BUS, sub_bus);
 385
 386         /*
 387          * Reserve an additional 4MB for mem space and 16KB for
 388          * I/O space.  This should cover any additional space
 389          * requirement of unusual CardBus devices with
 390          * additional bridges that can consume more address space.
 391          *
 392          * Although pcmcia-cs currently will reprogram bridge
 393          * windows, the goal is to add an option to leave them
 394          * alone and use the bridge window ranges as the regions
 395          * that are searched for free resources upon hot-insertion
 396          * of a device.  This will allow a PCI<->CardBus bridge
 397          * configured by this routine to happily live behind a
 398          * P2P bridge in a system.
 399          */
 400         /* Align memory and I/O to 4KB and 4 byte boundaries. */
 401         pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
 402                 & ~(0x1000 - 1);
 403         pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
 404                 & ~(0x4 - 1);
 405         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 406         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 407                 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
 408         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 409                 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
 410
 411         /* Enable memory and I/O accesses, enable bus master */
 412         early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 413                 PCI_COMMAND, &temp);
 414         early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 415                 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 416                 PCI_COMMAND_MASTER);
 417 }
 418
 419 #define PCIAUTO_IDE_MODE_MASK           0x05
 420
 421 static int __init
 422 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
 423 {
 424         int sub_bus;
 425         u32 pci_devfn, pci_class, cmdstat, found_multi=0;
 426         unsigned short vid, did;
 427         unsigned char header_type;
 428         int devfn_start = 0;
 429         int devfn_stop = 0xff;
 430
 431         sub_bus = current_bus;
 432
 433         if (hose->first_devfn)
 434                 devfn_start = hose->first_devfn;
 435         if (hose->last_devfn)
 436                 devfn_stop = hose->last_devfn;
 437
 438         for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
 439
 440                 if (PCI_FUNC(pci_devfn) && !found_multi)
 441                         continue;
 442
 443                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 444                                        PCI_VENDOR_ID, &vid);
 445
 446                 if (vid == 0xffff) continue;
 447
 448                 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
 449                                        PCI_HEADER_TYPE, &header_type);
 450
 451                 if (!PCI_FUNC(pci_devfn))
 452                         found_multi = header_type & 0x80;
 453
 454                 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
 455                                        PCI_DEVICE_ID, &did);
 456
 457                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 458                                         PCI_CLASS_REVISION, &pci_class);
 459
 460                 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
 461                         current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
 462                         pci_class >> 16, vid, did);
 463                 if (pci_class & 0xff)
 464                         DBG(" (rev %.2x)", pci_class & 0xff);
 465                 DBG("\n");
 466
 467                 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
 468                         DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 469                                 current_bus, sub_bus + 1);
 470                         pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
 471                                                      pci_devfn, sub_bus);
 472                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 473                                 sub_bus + 1,
 474                                 pciauto_lower_iospc, pciauto_lower_memspc);
 475                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 476                         DBG("Back to bus %.2x\n", current_bus);
 477                         pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
 478                                                         pci_devfn, sub_bus);
 479                         continue;
 480                 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
 481                         DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
 482                                 current_bus, sub_bus + 1);
 483                         DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
 484                         /* Place CardBus Socket/ExCA registers */
 485                         pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 486
 487                         pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
 488                                         current_bus, pci_devfn, sub_bus);
 489
 490                         DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 491                                 sub_bus + 1,
 492                                 pciauto_lower_iospc, pciauto_lower_memspc);
 493                         sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 494                         DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
 495                         pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
 496                                         current_bus, pci_devfn, sub_bus);
 497                         continue;
 498                 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
 499
 500                         unsigned char prg_iface;
 501
 502                         early_read_config_byte(hose, top_bus, current_bus,
 503                                 pci_devfn, PCI_CLASS_PROG, &prg_iface);
 504                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 505                                 DBG("Skipping legacy mode IDE controller\n");
 506                                 continue;
 507                         }
 508                 }
 509
 510                 /*
 511                  * Found a peripheral, enable some standard
 512                  * settings
 513                  */
 514                 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 515                                         PCI_COMMAND, &cmdstat);
 516                 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
 517                                          PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
 518                                          PCI_COMMAND_MEMORY |
 519                                          PCI_COMMAND_MASTER);
 520                 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
 521                                         PCI_LATENCY_TIMER, 0x80);
 522
 523                 /* Allocate PCI I/O and/or memory space */
 524                 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
 525         }
 526         return sub_bus;
 527 }
 528
 529 int __init
 530 pciauto_assign_resources(int busno, struct pci_channel *hose)
 531 {
 532         /* setup resource limits */
 533         io_resource_inuse = hose->io_resource;
 534         mem_resource_inuse = hose->mem_resource;
 535
 536         pciauto_lower_iospc = io_resource_inuse->start;
 537         pciauto_upper_iospc = io_resource_inuse->end + 1;
 538         pciauto_lower_memspc = mem_resource_inuse->start;
 539         pciauto_upper_memspc = mem_resource_inuse->end + 1;
 540         DBG("Autoconfig PCI channel 0x%p\n", hose);
 541         DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
 542                 busno, pciauto_lower_iospc, pciauto_upper_iospc,
 543                 pciauto_lower_memspc, pciauto_upper_memspc);
 544
 545         return pciauto_bus_scan(hose, busno, busno);
 546 }