2 comedi/drivers/gsc_hpdi.c
3 This is a driver for the General Standards Corporation High
4 Speed Parallel Digital Interface rs485 boards.
6 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
7 Copyright (C) 2003 Coherent Imaging Systems
9 COMEDI - Linux Control and Measurement Device Interface
10 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 ************************************************************************/
31 Description: General Standards Corporation High
32 Speed Parallel Digital Interface rs485 boards
33 Author: Frank Mori Hess <fmhess@users.sourceforge.net>
34 Status: only receive mode works, transmit not supported
36 Devices: [General Standards Corporation] PCI-HPDI32 (gsc_hpdi),
39 Configuration options:
40 [0] - PCI bus of device (optional)
41 [1] - PCI slot of device (optional)
43 There are some additional hpdi models available from GSC for which
44 support could be added to this driver.
48 #include "../comedidev.h"
49 #include <linux/delay.h>
51 #include "comedi_pci.h"
53 #include "comedi_fc.h"
55 static int hpdi_attach(struct comedi_device * dev, struct comedi_devconfig * it);
56 static int hpdi_detach(struct comedi_device * dev);
57 void abort_dma(struct comedi_device * dev, unsigned int channel);
58 static int hpdi_cmd(struct comedi_device * dev, struct comedi_subdevice * s);
59 static int hpdi_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
60 struct comedi_cmd * cmd);
61 static int hpdi_cancel(struct comedi_device * dev, struct comedi_subdevice * s);
62 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG);
63 static int dio_config_block_size(struct comedi_device * dev, unsigned int * data);
65 #undef HPDI_DEBUG // disable debugging messages
66 //#define HPDI_DEBUG // enable debugging code
69 #define DEBUG_PRINT(format, args...) rt_printk(format , ## args )
71 #define DEBUG_PRINT(format, args...)
74 #define TIMER_BASE 50 // 20MHz master clock
75 #define DMA_BUFFER_SIZE 0x10000
76 #define NUM_DMA_BUFFERS 4
77 #define NUM_DMA_DESCRIPTORS 256
79 // indices of base address regions
80 enum base_address_regions {
81 PLX9080_BADDRINDEX = 0,
86 FIRMWARE_REV_REG = 0x0,
87 BOARD_CONTROL_REG = 0x4,
88 BOARD_STATUS_REG = 0x8,
89 TX_PROG_ALMOST_REG = 0xc,
90 RX_PROG_ALMOST_REG = 0x10,
93 TX_STATUS_COUNT_REG = 0x1c,
94 TX_LINE_VALID_COUNT_REG = 0x20,
95 TX_LINE_INVALID_COUNT_REG = 0x24,
96 RX_STATUS_COUNT_REG = 0x28,
97 RX_LINE_COUNT_REG = 0x2c,
98 INTERRUPT_CONTROL_REG = 0x30,
99 INTERRUPT_STATUS_REG = 0x34,
100 TX_CLOCK_DIVIDER_REG = 0x38,
101 TX_FIFO_SIZE_REG = 0x40,
102 RX_FIFO_SIZE_REG = 0x44,
103 TX_FIFO_WORDS_REG = 0x48,
104 RX_FIFO_WORDS_REG = 0x4c,
105 INTERRUPT_EDGE_LEVEL_REG = 0x50,
106 INTERRUPT_POLARITY_REG = 0x54,
109 int command_channel_valid(unsigned int channel)
111 if (channel == 0 || channel > 6) {
112 rt_printk("gsc_hpdi: bug! invalid cable command channel\n");
120 enum firmware_revision_bits {
121 FEATURES_REG_PRESENT_BIT = 0x8000,
123 int firmware_revision(uint32_t fwr_bits)
125 return fwr_bits & 0xff;
128 int pcb_revision(uint32_t fwr_bits)
130 return (fwr_bits >> 8) & 0xff;
133 int hpdi_subid(uint32_t fwr_bits)
135 return (fwr_bits >> 16) & 0xff;
138 enum board_control_bits {
139 BOARD_RESET_BIT = 0x1, /* wait 10usec before accessing fifos */
140 TX_FIFO_RESET_BIT = 0x2,
141 RX_FIFO_RESET_BIT = 0x4,
142 TX_ENABLE_BIT = 0x10,
143 RX_ENABLE_BIT = 0x20,
144 DEMAND_DMA_DIRECTION_TX_BIT = 0x40, /* for channel 0, channel 1 can only transmit (when present) */
145 LINE_VALID_ON_STATUS_VALID_BIT = 0x80,
147 CABLE_THROTTLE_ENABLE_BIT = 0x20,
148 TEST_MODE_ENABLE_BIT = 0x80000000,
150 uint32_t command_discrete_output_bits(unsigned int channel, int output,
155 if (command_channel_valid(channel) == 0)
158 bits |= 0x1 << (16 + channel);
160 bits |= 0x1 << (24 + channel);
162 bits |= 0x1 << (24 + channel);
167 enum board_status_bits {
168 COMMAND_LINE_STATUS_MASK = 0x7f,
169 TX_IN_PROGRESS_BIT = 0x80,
170 TX_NOT_EMPTY_BIT = 0x100,
171 TX_NOT_ALMOST_EMPTY_BIT = 0x200,
172 TX_NOT_ALMOST_FULL_BIT = 0x400,
173 TX_NOT_FULL_BIT = 0x800,
174 RX_NOT_EMPTY_BIT = 0x1000,
175 RX_NOT_ALMOST_EMPTY_BIT = 0x2000,
176 RX_NOT_ALMOST_FULL_BIT = 0x4000,
177 RX_NOT_FULL_BIT = 0x8000,
178 BOARD_JUMPER0_INSTALLED_BIT = 0x10000,
179 BOARD_JUMPER1_INSTALLED_BIT = 0x20000,
180 TX_OVERRUN_BIT = 0x200000,
181 RX_UNDERRUN_BIT = 0x400000,
182 RX_OVERRUN_BIT = 0x800000,
185 uint32_t almost_full_bits(unsigned int num_words)
187 // XXX need to add or subtract one?
188 return (num_words << 16) & 0xff0000;
191 uint32_t almost_empty_bits(unsigned int num_words)
193 return num_words & 0xffff;
195 unsigned int almost_full_num_words(uint32_t bits)
197 // XXX need to add or subtract one?
198 return (bits >> 16) & 0xffff;
200 unsigned int almost_empty_num_words(uint32_t bits)
202 return bits & 0xffff;
206 FIFO_SIZE_PRESENT_BIT = 0x1,
207 FIFO_WORDS_PRESENT_BIT = 0x2,
208 LEVEL_EDGE_INTERRUPTS_PRESENT_BIT = 0x4,
209 GPIO_SUPPORTED_BIT = 0x8,
210 PLX_DMA_CH1_SUPPORTED_BIT = 0x10,
211 OVERRUN_UNDERRUN_SUPPORTED_BIT = 0x20,
214 enum interrupt_sources {
215 FRAME_VALID_START_INTR = 0,
216 FRAME_VALID_END_INTR = 1,
217 TX_FIFO_EMPTY_INTR = 8,
218 TX_FIFO_ALMOST_EMPTY_INTR = 9,
219 TX_FIFO_ALMOST_FULL_INTR = 10,
220 TX_FIFO_FULL_INTR = 11,
222 RX_ALMOST_EMPTY_INTR = 13,
223 RX_ALMOST_FULL_INTR = 14,
226 int command_intr_source(unsigned int channel)
228 if (command_channel_valid(channel) == 0)
233 uint32_t intr_bit(int interrupt_source)
235 return 0x1 << interrupt_source;
238 uint32_t tx_clock_divisor_bits(unsigned int divisor)
240 return divisor & 0xff;
243 unsigned int fifo_size(uint32_t fifo_size_bits)
245 return fifo_size_bits & 0xfffff;
248 unsigned int fifo_words(uint32_t fifo_words_bits)
250 return fifo_words_bits & 0xfffff;
253 uint32_t intr_edge_bit(int interrupt_source)
255 return 0x1 << interrupt_source;
258 uint32_t intr_active_high_bit(int interrupt_source)
260 return 0x1 << interrupt_source;
266 int device_id; // pci device id
267 int subdevice_id; // pci subdevice id
271 static const struct hpdi_board hpdi_boards[] = {
274 device_id:PCI_DEVICE_ID_PLX_9080,
286 static inline unsigned int num_boards(void)
288 return sizeof(hpdi_boards) / sizeof(struct hpdi_board);
291 static DEFINE_PCI_DEVICE_TABLE(hpdi_pci_table) = {
292 {PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9080, PCI_VENDOR_ID_PLX, 0x2400,
297 MODULE_DEVICE_TABLE(pci, hpdi_pci_table);
299 static inline struct hpdi_board *board(const struct comedi_device * dev)
301 return (struct hpdi_board *) dev->board_ptr;
304 struct hpdi_private {
306 struct pci_dev *hw_dev; // pointer to board's pci_dev struct
307 // base addresses (physical)
308 resource_size_t plx9080_phys_iobase;
309 resource_size_t hpdi_phys_iobase;
310 // base addresses (ioremapped)
311 void *plx9080_iobase;
313 uint32_t *dio_buffer[NUM_DMA_BUFFERS]; // dma buffers
314 dma_addr_t dio_buffer_phys_addr[NUM_DMA_BUFFERS]; // physical addresses of dma buffers
315 struct plx_dma_desc *dma_desc; // array of dma descriptors read by plx9080, allocated to get proper alignment
316 dma_addr_t dma_desc_phys_addr; // physical address of dma descriptor array
317 unsigned int num_dma_descriptors;
318 uint32_t *desc_dio_buffer[NUM_DMA_DESCRIPTORS]; // pointer to start of buffers indexed by descriptor
319 volatile unsigned int dma_desc_index; // index of the dma descriptor that is currently being used
320 unsigned int tx_fifo_size;
321 unsigned int rx_fifo_size;
322 volatile unsigned long dio_count;
323 volatile uint32_t bits[24]; // software copies of values written to hpdi registers
324 volatile unsigned int block_size; // number of bytes at which to generate COMEDI_CB_BLOCK events
325 unsigned dio_config_output:1;
329 static inline struct hpdi_private *priv(struct comedi_device * dev)
334 static struct comedi_driver driver_hpdi = {
335 driver_name:"gsc_hpdi",
341 COMEDI_PCI_INITCLEANUP(driver_hpdi, hpdi_pci_table);
343 static int dio_config_insn(struct comedi_device * dev, struct comedi_subdevice * s,
344 struct comedi_insn * insn, unsigned int * data)
347 case INSN_CONFIG_DIO_OUTPUT:
348 priv(dev)->dio_config_output = 1;
351 case INSN_CONFIG_DIO_INPUT:
352 priv(dev)->dio_config_output = 0;
355 case INSN_CONFIG_DIO_QUERY:
358 dio_config_output ? COMEDI_OUTPUT : COMEDI_INPUT;
361 case INSN_CONFIG_BLOCK_SIZE:
362 return dio_config_block_size(dev, data);
371 static void disable_plx_interrupts(struct comedi_device * dev)
373 writel(0, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
376 // initialize plx9080 chip
377 static void init_plx9080(struct comedi_device * dev)
380 void *plx_iobase = priv(dev)->plx9080_iobase;
383 DEBUG_PRINT(" plx interrupt status 0x%x\n",
384 readl(plx_iobase + PLX_INTRCS_REG));
385 DEBUG_PRINT(" plx id bits 0x%x\n", readl(plx_iobase + PLX_ID_REG));
386 DEBUG_PRINT(" plx control reg 0x%x\n",
387 readl(priv(dev)->plx9080_iobase + PLX_CONTROL_REG));
389 DEBUG_PRINT(" plx revision 0x%x\n",
390 readl(plx_iobase + PLX_REVISION_REG));
391 DEBUG_PRINT(" plx dma channel 0 mode 0x%x\n",
392 readl(plx_iobase + PLX_DMA0_MODE_REG));
393 DEBUG_PRINT(" plx dma channel 1 mode 0x%x\n",
394 readl(plx_iobase + PLX_DMA1_MODE_REG));
395 DEBUG_PRINT(" plx dma channel 0 pci address 0x%x\n",
396 readl(plx_iobase + PLX_DMA0_PCI_ADDRESS_REG));
397 DEBUG_PRINT(" plx dma channel 0 local address 0x%x\n",
398 readl(plx_iobase + PLX_DMA0_LOCAL_ADDRESS_REG));
399 DEBUG_PRINT(" plx dma channel 0 transfer size 0x%x\n",
400 readl(plx_iobase + PLX_DMA0_TRANSFER_SIZE_REG));
401 DEBUG_PRINT(" plx dma channel 0 descriptor 0x%x\n",
402 readl(plx_iobase + PLX_DMA0_DESCRIPTOR_REG));
403 DEBUG_PRINT(" plx dma channel 0 command status 0x%x\n",
404 readb(plx_iobase + PLX_DMA0_CS_REG));
405 DEBUG_PRINT(" plx dma channel 0 threshold 0x%x\n",
406 readl(plx_iobase + PLX_DMA0_THRESHOLD_REG));
407 DEBUG_PRINT(" plx bigend 0x%x\n", readl(plx_iobase + PLX_BIGEND_REG));
409 bits = BIGEND_DMA0 | BIGEND_DMA1;
413 writel(bits, priv(dev)->plx9080_iobase + PLX_BIGEND_REG);
415 disable_plx_interrupts(dev);
420 // configure dma0 mode
422 // enable ready input
423 bits |= PLX_DMA_EN_READYIN_BIT;
424 // enable dma chaining
425 bits |= PLX_EN_CHAIN_BIT;
426 // enable interrupt on dma done (probably don't need this, since chain never finishes)
427 bits |= PLX_EN_DMA_DONE_INTR_BIT;
428 // don't increment local address during transfers (we are transferring from a fixed fifo register)
429 bits |= PLX_LOCAL_ADDR_CONST_BIT;
430 // route dma interrupt to pci bus
431 bits |= PLX_DMA_INTR_PCI_BIT;
432 // enable demand mode
433 bits |= PLX_DEMAND_MODE_BIT;
434 // enable local burst mode
435 bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
436 bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
437 writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
440 /* Allocate and initialize the subdevice structures.
442 static int setup_subdevices(struct comedi_device * dev)
444 struct comedi_subdevice *s;
446 if (alloc_subdevices(dev, 1) < 0)
449 s = dev->subdevices + 0;
450 /* analog input subdevice */
451 dev->read_subdev = s;
452 /* dev->write_subdev = s; */
453 s->type = COMEDI_SUBD_DIO;
455 SDF_READABLE | SDF_WRITEABLE | SDF_LSAMPL | SDF_CMD_READ;
457 s->len_chanlist = 32;
459 s->range_table = &range_digital;
460 s->insn_config = dio_config_insn;
461 s->do_cmd = hpdi_cmd;
462 s->do_cmdtest = hpdi_cmd_test;
463 s->cancel = hpdi_cancel;
468 static int init_hpdi(struct comedi_device * dev)
470 uint32_t plx_intcsr_bits;
472 writel(BOARD_RESET_BIT, priv(dev)->hpdi_iobase + BOARD_CONTROL_REG);
475 writel(almost_empty_bits(32) | almost_full_bits(32),
476 priv(dev)->hpdi_iobase + RX_PROG_ALMOST_REG);
477 writel(almost_empty_bits(32) | almost_full_bits(32),
478 priv(dev)->hpdi_iobase + TX_PROG_ALMOST_REG);
480 priv(dev)->tx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
482 priv(dev)->rx_fifo_size = fifo_size(readl(priv(dev)->hpdi_iobase +
485 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
489 ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
491 writel(plx_intcsr_bits, priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
496 // setup dma descriptors so a link completes every 'transfer_size' bytes
497 static int setup_dma_descriptors(struct comedi_device * dev,
498 unsigned int transfer_size)
500 unsigned int buffer_index, buffer_offset;
501 uint32_t next_bits = PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
502 PLX_XFER_LOCAL_TO_PCI;
505 if (transfer_size > DMA_BUFFER_SIZE)
506 transfer_size = DMA_BUFFER_SIZE;
507 transfer_size -= transfer_size % sizeof(uint32_t);
508 if (transfer_size == 0)
511 DEBUG_PRINT(" transfer_size %i\n", transfer_size);
512 DEBUG_PRINT(" descriptors at 0x%lx\n",
513 (unsigned long)priv(dev)->dma_desc_phys_addr);
517 for (i = 0; i < NUM_DMA_DESCRIPTORS &&
518 buffer_index < NUM_DMA_BUFFERS; i++) {
519 priv(dev)->dma_desc[i].pci_start_addr =
520 cpu_to_le32(priv(dev)->
521 dio_buffer_phys_addr[buffer_index] + buffer_offset);
522 priv(dev)->dma_desc[i].local_start_addr = cpu_to_le32(FIFO_REG);
523 priv(dev)->dma_desc[i].transfer_size =
524 cpu_to_le32(transfer_size);
525 priv(dev)->dma_desc[i].next =
526 cpu_to_le32((priv(dev)->dma_desc_phys_addr + (i +
528 sizeof(priv(dev)->dma_desc[0])) | next_bits);
530 priv(dev)->desc_dio_buffer[i] =
531 priv(dev)->dio_buffer[buffer_index] +
532 (buffer_offset / sizeof(uint32_t));
534 buffer_offset += transfer_size;
535 if (transfer_size + buffer_offset > DMA_BUFFER_SIZE) {
540 DEBUG_PRINT(" desc %i\n", i);
541 DEBUG_PRINT(" start addr virt 0x%p, phys 0x%lx\n",
542 priv(dev)->desc_dio_buffer[i],
543 (unsigned long)priv(dev)->dma_desc[i].pci_start_addr);
544 DEBUG_PRINT(" next 0x%lx\n",
545 (unsigned long)priv(dev)->dma_desc[i].next);
547 priv(dev)->num_dma_descriptors = i;
548 // fix last descriptor to point back to first
549 priv(dev)->dma_desc[i - 1].next =
550 cpu_to_le32(priv(dev)->dma_desc_phys_addr | next_bits);
551 DEBUG_PRINT(" desc %i next fixup 0x%lx\n", i - 1,
552 (unsigned long)priv(dev)->dma_desc[i - 1].next);
554 priv(dev)->block_size = transfer_size;
556 return transfer_size;
559 static int hpdi_attach(struct comedi_device * dev, struct comedi_devconfig * it)
561 struct pci_dev *pcidev;
565 printk("comedi%d: gsc_hpdi\n", dev->minor);
567 if (alloc_private(dev, sizeof(struct hpdi_private)) < 0)
571 for (i = 0; i < num_boards() && dev->board_ptr == NULL; i++) {
573 pcidev = pci_get_subsys(PCI_VENDOR_ID_PLX,
574 hpdi_boards[i].device_id, PCI_VENDOR_ID_PLX,
575 hpdi_boards[i].subdevice_id, pcidev);
576 // was a particular bus/slot requested?
577 if (it->options[0] || it->options[1]) {
578 // are we on the wrong bus/slot?
579 if (pcidev->bus->number != it->options[0] ||
580 PCI_SLOT(pcidev->devfn) !=
585 priv(dev)->hw_dev = pcidev;
586 dev->board_ptr = hpdi_boards + i;
589 } while (pcidev != NULL);
591 if (dev->board_ptr == NULL) {
592 printk("gsc_hpdi: no hpdi card found\n");
596 printk("gsc_hpdi: found %s on bus %i, slot %i\n", board(dev)->name,
597 pcidev->bus->number, PCI_SLOT(pcidev->devfn));
599 if (comedi_pci_enable(pcidev, driver_hpdi.driver_name)) {
601 " failed enable PCI device and request regions\n");
604 pci_set_master(pcidev);
606 //Initialize dev->board_name
607 dev->board_name = board(dev)->name;
609 priv(dev)->plx9080_phys_iobase =
610 pci_resource_start(pcidev, PLX9080_BADDRINDEX);
611 priv(dev)->hpdi_phys_iobase =
612 pci_resource_start(pcidev, HPDI_BADDRINDEX);
614 // remap, won't work with 2.0 kernels but who cares
615 priv(dev)->plx9080_iobase = ioremap(priv(dev)->plx9080_phys_iobase,
616 pci_resource_len(pcidev, PLX9080_BADDRINDEX));
617 priv(dev)->hpdi_iobase = ioremap(priv(dev)->hpdi_phys_iobase,
618 pci_resource_len(pcidev, HPDI_BADDRINDEX));
619 if (!priv(dev)->plx9080_iobase || !priv(dev)->hpdi_iobase) {
620 printk(" failed to remap io memory\n");
624 DEBUG_PRINT(" plx9080 remapped to 0x%p\n", priv(dev)->plx9080_iobase);
625 DEBUG_PRINT(" hpdi remapped to 0x%p\n", priv(dev)->hpdi_iobase);
630 if (comedi_request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
631 driver_hpdi.driver_name, dev)) {
632 printk(" unable to allocate irq %u\n", pcidev->irq);
635 dev->irq = pcidev->irq;
637 printk(" irq %u\n", dev->irq);
639 // alocate pci dma buffers
640 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
641 priv(dev)->dio_buffer[i] =
642 pci_alloc_consistent(priv(dev)->hw_dev, DMA_BUFFER_SIZE,
643 &priv(dev)->dio_buffer_phys_addr[i]);
644 DEBUG_PRINT("dio_buffer at virt 0x%p, phys 0x%lx\n",
645 priv(dev)->dio_buffer[i],
646 (unsigned long)priv(dev)->dio_buffer_phys_addr[i]);
648 // allocate dma descriptors
649 priv(dev)->dma_desc = pci_alloc_consistent(priv(dev)->hw_dev,
650 sizeof(struct plx_dma_desc) * NUM_DMA_DESCRIPTORS,
651 &priv(dev)->dma_desc_phys_addr);
652 if (priv(dev)->dma_desc_phys_addr & 0xf) {
653 printk(" dma descriptors not quad-word aligned (bug)\n");
657 retval = setup_dma_descriptors(dev, 0x1000);
661 retval = setup_subdevices(dev);
665 return init_hpdi(dev);
668 static int hpdi_detach(struct comedi_device * dev)
672 printk("comedi%d: gsc_hpdi: remove\n", dev->minor);
675 comedi_free_irq(dev->irq, dev);
677 if (priv(dev)->hw_dev) {
678 if (priv(dev)->plx9080_iobase) {
679 disable_plx_interrupts(dev);
680 iounmap((void *)priv(dev)->plx9080_iobase);
682 if (priv(dev)->hpdi_iobase)
683 iounmap((void *)priv(dev)->hpdi_iobase);
684 // free pci dma buffers
685 for (i = 0; i < NUM_DMA_BUFFERS; i++) {
686 if (priv(dev)->dio_buffer[i])
687 pci_free_consistent(priv(dev)->hw_dev,
689 priv(dev)->dio_buffer[i],
691 dio_buffer_phys_addr[i]);
693 // free dma descriptors
694 if (priv(dev)->dma_desc)
695 pci_free_consistent(priv(dev)->hw_dev,
696 sizeof(struct plx_dma_desc) *
699 priv(dev)->dma_desc_phys_addr);
700 if (priv(dev)->hpdi_phys_iobase) {
701 comedi_pci_disable(priv(dev)->hw_dev);
703 pci_dev_put(priv(dev)->hw_dev);
709 static int dio_config_block_size(struct comedi_device * dev, unsigned int * data)
711 unsigned int requested_block_size;
714 requested_block_size = data[1];
716 retval = setup_dma_descriptors(dev, requested_block_size);
725 static int di_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
726 struct comedi_cmd * cmd)
732 /* step 1: make sure trigger sources are trivially valid */
734 tmp = cmd->start_src;
735 cmd->start_src &= TRIG_NOW;
736 if (!cmd->start_src || tmp != cmd->start_src)
739 tmp = cmd->scan_begin_src;
740 cmd->scan_begin_src &= TRIG_EXT;
741 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
744 tmp = cmd->convert_src;
745 cmd->convert_src &= TRIG_NOW;
746 if (!cmd->convert_src || tmp != cmd->convert_src)
749 tmp = cmd->scan_end_src;
750 cmd->scan_end_src &= TRIG_COUNT;
751 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
755 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
756 if (!cmd->stop_src || tmp != cmd->stop_src)
762 /* step 2: make sure trigger sources are unique and mutually compatible */
765 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
771 /* step 3: make sure arguments are trivially compatible */
773 if (!cmd->chanlist_len) {
774 cmd->chanlist_len = 32;
777 if (cmd->scan_end_arg != cmd->chanlist_len) {
778 cmd->scan_end_arg = cmd->chanlist_len;
782 switch (cmd->stop_src) {
784 if (!cmd->stop_arg) {
790 if (cmd->stop_arg != 0) {
802 /* step 4: fix up any arguments */
808 for (i = 1; i < cmd->chanlist_len; i++) {
809 if (CR_CHAN(cmd->chanlist[i]) != i) {
810 // XXX could support 8 channels or 16 channels
812 "chanlist must be channels 0 to 31 in order");
825 static int hpdi_cmd_test(struct comedi_device * dev, struct comedi_subdevice * s,
826 struct comedi_cmd * cmd)
828 if (priv(dev)->dio_config_output) {
831 return di_cmd_test(dev, s, cmd);
834 static inline void hpdi_writel(struct comedi_device * dev, uint32_t bits,
837 writel(bits | priv(dev)->bits[offset / sizeof(uint32_t)],
838 priv(dev)->hpdi_iobase + offset);
841 static int di_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
845 struct comedi_async *async = s->async;
846 struct comedi_cmd *cmd = &async->cmd;
848 hpdi_writel(dev, RX_FIFO_RESET_BIT, BOARD_CONTROL_REG);
850 DEBUG_PRINT("hpdi: in di_cmd\n");
854 priv(dev)->dma_desc_index = 0;
856 /* These register are supposedly unused during chained dma,
857 * but I have found that left over values from last operation
858 * occasionally cause problems with transfer of first dma
859 * block. Initializing them to zero seems to fix the problem. */
860 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
861 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
862 writel(0, priv(dev)->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
863 // give location of first dma descriptor
865 dma_desc_phys_addr | PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
866 PLX_XFER_LOCAL_TO_PCI;
867 writel(bits, priv(dev)->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
869 // spinlock for plx dma control/status reg
870 comedi_spin_lock_irqsave(&dev->spinlock, flags);
871 // enable dma transfer
872 writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT | PLX_CLEAR_DMA_INTR_BIT,
873 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
874 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
876 if (cmd->stop_src == TRIG_COUNT)
877 priv(dev)->dio_count = cmd->stop_arg;
879 priv(dev)->dio_count = 1;
881 // clear over/under run status flags
882 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT,
883 priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
885 writel(intr_bit(RX_FULL_INTR),
886 priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);
888 DEBUG_PRINT("hpdi: starting rx\n");
889 hpdi_writel(dev, RX_ENABLE_BIT, BOARD_CONTROL_REG);
894 static int hpdi_cmd(struct comedi_device * dev, struct comedi_subdevice * s)
896 if (priv(dev)->dio_config_output) {
899 return di_cmd(dev, s);
902 static void drain_dma_buffers(struct comedi_device * dev, unsigned int channel)
904 struct comedi_async *async = dev->read_subdev->async;
905 uint32_t next_transfer_addr;
912 priv(dev)->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
915 priv(dev)->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
917 // loop until we have read all the full buffers
919 for (next_transfer_addr = readl(pci_addr_reg);
920 (next_transfer_addr <
921 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->
922 dma_desc_index].pci_start_addr)
923 || next_transfer_addr >=
924 le32_to_cpu(priv(dev)->dma_desc[priv(dev)->
925 dma_desc_index].pci_start_addr) +
926 priv(dev)->block_size)
927 && j < priv(dev)->num_dma_descriptors; j++) {
928 // transfer data from dma buffer to comedi buffer
929 num_samples = priv(dev)->block_size / sizeof(uint32_t);
930 if (async->cmd.stop_src == TRIG_COUNT) {
931 if (num_samples > priv(dev)->dio_count)
932 num_samples = priv(dev)->dio_count;
933 priv(dev)->dio_count -= num_samples;
935 cfc_write_array_to_buffer(dev->read_subdev,
936 priv(dev)->desc_dio_buffer[priv(dev)->dma_desc_index],
937 num_samples * sizeof(uint32_t));
938 priv(dev)->dma_desc_index++;
939 priv(dev)->dma_desc_index %= priv(dev)->num_dma_descriptors;
941 DEBUG_PRINT("next desc addr 0x%lx\n", (unsigned long)
942 priv(dev)->dma_desc[priv(dev)->dma_desc_index].next);
943 DEBUG_PRINT("pci addr reg 0x%x\n", next_transfer_addr);
945 // XXX check for buffer overrun somehow
948 static irqreturn_t handle_interrupt(int irq, void *d PT_REGS_ARG)
950 struct comedi_device *dev = d;
951 struct comedi_subdevice *s = dev->read_subdev;
952 struct comedi_async *async = s->async;
953 uint32_t hpdi_intr_status, hpdi_board_status;
956 uint8_t dma0_status, dma1_status;
959 if (!dev->attached) {
963 plx_status = readl(priv(dev)->plx9080_iobase + PLX_INTRCS_REG);
964 if ((plx_status & (ICS_DMA0_A | ICS_DMA1_A | ICS_LIA)) == 0) {
968 hpdi_intr_status = readl(priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
969 hpdi_board_status = readl(priv(dev)->hpdi_iobase + BOARD_STATUS_REG);
973 if (hpdi_intr_status) {
974 DEBUG_PRINT("hpdi: intr status 0x%x, ", hpdi_intr_status);
975 writel(hpdi_intr_status,
976 priv(dev)->hpdi_iobase + INTERRUPT_STATUS_REG);
978 // spin lock makes sure noone else changes plx dma control reg
979 comedi_spin_lock_irqsave(&dev->spinlock, flags);
980 dma0_status = readb(priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
981 if (plx_status & ICS_DMA0_A) { // dma chan 0 interrupt
982 writeb((dma0_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
983 priv(dev)->plx9080_iobase + PLX_DMA0_CS_REG);
985 DEBUG_PRINT("dma0 status 0x%x\n", dma0_status);
986 if (dma0_status & PLX_DMA_EN_BIT) {
987 drain_dma_buffers(dev, 0);
989 DEBUG_PRINT(" cleared dma ch0 interrupt\n");
991 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
993 // spin lock makes sure noone else changes plx dma control reg
994 comedi_spin_lock_irqsave(&dev->spinlock, flags);
995 dma1_status = readb(priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
996 if (plx_status & ICS_DMA1_A) // XXX
997 { // dma chan 1 interrupt
998 writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
999 priv(dev)->plx9080_iobase + PLX_DMA1_CS_REG);
1000 DEBUG_PRINT("dma1 status 0x%x\n", dma1_status);
1002 DEBUG_PRINT(" cleared dma ch1 interrupt\n");
1004 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1006 // clear possible plx9080 interrupt sources
1007 if (plx_status & ICS_LDIA) { // clear local doorbell interrupt
1008 plx_bits = readl(priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1009 writel(plx_bits, priv(dev)->plx9080_iobase + PLX_DBR_OUT_REG);
1010 DEBUG_PRINT(" cleared local doorbell bits 0x%x\n", plx_bits);
1013 if (hpdi_board_status & RX_OVERRUN_BIT) {
1014 comedi_error(dev, "rx fifo overrun");
1015 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1016 DEBUG_PRINT("dma0_status 0x%x\n",
1017 (int)readb(priv(dev)->plx9080_iobase +
1021 if (hpdi_board_status & RX_UNDERRUN_BIT) {
1022 comedi_error(dev, "rx fifo underrun");
1023 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1026 if (priv(dev)->dio_count == 0)
1027 async->events |= COMEDI_CB_EOA;
1029 DEBUG_PRINT("board status 0x%x, ", hpdi_board_status);
1030 DEBUG_PRINT("plx status 0x%x\n", plx_status);
1032 DEBUG_PRINT(" events 0x%x\n", async->events);
1034 cfc_handle_events(dev, s);
1039 void abort_dma(struct comedi_device * dev, unsigned int channel)
1041 unsigned long flags;
1043 // spinlock for plx dma control/status reg
1044 comedi_spin_lock_irqsave(&dev->spinlock, flags);
1046 plx9080_abort_dma(priv(dev)->plx9080_iobase, channel);
1048 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1051 static int hpdi_cancel(struct comedi_device * dev, struct comedi_subdevice * s)
1053 hpdi_writel(dev, 0, BOARD_CONTROL_REG);
1055 writel(0, priv(dev)->hpdi_iobase + INTERRUPT_CONTROL_REG);