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   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  70 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  71
  72 #define R8169_REGS_SIZE         256
  73 #define R8169_NAPI_WEIGHT       64
  74 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  75 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  76 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  77 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  78 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  79
  80 #define RTL8169_TX_TIMEOUT      (6*HZ)
  81 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  82
  83 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  84 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  85 #define RTL_EEPROM_SIG_ADDR     0x0000
  86
  87 /* write/read MMIO register */
  88 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  89 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  90 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  91 #define RTL_R8(reg)             readb (ioaddr + (reg))
  92 #define RTL_R16(reg)            readw (ioaddr + (reg))
  93 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  94
  95 enum mac_version {
  96         RTL_GIGA_MAC_NONE   = 0x00,
  97         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  98         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  99         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 100         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 101         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 102         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 103         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 104         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 105         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 106         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 107         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 108         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 109         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 110         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 111         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 112         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 113         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 114         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 115         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 116         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 117         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 118         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 119         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 120         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 121         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
 122 };
 123
 124 #define _R(NAME,MAC,MASK) \
 125         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 126
 127 static const struct {
 128         const char *name;
 129         u8 mac_version;
 130         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 131 } rtl_chip_info[] = {
 132         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 133         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 134         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 135         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 136         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 137         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 138         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 139         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 140         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 141         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 142         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 144         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 145         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 148         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 149         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 150         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 151         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 152         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 153         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 154         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 155         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 156         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
 157 };
 158 #undef _R
 159
 160 enum cfg_version {
 161         RTL_CFG_0 = 0x00,
 162         RTL_CFG_1,
 163         RTL_CFG_2
 164 };
 165
 166 static void rtl_hw_start_8169(struct net_device *);
 167 static void rtl_hw_start_8168(struct net_device *);
 168 static void rtl_hw_start_8101(struct net_device *);
 169
 170 static struct pci_device_id rtl8169_pci_tbl[] = {
 171         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 172         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 173         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 174         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 175         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 176         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 177         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 178         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 179         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 180                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 181         { 0x0001,                               0x8168,
 182                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 183         {0,},
 184 };
 185
 186 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 187
 188 static int rx_copybreak = 200;
 189 static int use_dac;
 190 static struct {
 191         u32 msg_enable;
 192 } debug = { -1 };
 193
 194 enum rtl_registers {
 195         MAC0            = 0,    /* Ethernet hardware address. */
 196         MAC4            = 4,
 197         MAR0            = 8,    /* Multicast filter. */
 198         CounterAddrLow          = 0x10,
 199         CounterAddrHigh         = 0x14,
 200         TxDescStartAddrLow      = 0x20,
 201         TxDescStartAddrHigh     = 0x24,
 202         TxHDescStartAddrLow     = 0x28,
 203         TxHDescStartAddrHigh    = 0x2c,
 204         FLASH           = 0x30,
 205         ERSR            = 0x36,
 206         ChipCmd         = 0x37,
 207         TxPoll          = 0x38,
 208         IntrMask        = 0x3c,
 209         IntrStatus      = 0x3e,
 210         TxConfig        = 0x40,
 211         RxConfig        = 0x44,
 212         RxMissed        = 0x4c,
 213         Cfg9346         = 0x50,
 214         Config0         = 0x51,
 215         Config1         = 0x52,
 216         Config2         = 0x53,
 217         Config3         = 0x54,
 218         Config4         = 0x55,
 219         Config5         = 0x56,
 220         MultiIntr       = 0x5c,
 221         PHYAR           = 0x60,
 222         PHYstatus       = 0x6c,
 223         RxMaxSize       = 0xda,
 224         CPlusCmd        = 0xe0,
 225         IntrMitigate    = 0xe2,
 226         RxDescAddrLow   = 0xe4,
 227         RxDescAddrHigh  = 0xe8,
 228         EarlyTxThres    = 0xec,
 229         FuncEvent       = 0xf0,
 230         FuncEventMask   = 0xf4,
 231         FuncPresetState = 0xf8,
 232         FuncForceEvent  = 0xfc,
 233 };
 234
 235 enum rtl8110_registers {
 236         TBICSR                  = 0x64,
 237         TBI_ANAR                = 0x68,
 238         TBI_LPAR                = 0x6a,
 239 };
 240
 241 enum rtl8168_8101_registers {
 242         CSIDR                   = 0x64,
 243         CSIAR                   = 0x68,
 244 #define CSIAR_FLAG                      0x80000000
 245 #define CSIAR_WRITE_CMD                 0x80000000
 246 #define CSIAR_BYTE_ENABLE               0x0f
 247 #define CSIAR_BYTE_ENABLE_SHIFT         12
 248 #define CSIAR_ADDR_MASK                 0x0fff
 249
 250         EPHYAR                  = 0x80,
 251 #define EPHYAR_FLAG                     0x80000000
 252 #define EPHYAR_WRITE_CMD                0x80000000
 253 #define EPHYAR_REG_MASK                 0x1f
 254 #define EPHYAR_REG_SHIFT                16
 255 #define EPHYAR_DATA_MASK                0xffff
 256         DBG_REG                 = 0xd1,
 257 #define FIX_NAK_1                       (1 << 4)
 258 #define FIX_NAK_2                       (1 << 3)
 259 };
 260
 261 enum rtl_register_content {
 262         /* InterruptStatusBits */
 263         SYSErr          = 0x8000,
 264         PCSTimeout      = 0x4000,
 265         SWInt           = 0x0100,
 266         TxDescUnavail   = 0x0080,
 267         RxFIFOOver      = 0x0040,
 268         LinkChg         = 0x0020,
 269         RxOverflow      = 0x0010,
 270         TxErr           = 0x0008,
 271         TxOK            = 0x0004,
 272         RxErr           = 0x0002,
 273         RxOK            = 0x0001,
 274
 275         /* RxStatusDesc */
 276         RxFOVF  = (1 << 23),
 277         RxRWT   = (1 << 22),
 278         RxRES   = (1 << 21),
 279         RxRUNT  = (1 << 20),
 280         RxCRC   = (1 << 19),
 281
 282         /* ChipCmdBits */
 283         CmdReset        = 0x10,
 284         CmdRxEnb        = 0x08,
 285         CmdTxEnb        = 0x04,
 286         RxBufEmpty      = 0x01,
 287
 288         /* TXPoll register p.5 */
 289         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 290         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 291         FSWInt          = 0x01,         /* Forced software interrupt */
 292
 293         /* Cfg9346Bits */
 294         Cfg9346_Lock    = 0x00,
 295         Cfg9346_Unlock  = 0xc0,
 296
 297         /* rx_mode_bits */
 298         AcceptErr       = 0x20,
 299         AcceptRunt      = 0x10,
 300         AcceptBroadcast = 0x08,
 301         AcceptMulticast = 0x04,
 302         AcceptMyPhys    = 0x02,
 303         AcceptAllPhys   = 0x01,
 304
 305         /* RxConfigBits */
 306         RxCfgFIFOShift  = 13,
 307         RxCfgDMAShift   =  8,
 308
 309         /* TxConfigBits */
 310         TxInterFrameGapShift = 24,
 311         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 312
 313         /* Config1 register p.24 */
 314         LEDS1           = (1 << 7),
 315         LEDS0           = (1 << 6),
 316         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 317         Speed_down      = (1 << 4),
 318         MEMMAP          = (1 << 3),
 319         IOMAP           = (1 << 2),
 320         VPD             = (1 << 1),
 321         PMEnable        = (1 << 0),     /* Power Management Enable */
 322
 323         /* Config2 register p. 25 */
 324         PCI_Clock_66MHz = 0x01,
 325         PCI_Clock_33MHz = 0x00,
 326
 327         /* Config3 register p.25 */
 328         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 329         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 330         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 331
 332         /* Config5 register p.27 */
 333         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 334         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 335         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 336         LanWake         = (1 << 1),     /* LanWake enable/disable */
 337         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 338
 339         /* TBICSR p.28 */
 340         TBIReset        = 0x80000000,
 341         TBILoopback     = 0x40000000,
 342         TBINwEnable     = 0x20000000,
 343         TBINwRestart    = 0x10000000,
 344         TBILinkOk       = 0x02000000,
 345         TBINwComplete   = 0x01000000,
 346
 347         /* CPlusCmd p.31 */
 348         EnableBist      = (1 << 15),    // 8168 8101
 349         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 350         Normal_mode     = (1 << 13),    // unused
 351         Force_half_dup  = (1 << 12),    // 8168 8101
 352         Force_rxflow_en = (1 << 11),    // 8168 8101
 353         Force_txflow_en = (1 << 10),    // 8168 8101
 354         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 355         ASF             = (1 << 8),     // 8168 8101
 356         PktCntrDisable  = (1 << 7),     // 8168 8101
 357         Mac_dbgo_sel    = 0x001c,       // 8168
 358         RxVlan          = (1 << 6),
 359         RxChkSum        = (1 << 5),
 360         PCIDAC          = (1 << 4),
 361         PCIMulRW        = (1 << 3),
 362         INTT_0          = 0x0000,       // 8168
 363         INTT_1          = 0x0001,       // 8168
 364         INTT_2          = 0x0002,       // 8168
 365         INTT_3          = 0x0003,       // 8168
 366
 367         /* rtl8169_PHYstatus */
 368         TBI_Enable      = 0x80,
 369         TxFlowCtrl      = 0x40,
 370         RxFlowCtrl      = 0x20,
 371         _1000bpsF       = 0x10,
 372         _100bps         = 0x08,
 373         _10bps          = 0x04,
 374         LinkStatus      = 0x02,
 375         FullDup         = 0x01,
 376
 377         /* _TBICSRBit */
 378         TBILinkOK       = 0x02000000,
 379
 380         /* DumpCounterCommand */
 381         CounterDump     = 0x8,
 382 };
 383
 384 enum desc_status_bit {
 385         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 386         RingEnd         = (1 << 30), /* End of descriptor ring */
 387         FirstFrag       = (1 << 29), /* First segment of a packet */
 388         LastFrag        = (1 << 28), /* Final segment of a packet */
 389
 390         /* Tx private */
 391         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 392         MSSShift        = 16,        /* MSS value position */
 393         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 394         IPCS            = (1 << 18), /* Calculate IP checksum */
 395         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 396         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 397         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 398
 399         /* Rx private */
 400         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 401         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 402
 403 #define RxProtoUDP      (PID1)
 404 #define RxProtoTCP      (PID0)
 405 #define RxProtoIP       (PID1 | PID0)
 406 #define RxProtoMask     RxProtoIP
 407
 408         IPFail          = (1 << 16), /* IP checksum failed */
 409         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 410         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 411         RxVlanTag       = (1 << 16), /* VLAN tag available */
 412 };
 413
 414 #define RsvdMask        0x3fffc000
 415
 416 struct TxDesc {
 417         __le32 opts1;
 418         __le32 opts2;
 419         __le64 addr;
 420 };
 421
 422 struct RxDesc {
 423         __le32 opts1;
 424         __le32 opts2;
 425         __le64 addr;
 426 };
 427
 428 struct ring_info {
 429         struct sk_buff  *skb;
 430         u32             len;
 431         u8              __pad[sizeof(void *) - sizeof(u32)];
 432 };
 433
 434 enum features {
 435         RTL_FEATURE_WOL         = (1 << 0),
 436         RTL_FEATURE_MSI         = (1 << 1),
 437         RTL_FEATURE_GMII        = (1 << 2),
 438 };
 439
 440 struct rtl8169_counters {
 441         __le64  tx_packets;
 442         __le64  rx_packets;
 443         __le64  tx_errors;
 444         __le32  rx_errors;
 445         __le16  rx_missed;
 446         __le16  align_errors;
 447         __le32  tx_one_collision;
 448         __le32  tx_multi_collision;
 449         __le64  rx_unicast;
 450         __le64  rx_broadcast;
 451         __le32  rx_multicast;
 452         __le16  tx_aborted;
 453         __le16  tx_underun;
 454 };
 455
 456 struct rtl8169_private {
 457         void __iomem *mmio_addr;        /* memory map physical address */
 458         struct pci_dev *pci_dev;        /* Index of PCI device */
 459         struct net_device *dev;
 460         struct napi_struct napi;
 461         spinlock_t lock;                /* spin lock flag */
 462         u32 msg_enable;
 463         int chipset;
 464         int mac_version;
 465         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 466         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 467         u32 dirty_rx;
 468         u32 dirty_tx;
 469         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 470         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 471         dma_addr_t TxPhyAddr;
 472         dma_addr_t RxPhyAddr;
 473         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 474         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 475         unsigned align;
 476         unsigned rx_buf_sz;
 477         struct timer_list timer;
 478         u16 cp_cmd;
 479         u16 intr_event;
 480         u16 napi_event;
 481         u16 intr_mask;
 482         int phy_1000_ctrl_reg;
 483 #ifdef CONFIG_R8169_VLAN
 484         struct vlan_group *vlgrp;
 485 #endif
 486         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 487         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 488         void (*phy_reset_enable)(void __iomem *);
 489         void (*hw_start)(struct net_device *);
 490         unsigned int (*phy_reset_pending)(void __iomem *);
 491         unsigned int (*link_ok)(void __iomem *);
 492         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 493         int pcie_cap;
 494         struct delayed_work task;
 495         unsigned features;
 496
 497         struct mii_if_info mii;
 498         struct rtl8169_counters counters;
 499 };
 500
 501 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 502 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 503 module_param(rx_copybreak, int, 0);
 504 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 505 module_param(use_dac, int, 0);
 506 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 507 module_param_named(debug, debug.msg_enable, int, 0);
 508 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 509 MODULE_LICENSE("GPL");
 510 MODULE_VERSION(RTL8169_VERSION);
 511
 512 static int rtl8169_open(struct net_device *dev);
 513 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 514 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 515 static int rtl8169_init_ring(struct net_device *dev);
 516 static void rtl_hw_start(struct net_device *dev);
 517 static int rtl8169_close(struct net_device *dev);
 518 static void rtl_set_rx_mode(struct net_device *dev);
 519 static void rtl8169_tx_timeout(struct net_device *dev);
 520 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 521 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 522                                 void __iomem *, u32 budget);
 523 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 524 static void rtl8169_down(struct net_device *dev);
 525 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 526 static int rtl8169_poll(struct napi_struct *napi, int budget);
 527
 528 static const unsigned int rtl8169_rx_config =
 529         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 530
 531 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 532 {
 533         int i;
 534
 535         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 536
 537         for (i = 20; i > 0; i--) {
 538                 /*
 539                  * Check if the RTL8169 has completed writing to the specified
 540                  * MII register.
 541                  */
 542                 if (!(RTL_R32(PHYAR) & 0x80000000))
 543                         break;
 544                 udelay(25);
 545         }
 546 }
 547
 548 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 549 {
 550         int i, value = -1;
 551
 552         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 553
 554         for (i = 20; i > 0; i--) {
 555                 /*
 556                  * Check if the RTL8169 has completed retrieving data from
 557                  * the specified MII register.
 558                  */
 559                 if (RTL_R32(PHYAR) & 0x80000000) {
 560                         value = RTL_R32(PHYAR) & 0xffff;
 561                         break;
 562                 }
 563                 udelay(25);
 564         }
 565         return value;
 566 }
 567
 568 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 569 {
 570         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 571 }
 572
 573 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 574                            int val)
 575 {
 576         struct rtl8169_private *tp = netdev_priv(dev);
 577         void __iomem *ioaddr = tp->mmio_addr;
 578
 579         mdio_write(ioaddr, location, val);
 580 }
 581
 582 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 583 {
 584         struct rtl8169_private *tp = netdev_priv(dev);
 585         void __iomem *ioaddr = tp->mmio_addr;
 586
 587         return mdio_read(ioaddr, location);
 588 }
 589
 590 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 591 {
 592         unsigned int i;
 593
 594         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 595                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 596
 597         for (i = 0; i < 100; i++) {
 598                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 599                         break;
 600                 udelay(10);
 601         }
 602 }
 603
 604 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 605 {
 606         u16 value = 0xffff;
 607         unsigned int i;
 608
 609         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 610
 611         for (i = 0; i < 100; i++) {
 612                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 613                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 614                         break;
 615                 }
 616                 udelay(10);
 617         }
 618
 619         return value;
 620 }
 621
 622 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 623 {
 624         unsigned int i;
 625
 626         RTL_W32(CSIDR, value);
 627         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 628                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 629
 630         for (i = 0; i < 100; i++) {
 631                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 632                         break;
 633                 udelay(10);
 634         }
 635 }
 636
 637 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 638 {
 639         u32 value = ~0x00;
 640         unsigned int i;
 641
 642         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 643                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 644
 645         for (i = 0; i < 100; i++) {
 646                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 647                         value = RTL_R32(CSIDR);
 648                         break;
 649                 }
 650                 udelay(10);
 651         }
 652
 653         return value;
 654 }
 655
 656 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 657 {
 658         RTL_W16(IntrMask, 0x0000);
 659
 660         RTL_W16(IntrStatus, 0xffff);
 661 }
 662
 663 static void rtl8169_asic_down(void __iomem *ioaddr)
 664 {
 665         RTL_W8(ChipCmd, 0x00);
 666         rtl8169_irq_mask_and_ack(ioaddr);
 667         RTL_R16(CPlusCmd);
 668 }
 669
 670 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 671 {
 672         return RTL_R32(TBICSR) & TBIReset;
 673 }
 674
 675 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 676 {
 677         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 678 }
 679
 680 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 681 {
 682         return RTL_R32(TBICSR) & TBILinkOk;
 683 }
 684
 685 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 686 {
 687         return RTL_R8(PHYstatus) & LinkStatus;
 688 }
 689
 690 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 691 {
 692         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 693 }
 694
 695 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 696 {
 697         unsigned int val;
 698
 699         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 700         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 701 }
 702
 703 static void rtl8169_check_link_status(struct net_device *dev,
 704                                       struct rtl8169_private *tp,
 705                                       void __iomem *ioaddr)
 706 {
 707         unsigned long flags;
 708
 709         spin_lock_irqsave(&tp->lock, flags);
 710         if (tp->link_ok(ioaddr)) {
 711                 netif_carrier_on(dev);
 712                 if (netif_msg_ifup(tp))
 713                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 714         } else {
 715                 if (netif_msg_ifdown(tp))
 716                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 717                 netif_carrier_off(dev);
 718         }
 719         spin_unlock_irqrestore(&tp->lock, flags);
 720 }
 721
 722 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 723 {
 724         struct rtl8169_private *tp = netdev_priv(dev);
 725         void __iomem *ioaddr = tp->mmio_addr;
 726         u8 options;
 727
 728         wol->wolopts = 0;
 729
 730 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 731         wol->supported = WAKE_ANY;
 732
 733         spin_lock_irq(&tp->lock);
 734
 735         options = RTL_R8(Config1);
 736         if (!(options & PMEnable))
 737                 goto out_unlock;
 738
 739         options = RTL_R8(Config3);
 740         if (options & LinkUp)
 741                 wol->wolopts |= WAKE_PHY;
 742         if (options & MagicPacket)
 743                 wol->wolopts |= WAKE_MAGIC;
 744
 745         options = RTL_R8(Config5);
 746         if (options & UWF)
 747                 wol->wolopts |= WAKE_UCAST;
 748         if (options & BWF)
 749                 wol->wolopts |= WAKE_BCAST;
 750         if (options & MWF)
 751                 wol->wolopts |= WAKE_MCAST;
 752
 753 out_unlock:
 754         spin_unlock_irq(&tp->lock);
 755 }
 756
 757 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 758 {
 759         struct rtl8169_private *tp = netdev_priv(dev);
 760         void __iomem *ioaddr = tp->mmio_addr;
 761         unsigned int i;
 762         static struct {
 763                 u32 opt;
 764                 u16 reg;
 765                 u8  mask;
 766         } cfg[] = {
 767                 { WAKE_ANY,   Config1, PMEnable },
 768                 { WAKE_PHY,   Config3, LinkUp },
 769                 { WAKE_MAGIC, Config3, MagicPacket },
 770                 { WAKE_UCAST, Config5, UWF },
 771                 { WAKE_BCAST, Config5, BWF },
 772                 { WAKE_MCAST, Config5, MWF },
 773                 { WAKE_ANY,   Config5, LanWake }
 774         };
 775
 776         spin_lock_irq(&tp->lock);
 777
 778         RTL_W8(Cfg9346, Cfg9346_Unlock);
 779
 780         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 781                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 782                 if (wol->wolopts & cfg[i].opt)
 783                         options |= cfg[i].mask;
 784                 RTL_W8(cfg[i].reg, options);
 785         }
 786
 787         RTL_W8(Cfg9346, Cfg9346_Lock);
 788
 789         if (wol->wolopts)
 790                 tp->features |= RTL_FEATURE_WOL;
 791         else
 792                 tp->features &= ~RTL_FEATURE_WOL;
 793         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 794
 795         spin_unlock_irq(&tp->lock);
 796
 797         return 0;
 798 }
 799
 800 static void rtl8169_get_drvinfo(struct net_device *dev,
 801                                 struct ethtool_drvinfo *info)
 802 {
 803         struct rtl8169_private *tp = netdev_priv(dev);
 804
 805         strcpy(info->driver, MODULENAME);
 806         strcpy(info->version, RTL8169_VERSION);
 807         strcpy(info->bus_info, pci_name(tp->pci_dev));
 808 }
 809
 810 static int rtl8169_get_regs_len(struct net_device *dev)
 811 {
 812         return R8169_REGS_SIZE;
 813 }
 814
 815 static int rtl8169_set_speed_tbi(struct net_device *dev,
 816                                  u8 autoneg, u16 speed, u8 duplex)
 817 {
 818         struct rtl8169_private *tp = netdev_priv(dev);
 819         void __iomem *ioaddr = tp->mmio_addr;
 820         int ret = 0;
 821         u32 reg;
 822
 823         reg = RTL_R32(TBICSR);
 824         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 825             (duplex == DUPLEX_FULL)) {
 826                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 827         } else if (autoneg == AUTONEG_ENABLE)
 828                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 829         else {
 830                 if (netif_msg_link(tp)) {
 831                         printk(KERN_WARNING "%s: "
 832                                "incorrect speed setting refused in TBI mode\n",
 833                                dev->name);
 834                 }
 835                 ret = -EOPNOTSUPP;
 836         }
 837
 838         return ret;
 839 }
 840
 841 static int rtl8169_set_speed_xmii(struct net_device *dev,
 842                                   u8 autoneg, u16 speed, u8 duplex)
 843 {
 844         struct rtl8169_private *tp = netdev_priv(dev);
 845         void __iomem *ioaddr = tp->mmio_addr;
 846         int giga_ctrl, bmcr;
 847
 848         if (autoneg == AUTONEG_ENABLE) {
 849                 int auto_nego;
 850
 851                 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 852                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 853                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 854                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 855
 856                 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 857                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 858
 859                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
 860                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
 861                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
 862                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
 863                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
 864                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
 865                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
 866                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
 867                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
 868                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 869                 } else if (netif_msg_link(tp)) {
 870                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 871                                dev->name);
 872                 }
 873
 874                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 875
 876                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 877                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 878                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 879                         /*
 880                          * Wake up the PHY.
 881                          * Vendor specific (0x1f) and reserved (0x0e) MII
 882                          * registers.
 883                          */
 884                         mdio_write(ioaddr, 0x1f, 0x0000);
 885                         mdio_write(ioaddr, 0x0e, 0x0000);
 886                 }
 887
 888                 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 889                 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 890         } else {
 891                 giga_ctrl = 0;
 892
 893                 if (speed == SPEED_10)
 894                         bmcr = 0;
 895                 else if (speed == SPEED_100)
 896                         bmcr = BMCR_SPEED100;
 897                 else
 898                         return -EINVAL;
 899
 900                 if (duplex == DUPLEX_FULL)
 901                         bmcr |= BMCR_FULLDPLX;
 902
 903                 mdio_write(ioaddr, 0x1f, 0x0000);
 904         }
 905
 906         tp->phy_1000_ctrl_reg = giga_ctrl;
 907
 908         mdio_write(ioaddr, MII_BMCR, bmcr);
 909
 910         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
 911             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
 912                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
 913                         mdio_write(ioaddr, 0x17, 0x2138);
 914                         mdio_write(ioaddr, 0x0e, 0x0260);
 915                 } else {
 916                         mdio_write(ioaddr, 0x17, 0x2108);
 917                         mdio_write(ioaddr, 0x0e, 0x0000);
 918                 }
 919         }
 920
 921         return 0;
 922 }
 923
 924 static int rtl8169_set_speed(struct net_device *dev,
 925                              u8 autoneg, u16 speed, u8 duplex)
 926 {
 927         struct rtl8169_private *tp = netdev_priv(dev);
 928         int ret;
 929
 930         ret = tp->set_speed(dev, autoneg, speed, duplex);
 931
 932         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 933                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 934
 935         return ret;
 936 }
 937
 938 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 939 {
 940         struct rtl8169_private *tp = netdev_priv(dev);
 941         unsigned long flags;
 942         int ret;
 943
 944         spin_lock_irqsave(&tp->lock, flags);
 945         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 946         spin_unlock_irqrestore(&tp->lock, flags);
 947
 948         return ret;
 949 }
 950
 951 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 952 {
 953         struct rtl8169_private *tp = netdev_priv(dev);
 954
 955         return tp->cp_cmd & RxChkSum;
 956 }
 957
 958 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 959 {
 960         struct rtl8169_private *tp = netdev_priv(dev);
 961         void __iomem *ioaddr = tp->mmio_addr;
 962         unsigned long flags;
 963
 964         spin_lock_irqsave(&tp->lock, flags);
 965
 966         if (data)
 967                 tp->cp_cmd |= RxChkSum;
 968         else
 969                 tp->cp_cmd &= ~RxChkSum;
 970
 971         RTL_W16(CPlusCmd, tp->cp_cmd);
 972         RTL_R16(CPlusCmd);
 973
 974         spin_unlock_irqrestore(&tp->lock, flags);
 975
 976         return 0;
 977 }
 978
 979 #ifdef CONFIG_R8169_VLAN
 980
 981 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 982                                       struct sk_buff *skb)
 983 {
 984         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 985                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 986 }
 987
 988 static void rtl8169_vlan_rx_register(struct net_device *dev,
 989                                      struct vlan_group *grp)
 990 {
 991         struct rtl8169_private *tp = netdev_priv(dev);
 992         void __iomem *ioaddr = tp->mmio_addr;
 993         unsigned long flags;
 994
 995         spin_lock_irqsave(&tp->lock, flags);
 996         tp->vlgrp = grp;
 997         if (tp->vlgrp)
 998                 tp->cp_cmd |= RxVlan;
 999         else
1000                 tp->cp_cmd &= ~RxVlan;
1001         RTL_W16(CPlusCmd, tp->cp_cmd);
1002         RTL_R16(CPlusCmd);
1003         spin_unlock_irqrestore(&tp->lock, flags);
1004 }
1005
1006 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1007                                struct sk_buff *skb)
1008 {
1009         u32 opts2 = le32_to_cpu(desc->opts2);
1010         struct vlan_group *vlgrp = tp->vlgrp;
1011         int ret;
1012
1013         if (vlgrp && (opts2 & RxVlanTag)) {
1014                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1015                 ret = 0;
1016         } else
1017                 ret = -1;
1018         desc->opts2 = 0;
1019         return ret;
1020 }
1021
1022 #else /* !CONFIG_R8169_VLAN */
1023
1024 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1025                                       struct sk_buff *skb)
1026 {
1027         return 0;
1028 }
1029
1030 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1031                                struct sk_buff *skb)
1032 {
1033         return -1;
1034 }
1035
1036 #endif
1037
1038 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1039 {
1040         struct rtl8169_private *tp = netdev_priv(dev);
1041         void __iomem *ioaddr = tp->mmio_addr;
1042         u32 status;
1043
1044         cmd->supported =
1045                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1046         cmd->port = PORT_FIBRE;
1047         cmd->transceiver = XCVR_INTERNAL;
1048
1049         status = RTL_R32(TBICSR);
1050         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1051         cmd->autoneg = !!(status & TBINwEnable);
1052
1053         cmd->speed = SPEED_1000;
1054         cmd->duplex = DUPLEX_FULL; /* Always set */
1055
1056         return 0;
1057 }
1058
1059 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1060 {
1061         struct rtl8169_private *tp = netdev_priv(dev);
1062
1063         return mii_ethtool_gset(&tp->mii, cmd);
1064 }
1065
1066 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1067 {
1068         struct rtl8169_private *tp = netdev_priv(dev);
1069         unsigned long flags;
1070         int rc;
1071
1072         spin_lock_irqsave(&tp->lock, flags);
1073
1074         rc = tp->get_settings(dev, cmd);
1075
1076         spin_unlock_irqrestore(&tp->lock, flags);
1077         return rc;
1078 }
1079
1080 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1081                              void *p)
1082 {
1083         struct rtl8169_private *tp = netdev_priv(dev);
1084         unsigned long flags;
1085
1086         if (regs->len > R8169_REGS_SIZE)
1087                 regs->len = R8169_REGS_SIZE;
1088
1089         spin_lock_irqsave(&tp->lock, flags);
1090         memcpy_fromio(p, tp->mmio_addr, regs->len);
1091         spin_unlock_irqrestore(&tp->lock, flags);
1092 }
1093
1094 static u32 rtl8169_get_msglevel(struct net_device *dev)
1095 {
1096         struct rtl8169_private *tp = netdev_priv(dev);
1097
1098         return tp->msg_enable;
1099 }
1100
1101 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1102 {
1103         struct rtl8169_private *tp = netdev_priv(dev);
1104
1105         tp->msg_enable = value;
1106 }
1107
1108 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1109         "tx_packets",
1110         "rx_packets",
1111         "tx_errors",
1112         "rx_errors",
1113         "rx_missed",
1114         "align_errors",
1115         "tx_single_collisions",
1116         "tx_multi_collisions",
1117         "unicast",
1118         "broadcast",
1119         "multicast",
1120         "tx_aborted",
1121         "tx_underrun",
1122 };
1123
1124 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1125 {
1126         switch (sset) {
1127         case ETH_SS_STATS:
1128                 return ARRAY_SIZE(rtl8169_gstrings);
1129         default:
1130                 return -EOPNOTSUPP;
1131         }
1132 }
1133
1134 static void rtl8169_update_counters(struct net_device *dev)
1135 {
1136         struct rtl8169_private *tp = netdev_priv(dev);
1137         void __iomem *ioaddr = tp->mmio_addr;
1138         struct rtl8169_counters *counters;
1139         dma_addr_t paddr;
1140         u32 cmd;
1141         int wait = 1000;
1142
1143         /*
1144          * Some chips are unable to dump tally counters when the receiver
1145          * is disabled.
1146          */
1147         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1148                 return;
1149
1150         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1151         if (!counters)
1152                 return;
1153
1154         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1155         cmd = (u64)paddr & DMA_BIT_MASK(32);
1156         RTL_W32(CounterAddrLow, cmd);
1157         RTL_W32(CounterAddrLow, cmd | CounterDump);
1158
1159         while (wait--) {
1160                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1161                         /* copy updated counters */
1162                         memcpy(&tp->counters, counters, sizeof(*counters));
1163                         break;
1164                 }
1165                 udelay(10);
1166         }
1167
1168         RTL_W32(CounterAddrLow, 0);
1169         RTL_W32(CounterAddrHigh, 0);
1170
1171         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1172 }
1173
1174 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1175                                       struct ethtool_stats *stats, u64 *data)
1176 {
1177         struct rtl8169_private *tp = netdev_priv(dev);
1178
1179         ASSERT_RTNL();
1180
1181         rtl8169_update_counters(dev);
1182
1183         data[0] = le64_to_cpu(tp->counters.tx_packets);
1184         data[1] = le64_to_cpu(tp->counters.rx_packets);
1185         data[2] = le64_to_cpu(tp->counters.tx_errors);
1186         data[3] = le32_to_cpu(tp->counters.rx_errors);
1187         data[4] = le16_to_cpu(tp->counters.rx_missed);
1188         data[5] = le16_to_cpu(tp->counters.align_errors);
1189         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1190         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1191         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1192         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1193         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1194         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1195         data[12] = le16_to_cpu(tp->counters.tx_underun);
1196 }
1197
1198 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1199 {
1200         switch(stringset) {
1201         case ETH_SS_STATS:
1202                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1203                 break;
1204         }
1205 }
1206
1207 static const struct ethtool_ops rtl8169_ethtool_ops = {
1208         .get_drvinfo            = rtl8169_get_drvinfo,
1209         .get_regs_len           = rtl8169_get_regs_len,
1210         .get_link               = ethtool_op_get_link,
1211         .get_settings           = rtl8169_get_settings,
1212         .set_settings           = rtl8169_set_settings,
1213         .get_msglevel           = rtl8169_get_msglevel,
1214         .set_msglevel           = rtl8169_set_msglevel,
1215         .get_rx_csum            = rtl8169_get_rx_csum,
1216         .set_rx_csum            = rtl8169_set_rx_csum,
1217         .set_tx_csum            = ethtool_op_set_tx_csum,
1218         .set_sg                 = ethtool_op_set_sg,
1219         .set_tso                = ethtool_op_set_tso,
1220         .get_regs               = rtl8169_get_regs,
1221         .get_wol                = rtl8169_get_wol,
1222         .set_wol                = rtl8169_set_wol,
1223         .get_strings            = rtl8169_get_strings,
1224         .get_sset_count         = rtl8169_get_sset_count,
1225         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1226 };
1227
1228 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1229                                        int bitnum, int bitval)
1230 {
1231         int val;
1232
1233         val = mdio_read(ioaddr, reg);
1234         val = (bitval == 1) ?
1235                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1236         mdio_write(ioaddr, reg, val & 0xffff);
1237 }
1238
1239 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1240                                     void __iomem *ioaddr)
1241 {
1242         /*
1243          * The driver currently handles the 8168Bf and the 8168Be identically
1244          * but they can be identified more specifically through the test below
1245          * if needed:
1246          *
1247          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1248          *
1249          * Same thing for the 8101Eb and the 8101Ec:
1250          *
1251          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1252          */
1253         const struct {
1254                 u32 mask;
1255                 u32 val;
1256                 int mac_version;
1257         } mac_info[] = {
1258                 /* 8168D family. */
1259                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1260
1261                 /* 8168C family. */
1262                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1263                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1264                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1265                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1266                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1267                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1268                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1269                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1270                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1271
1272                 /* 8168B family. */
1273                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1274                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1275                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1276                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1277
1278                 /* 8101 family. */
1279                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1280                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1281                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1282                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1283                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1284                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1285                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1286                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1287                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1288                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1289                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1290                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1291                 /* FIXME: where did these entries come from ? -- FR */
1292                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1293                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1294
1295                 /* 8110 family. */
1296                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1297                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1298                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1299                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1300                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1301                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1302
1303                 /* Catch-all */
1304                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1305         }, *p = mac_info;
1306         u32 reg;
1307
1308         reg = RTL_R32(TxConfig);
1309         while ((reg & p->mask) != p->val)
1310                 p++;
1311         tp->mac_version = p->mac_version;
1312 }
1313
1314 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1315 {
1316         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1317 }
1318
1319 struct phy_reg {
1320         u16 reg;
1321         u16 val;
1322 };
1323
1324 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1325 {
1326         while (len-- > 0) {
1327                 mdio_write(ioaddr, regs->reg, regs->val);
1328                 regs++;
1329         }
1330 }
1331
1332 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1333 {
1334         struct {
1335                 u16 regs[5]; /* Beware of bit-sign propagation */
1336         } phy_magic[5] = { {
1337                 { 0x0000,       //w 4 15 12 0
1338                   0x00a1,       //w 3 15 0 00a1
1339                   0x0008,       //w 2 15 0 0008
1340                   0x1020,       //w 1 15 0 1020
1341                   0x1000 } },{  //w 0 15 0 1000
1342                 { 0x7000,       //w 4 15 12 7
1343                   0xff41,       //w 3 15 0 ff41
1344                   0xde60,       //w 2 15 0 de60
1345                   0x0140,       //w 1 15 0 0140
1346                   0x0077 } },{  //w 0 15 0 0077
1347                 { 0xa000,       //w 4 15 12 a
1348                   0xdf01,       //w 3 15 0 df01
1349                   0xdf20,       //w 2 15 0 df20
1350                   0xff95,       //w 1 15 0 ff95
1351                   0xfa00 } },{  //w 0 15 0 fa00
1352                 { 0xb000,       //w 4 15 12 b
1353                   0xff41,       //w 3 15 0 ff41
1354                   0xde20,       //w 2 15 0 de20
1355                   0x0140,       //w 1 15 0 0140
1356                   0x00bb } },{  //w 0 15 0 00bb
1357                 { 0xf000,       //w 4 15 12 f
1358                   0xdf01,       //w 3 15 0 df01
1359                   0xdf20,       //w 2 15 0 df20
1360                   0xff95,       //w 1 15 0 ff95
1361                   0xbf00 }      //w 0 15 0 bf00
1362                 }
1363         }, *p = phy_magic;
1364         unsigned int i;
1365
1366         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1367         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1368         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1369         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1370
1371         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1372                 int val, pos = 4;
1373
1374                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1375                 mdio_write(ioaddr, pos, val);
1376                 while (--pos >= 0)
1377                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1378                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1379                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1380         }
1381         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1382 }
1383
1384 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1385 {
1386         struct phy_reg phy_reg_init[] = {
1387                 { 0x1f, 0x0002 },
1388                 { 0x01, 0x90d0 },
1389                 { 0x1f, 0x0000 }
1390         };
1391
1392         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1393 }
1394
1395 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1396 {
1397         struct phy_reg phy_reg_init[] = {
1398                 { 0x10, 0xf41b },
1399                 { 0x1f, 0x0000 }
1400         };
1401
1402         mdio_write(ioaddr, 0x1f, 0x0001);
1403         mdio_patch(ioaddr, 0x16, 1 << 0);
1404
1405         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1406 }
1407
1408 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1409 {
1410         struct phy_reg phy_reg_init[] = {
1411                 { 0x1f, 0x0001 },
1412                 { 0x10, 0xf41b },
1413                 { 0x1f, 0x0000 }
1414         };
1415
1416         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1417 }
1418
1419 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1420 {
1421         struct phy_reg phy_reg_init[] = {
1422                 { 0x1f, 0x0000 },
1423                 { 0x1d, 0x0f00 },
1424                 { 0x1f, 0x0002 },
1425                 { 0x0c, 0x1ec8 },
1426                 { 0x1f, 0x0000 }
1427         };
1428
1429         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1430 }
1431
1432 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1433 {
1434         struct phy_reg phy_reg_init[] = {
1435                 { 0x1f, 0x0001 },
1436                 { 0x1d, 0x3d98 },
1437                 { 0x1f, 0x0000 }
1438         };
1439
1440         mdio_write(ioaddr, 0x1f, 0x0000);
1441         mdio_patch(ioaddr, 0x14, 1 << 5);
1442         mdio_patch(ioaddr, 0x0d, 1 << 5);
1443
1444         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1445 }
1446
1447 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1448 {
1449         struct phy_reg phy_reg_init[] = {
1450                 { 0x1f, 0x0001 },
1451                 { 0x12, 0x2300 },
1452                 { 0x1f, 0x0002 },
1453                 { 0x00, 0x88d4 },
1454                 { 0x01, 0x82b1 },
1455                 { 0x03, 0x7002 },
1456                 { 0x08, 0x9e30 },
1457                 { 0x09, 0x01f0 },
1458                 { 0x0a, 0x5500 },
1459                 { 0x0c, 0x00c8 },
1460                 { 0x1f, 0x0003 },
1461                 { 0x12, 0xc096 },
1462                 { 0x16, 0x000a },
1463                 { 0x1f, 0x0000 },
1464                 { 0x1f, 0x0000 },
1465                 { 0x09, 0x2000 },
1466                 { 0x09, 0x0000 }
1467         };
1468
1469         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1470
1471         mdio_patch(ioaddr, 0x14, 1 << 5);
1472         mdio_patch(ioaddr, 0x0d, 1 << 5);
1473         mdio_write(ioaddr, 0x1f, 0x0000);
1474 }
1475
1476 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1477 {
1478         struct phy_reg phy_reg_init[] = {
1479                 { 0x1f, 0x0001 },
1480                 { 0x12, 0x2300 },
1481                 { 0x03, 0x802f },
1482                 { 0x02, 0x4f02 },
1483                 { 0x01, 0x0409 },
1484                 { 0x00, 0xf099 },
1485                 { 0x04, 0x9800 },
1486                 { 0x04, 0x9000 },
1487                 { 0x1d, 0x3d98 },
1488                 { 0x1f, 0x0002 },
1489                 { 0x0c, 0x7eb8 },
1490                 { 0x06, 0x0761 },
1491                 { 0x1f, 0x0003 },
1492                 { 0x16, 0x0f0a },
1493                 { 0x1f, 0x0000 }
1494         };
1495
1496         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1497
1498         mdio_patch(ioaddr, 0x16, 1 << 0);
1499         mdio_patch(ioaddr, 0x14, 1 << 5);
1500         mdio_patch(ioaddr, 0x0d, 1 << 5);
1501         mdio_write(ioaddr, 0x1f, 0x0000);
1502 }
1503
1504 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1505 {
1506         struct phy_reg phy_reg_init[] = {
1507                 { 0x1f, 0x0001 },
1508                 { 0x12, 0x2300 },
1509                 { 0x1d, 0x3d98 },
1510                 { 0x1f, 0x0002 },
1511                 { 0x0c, 0x7eb8 },
1512                 { 0x06, 0x5461 },
1513                 { 0x1f, 0x0003 },
1514                 { 0x16, 0x0f0a },
1515                 { 0x1f, 0x0000 }
1516         };
1517
1518         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1519
1520         mdio_patch(ioaddr, 0x16, 1 << 0);
1521         mdio_patch(ioaddr, 0x14, 1 << 5);
1522         mdio_patch(ioaddr, 0x0d, 1 << 5);
1523         mdio_write(ioaddr, 0x1f, 0x0000);
1524 }
1525
1526 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1527 {
1528         rtl8168c_3_hw_phy_config(ioaddr);
1529 }
1530
1531 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1532 {
1533         struct phy_reg phy_reg_init_0[] = {
1534                 { 0x1f, 0x0001 },
1535                 { 0x09, 0x2770 },
1536                 { 0x08, 0x04d0 },
1537                 { 0x0b, 0xad15 },
1538                 { 0x0c, 0x5bf0 },
1539                 { 0x1c, 0xf101 },
1540                 { 0x1f, 0x0003 },
1541                 { 0x14, 0x94d7 },
1542                 { 0x12, 0xf4d6 },
1543                 { 0x09, 0xca0f },
1544                 { 0x1f, 0x0002 },
1545                 { 0x0b, 0x0b10 },
1546                 { 0x0c, 0xd1f7 },
1547                 { 0x1f, 0x0002 },
1548                 { 0x06, 0x5461 },
1549                 { 0x1f, 0x0002 },
1550                 { 0x05, 0x6662 },
1551                 { 0x1f, 0x0000 },
1552                 { 0x14, 0x0060 },
1553                 { 0x1f, 0x0000 },
1554                 { 0x0d, 0xf8a0 },
1555                 { 0x1f, 0x0005 },
1556                 { 0x05, 0xffc2 }
1557         };
1558
1559         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1560
1561         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1562                 struct phy_reg phy_reg_init_1[] = {
1563                         { 0x1f, 0x0005 },
1564                         { 0x01, 0x0300 },
1565                         { 0x1f, 0x0000 },
1566                         { 0x11, 0x401c },
1567                         { 0x16, 0x4100 },
1568                         { 0x1f, 0x0005 },
1569                         { 0x07, 0x0010 },
1570                         { 0x05, 0x83dc },
1571                         { 0x06, 0x087d },
1572                         { 0x05, 0x8300 },
1573                         { 0x06, 0x0101 },
1574                         { 0x06, 0x05f8 },
1575                         { 0x06, 0xf9fa },
1576                         { 0x06, 0xfbef },
1577                         { 0x06, 0x79e2 },
1578                         { 0x06, 0x835f },
1579                         { 0x06, 0xe0f8 },
1580                         { 0x06, 0x9ae1 },
1581                         { 0x06, 0xf89b },
1582                         { 0x06, 0xef31 },
1583                         { 0x06, 0x3b65 },
1584                         { 0x06, 0xaa07 },
1585                         { 0x06, 0x81e4 },
1586                         { 0x06, 0xf89a },
1587                         { 0x06, 0xe5f8 },
1588                         { 0x06, 0x9baf },
1589                         { 0x06, 0x06ae },
1590                         { 0x05, 0x83dc },
1591                         { 0x06, 0x8300 },
1592                 };
1593
1594                 rtl_phy_write(ioaddr, phy_reg_init_1,
1595                               ARRAY_SIZE(phy_reg_init_1));
1596         }
1597
1598         mdio_write(ioaddr, 0x1f, 0x0000);
1599 }
1600
1601 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1602 {
1603         struct phy_reg phy_reg_init[] = {
1604                 { 0x1f, 0x0003 },
1605                 { 0x08, 0x441d },
1606                 { 0x01, 0x9100 },
1607                 { 0x1f, 0x0000 }
1608         };
1609
1610         mdio_write(ioaddr, 0x1f, 0x0000);
1611         mdio_patch(ioaddr, 0x11, 1 << 12);
1612         mdio_patch(ioaddr, 0x19, 1 << 13);
1613
1614         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1615 }
1616
1617 static void rtl_hw_phy_config(struct net_device *dev)
1618 {
1619         struct rtl8169_private *tp = netdev_priv(dev);
1620         void __iomem *ioaddr = tp->mmio_addr;
1621
1622         rtl8169_print_mac_version(tp);
1623
1624         switch (tp->mac_version) {
1625         case RTL_GIGA_MAC_VER_01:
1626                 break;
1627         case RTL_GIGA_MAC_VER_02:
1628         case RTL_GIGA_MAC_VER_03:
1629                 rtl8169s_hw_phy_config(ioaddr);
1630                 break;
1631         case RTL_GIGA_MAC_VER_04:
1632                 rtl8169sb_hw_phy_config(ioaddr);
1633                 break;
1634         case RTL_GIGA_MAC_VER_07:
1635         case RTL_GIGA_MAC_VER_08:
1636         case RTL_GIGA_MAC_VER_09:
1637                 rtl8102e_hw_phy_config(ioaddr);
1638                 break;
1639         case RTL_GIGA_MAC_VER_11:
1640                 rtl8168bb_hw_phy_config(ioaddr);
1641                 break;
1642         case RTL_GIGA_MAC_VER_12:
1643                 rtl8168bef_hw_phy_config(ioaddr);
1644                 break;
1645         case RTL_GIGA_MAC_VER_17:
1646                 rtl8168bef_hw_phy_config(ioaddr);
1647                 break;
1648         case RTL_GIGA_MAC_VER_18:
1649                 rtl8168cp_1_hw_phy_config(ioaddr);
1650                 break;
1651         case RTL_GIGA_MAC_VER_19:
1652                 rtl8168c_1_hw_phy_config(ioaddr);
1653                 break;
1654         case RTL_GIGA_MAC_VER_20:
1655                 rtl8168c_2_hw_phy_config(ioaddr);
1656                 break;
1657         case RTL_GIGA_MAC_VER_21:
1658                 rtl8168c_3_hw_phy_config(ioaddr);
1659                 break;
1660         case RTL_GIGA_MAC_VER_22:
1661                 rtl8168c_4_hw_phy_config(ioaddr);
1662                 break;
1663         case RTL_GIGA_MAC_VER_23:
1664         case RTL_GIGA_MAC_VER_24:
1665                 rtl8168cp_2_hw_phy_config(ioaddr);
1666                 break;
1667         case RTL_GIGA_MAC_VER_25:
1668                 rtl8168d_hw_phy_config(ioaddr);
1669                 break;
1670
1671         default:
1672                 break;
1673         }
1674 }
1675
1676 static void rtl8169_phy_timer(unsigned long __opaque)
1677 {
1678         struct net_device *dev = (struct net_device *)__opaque;
1679         struct rtl8169_private *tp = netdev_priv(dev);
1680         struct timer_list *timer = &tp->timer;
1681         void __iomem *ioaddr = tp->mmio_addr;
1682         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1683
1684         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1685
1686         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1687                 return;
1688
1689         spin_lock_irq(&tp->lock);
1690
1691         if (tp->phy_reset_pending(ioaddr)) {
1692                 /*
1693                  * A busy loop could burn quite a few cycles on nowadays CPU.
1694                  * Let's delay the execution of the timer for a few ticks.
1695                  */
1696                 timeout = HZ/10;
1697                 goto out_mod_timer;
1698         }
1699
1700         if (tp->link_ok(ioaddr))
1701                 goto out_unlock;
1702
1703         if (netif_msg_link(tp))
1704                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1705
1706         tp->phy_reset_enable(ioaddr);
1707
1708 out_mod_timer:
1709         mod_timer(timer, jiffies + timeout);
1710 out_unlock:
1711         spin_unlock_irq(&tp->lock);
1712 }
1713
1714 static inline void rtl8169_delete_timer(struct net_device *dev)
1715 {
1716         struct rtl8169_private *tp = netdev_priv(dev);
1717         struct timer_list *timer = &tp->timer;
1718
1719         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1720                 return;
1721
1722         del_timer_sync(timer);
1723 }
1724
1725 static inline void rtl8169_request_timer(struct net_device *dev)
1726 {
1727         struct rtl8169_private *tp = netdev_priv(dev);
1728         struct timer_list *timer = &tp->timer;
1729
1730         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1731                 return;
1732
1733         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1734 }
1735
1736 #ifdef CONFIG_NET_POLL_CONTROLLER
1737 /*
1738  * Polling 'interrupt' - used by things like netconsole to send skbs
1739  * without having to re-enable interrupts. It's not called while
1740  * the interrupt routine is executing.
1741  */
1742 static void rtl8169_netpoll(struct net_device *dev)
1743 {
1744         struct rtl8169_private *tp = netdev_priv(dev);
1745         struct pci_dev *pdev = tp->pci_dev;
1746
1747         disable_irq(pdev->irq);
1748         rtl8169_interrupt(pdev->irq, dev);
1749         enable_irq(pdev->irq);
1750 }
1751 #endif
1752
1753 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1754                                   void __iomem *ioaddr)
1755 {
1756         iounmap(ioaddr);
1757         pci_release_regions(pdev);
1758         pci_disable_device(pdev);
1759         free_netdev(dev);
1760 }
1761
1762 static void rtl8169_phy_reset(struct net_device *dev,
1763                               struct rtl8169_private *tp)
1764 {
1765         void __iomem *ioaddr = tp->mmio_addr;
1766         unsigned int i;
1767
1768         tp->phy_reset_enable(ioaddr);
1769         for (i = 0; i < 100; i++) {
1770                 if (!tp->phy_reset_pending(ioaddr))
1771                         return;
1772                 msleep(1);
1773         }
1774         if (netif_msg_link(tp))
1775                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1776 }
1777
1778 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1779 {
1780         void __iomem *ioaddr = tp->mmio_addr;
1781
1782         rtl_hw_phy_config(dev);
1783
1784         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1785                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1786                 RTL_W8(0x82, 0x01);
1787         }
1788
1789         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1790
1791         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1792                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1793
1794         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1795                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1796                 RTL_W8(0x82, 0x01);
1797                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1798                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1799         }
1800
1801         rtl8169_phy_reset(dev, tp);
1802
1803         /*
1804          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1805          * only 8101. Don't panic.
1806          */
1807         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1808
1809         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1810                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1811 }
1812
1813 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1814 {
1815         void __iomem *ioaddr = tp->mmio_addr;
1816         u32 high;
1817         u32 low;
1818
1819         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1820         high = addr[4] | (addr[5] << 8);
1821
1822         spin_lock_irq(&tp->lock);
1823
1824         RTL_W8(Cfg9346, Cfg9346_Unlock);
1825         RTL_W32(MAC0, low);
1826         RTL_W32(MAC4, high);
1827         RTL_W8(Cfg9346, Cfg9346_Lock);
1828
1829         spin_unlock_irq(&tp->lock);
1830 }
1831
1832 static int rtl_set_mac_address(struct net_device *dev, void *p)
1833 {
1834         struct rtl8169_private *tp = netdev_priv(dev);
1835         struct sockaddr *addr = p;
1836
1837         if (!is_valid_ether_addr(addr->sa_data))
1838                 return -EADDRNOTAVAIL;
1839
1840         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1841
1842         rtl_rar_set(tp, dev->dev_addr);
1843
1844         return 0;
1845 }
1846
1847 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1848 {
1849         struct rtl8169_private *tp = netdev_priv(dev);
1850         struct mii_ioctl_data *data = if_mii(ifr);
1851
1852         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1853 }
1854
1855 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1856 {
1857         switch (cmd) {
1858         case SIOCGMIIPHY:
1859                 data->phy_id = 32; /* Internal PHY */
1860                 return 0;
1861
1862         case SIOCGMIIREG:
1863                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1864                 return 0;
1865
1866         case SIOCSMIIREG:
1867                 if (!capable(CAP_NET_ADMIN))
1868                         return -EPERM;
1869                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1870                 return 0;
1871         }
1872         return -EOPNOTSUPP;
1873 }
1874
1875 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1876 {
1877         return -EOPNOTSUPP;
1878 }
1879
1880 static const struct rtl_cfg_info {
1881         void (*hw_start)(struct net_device *);
1882         unsigned int region;
1883         unsigned int align;
1884         u16 intr_event;
1885         u16 napi_event;
1886         unsigned features;
1887         u8 default_ver;
1888 } rtl_cfg_infos [] = {
1889         [RTL_CFG_0] = {
1890                 .hw_start       = rtl_hw_start_8169,
1891                 .region         = 1,
1892                 .align          = 0,
1893                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1894                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1895                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1896                 .features       = RTL_FEATURE_GMII,
1897                 .default_ver    = RTL_GIGA_MAC_VER_01,
1898         },
1899         [RTL_CFG_1] = {
1900                 .hw_start       = rtl_hw_start_8168,
1901                 .region         = 2,
1902                 .align          = 8,
1903                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1904                                   TxErr | TxOK | RxOK | RxErr,
1905                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1906                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
1907                 .default_ver    = RTL_GIGA_MAC_VER_11,
1908         },
1909         [RTL_CFG_2] = {
1910                 .hw_start       = rtl_hw_start_8101,
1911                 .region         = 2,
1912                 .align          = 8,
1913                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1914                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1915                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1916                 .features       = RTL_FEATURE_MSI,
1917                 .default_ver    = RTL_GIGA_MAC_VER_13,
1918         }
1919 };
1920
1921 /* Cfg9346_Unlock assumed. */
1922 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1923                             const struct rtl_cfg_info *cfg)
1924 {
1925         unsigned msi = 0;
1926         u8 cfg2;
1927
1928         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1929         if (cfg->features & RTL_FEATURE_MSI) {
1930                 if (pci_enable_msi(pdev)) {
1931                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1932                 } else {
1933                         cfg2 |= MSIEnable;
1934                         msi = RTL_FEATURE_MSI;
1935                 }
1936         }
1937         RTL_W8(Config2, cfg2);
1938         return msi;
1939 }
1940
1941 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1942 {
1943         if (tp->features & RTL_FEATURE_MSI) {
1944                 pci_disable_msi(pdev);
1945                 tp->features &= ~RTL_FEATURE_MSI;
1946         }
1947 }
1948
1949 static const struct net_device_ops rtl8169_netdev_ops = {
1950         .ndo_open               = rtl8169_open,
1951         .ndo_stop               = rtl8169_close,
1952         .ndo_get_stats          = rtl8169_get_stats,
1953         .ndo_start_xmit         = rtl8169_start_xmit,
1954         .ndo_tx_timeout         = rtl8169_tx_timeout,
1955         .ndo_validate_addr      = eth_validate_addr,
1956         .ndo_change_mtu         = rtl8169_change_mtu,
1957         .ndo_set_mac_address    = rtl_set_mac_address,
1958         .ndo_do_ioctl           = rtl8169_ioctl,
1959         .ndo_set_multicast_list = rtl_set_rx_mode,
1960 #ifdef CONFIG_R8169_VLAN
1961         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
1962 #endif
1963 #ifdef CONFIG_NET_POLL_CONTROLLER
1964         .ndo_poll_controller    = rtl8169_netpoll,
1965 #endif
1966
1967 };
1968
1969 static int __devinit
1970 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1971 {
1972         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1973         const unsigned int region = cfg->region;
1974         struct rtl8169_private *tp;
1975         struct mii_if_info *mii;
1976         struct net_device *dev;
1977         void __iomem *ioaddr;
1978         unsigned int i;
1979         int rc;
1980
1981         if (netif_msg_drv(&debug)) {
1982                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1983                        MODULENAME, RTL8169_VERSION);
1984         }
1985
1986         dev = alloc_etherdev(sizeof (*tp));
1987         if (!dev) {
1988                 if (netif_msg_drv(&debug))
1989                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1990                 rc = -ENOMEM;
1991                 goto out;
1992         }
1993
1994         SET_NETDEV_DEV(dev, &pdev->dev);
1995         dev->netdev_ops = &rtl8169_netdev_ops;
1996         tp = netdev_priv(dev);
1997         tp->dev = dev;
1998         tp->pci_dev = pdev;
1999         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2000
2001         mii = &tp->mii;
2002         mii->dev = dev;
2003         mii->mdio_read = rtl_mdio_read;
2004         mii->mdio_write = rtl_mdio_write;
2005         mii->phy_id_mask = 0x1f;
2006         mii->reg_num_mask = 0x1f;
2007         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2008
2009         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2010         rc = pci_enable_device(pdev);
2011         if (rc < 0) {
2012                 if (netif_msg_probe(tp))
2013                         dev_err(&pdev->dev, "enable failure\n");
2014                 goto err_out_free_dev_1;
2015         }
2016
2017         rc = pci_set_mwi(pdev);
2018         if (rc < 0)
2019                 goto err_out_disable_2;
2020
2021         /* make sure PCI base addr 1 is MMIO */
2022         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2023                 if (netif_msg_probe(tp)) {
2024                         dev_err(&pdev->dev,
2025                                 "region #%d not an MMIO resource, aborting\n",
2026                                 region);
2027                 }
2028                 rc = -ENODEV;
2029                 goto err_out_mwi_3;
2030         }
2031
2032         /* check for weird/broken PCI region reporting */
2033         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2034                 if (netif_msg_probe(tp)) {
2035                         dev_err(&pdev->dev,
2036                                 "Invalid PCI region size(s), aborting\n");
2037                 }
2038                 rc = -ENODEV;
2039                 goto err_out_mwi_3;
2040         }
2041
2042         rc = pci_request_regions(pdev, MODULENAME);
2043         if (rc < 0) {
2044                 if (netif_msg_probe(tp))
2045                         dev_err(&pdev->dev, "could not request regions.\n");
2046                 goto err_out_mwi_3;
2047         }
2048
2049         tp->cp_cmd = PCIMulRW | RxChkSum;
2050
2051         if ((sizeof(dma_addr_t) > 4) &&
2052             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
2053                 tp->cp_cmd |= PCIDAC;
2054                 dev->features |= NETIF_F_HIGHDMA;
2055         } else {
2056                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2057                 if (rc < 0) {
2058                         if (netif_msg_probe(tp)) {
2059                                 dev_err(&pdev->dev,
2060                                         "DMA configuration failed.\n");
2061                         }
2062                         goto err_out_free_res_4;
2063                 }
2064         }
2065
2066         pci_set_master(pdev);
2067
2068         /* ioremap MMIO region */
2069         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2070         if (!ioaddr) {
2071                 if (netif_msg_probe(tp))
2072                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2073                 rc = -EIO;
2074                 goto err_out_free_res_4;
2075         }
2076
2077         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2078         if (!tp->pcie_cap && netif_msg_probe(tp))
2079                 dev_info(&pdev->dev, "no PCI Express capability\n");
2080
2081         RTL_W16(IntrMask, 0x0000);
2082
2083         /* Soft reset the chip. */
2084         RTL_W8(ChipCmd, CmdReset);
2085
2086         /* Check that the chip has finished the reset. */
2087         for (i = 0; i < 100; i++) {
2088                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2089                         break;
2090                 msleep_interruptible(1);
2091         }
2092
2093         RTL_W16(IntrStatus, 0xffff);
2094
2095         /* Identify chip attached to board */
2096         rtl8169_get_mac_version(tp, ioaddr);
2097
2098         /* Use appropriate default if unknown */
2099         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2100                 if (netif_msg_probe(tp)) {
2101                         dev_notice(&pdev->dev,
2102                                    "unknown MAC, using family default\n");
2103                 }
2104                 tp->mac_version = cfg->default_ver;
2105         }
2106
2107         rtl8169_print_mac_version(tp);
2108
2109         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2110                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2111                         break;
2112         }
2113         if (i == ARRAY_SIZE(rtl_chip_info)) {
2114                 dev_err(&pdev->dev,
2115                         "driver bug, MAC version not found in rtl_chip_info\n");
2116                 goto err_out_msi_5;
2117         }
2118         tp->chipset = i;
2119
2120         RTL_W8(Cfg9346, Cfg9346_Unlock);
2121         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2122         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2123         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2124                 tp->features |= RTL_FEATURE_WOL;
2125         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2126                 tp->features |= RTL_FEATURE_WOL;
2127         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2128         RTL_W8(Cfg9346, Cfg9346_Lock);
2129
2130         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2131             (RTL_R8(PHYstatus) & TBI_Enable)) {
2132                 tp->set_speed = rtl8169_set_speed_tbi;
2133                 tp->get_settings = rtl8169_gset_tbi;
2134                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2135                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2136                 tp->link_ok = rtl8169_tbi_link_ok;
2137                 tp->do_ioctl = rtl_tbi_ioctl;
2138
2139                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2140         } else {
2141                 tp->set_speed = rtl8169_set_speed_xmii;
2142                 tp->get_settings = rtl8169_gset_xmii;
2143                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2144                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2145                 tp->link_ok = rtl8169_xmii_link_ok;
2146                 tp->do_ioctl = rtl_xmii_ioctl;
2147         }
2148
2149         spin_lock_init(&tp->lock);
2150
2151         tp->mmio_addr = ioaddr;
2152
2153         /* Get MAC address */
2154         for (i = 0; i < MAC_ADDR_LEN; i++)
2155                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2156         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2157
2158         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2159         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2160         dev->irq = pdev->irq;
2161         dev->base_addr = (unsigned long) ioaddr;
2162
2163         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2164
2165 #ifdef CONFIG_R8169_VLAN
2166         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2167 #endif
2168
2169         tp->intr_mask = 0xffff;
2170         tp->align = cfg->align;
2171         tp->hw_start = cfg->hw_start;
2172         tp->intr_event = cfg->intr_event;
2173         tp->napi_event = cfg->napi_event;
2174
2175         init_timer(&tp->timer);
2176         tp->timer.data = (unsigned long) dev;
2177         tp->timer.function = rtl8169_phy_timer;
2178
2179         rc = register_netdev(dev);
2180         if (rc < 0)
2181                 goto err_out_msi_5;
2182
2183         pci_set_drvdata(pdev, dev);
2184
2185         if (netif_msg_probe(tp)) {
2186                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2187
2188                 printk(KERN_INFO "%s: %s at 0x%lx, "
2189                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2190                        "XID %08x IRQ %d\n",
2191                        dev->name,
2192                        rtl_chip_info[tp->chipset].name,
2193                        dev->base_addr,
2194                        dev->dev_addr[0], dev->dev_addr[1],
2195                        dev->dev_addr[2], dev->dev_addr[3],
2196                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2197         }
2198
2199         rtl8169_init_phy(dev, tp);
2200         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2201
2202 out:
2203         return rc;
2204
2205 err_out_msi_5:
2206         rtl_disable_msi(pdev, tp);
2207         iounmap(ioaddr);
2208 err_out_free_res_4:
2209         pci_release_regions(pdev);
2210 err_out_mwi_3:
2211         pci_clear_mwi(pdev);
2212 err_out_disable_2:
2213         pci_disable_device(pdev);
2214 err_out_free_dev_1:
2215         free_netdev(dev);
2216         goto out;
2217 }
2218
2219 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2220 {
2221         struct net_device *dev = pci_get_drvdata(pdev);
2222         struct rtl8169_private *tp = netdev_priv(dev);
2223
2224         flush_scheduled_work();
2225
2226         unregister_netdev(dev);
2227         rtl_disable_msi(pdev, tp);
2228         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2229         pci_set_drvdata(pdev, NULL);
2230 }
2231
2232 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2233                                   struct net_device *dev)
2234 {
2235         unsigned int mtu = dev->mtu;
2236
2237         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2238 }
2239
2240 static int rtl8169_open(struct net_device *dev)
2241 {
2242         struct rtl8169_private *tp = netdev_priv(dev);
2243         struct pci_dev *pdev = tp->pci_dev;
2244         int retval = -ENOMEM;
2245
2246
2247         rtl8169_set_rxbufsize(tp, dev);
2248
2249         /*
2250          * Rx and Tx desscriptors needs 256 bytes alignment.
2251          * pci_alloc_consistent provides more.
2252          */
2253         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2254                                                &tp->TxPhyAddr);
2255         if (!tp->TxDescArray)
2256                 goto out;
2257
2258         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2259                                                &tp->RxPhyAddr);
2260         if (!tp->RxDescArray)
2261                 goto err_free_tx_0;
2262
2263         retval = rtl8169_init_ring(dev);
2264         if (retval < 0)
2265                 goto err_free_rx_1;
2266
2267         INIT_DELAYED_WORK(&tp->task, NULL);
2268
2269         smp_mb();
2270
2271         retval = request_irq(dev->irq, rtl8169_interrupt,
2272                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2273                              dev->name, dev);
2274         if (retval < 0)
2275                 goto err_release_ring_2;
2276
2277         napi_enable(&tp->napi);
2278
2279         rtl_hw_start(dev);
2280
2281         rtl8169_request_timer(dev);
2282
2283         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2284 out:
2285         return retval;
2286
2287 err_release_ring_2:
2288         rtl8169_rx_clear(tp);
2289 err_free_rx_1:
2290         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2291                             tp->RxPhyAddr);
2292 err_free_tx_0:
2293         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2294                             tp->TxPhyAddr);
2295         goto out;
2296 }
2297
2298 static void rtl8169_hw_reset(void __iomem *ioaddr)
2299 {
2300         /* Disable interrupts */
2301         rtl8169_irq_mask_and_ack(ioaddr);
2302
2303         /* Reset the chipset */
2304         RTL_W8(ChipCmd, CmdReset);
2305
2306         /* PCI commit */
2307         RTL_R8(ChipCmd);
2308 }
2309
2310 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2311 {
2312         void __iomem *ioaddr = tp->mmio_addr;
2313         u32 cfg = rtl8169_rx_config;
2314
2315         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2316         RTL_W32(RxConfig, cfg);
2317
2318         /* Set DMA burst size and Interframe Gap Time */
2319         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2320                 (InterFrameGap << TxInterFrameGapShift));
2321 }
2322
2323 static void rtl_hw_start(struct net_device *dev)
2324 {
2325         struct rtl8169_private *tp = netdev_priv(dev);
2326         void __iomem *ioaddr = tp->mmio_addr;
2327         unsigned int i;
2328
2329         /* Soft reset the chip. */
2330         RTL_W8(ChipCmd, CmdReset);
2331
2332         /* Check that the chip has finished the reset. */
2333         for (i = 0; i < 100; i++) {
2334                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2335                         break;
2336                 msleep_interruptible(1);
2337         }
2338
2339         tp->hw_start(dev);
2340
2341         netif_start_queue(dev);
2342 }
2343
2344
2345 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2346                                          void __iomem *ioaddr)
2347 {
2348         /*
2349          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2350          * register to be written before TxDescAddrLow to work.
2351          * Switching from MMIO to I/O access fixes the issue as well.
2352          */
2353         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2354         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2355         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2356         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2357 }
2358
2359 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2360 {
2361         u16 cmd;
2362
2363         cmd = RTL_R16(CPlusCmd);
2364         RTL_W16(CPlusCmd, cmd);
2365         return cmd;
2366 }
2367
2368 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
2369 {
2370         /* Low hurts. Let's disable the filtering. */
2371         RTL_W16(RxMaxSize, rx_buf_sz);
2372 }
2373
2374 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2375 {
2376         struct {
2377                 u32 mac_version;
2378                 u32 clk;
2379                 u32 val;
2380         } cfg2_info [] = {
2381                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2382                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2383                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2384                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2385         }, *p = cfg2_info;
2386         unsigned int i;
2387         u32 clk;
2388
2389         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2390         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2391                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2392                         RTL_W32(0x7c, p->val);
2393                         break;
2394                 }
2395         }
2396 }
2397
2398 static void rtl_hw_start_8169(struct net_device *dev)
2399 {
2400         struct rtl8169_private *tp = netdev_priv(dev);
2401         void __iomem *ioaddr = tp->mmio_addr;
2402         struct pci_dev *pdev = tp->pci_dev;
2403
2404         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2405                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2406                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2407         }
2408
2409         RTL_W8(Cfg9346, Cfg9346_Unlock);
2410         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2411             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2412             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2413             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2414                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2415
2416         RTL_W8(EarlyTxThres, EarlyTxThld);
2417
2418         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2419
2420         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2421             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2422             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2423             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2424                 rtl_set_rx_tx_config_registers(tp);
2425
2426         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2427
2428         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2429             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2430                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2431                         "Bit-3 and bit-14 MUST be 1\n");
2432                 tp->cp_cmd |= (1 << 14);
2433         }
2434
2435         RTL_W16(CPlusCmd, tp->cp_cmd);
2436
2437         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2438
2439         /*
2440          * Undocumented corner. Supposedly:
2441          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2442          */
2443         RTL_W16(IntrMitigate, 0x0000);
2444
2445         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2446
2447         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2448             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2449             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2450             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2451                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2452                 rtl_set_rx_tx_config_registers(tp);
2453         }
2454
2455         RTL_W8(Cfg9346, Cfg9346_Lock);
2456
2457         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2458         RTL_R8(IntrMask);
2459
2460         RTL_W32(RxMissed, 0);
2461
2462         rtl_set_rx_mode(dev);
2463
2464         /* no early-rx interrupts */
2465         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2466
2467         /* Enable all known interrupts by setting the interrupt mask. */
2468         RTL_W16(IntrMask, tp->intr_event);
2469 }
2470
2471 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2472 {
2473         struct net_device *dev = pci_get_drvdata(pdev);
2474         struct rtl8169_private *tp = netdev_priv(dev);
2475         int cap = tp->pcie_cap;
2476
2477         if (cap) {
2478                 u16 ctl;
2479
2480                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2481                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2482                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2483         }
2484 }
2485
2486 static void rtl_csi_access_enable(void __iomem *ioaddr)
2487 {
2488         u32 csi;
2489
2490         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2491         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2492 }
2493
2494 struct ephy_info {
2495         unsigned int offset;
2496         u16 mask;
2497         u16 bits;
2498 };
2499
2500 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2501 {
2502         u16 w;
2503
2504         while (len-- > 0) {
2505                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2506                 rtl_ephy_write(ioaddr, e->offset, w);
2507                 e++;
2508         }
2509 }
2510
2511 static void rtl_disable_clock_request(struct pci_dev *pdev)
2512 {
2513         struct net_device *dev = pci_get_drvdata(pdev);
2514         struct rtl8169_private *tp = netdev_priv(dev);
2515         int cap = tp->pcie_cap;
2516
2517         if (cap) {
2518                 u16 ctl;
2519
2520                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2521                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2522                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2523         }
2524 }
2525
2526 #define R8168_CPCMD_QUIRK_MASK (\
2527         EnableBist | \
2528         Mac_dbgo_oe | \
2529         Force_half_dup | \
2530         Force_rxflow_en | \
2531         Force_txflow_en | \
2532         Cxpl_dbg_sel | \
2533         ASF | \
2534         PktCntrDisable | \
2535         Mac_dbgo_sel)
2536
2537 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2538 {
2539         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2540
2541         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2542
2543         rtl_tx_performance_tweak(pdev,
2544                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2545 }
2546
2547 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2548 {
2549         rtl_hw_start_8168bb(ioaddr, pdev);
2550
2551         RTL_W8(EarlyTxThres, EarlyTxThld);
2552
2553         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2554 }
2555
2556 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2557 {
2558         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2559
2560         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2561
2562         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2563
2564         rtl_disable_clock_request(pdev);
2565
2566         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2567 }
2568
2569 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2570 {
2571         static struct ephy_info e_info_8168cp[] = {
2572                 { 0x01, 0,      0x0001 },
2573                 { 0x02, 0x0800, 0x1000 },
2574                 { 0x03, 0,      0x0042 },
2575                 { 0x06, 0x0080, 0x0000 },
2576                 { 0x07, 0,      0x2000 }
2577         };
2578
2579         rtl_csi_access_enable(ioaddr);
2580
2581         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2582
2583         __rtl_hw_start_8168cp(ioaddr, pdev);
2584 }
2585
2586 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2587 {
2588         rtl_csi_access_enable(ioaddr);
2589
2590         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2591
2592         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2593
2594         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2595 }
2596
2597 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2598 {
2599         rtl_csi_access_enable(ioaddr);
2600
2601         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2602
2603         /* Magic. */
2604         RTL_W8(DBG_REG, 0x20);
2605
2606         RTL_W8(EarlyTxThres, EarlyTxThld);
2607
2608         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2609
2610         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2611 }
2612
2613 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2614 {
2615         static struct ephy_info e_info_8168c_1[] = {
2616                 { 0x02, 0x0800, 0x1000 },
2617                 { 0x03, 0,      0x0002 },
2618                 { 0x06, 0x0080, 0x0000 }
2619         };
2620
2621         rtl_csi_access_enable(ioaddr);
2622
2623         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2624
2625         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2626
2627         __rtl_hw_start_8168cp(ioaddr, pdev);
2628 }
2629
2630 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2631 {
2632         static struct ephy_info e_info_8168c_2[] = {
2633                 { 0x01, 0,      0x0001 },
2634                 { 0x03, 0x0400, 0x0220 }
2635         };
2636
2637         rtl_csi_access_enable(ioaddr);
2638
2639         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2640
2641         __rtl_hw_start_8168cp(ioaddr, pdev);
2642 }
2643
2644 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2645 {
2646         rtl_hw_start_8168c_2(ioaddr, pdev);
2647 }
2648
2649 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2650 {
2651         rtl_csi_access_enable(ioaddr);
2652
2653         __rtl_hw_start_8168cp(ioaddr, pdev);
2654 }
2655
2656 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2657 {
2658         rtl_csi_access_enable(ioaddr);
2659
2660         rtl_disable_clock_request(pdev);
2661
2662         RTL_W8(EarlyTxThres, EarlyTxThld);
2663
2664         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2665
2666         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2667 }
2668
2669 static void rtl_hw_start_8168(struct net_device *dev)
2670 {
2671         struct rtl8169_private *tp = netdev_priv(dev);
2672         void __iomem *ioaddr = tp->mmio_addr;
2673         struct pci_dev *pdev = tp->pci_dev;
2674
2675         RTL_W8(Cfg9346, Cfg9346_Unlock);
2676
2677         RTL_W8(EarlyTxThres, EarlyTxThld);
2678
2679         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2680
2681         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2682
2683         RTL_W16(CPlusCmd, tp->cp_cmd);
2684
2685         RTL_W16(IntrMitigate, 0x5151);
2686
2687         /* Work around for RxFIFO overflow. */
2688         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2689                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2690                 tp->intr_event &= ~RxOverflow;
2691         }
2692
2693         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2694
2695         rtl_set_rx_mode(dev);
2696
2697         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2698                 (InterFrameGap << TxInterFrameGapShift));
2699
2700         RTL_R8(IntrMask);
2701
2702         switch (tp->mac_version) {
2703         case RTL_GIGA_MAC_VER_11:
2704                 rtl_hw_start_8168bb(ioaddr, pdev);
2705         break;
2706
2707         case RTL_GIGA_MAC_VER_12:
2708         case RTL_GIGA_MAC_VER_17:
2709                 rtl_hw_start_8168bef(ioaddr, pdev);
2710         break;
2711
2712         case RTL_GIGA_MAC_VER_18:
2713                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2714         break;
2715
2716         case RTL_GIGA_MAC_VER_19:
2717                 rtl_hw_start_8168c_1(ioaddr, pdev);
2718         break;
2719
2720         case RTL_GIGA_MAC_VER_20:
2721                 rtl_hw_start_8168c_2(ioaddr, pdev);
2722         break;
2723
2724         case RTL_GIGA_MAC_VER_21:
2725                 rtl_hw_start_8168c_3(ioaddr, pdev);
2726         break;
2727
2728         case RTL_GIGA_MAC_VER_22:
2729                 rtl_hw_start_8168c_4(ioaddr, pdev);
2730         break;
2731
2732         case RTL_GIGA_MAC_VER_23:
2733                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2734         break;
2735
2736         case RTL_GIGA_MAC_VER_24:
2737                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2738         break;
2739
2740         case RTL_GIGA_MAC_VER_25:
2741                 rtl_hw_start_8168d(ioaddr, pdev);
2742         break;
2743
2744         default:
2745                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2746                         dev->name, tp->mac_version);
2747         break;
2748         }
2749
2750         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2751
2752         RTL_W8(Cfg9346, Cfg9346_Lock);
2753
2754         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2755
2756         RTL_W16(IntrMask, tp->intr_event);
2757 }
2758
2759 #define R810X_CPCMD_QUIRK_MASK (\
2760         EnableBist | \
2761         Mac_dbgo_oe | \
2762         Force_half_dup | \
2763         Force_half_dup | \
2764         Force_txflow_en | \
2765         Cxpl_dbg_sel | \
2766         ASF | \
2767         PktCntrDisable | \
2768         PCIDAC | \
2769         PCIMulRW)
2770
2771 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2772 {
2773         static struct ephy_info e_info_8102e_1[] = {
2774                 { 0x01, 0, 0x6e65 },
2775                 { 0x02, 0, 0x091f },
2776                 { 0x03, 0, 0xc2f9 },
2777                 { 0x06, 0, 0xafb5 },
2778                 { 0x07, 0, 0x0e00 },
2779                 { 0x19, 0, 0xec80 },
2780                 { 0x01, 0, 0x2e65 },
2781                 { 0x01, 0, 0x6e65 }
2782         };
2783         u8 cfg1;
2784
2785         rtl_csi_access_enable(ioaddr);
2786
2787         RTL_W8(DBG_REG, FIX_NAK_1);
2788
2789         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2790
2791         RTL_W8(Config1,
2792                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2793         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2794
2795         cfg1 = RTL_R8(Config1);
2796         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2797                 RTL_W8(Config1, cfg1 & ~LEDS0);
2798
2799         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2800
2801         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2802 }
2803
2804 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2805 {
2806         rtl_csi_access_enable(ioaddr);
2807
2808         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2809
2810         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2811         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2812
2813         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2814 }
2815
2816 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2817 {
2818         rtl_hw_start_8102e_2(ioaddr, pdev);
2819
2820         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2821 }
2822
2823 static void rtl_hw_start_8101(struct net_device *dev)
2824 {
2825         struct rtl8169_private *tp = netdev_priv(dev);
2826         void __iomem *ioaddr = tp->mmio_addr;
2827         struct pci_dev *pdev = tp->pci_dev;
2828
2829         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2830             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2831                 int cap = tp->pcie_cap;
2832
2833                 if (cap) {
2834                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2835                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2836                 }
2837         }
2838
2839         switch (tp->mac_version) {
2840         case RTL_GIGA_MAC_VER_07:
2841                 rtl_hw_start_8102e_1(ioaddr, pdev);
2842                 break;
2843
2844         case RTL_GIGA_MAC_VER_08:
2845                 rtl_hw_start_8102e_3(ioaddr, pdev);
2846                 break;
2847
2848         case RTL_GIGA_MAC_VER_09:
2849                 rtl_hw_start_8102e_2(ioaddr, pdev);
2850                 break;
2851         }
2852
2853         RTL_W8(Cfg9346, Cfg9346_Unlock);
2854
2855         RTL_W8(EarlyTxThres, EarlyTxThld);
2856
2857         rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
2858
2859         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2860
2861         RTL_W16(CPlusCmd, tp->cp_cmd);
2862
2863         RTL_W16(IntrMitigate, 0x0000);
2864
2865         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2866
2867         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2868         rtl_set_rx_tx_config_registers(tp);
2869
2870         RTL_W8(Cfg9346, Cfg9346_Lock);
2871
2872         RTL_R8(IntrMask);
2873
2874         rtl_set_rx_mode(dev);
2875
2876         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2877
2878         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2879
2880         RTL_W16(IntrMask, tp->intr_event);
2881 }
2882
2883 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2884 {
2885         struct rtl8169_private *tp = netdev_priv(dev);
2886         int ret = 0;
2887
2888         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2889                 return -EINVAL;
2890
2891         dev->mtu = new_mtu;
2892
2893         if (!netif_running(dev))
2894                 goto out;
2895
2896         rtl8169_down(dev);
2897
2898         rtl8169_set_rxbufsize(tp, dev);
2899
2900         ret = rtl8169_init_ring(dev);
2901         if (ret < 0)
2902                 goto out;
2903
2904         napi_enable(&tp->napi);
2905
2906         rtl_hw_start(dev);
2907
2908         rtl8169_request_timer(dev);
2909
2910 out:
2911         return ret;
2912 }
2913
2914 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2915 {
2916         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2917         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2918 }
2919
2920 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2921                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2922 {
2923         struct pci_dev *pdev = tp->pci_dev;
2924
2925         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2926                          PCI_DMA_FROMDEVICE);
2927         dev_kfree_skb(*sk_buff);
2928         *sk_buff = NULL;
2929         rtl8169_make_unusable_by_asic(desc);
2930 }
2931
2932 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2933 {
2934         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2935
2936         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2937 }
2938
2939 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2940                                        u32 rx_buf_sz)
2941 {
2942         desc->addr = cpu_to_le64(mapping);
2943         wmb();
2944         rtl8169_mark_to_asic(desc, rx_buf_sz);
2945 }
2946
2947 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2948                                             struct net_device *dev,
2949                                             struct RxDesc *desc, int rx_buf_sz,
2950                                             unsigned int align)
2951 {
2952         struct sk_buff *skb;
2953         dma_addr_t mapping;
2954         unsigned int pad;
2955
2956         pad = align ? align : NET_IP_ALIGN;
2957
2958         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2959         if (!skb)
2960                 goto err_out;
2961
2962         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2963
2964         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2965                                  PCI_DMA_FROMDEVICE);
2966
2967         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2968 out:
2969         return skb;
2970
2971 err_out:
2972         rtl8169_make_unusable_by_asic(desc);
2973         goto out;
2974 }
2975
2976 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2977 {
2978         unsigned int i;
2979
2980         for (i = 0; i < NUM_RX_DESC; i++) {
2981                 if (tp->Rx_skbuff[i]) {
2982                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2983                                             tp->RxDescArray + i);
2984                 }
2985         }
2986 }
2987
2988 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2989                            u32 start, u32 end)
2990 {
2991         u32 cur;
2992
2993         for (cur = start; end - cur != 0; cur++) {
2994                 struct sk_buff *skb;
2995                 unsigned int i = cur % NUM_RX_DESC;
2996
2997                 WARN_ON((s32)(end - cur) < 0);
2998
2999                 if (tp->Rx_skbuff[i])
3000                         continue;
3001
3002                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3003                                            tp->RxDescArray + i,
3004                                            tp->rx_buf_sz, tp->align);
3005                 if (!skb)
3006                         break;
3007
3008                 tp->Rx_skbuff[i] = skb;
3009         }
3010         return cur - start;
3011 }
3012
3013 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3014 {
3015         desc->opts1 |= cpu_to_le32(RingEnd);
3016 }
3017
3018 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3019 {
3020         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3021 }
3022
3023 static int rtl8169_init_ring(struct net_device *dev)
3024 {
3025         struct rtl8169_private *tp = netdev_priv(dev);
3026
3027         rtl8169_init_ring_indexes(tp);
3028
3029         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3030         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3031
3032         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3033                 goto err_out;
3034
3035         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3036
3037         return 0;
3038
3039 err_out:
3040         rtl8169_rx_clear(tp);
3041         return -ENOMEM;
3042 }
3043
3044 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3045                                  struct TxDesc *desc)
3046 {
3047         unsigned int len = tx_skb->len;
3048
3049         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3050         desc->opts1 = 0x00;
3051         desc->opts2 = 0x00;
3052         desc->addr = 0x00;
3053         tx_skb->len = 0;
3054 }
3055
3056 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3057 {
3058         unsigned int i;
3059
3060         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3061                 unsigned int entry = i % NUM_TX_DESC;
3062                 struct ring_info *tx_skb = tp->tx_skb + entry;
3063                 unsigned int len = tx_skb->len;
3064
3065                 if (len) {
3066                         struct sk_buff *skb = tx_skb->skb;
3067
3068                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3069                                              tp->TxDescArray + entry);
3070                         if (skb) {
3071                                 dev_kfree_skb(skb);
3072                                 tx_skb->skb = NULL;
3073                         }
3074                         tp->dev->stats.tx_dropped++;
3075                 }
3076         }
3077         tp->cur_tx = tp->dirty_tx = 0;
3078 }
3079
3080 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3081 {
3082         struct rtl8169_private *tp = netdev_priv(dev);
3083
3084         PREPARE_DELAYED_WORK(&tp->task, task);
3085         schedule_delayed_work(&tp->task, 4);
3086 }
3087
3088 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3089 {
3090         struct rtl8169_private *tp = netdev_priv(dev);
3091         void __iomem *ioaddr = tp->mmio_addr;
3092
3093         synchronize_irq(dev->irq);
3094
3095         /* Wait for any pending NAPI task to complete */
3096         napi_disable(&tp->napi);
3097
3098         rtl8169_irq_mask_and_ack(ioaddr);
3099
3100         tp->intr_mask = 0xffff;
3101         RTL_W16(IntrMask, tp->intr_event);
3102         napi_enable(&tp->napi);
3103 }
3104
3105 static void rtl8169_reinit_task(struct work_struct *work)
3106 {
3107         struct rtl8169_private *tp =
3108                 container_of(work, struct rtl8169_private, task.work);
3109         struct net_device *dev = tp->dev;
3110         int ret;
3111
3112         rtnl_lock();
3113
3114         if (!netif_running(dev))
3115                 goto out_unlock;
3116
3117         rtl8169_wait_for_quiescence(dev);
3118         rtl8169_close(dev);
3119
3120         ret = rtl8169_open(dev);
3121         if (unlikely(ret < 0)) {
3122                 if (net_ratelimit() && netif_msg_drv(tp)) {
3123                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3124                                " Rescheduling.\n", dev->name, ret);
3125                 }
3126                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3127         }
3128
3129 out_unlock:
3130         rtnl_unlock();
3131 }
3132
3133 static void rtl8169_reset_task(struct work_struct *work)
3134 {
3135         struct rtl8169_private *tp =
3136                 container_of(work, struct rtl8169_private, task.work);
3137         struct net_device *dev = tp->dev;
3138
3139         rtnl_lock();
3140
3141         if (!netif_running(dev))
3142                 goto out_unlock;
3143
3144         rtl8169_wait_for_quiescence(dev);
3145
3146         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3147         rtl8169_tx_clear(tp);
3148
3149         if (tp->dirty_rx == tp->cur_rx) {
3150                 rtl8169_init_ring_indexes(tp);
3151                 rtl_hw_start(dev);
3152                 netif_wake_queue(dev);
3153                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3154         } else {
3155                 if (net_ratelimit() && netif_msg_intr(tp)) {
3156                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3157                                dev->name);
3158                 }
3159                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3160         }
3161
3162 out_unlock:
3163         rtnl_unlock();
3164 }
3165
3166 static void rtl8169_tx_timeout(struct net_device *dev)
3167 {
3168         struct rtl8169_private *tp = netdev_priv(dev);
3169
3170         rtl8169_hw_reset(tp->mmio_addr);
3171
3172         /* Let's wait a bit while any (async) irq lands on */
3173         rtl8169_schedule_work(dev, rtl8169_reset_task);
3174 }
3175
3176 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3177                               u32 opts1)
3178 {
3179         struct skb_shared_info *info = skb_shinfo(skb);
3180         unsigned int cur_frag, entry;
3181         struct TxDesc * uninitialized_var(txd);
3182
3183         entry = tp->cur_tx;
3184         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3185                 skb_frag_t *frag = info->frags + cur_frag;
3186                 dma_addr_t mapping;
3187                 u32 status, len;
3188                 void *addr;
3189
3190                 entry = (entry + 1) % NUM_TX_DESC;
3191
3192                 txd = tp->TxDescArray + entry;
3193                 len = frag->size;
3194                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3195                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3196
3197                 /* anti gcc 2.95.3 bugware (sic) */
3198                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3199
3200                 txd->opts1 = cpu_to_le32(status);
3201                 txd->addr = cpu_to_le64(mapping);
3202
3203                 tp->tx_skb[entry].len = len;
3204         }
3205
3206         if (cur_frag) {
3207                 tp->tx_skb[entry].skb = skb;
3208                 txd->opts1 |= cpu_to_le32(LastFrag);
3209         }
3210
3211         return cur_frag;
3212 }
3213
3214 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3215 {
3216         if (dev->features & NETIF_F_TSO) {
3217                 u32 mss = skb_shinfo(skb)->gso_size;
3218
3219                 if (mss)
3220                         return LargeSend | ((mss & MSSMask) << MSSShift);
3221         }
3222         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3223                 const struct iphdr *ip = ip_hdr(skb);
3224
3225                 if (ip->protocol == IPPROTO_TCP)
3226                         return IPCS | TCPCS;
3227                 else if (ip->protocol == IPPROTO_UDP)
3228                         return IPCS | UDPCS;
3229                 WARN_ON(1);     /* we need a WARN() */
3230         }
3231         return 0;
3232 }
3233
3234 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3235 {
3236         struct rtl8169_private *tp = netdev_priv(dev);
3237         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3238         struct TxDesc *txd = tp->TxDescArray + entry;
3239         void __iomem *ioaddr = tp->mmio_addr;
3240         dma_addr_t mapping;
3241         u32 status, len;
3242         u32 opts1;
3243         int ret = NETDEV_TX_OK;
3244
3245         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3246                 if (netif_msg_drv(tp)) {
3247                         printk(KERN_ERR
3248                                "%s: BUG! Tx Ring full when queue awake!\n",
3249                                dev->name);
3250                 }
3251                 goto err_stop;
3252         }
3253
3254         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3255                 goto err_stop;
3256
3257         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3258
3259         frags = rtl8169_xmit_frags(tp, skb, opts1);
3260         if (frags) {
3261                 len = skb_headlen(skb);
3262                 opts1 |= FirstFrag;
3263         } else {
3264                 len = skb->len;
3265                 opts1 |= FirstFrag | LastFrag;
3266                 tp->tx_skb[entry].skb = skb;
3267         }
3268
3269         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3270
3271         tp->tx_skb[entry].len = len;
3272         txd->addr = cpu_to_le64(mapping);
3273         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3274
3275         wmb();
3276
3277         /* anti gcc 2.95.3 bugware (sic) */
3278         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3279         txd->opts1 = cpu_to_le32(status);
3280
3281         tp->cur_tx += frags + 1;
3282
3283         smp_wmb();
3284
3285         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3286
3287         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3288                 netif_stop_queue(dev);
3289                 smp_rmb();
3290                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3291                         netif_wake_queue(dev);
3292         }
3293
3294 out:
3295         return ret;
3296
3297 err_stop:
3298         netif_stop_queue(dev);
3299         ret = NETDEV_TX_BUSY;
3300         dev->stats.tx_dropped++;
3301         goto out;
3302 }
3303
3304 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3305 {
3306         struct rtl8169_private *tp = netdev_priv(dev);
3307         struct pci_dev *pdev = tp->pci_dev;
3308         void __iomem *ioaddr = tp->mmio_addr;
3309         u16 pci_status, pci_cmd;
3310
3311         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3312         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3313
3314         if (netif_msg_intr(tp)) {
3315                 printk(KERN_ERR
3316                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3317                        dev->name, pci_cmd, pci_status);
3318         }
3319
3320         /*
3321          * The recovery sequence below admits a very elaborated explanation:
3322          * - it seems to work;
3323          * - I did not see what else could be done;
3324          * - it makes iop3xx happy.
3325          *
3326          * Feel free to adjust to your needs.
3327          */
3328         if (pdev->broken_parity_status)
3329                 pci_cmd &= ~PCI_COMMAND_PARITY;
3330         else
3331                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3332
3333         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3334
3335         pci_write_config_word(pdev, PCI_STATUS,
3336                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3337                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3338                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3339
3340         /* The infamous DAC f*ckup only happens at boot time */
3341         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3342                 if (netif_msg_intr(tp))
3343                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3344                 tp->cp_cmd &= ~PCIDAC;
3345                 RTL_W16(CPlusCmd, tp->cp_cmd);
3346                 dev->features &= ~NETIF_F_HIGHDMA;
3347         }
3348
3349         rtl8169_hw_reset(ioaddr);
3350
3351         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3352 }
3353
3354 static void rtl8169_tx_interrupt(struct net_device *dev,
3355                                  struct rtl8169_private *tp,
3356                                  void __iomem *ioaddr)
3357 {
3358         unsigned int dirty_tx, tx_left;
3359
3360         dirty_tx = tp->dirty_tx;
3361         smp_rmb();
3362         tx_left = tp->cur_tx - dirty_tx;
3363
3364         while (tx_left > 0) {
3365                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3366                 struct ring_info *tx_skb = tp->tx_skb + entry;
3367                 u32 len = tx_skb->len;
3368                 u32 status;
3369
3370                 rmb();
3371                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3372                 if (status & DescOwn)
3373                         break;
3374
3375                 dev->stats.tx_bytes += len;
3376                 dev->stats.tx_packets++;
3377
3378                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3379
3380                 if (status & LastFrag) {
3381                         dev_kfree_skb(tx_skb->skb);
3382                         tx_skb->skb = NULL;
3383                 }
3384                 dirty_tx++;
3385                 tx_left--;
3386         }
3387
3388         if (tp->dirty_tx != dirty_tx) {
3389                 tp->dirty_tx = dirty_tx;
3390                 smp_wmb();
3391                 if (netif_queue_stopped(dev) &&
3392                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3393                         netif_wake_queue(dev);
3394                 }
3395                 /*
3396                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3397                  * too close. Let's kick an extra TxPoll request when a burst
3398                  * of start_xmit activity is detected (if it is not detected,
3399                  * it is slow enough). -- FR
3400                  */
3401                 smp_rmb();
3402                 if (tp->cur_tx != dirty_tx)
3403                         RTL_W8(TxPoll, NPQ);
3404         }
3405 }
3406
3407 static inline int rtl8169_fragmented_frame(u32 status)
3408 {
3409         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3410 }
3411
3412 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3413 {
3414         u32 opts1 = le32_to_cpu(desc->opts1);
3415         u32 status = opts1 & RxProtoMask;
3416
3417         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3418             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3419             ((status == RxProtoIP) && !(opts1 & IPFail)))
3420                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3421         else
3422                 skb->ip_summed = CHECKSUM_NONE;
3423 }
3424
3425 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3426                                        struct rtl8169_private *tp, int pkt_size,
3427                                        dma_addr_t addr)
3428 {
3429         struct sk_buff *skb;
3430         bool done = false;
3431
3432         if (pkt_size >= rx_copybreak)
3433                 goto out;
3434
3435         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3436         if (!skb)
3437                 goto out;
3438
3439         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3440                                     PCI_DMA_FROMDEVICE);
3441         skb_reserve(skb, NET_IP_ALIGN);
3442         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3443         *sk_buff = skb;
3444         done = true;
3445 out:
3446         return done;
3447 }
3448
3449 static int rtl8169_rx_interrupt(struct net_device *dev,
3450                                 struct rtl8169_private *tp,
3451                                 void __iomem *ioaddr, u32 budget)
3452 {
3453         unsigned int cur_rx, rx_left;
3454         unsigned int delta, count;
3455
3456         cur_rx = tp->cur_rx;
3457         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3458         rx_left = min(rx_left, budget);
3459
3460         for (; rx_left > 0; rx_left--, cur_rx++) {
3461                 unsigned int entry = cur_rx % NUM_RX_DESC;
3462                 struct RxDesc *desc = tp->RxDescArray + entry;
3463                 u32 status;
3464
3465                 rmb();
3466                 status = le32_to_cpu(desc->opts1);
3467
3468                 if (status & DescOwn)
3469                         break;
3470                 if (unlikely(status & RxRES)) {
3471                         if (netif_msg_rx_err(tp)) {
3472                                 printk(KERN_INFO
3473                                        "%s: Rx ERROR. status = %08x\n",
3474                                        dev->name, status);
3475                         }
3476                         dev->stats.rx_errors++;
3477                         if (status & (RxRWT | RxRUNT))
3478                                 dev->stats.rx_length_errors++;
3479                         if (status & RxCRC)
3480                                 dev->stats.rx_crc_errors++;
3481                         if (status & RxFOVF) {
3482                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3483                                 dev->stats.rx_fifo_errors++;
3484                         }
3485                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3486                 } else {
3487                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3488                         dma_addr_t addr = le64_to_cpu(desc->addr);
3489                         int pkt_size = (status & 0x00001FFF) - 4;
3490                         struct pci_dev *pdev = tp->pci_dev;
3491
3492                         /*
3493                          * The driver does not support incoming fragmented
3494                          * frames. They are seen as a symptom of over-mtu
3495                          * sized frames.
3496                          */
3497                         if (unlikely(rtl8169_fragmented_frame(status))) {
3498                                 dev->stats.rx_dropped++;
3499                                 dev->stats.rx_length_errors++;
3500                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3501                                 continue;
3502                         }
3503
3504                         rtl8169_rx_csum(skb, desc);
3505
3506                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3507                                 pci_dma_sync_single_for_device(pdev, addr,
3508                                         pkt_size, PCI_DMA_FROMDEVICE);
3509                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3510                         } else {
3511                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3512                                                  PCI_DMA_FROMDEVICE);
3513                                 tp->Rx_skbuff[entry] = NULL;
3514                         }
3515
3516                         skb_put(skb, pkt_size);
3517                         skb->protocol = eth_type_trans(skb, dev);
3518
3519                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3520                                 netif_receive_skb(skb);
3521
3522                         dev->stats.rx_bytes += pkt_size;
3523                         dev->stats.rx_packets++;
3524                 }
3525
3526                 /* Work around for AMD plateform. */
3527                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3528                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3529                         desc->opts2 = 0;
3530                         cur_rx++;
3531                 }
3532         }
3533
3534         count = cur_rx - tp->cur_rx;
3535         tp->cur_rx = cur_rx;
3536
3537         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3538         if (!delta && count && netif_msg_intr(tp))
3539                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3540         tp->dirty_rx += delta;
3541
3542         /*
3543          * FIXME: until there is periodic timer to try and refill the ring,
3544          * a temporary shortage may definitely kill the Rx process.
3545          * - disable the asic to try and avoid an overflow and kick it again
3546          *   after refill ?
3547          * - how do others driver handle this condition (Uh oh...).
3548          */
3549         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3550                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3551
3552         return count;
3553 }
3554
3555 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3556 {
3557         struct net_device *dev = dev_instance;
3558         struct rtl8169_private *tp = netdev_priv(dev);
3559         void __iomem *ioaddr = tp->mmio_addr;
3560         int handled = 0;
3561         int status;
3562
3563         /* loop handling interrupts until we have no new ones or
3564          * we hit a invalid/hotplug case.
3565          */
3566         status = RTL_R16(IntrStatus);
3567         while (status && status != 0xffff) {
3568                 handled = 1;
3569
3570                 /* Handle all of the error cases first. These will reset
3571                  * the chip, so just exit the loop.
3572                  */
3573                 if (unlikely(!netif_running(dev))) {
3574                         rtl8169_asic_down(ioaddr);
3575                         break;
3576                 }
3577
3578                 /* Work around for rx fifo overflow */
3579                 if (unlikely(status & RxFIFOOver) &&
3580                 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3581                         netif_stop_queue(dev);
3582                         rtl8169_tx_timeout(dev);
3583                         break;
3584                 }
3585
3586                 if (unlikely(status & SYSErr)) {
3587                         rtl8169_pcierr_interrupt(dev);
3588                         break;
3589                 }
3590
3591                 if (status & LinkChg)
3592                         rtl8169_check_link_status(dev, tp, ioaddr);
3593
3594                 /* We need to see the lastest version of tp->intr_mask to
3595                  * avoid ignoring an MSI interrupt and having to wait for
3596                  * another event which may never come.
3597                  */
3598                 smp_rmb();
3599                 if (status & tp->intr_mask & tp->napi_event) {
3600                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3601                         tp->intr_mask = ~tp->napi_event;
3602
3603                         if (likely(napi_schedule_prep(&tp->napi)))
3604                                 __napi_schedule(&tp->napi);
3605                         else if (netif_msg_intr(tp)) {
3606                                 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3607                                 dev->name, status);
3608                         }
3609                 }
3610
3611                 /* We only get a new MSI interrupt when all active irq
3612                  * sources on the chip have been acknowledged. So, ack
3613                  * everything we've seen and check if new sources have become
3614                  * active to avoid blocking all interrupts from the chip.
3615                  */
3616                 RTL_W16(IntrStatus,
3617                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
3618                 status = RTL_R16(IntrStatus);
3619         }
3620
3621         return IRQ_RETVAL(handled);
3622 }
3623
3624 static int rtl8169_poll(struct napi_struct *napi, int budget)
3625 {
3626         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3627         struct net_device *dev = tp->dev;
3628         void __iomem *ioaddr = tp->mmio_addr;
3629         int work_done;
3630
3631         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3632         rtl8169_tx_interrupt(dev, tp, ioaddr);
3633
3634         if (work_done < budget) {
3635                 napi_complete(napi);
3636
3637                 /* We need for force the visibility of tp->intr_mask
3638                  * for other CPUs, as we can loose an MSI interrupt
3639                  * and potentially wait for a retransmit timeout if we don't.
3640                  * The posted write to IntrMask is safe, as it will
3641                  * eventually make it to the chip and we won't loose anything
3642                  * until it does.
3643                  */
3644                 tp->intr_mask = 0xffff;
3645                 smp_wmb();
3646                 RTL_W16(IntrMask, tp->intr_event);
3647         }
3648
3649         return work_done;
3650 }
3651
3652 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3653 {
3654         struct rtl8169_private *tp = netdev_priv(dev);
3655
3656         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3657                 return;
3658
3659         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3660         RTL_W32(RxMissed, 0);
3661 }
3662
3663 static void rtl8169_down(struct net_device *dev)
3664 {
3665         struct rtl8169_private *tp = netdev_priv(dev);
3666         void __iomem *ioaddr = tp->mmio_addr;
3667         unsigned int intrmask;
3668
3669         rtl8169_delete_timer(dev);
3670
3671         netif_stop_queue(dev);
3672
3673         napi_disable(&tp->napi);
3674
3675 core_down:
3676         spin_lock_irq(&tp->lock);
3677
3678         rtl8169_asic_down(ioaddr);
3679
3680         rtl8169_rx_missed(dev, ioaddr);
3681
3682         spin_unlock_irq(&tp->lock);
3683
3684         synchronize_irq(dev->irq);
3685
3686         /* Give a racing hard_start_xmit a few cycles to complete. */
3687         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3688
3689         /*
3690          * And now for the 50k$ question: are IRQ disabled or not ?
3691          *
3692          * Two paths lead here:
3693          * 1) dev->close
3694          *    -> netif_running() is available to sync the current code and the
3695          *       IRQ handler. See rtl8169_interrupt for details.
3696          * 2) dev->change_mtu
3697          *    -> rtl8169_poll can not be issued again and re-enable the
3698          *       interruptions. Let's simply issue the IRQ down sequence again.
3699          *
3700          * No loop if hotpluged or major error (0xffff).
3701          */
3702         intrmask = RTL_R16(IntrMask);
3703         if (intrmask && (intrmask != 0xffff))
3704                 goto core_down;
3705
3706         rtl8169_tx_clear(tp);
3707
3708         rtl8169_rx_clear(tp);
3709 }
3710
3711 static int rtl8169_close(struct net_device *dev)
3712 {
3713         struct rtl8169_private *tp = netdev_priv(dev);
3714         struct pci_dev *pdev = tp->pci_dev;
3715
3716         /* update counters before going down */
3717         rtl8169_update_counters(dev);
3718
3719         rtl8169_down(dev);
3720
3721         free_irq(dev->irq, dev);
3722
3723         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3724                             tp->RxPhyAddr);
3725         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3726                             tp->TxPhyAddr);
3727         tp->TxDescArray = NULL;
3728         tp->RxDescArray = NULL;
3729
3730         return 0;
3731 }
3732
3733 static void rtl_set_rx_mode(struct net_device *dev)
3734 {
3735         struct rtl8169_private *tp = netdev_priv(dev);
3736         void __iomem *ioaddr = tp->mmio_addr;
3737         unsigned long flags;
3738         u32 mc_filter[2];       /* Multicast hash filter */
3739         int rx_mode;
3740         u32 tmp = 0;
3741
3742         if (dev->flags & IFF_PROMISC) {
3743                 /* Unconditionally log net taps. */
3744                 if (netif_msg_link(tp)) {
3745                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3746                                dev->name);
3747                 }
3748                 rx_mode =
3749                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3750                     AcceptAllPhys;
3751                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3752         } else if ((dev->mc_count > multicast_filter_limit)
3753                    || (dev->flags & IFF_ALLMULTI)) {
3754                 /* Too many to filter perfectly -- accept all multicasts. */
3755                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3756                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3757         } else {
3758                 struct dev_mc_list *mclist;
3759                 unsigned int i;
3760
3761                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3762                 mc_filter[1] = mc_filter[0] = 0;
3763                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3764                      i++, mclist = mclist->next) {
3765                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3766                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3767                         rx_mode |= AcceptMulticast;
3768                 }
3769         }
3770
3771         spin_lock_irqsave(&tp->lock, flags);
3772
3773         tmp = rtl8169_rx_config | rx_mode |
3774               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3775
3776         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3777                 u32 data = mc_filter[0];
3778
3779                 mc_filter[0] = swab32(mc_filter[1]);
3780                 mc_filter[1] = swab32(data);
3781         }
3782
3783         RTL_W32(MAR0 + 0, mc_filter[0]);
3784         RTL_W32(MAR0 + 4, mc_filter[1]);
3785
3786         RTL_W32(RxConfig, tmp);
3787
3788         spin_unlock_irqrestore(&tp->lock, flags);
3789 }
3790
3791 /**
3792  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3793  *  @dev: The Ethernet Device to get statistics for
3794  *
3795  *  Get TX/RX statistics for rtl8169
3796  */
3797 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3798 {
3799         struct rtl8169_private *tp = netdev_priv(dev);
3800         void __iomem *ioaddr = tp->mmio_addr;
3801         unsigned long flags;
3802
3803         if (netif_running(dev)) {
3804                 spin_lock_irqsave(&tp->lock, flags);
3805                 rtl8169_rx_missed(dev, ioaddr);
3806                 spin_unlock_irqrestore(&tp->lock, flags);
3807         }
3808
3809         return &dev->stats;
3810 }
3811
3812 static void rtl8169_net_suspend(struct net_device *dev)
3813 {
3814         struct rtl8169_private *tp = netdev_priv(dev);
3815         void __iomem *ioaddr = tp->mmio_addr;
3816
3817         if (!netif_running(dev))
3818                 return;
3819
3820         netif_device_detach(dev);
3821         netif_stop_queue(dev);
3822
3823         spin_lock_irq(&tp->lock);
3824
3825         rtl8169_asic_down(ioaddr);
3826
3827         rtl8169_rx_missed(dev, ioaddr);
3828
3829         spin_unlock_irq(&tp->lock);
3830 }
3831
3832 #ifdef CONFIG_PM
3833
3834 static int rtl8169_suspend(struct device *device)
3835 {
3836         struct pci_dev *pdev = to_pci_dev(device);
3837         struct net_device *dev = pci_get_drvdata(pdev);
3838
3839         rtl8169_net_suspend(dev);
3840
3841         return 0;
3842 }
3843
3844 static int rtl8169_resume(struct device *device)
3845 {
3846         struct pci_dev *pdev = to_pci_dev(device);
3847         struct net_device *dev = pci_get_drvdata(pdev);
3848
3849         if (!netif_running(dev))
3850                 goto out;
3851
3852         netif_device_attach(dev);
3853
3854         rtl8169_schedule_work(dev, rtl8169_reset_task);
3855 out:
3856         return 0;
3857 }
3858
3859 static struct dev_pm_ops rtl8169_pm_ops = {
3860         .suspend = rtl8169_suspend,
3861         .resume = rtl8169_resume,
3862         .freeze = rtl8169_suspend,
3863         .thaw = rtl8169_resume,
3864         .poweroff = rtl8169_suspend,
3865         .restore = rtl8169_resume,
3866 };
3867
3868 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
3869
3870 #else /* !CONFIG_PM */
3871
3872 #define RTL8169_PM_OPS  NULL
3873
3874 #endif /* !CONFIG_PM */
3875
3876 static void rtl_shutdown(struct pci_dev *pdev)
3877 {
3878         struct net_device *dev = pci_get_drvdata(pdev);
3879
3880         rtl8169_net_suspend(dev);
3881
3882         if (system_state == SYSTEM_POWER_OFF) {
3883                 pci_wake_from_d3(pdev, true);
3884                 pci_set_power_state(pdev, PCI_D3hot);
3885         }
3886 }
3887
3888 static struct pci_driver rtl8169_pci_driver = {
3889         .name           = MODULENAME,
3890         .id_table       = rtl8169_pci_tbl,
3891         .probe          = rtl8169_init_one,
3892         .remove         = __devexit_p(rtl8169_remove_one),
3893         .shutdown       = rtl_shutdown,
3894         .driver.pm      = RTL8169_PM_OPS,
3895 };
3896
3897 static int __init rtl8169_init_module(void)
3898 {
3899         return pci_register_driver(&rtl8169_pci_driver);
3900 }
3901
3902 static void __exit rtl8169_cleanup_module(void)
3903 {
3904         pci_unregister_driver(&rtl8169_pci_driver);
3905 }
3906
3907 module_init(rtl8169_init_module);
3908 module_exit(rtl8169_cleanup_module);