Merge git://git.infradead.org/mtd-2.6
[linux-2.6] / drivers / char / hw_random / intel-rng.c
1 /*
2  * RNG driver for Intel RNGs
3  *
4  * Copyright 2005 (c) MontaVista Software, Inc.
5  *
6  * with the majority of the code coming from:
7  *
8  * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
9  * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
10  *
11  * derived from
12  *
13  * Hardware driver for the AMD 768 Random Number Generator (RNG)
14  * (c) Copyright 2001 Red Hat Inc <alan@redhat.com>
15  *
16  * derived from
17  *
18  * Hardware driver for Intel i810 Random Number Generator (RNG)
19  * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
20  * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
21  *
22  * This file is licensed under  the terms of the GNU General Public
23  * License version 2. This program is licensed "as is" without any
24  * warranty of any kind, whether express or implied.
25  */
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/hw_random.h>
31 #include <asm/io.h>
32
33
34 #define PFX     KBUILD_MODNAME ": "
35
36 /*
37  * RNG registers
38  */
39 #define INTEL_RNG_HW_STATUS                     0
40 #define         INTEL_RNG_PRESENT               0x40
41 #define         INTEL_RNG_ENABLED               0x01
42 #define INTEL_RNG_STATUS                        1
43 #define         INTEL_RNG_DATA_PRESENT          0x01
44 #define INTEL_RNG_DATA                          2
45
46 /*
47  * Magic address at which Intel PCI bridges locate the RNG
48  */
49 #define INTEL_RNG_ADDR                          0xFFBC015F
50 #define INTEL_RNG_ADDR_LEN                      3
51
52 /*
53  * LPC bridge PCI config space registers
54  */
55 #define FWH_DEC_EN1_REG_OLD                     0xe3
56 #define FWH_DEC_EN1_REG_NEW                     0xd9 /* high byte of 16-bit register */
57 #define FWH_F8_EN_MASK                          0x80
58
59 #define BIOS_CNTL_REG_OLD                       0x4e
60 #define BIOS_CNTL_REG_NEW                       0xdc
61 #define BIOS_CNTL_WRITE_ENABLE_MASK             0x01
62 #define BIOS_CNTL_LOCK_ENABLE_MASK              0x02
63
64 /*
65  * Magic address at which Intel Firmware Hubs get accessed
66  */
67 #define INTEL_FWH_ADDR                          0xffff0000
68 #define INTEL_FWH_ADDR_LEN                      2
69
70 /*
71  * Intel Firmware Hub command codes (write to any address inside the device)
72  */
73 #define INTEL_FWH_RESET_CMD                     0xff /* aka READ_ARRAY */
74 #define INTEL_FWH_READ_ID_CMD                   0x90
75
76 /*
77  * Intel Firmware Hub Read ID command result addresses
78  */
79 #define INTEL_FWH_MANUFACTURER_CODE_ADDRESS     0x000000
80 #define INTEL_FWH_DEVICE_CODE_ADDRESS           0x000001
81
82 /*
83  * Intel Firmware Hub Read ID command result values
84  */
85 #define INTEL_FWH_MANUFACTURER_CODE             0x89
86 #define INTEL_FWH_DEVICE_CODE_8M                0xac
87 #define INTEL_FWH_DEVICE_CODE_4M                0xad
88
89 /*
90  * Data for PCI driver interface
91  *
92  * This data only exists for exporting the supported
93  * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
94  * register a pci_driver, because someone else might one day
95  * want to register another driver on the same PCI id.
96  */
97 static const struct pci_device_id pci_tbl[] = {
98 /* AA
99         { PCI_DEVICE(0x8086, 0x2418) }, */
100         { PCI_DEVICE(0x8086, 0x2410) }, /* AA */
101 /* AB
102         { PCI_DEVICE(0x8086, 0x2428) }, */
103         { PCI_DEVICE(0x8086, 0x2420) }, /* AB */
104 /* ??
105         { PCI_DEVICE(0x8086, 0x2430) }, */
106 /* BAM, CAM, DBM, FBM, GxM
107         { PCI_DEVICE(0x8086, 0x2448) }, */
108         { PCI_DEVICE(0x8086, 0x244c) }, /* BAM */
109         { PCI_DEVICE(0x8086, 0x248c) }, /* CAM */
110         { PCI_DEVICE(0x8086, 0x24cc) }, /* DBM */
111         { PCI_DEVICE(0x8086, 0x2641) }, /* FBM */
112         { PCI_DEVICE(0x8086, 0x27b9) }, /* GxM */
113         { PCI_DEVICE(0x8086, 0x27bd) }, /* GxM DH */
114 /* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx
115         { PCI_DEVICE(0x8086, 0x244e) }, */
116         { PCI_DEVICE(0x8086, 0x2440) }, /* BA */
117         { PCI_DEVICE(0x8086, 0x2480) }, /* CA */
118         { PCI_DEVICE(0x8086, 0x24c0) }, /* DB */
119         { PCI_DEVICE(0x8086, 0x24d0) }, /* Ex */
120         { PCI_DEVICE(0x8086, 0x25a1) }, /* 6300 */
121         { PCI_DEVICE(0x8086, 0x2640) }, /* Fx */
122         { PCI_DEVICE(0x8086, 0x2670) }, /* 631x/632x */
123         { PCI_DEVICE(0x8086, 0x2671) }, /* 631x/632x */
124         { PCI_DEVICE(0x8086, 0x2672) }, /* 631x/632x */
125         { PCI_DEVICE(0x8086, 0x2673) }, /* 631x/632x */
126         { PCI_DEVICE(0x8086, 0x2674) }, /* 631x/632x */
127         { PCI_DEVICE(0x8086, 0x2675) }, /* 631x/632x */
128         { PCI_DEVICE(0x8086, 0x2676) }, /* 631x/632x */
129         { PCI_DEVICE(0x8086, 0x2677) }, /* 631x/632x */
130         { PCI_DEVICE(0x8086, 0x2678) }, /* 631x/632x */
131         { PCI_DEVICE(0x8086, 0x2679) }, /* 631x/632x */
132         { PCI_DEVICE(0x8086, 0x267a) }, /* 631x/632x */
133         { PCI_DEVICE(0x8086, 0x267b) }, /* 631x/632x */
134         { PCI_DEVICE(0x8086, 0x267c) }, /* 631x/632x */
135         { PCI_DEVICE(0x8086, 0x267d) }, /* 631x/632x */
136         { PCI_DEVICE(0x8086, 0x267e) }, /* 631x/632x */
137         { PCI_DEVICE(0x8086, 0x267f) }, /* 631x/632x */
138         { PCI_DEVICE(0x8086, 0x27b8) }, /* Gx */
139 /* E
140         { PCI_DEVICE(0x8086, 0x245e) }, */
141         { PCI_DEVICE(0x8086, 0x2450) }, /* E  */
142         { 0, }, /* terminate list */
143 };
144 MODULE_DEVICE_TABLE(pci, pci_tbl);
145
146 static __initdata int no_fwh_detect;
147 module_param(no_fwh_detect, int, 0);
148 MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n"
149                                 " positive value - skip if FWH space locked read-only\n"
150                                 " negative value - skip always");
151
152 static inline u8 hwstatus_get(void __iomem *mem)
153 {
154         return readb(mem + INTEL_RNG_HW_STATUS);
155 }
156
157 static inline u8 hwstatus_set(void __iomem *mem,
158                               u8 hw_status)
159 {
160         writeb(hw_status, mem + INTEL_RNG_HW_STATUS);
161         return hwstatus_get(mem);
162 }
163
164 static int intel_rng_data_present(struct hwrng *rng)
165 {
166         void __iomem *mem = (void __iomem *)rng->priv;
167
168         return !!(readb(mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT);
169 }
170
171 static int intel_rng_data_read(struct hwrng *rng, u32 *data)
172 {
173         void __iomem *mem = (void __iomem *)rng->priv;
174
175         *data = readb(mem + INTEL_RNG_DATA);
176
177         return 1;
178 }
179
180 static int intel_rng_init(struct hwrng *rng)
181 {
182         void __iomem *mem = (void __iomem *)rng->priv;
183         u8 hw_status;
184         int err = -EIO;
185
186         hw_status = hwstatus_get(mem);
187         /* turn RNG h/w on, if it's off */
188         if ((hw_status & INTEL_RNG_ENABLED) == 0)
189                 hw_status = hwstatus_set(mem, hw_status | INTEL_RNG_ENABLED);
190         if ((hw_status & INTEL_RNG_ENABLED) == 0) {
191                 printk(KERN_ERR PFX "cannot enable RNG, aborting\n");
192                 goto out;
193         }
194         err = 0;
195 out:
196         return err;
197 }
198
199 static void intel_rng_cleanup(struct hwrng *rng)
200 {
201         void __iomem *mem = (void __iomem *)rng->priv;
202         u8 hw_status;
203
204         hw_status = hwstatus_get(mem);
205         if (hw_status & INTEL_RNG_ENABLED)
206                 hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED);
207         else
208                 printk(KERN_WARNING PFX "unusual: RNG already disabled\n");
209 }
210
211
212 static struct hwrng intel_rng = {
213         .name           = "intel",
214         .init           = intel_rng_init,
215         .cleanup        = intel_rng_cleanup,
216         .data_present   = intel_rng_data_present,
217         .data_read      = intel_rng_data_read,
218 };
219
220
221 #ifdef CONFIG_SMP
222 static char __initdata waitflag;
223
224 static void __init intel_init_wait(void *unused)
225 {
226         while (waitflag)
227                 cpu_relax();
228 }
229 #endif
230
231 static int __init mod_init(void)
232 {
233         int err = -ENODEV;
234         unsigned i;
235         struct pci_dev *dev = NULL;
236         void __iomem *mem;
237         unsigned long flags;
238         u8 bios_cntl_off, fwh_dec_en1_off;
239         u8 bios_cntl_val = 0xff, fwh_dec_en1_val = 0xff;
240         u8 hw_status, mfc, dvc;
241
242         for (i = 0; !dev && pci_tbl[i].vendor; ++i)
243                 dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device, NULL);
244
245         if (!dev)
246                 goto out; /* Device not found. */
247
248         if (no_fwh_detect < 0) {
249                 pci_dev_put(dev);
250                 goto fwh_done;
251         }
252
253         /* Check for Intel 82802 */
254         if (dev->device < 0x2640) {
255                 fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD;
256                 bios_cntl_off = BIOS_CNTL_REG_OLD;
257         } else {
258                 fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW;
259                 bios_cntl_off = BIOS_CNTL_REG_NEW;
260         }
261
262         pci_read_config_byte(dev, fwh_dec_en1_off, &fwh_dec_en1_val);
263         pci_read_config_byte(dev, bios_cntl_off, &bios_cntl_val);
264
265         if ((bios_cntl_val &
266              (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))
267             == BIOS_CNTL_LOCK_ENABLE_MASK) {
268                 static __initdata /*const*/ char warning[] =
269                         KERN_WARNING PFX "Firmware space is locked read-only. If you can't or\n"
270                         KERN_WARNING PFX "don't want to disable this in firmware setup, and if\n"
271                         KERN_WARNING PFX "you are certain that your system has a functional\n"
272                         KERN_WARNING PFX "RNG, try using the 'no_fwh_detect' option.\n";
273
274                 pci_dev_put(dev);
275                 if (no_fwh_detect)
276                         goto fwh_done;
277                 printk(warning);
278                 err = -EBUSY;
279                 goto out;
280         }
281
282         mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
283         if (mem == NULL) {
284                 pci_dev_put(dev);
285                 err = -EBUSY;
286                 goto out;
287         }
288
289         /*
290          * Since the BIOS code/data is going to disappear from its normal
291          * location with the Read ID command, all activity on the system
292          * must be stopped until the state is back to normal.
293          */
294 #ifdef CONFIG_SMP
295         set_mb(waitflag, 1);
296         if (smp_call_function(intel_init_wait, NULL, 1, 0) != 0) {
297                 set_mb(waitflag, 0);
298                 pci_dev_put(dev);
299                 printk(KERN_ERR PFX "cannot run on all processors\n");
300                 err = -EAGAIN;
301                 goto err_unmap;
302         }
303 #endif
304         local_irq_save(flags);
305
306         if (!(fwh_dec_en1_val & FWH_F8_EN_MASK))
307                 pci_write_config_byte(dev,
308                                       fwh_dec_en1_off,
309                                       fwh_dec_en1_val | FWH_F8_EN_MASK);
310         if (!(bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK))
311                 pci_write_config_byte(dev,
312                                       bios_cntl_off,
313                                       bios_cntl_val | BIOS_CNTL_WRITE_ENABLE_MASK);
314
315         writeb(INTEL_FWH_RESET_CMD, mem);
316         writeb(INTEL_FWH_READ_ID_CMD, mem);
317         mfc = readb(mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS);
318         dvc = readb(mem + INTEL_FWH_DEVICE_CODE_ADDRESS);
319         writeb(INTEL_FWH_RESET_CMD, mem);
320
321         if (!(bios_cntl_val &
322               (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK)))
323                 pci_write_config_byte(dev, bios_cntl_off, bios_cntl_val);
324         if (!(fwh_dec_en1_val & FWH_F8_EN_MASK))
325                 pci_write_config_byte(dev, fwh_dec_en1_off, fwh_dec_en1_val);
326
327         local_irq_restore(flags);
328 #ifdef CONFIG_SMP
329         /* Tell other CPUs to resume. */
330         set_mb(waitflag, 0);
331 #endif
332
333         iounmap(mem);
334         pci_dev_put(dev);
335
336         if (mfc != INTEL_FWH_MANUFACTURER_CODE ||
337             (dvc != INTEL_FWH_DEVICE_CODE_8M &&
338              dvc != INTEL_FWH_DEVICE_CODE_4M)) {
339                 printk(KERN_ERR PFX "FWH not detected\n");
340                 err = -ENODEV;
341                 goto out;
342         }
343
344 fwh_done:
345
346         err = -ENOMEM;
347         mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
348         if (!mem)
349                 goto out;
350         intel_rng.priv = (unsigned long)mem;
351
352         /* Check for Random Number Generator */
353         err = -ENODEV;
354         hw_status = hwstatus_get(mem);
355         if ((hw_status & INTEL_RNG_PRESENT) == 0)
356                 goto err_unmap;
357
358         printk(KERN_INFO "Intel 82802 RNG detected\n");
359         err = hwrng_register(&intel_rng);
360         if (err) {
361                 printk(KERN_ERR PFX "RNG registering failed (%d)\n",
362                        err);
363                 goto err_unmap;
364         }
365 out:
366         return err;
367
368 err_unmap:
369         iounmap(mem);
370         goto out;
371 }
372
373 static void __exit mod_exit(void)
374 {
375         void __iomem *mem = (void __iomem *)intel_rng.priv;
376
377         hwrng_unregister(&intel_rng);
378         iounmap(mem);
379 }
380
381 module_init(mod_init);
382 module_exit(mod_exit);
383
384 MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets");
385 MODULE_LICENSE("GPL");