2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct pci_dev *pdev,
200 static int ath5k_pci_resume(struct pci_dev *pdev);
202 #define ath5k_pci_suspend NULL
203 #define ath5k_pci_resume NULL
204 #endif /* CONFIG_PM */
206 static struct pci_driver ath5k_pci_driver = {
207 .name = KBUILD_MODNAME,
208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
222 static int ath5k_reset_wake(struct ath5k_softc *sc);
223 static int ath5k_start(struct ieee80211_hw *hw);
224 static void ath5k_stop(struct ieee80211_hw *hw);
225 static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227 static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
230 static int ath5k_config_interface(struct ieee80211_hw *hw,
231 struct ieee80211_vif *vif,
232 struct ieee80211_if_conf *conf);
233 static void ath5k_configure_filter(struct ieee80211_hw *hw,
234 unsigned int changed_flags,
235 unsigned int *new_flags,
236 int mc_count, struct dev_mc_list *mclist);
237 static int ath5k_set_key(struct ieee80211_hw *hw,
238 enum set_key_cmd cmd,
239 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
240 struct ieee80211_key_conf *key);
241 static int ath5k_get_stats(struct ieee80211_hw *hw,
242 struct ieee80211_low_level_stats *stats);
243 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
244 struct ieee80211_tx_queue_stats *stats);
245 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
246 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
247 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
248 static int ath5k_beacon_update(struct ath5k_softc *sc,
249 struct sk_buff *skb);
250 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif,
252 struct ieee80211_bss_conf *bss_conf,
255 static const struct ieee80211_ops ath5k_hw_ops = {
257 .start = ath5k_start,
259 .add_interface = ath5k_add_interface,
260 .remove_interface = ath5k_remove_interface,
261 .config = ath5k_config,
262 .config_interface = ath5k_config_interface,
263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
269 .set_tsf = ath5k_set_tsf,
270 .reset_tsf = ath5k_reset_tsf,
271 .bss_info_changed = ath5k_bss_info_changed,
275 * Prototypes - Internal functions
278 static int ath5k_attach(struct pci_dev *pdev,
279 struct ieee80211_hw *hw);
280 static void ath5k_detach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282 /* Channel/mode setup */
283 static inline short ath5k_ieee2mhz(short chan);
284 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
285 struct ieee80211_channel *channels,
288 static int ath5k_setup_bands(struct ieee80211_hw *hw);
289 static int ath5k_chan_set(struct ath5k_softc *sc,
290 struct ieee80211_channel *chan);
291 static void ath5k_setcurmode(struct ath5k_softc *sc,
293 static void ath5k_mode_setup(struct ath5k_softc *sc);
295 /* Descriptor setup */
296 static int ath5k_desc_alloc(struct ath5k_softc *sc,
297 struct pci_dev *pdev);
298 static void ath5k_desc_free(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
301 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
302 struct ath5k_buf *bf);
303 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
306 struct ath5k_buf *bf)
311 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
313 dev_kfree_skb_any(bf->skb);
317 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
318 struct ath5k_buf *bf)
323 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
325 dev_kfree_skb_any(bf->skb);
331 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
332 int qtype, int subtype);
333 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
334 static int ath5k_beaconq_config(struct ath5k_softc *sc);
335 static void ath5k_txq_drainq(struct ath5k_softc *sc,
336 struct ath5k_txq *txq);
337 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
338 static void ath5k_txq_release(struct ath5k_softc *sc);
340 static int ath5k_rx_start(struct ath5k_softc *sc);
341 static void ath5k_rx_stop(struct ath5k_softc *sc);
342 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
343 struct ath5k_desc *ds,
345 struct ath5k_rx_status *rs);
346 static void ath5k_tasklet_rx(unsigned long data);
348 static void ath5k_tx_processq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350 static void ath5k_tasklet_tx(unsigned long data);
351 /* Beacon handling */
352 static int ath5k_beacon_setup(struct ath5k_softc *sc,
353 struct ath5k_buf *bf);
354 static void ath5k_beacon_send(struct ath5k_softc *sc);
355 static void ath5k_beacon_config(struct ath5k_softc *sc);
356 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
357 static void ath5k_tasklet_beacon(unsigned long data);
359 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
361 u64 tsf = ath5k_hw_get_tsf64(ah);
363 if ((tsf & 0x7fff) < rstamp)
366 return (tsf & ~0x7fff) | rstamp;
369 /* Interrupt handling */
370 static int ath5k_init(struct ath5k_softc *sc);
371 static int ath5k_stop_locked(struct ath5k_softc *sc);
372 static int ath5k_stop_hw(struct ath5k_softc *sc);
373 static irqreturn_t ath5k_intr(int irq, void *dev_id);
374 static void ath5k_tasklet_reset(unsigned long data);
376 static void ath5k_calibrate(unsigned long data);
379 * Module init/exit functions
388 ret = pci_register_driver(&ath5k_pci_driver);
390 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
400 pci_unregister_driver(&ath5k_pci_driver);
402 ath5k_debug_finish();
405 module_init(init_ath5k_pci);
406 module_exit(exit_ath5k_pci);
409 /********************\
410 * PCI Initialization *
411 \********************/
414 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
416 const char *name = "xxxxx";
419 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
420 if (srev_names[i].sr_type != type)
423 if ((val & 0xf0) == srev_names[i].sr_val)
424 name = srev_names[i].sr_name;
426 if ((val & 0xff) == srev_names[i].sr_val) {
427 name = srev_names[i].sr_name;
436 ath5k_pci_probe(struct pci_dev *pdev,
437 const struct pci_device_id *id)
440 struct ath5k_softc *sc;
441 struct ieee80211_hw *hw;
445 ret = pci_enable_device(pdev);
447 dev_err(&pdev->dev, "can't enable device\n");
451 /* XXX 32-bit addressing only */
452 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
454 dev_err(&pdev->dev, "32-bit DMA not available\n");
459 * Cache line size is used to size and align various
460 * structures used to communicate with the hardware.
462 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
465 * Linux 2.4.18 (at least) writes the cache line size
466 * register as a 16-bit wide register which is wrong.
467 * We must have this setup properly for rx buffer
468 * DMA to work so force a reasonable value here if it
471 csz = L1_CACHE_BYTES / sizeof(u32);
472 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
475 * The default setting of latency timer yields poor results,
476 * set it to the value used by other systems. It may be worth
477 * tweaking this setting more.
479 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
481 /* Enable bus mastering */
482 pci_set_master(pdev);
485 * Disable the RETRY_TIMEOUT register (0x41) to keep
486 * PCI Tx retries from interfering with C3 CPU state.
488 pci_write_config_byte(pdev, 0x41, 0);
490 ret = pci_request_region(pdev, 0, "ath5k");
492 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
496 mem = pci_iomap(pdev, 0, 0);
498 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
504 * Allocate hw (mac80211 main struct)
505 * and hw->priv (driver private data)
507 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
509 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
514 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
516 /* Initialize driver private data */
517 SET_IEEE80211_DEV(hw, &pdev->dev);
518 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
519 IEEE80211_HW_SIGNAL_DBM |
520 IEEE80211_HW_NOISE_DBM;
522 hw->wiphy->interface_modes =
523 BIT(NL80211_IFTYPE_STATION) |
524 BIT(NL80211_IFTYPE_ADHOC) |
525 BIT(NL80211_IFTYPE_MESH_POINT);
527 hw->extra_tx_headroom = 2;
528 hw->channel_change_time = 5000;
533 ath5k_debug_init_device(sc);
536 * Mark the device as detached to avoid processing
537 * interrupts until setup is complete.
539 __set_bit(ATH_STAT_INVALID, sc->status);
541 sc->iobase = mem; /* So we can unmap it on detach */
542 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
543 sc->opmode = NL80211_IFTYPE_STATION;
544 mutex_init(&sc->lock);
545 spin_lock_init(&sc->rxbuflock);
546 spin_lock_init(&sc->txbuflock);
547 spin_lock_init(&sc->block);
549 /* Set private data */
550 pci_set_drvdata(pdev, hw);
552 /* Setup interrupt handler */
553 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
555 ATH5K_ERR(sc, "request_irq failed\n");
559 /* Initialize device */
560 sc->ah = ath5k_hw_attach(sc, id->driver_data);
561 if (IS_ERR(sc->ah)) {
562 ret = PTR_ERR(sc->ah);
566 /* set up multi-rate retry capabilities */
567 if (sc->ah->ah_version == AR5K_AR5212) {
569 hw->max_rate_tries = 11;
572 /* Finish private driver data initialization */
573 ret = ath5k_attach(pdev, hw);
577 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
578 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
580 sc->ah->ah_phy_revision);
582 if (!sc->ah->ah_single_chip) {
583 /* Single chip radio (!RF5111) */
584 if (sc->ah->ah_radio_5ghz_revision &&
585 !sc->ah->ah_radio_2ghz_revision) {
586 /* No 5GHz support -> report 2GHz radio */
587 if (!test_bit(AR5K_MODE_11A,
588 sc->ah->ah_capabilities.cap_mode)) {
589 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
593 /* No 2GHz support (5110 and some
594 * 5Ghz only cards) -> report 5Ghz radio */
595 } else if (!test_bit(AR5K_MODE_11B,
596 sc->ah->ah_capabilities.cap_mode)) {
597 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_5ghz_revision),
600 sc->ah->ah_radio_5ghz_revision);
601 /* Multiband radio */
603 ATH5K_INFO(sc, "RF%s multiband radio found"
605 ath5k_chip_name(AR5K_VERSION_RAD,
606 sc->ah->ah_radio_5ghz_revision),
607 sc->ah->ah_radio_5ghz_revision);
610 /* Multi chip radio (RF5111 - RF2111) ->
611 * report both 2GHz/5GHz radios */
612 else if (sc->ah->ah_radio_5ghz_revision &&
613 sc->ah->ah_radio_2ghz_revision){
614 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_5ghz_revision),
617 sc->ah->ah_radio_5ghz_revision);
618 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
619 ath5k_chip_name(AR5K_VERSION_RAD,
620 sc->ah->ah_radio_2ghz_revision),
621 sc->ah->ah_radio_2ghz_revision);
626 /* ready to process interrupts */
627 __clear_bit(ATH_STAT_INVALID, sc->status);
631 ath5k_hw_detach(sc->ah);
633 free_irq(pdev->irq, sc);
635 ieee80211_free_hw(hw);
637 pci_iounmap(pdev, mem);
639 pci_release_region(pdev, 0);
641 pci_disable_device(pdev);
646 static void __devexit
647 ath5k_pci_remove(struct pci_dev *pdev)
649 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
650 struct ath5k_softc *sc = hw->priv;
652 ath5k_debug_finish_device(sc);
653 ath5k_detach(pdev, hw);
654 ath5k_hw_detach(sc->ah);
655 free_irq(pdev->irq, sc);
656 pci_iounmap(pdev, sc->iobase);
657 pci_release_region(pdev, 0);
658 pci_disable_device(pdev);
659 ieee80211_free_hw(hw);
664 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
666 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
667 struct ath5k_softc *sc = hw->priv;
671 free_irq(pdev->irq, sc);
672 pci_save_state(pdev);
673 pci_disable_device(pdev);
674 pci_set_power_state(pdev, PCI_D3hot);
680 ath5k_pci_resume(struct pci_dev *pdev)
682 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
683 struct ath5k_softc *sc = hw->priv;
686 pci_restore_state(pdev);
688 err = pci_enable_device(pdev);
692 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
694 ATH5K_ERR(sc, "request_irq failed\n");
698 ath5k_led_enable(sc);
702 pci_disable_device(pdev);
705 #endif /* CONFIG_PM */
708 /***********************\
709 * Driver Initialization *
710 \***********************/
712 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
714 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
715 struct ath5k_softc *sc = hw->priv;
716 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
718 return ath_reg_notifier_apply(wiphy, request, reg);
722 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
724 struct ath5k_softc *sc = hw->priv;
725 struct ath5k_hw *ah = sc->ah;
726 u8 mac[ETH_ALEN] = {};
729 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
732 * Check if the MAC has multi-rate retry support.
733 * We do this by trying to setup a fake extended
734 * descriptor. MAC's that don't have support will
735 * return false w/o doing anything. MAC's that do
736 * support it will return true w/o doing anything.
738 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
742 __set_bit(ATH_STAT_MRRETRY, sc->status);
745 * Collect the channel list. The 802.11 layer
746 * is resposible for filtering this list based
747 * on settings like the phy mode and regulatory
748 * domain restrictions.
750 ret = ath5k_setup_bands(hw);
752 ATH5K_ERR(sc, "can't get channels\n");
756 /* NB: setup here so ath5k_rate_update is happy */
757 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
758 ath5k_setcurmode(sc, AR5K_MODE_11A);
760 ath5k_setcurmode(sc, AR5K_MODE_11B);
763 * Allocate tx+rx descriptors and populate the lists.
765 ret = ath5k_desc_alloc(sc, pdev);
767 ATH5K_ERR(sc, "can't allocate descriptors\n");
772 * Allocate hardware transmit queues: one queue for
773 * beacon frames and one data queue for each QoS
774 * priority. Note that hw functions handle reseting
775 * these queues at the needed time.
777 ret = ath5k_beaconq_setup(ah);
779 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
784 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
785 if (IS_ERR(sc->txq)) {
786 ATH5K_ERR(sc, "can't setup xmit queue\n");
787 ret = PTR_ERR(sc->txq);
791 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
792 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
793 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
794 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
795 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
797 ret = ath5k_eeprom_read_mac(ah, mac);
799 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
804 SET_IEEE80211_PERM_ADDR(hw, mac);
805 /* All MAC address bits matter for ACKs */
806 memset(sc->bssidmask, 0xff, ETH_ALEN);
807 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
809 ah->ah_regulatory.current_rd =
810 ah->ah_capabilities.cap_eeprom.ee_regdomain;
811 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
813 ATH5K_ERR(sc, "can't initialize regulatory system\n");
817 ret = ieee80211_register_hw(hw);
819 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
823 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
824 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
830 ath5k_txq_release(sc);
832 ath5k_hw_release_tx_queue(ah, sc->bhalq);
834 ath5k_desc_free(sc, pdev);
840 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
842 struct ath5k_softc *sc = hw->priv;
845 * NB: the order of these is important:
846 * o call the 802.11 layer before detaching ath5k_hw to
847 * insure callbacks into the driver to delete global
848 * key cache entries can be handled
849 * o reclaim the tx queue data structures after calling
850 * the 802.11 layer as we'll get called back to reclaim
851 * node state and potentially want to use them
852 * o to cleanup the tx queues the hal is called, so detach
854 * XXX: ??? detach ath5k_hw ???
855 * Other than that, it's straightforward...
857 ieee80211_unregister_hw(hw);
858 ath5k_desc_free(sc, pdev);
859 ath5k_txq_release(sc);
860 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
861 ath5k_unregister_leds(sc);
864 * NB: can't reclaim these until after ieee80211_ifdetach
865 * returns because we'll get called back to reclaim node
866 * state and potentially want to use them.
873 /********************\
874 * Channel/mode setup *
875 \********************/
878 * Convert IEEE channel number to MHz frequency.
881 ath5k_ieee2mhz(short chan)
883 if (chan <= 14 || chan >= 27)
884 return ieee80211chan2mhz(chan);
886 return 2212 + chan * 20;
890 * Returns true for the channel numbers used without all_channels modparam.
892 static bool ath5k_is_standard_channel(short chan)
894 return ((chan <= 14) ||
896 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
898 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
900 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
904 ath5k_copy_channels(struct ath5k_hw *ah,
905 struct ieee80211_channel *channels,
909 unsigned int i, count, size, chfreq, freq, ch;
911 if (!test_bit(mode, ah->ah_modes))
916 case AR5K_MODE_11A_TURBO:
917 /* 1..220, but 2GHz frequencies are filtered by check_channel */
919 chfreq = CHANNEL_5GHZ;
923 case AR5K_MODE_11G_TURBO:
925 chfreq = CHANNEL_2GHZ;
928 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
932 for (i = 0, count = 0; i < size && max > 0; i++) {
934 freq = ath5k_ieee2mhz(ch);
936 /* Check if channel is supported by the chipset */
937 if (!ath5k_channel_ok(ah, freq, chfreq))
940 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
943 /* Write channel info and increment counter */
944 channels[count].center_freq = freq;
945 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
946 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
950 channels[count].hw_value = chfreq | CHANNEL_OFDM;
952 case AR5K_MODE_11A_TURBO:
953 case AR5K_MODE_11G_TURBO:
954 channels[count].hw_value = chfreq |
955 CHANNEL_OFDM | CHANNEL_TURBO;
958 channels[count].hw_value = CHANNEL_B;
969 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
973 for (i = 0; i < AR5K_MAX_RATES; i++)
974 sc->rate_idx[b->band][i] = -1;
976 for (i = 0; i < b->n_bitrates; i++) {
977 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
978 if (b->bitrates[i].hw_value_short)
979 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
984 ath5k_setup_bands(struct ieee80211_hw *hw)
986 struct ath5k_softc *sc = hw->priv;
987 struct ath5k_hw *ah = sc->ah;
988 struct ieee80211_supported_band *sband;
989 int max_c, count_c = 0;
992 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
993 max_c = ARRAY_SIZE(sc->channels);
996 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
997 sband->band = IEEE80211_BAND_2GHZ;
998 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1000 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1002 memcpy(sband->bitrates, &ath5k_rates[0],
1003 sizeof(struct ieee80211_rate) * 12);
1004 sband->n_bitrates = 12;
1006 sband->channels = sc->channels;
1007 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1008 AR5K_MODE_11G, max_c);
1010 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1011 count_c = sband->n_channels;
1013 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1015 memcpy(sband->bitrates, &ath5k_rates[0],
1016 sizeof(struct ieee80211_rate) * 4);
1017 sband->n_bitrates = 4;
1019 /* 5211 only supports B rates and uses 4bit rate codes
1020 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1023 if (ah->ah_version == AR5K_AR5211) {
1024 for (i = 0; i < 4; i++) {
1025 sband->bitrates[i].hw_value =
1026 sband->bitrates[i].hw_value & 0xF;
1027 sband->bitrates[i].hw_value_short =
1028 sband->bitrates[i].hw_value_short & 0xF;
1032 sband->channels = sc->channels;
1033 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1034 AR5K_MODE_11B, max_c);
1036 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1037 count_c = sband->n_channels;
1040 ath5k_setup_rate_idx(sc, sband);
1042 /* 5GHz band, A mode */
1043 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1044 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1045 sband->band = IEEE80211_BAND_5GHZ;
1046 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1048 memcpy(sband->bitrates, &ath5k_rates[4],
1049 sizeof(struct ieee80211_rate) * 8);
1050 sband->n_bitrates = 8;
1052 sband->channels = &sc->channels[count_c];
1053 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1054 AR5K_MODE_11A, max_c);
1056 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1058 ath5k_setup_rate_idx(sc, sband);
1060 ath5k_debug_dump_bands(sc);
1066 * Set/change channels. If the channel is really being changed,
1067 * it's done by reseting the chip. To accomplish this we must
1068 * first cleanup any pending DMA, then restart stuff after a la
1071 * Called with sc->lock.
1074 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1076 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1077 sc->curchan->center_freq, chan->center_freq);
1079 if (chan->center_freq != sc->curchan->center_freq ||
1080 chan->hw_value != sc->curchan->hw_value) {
1083 sc->curband = &sc->sbands[chan->band];
1086 * To switch channels clear any pending DMA operations;
1087 * wait long enough for the RX fifo to drain, reset the
1088 * hardware at the new frequency, and then re-enable
1089 * the relevant bits of the h/w.
1091 return ath5k_reset(sc, true, true);
1098 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1102 if (mode == AR5K_MODE_11A) {
1103 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1105 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1110 ath5k_mode_setup(struct ath5k_softc *sc)
1112 struct ath5k_hw *ah = sc->ah;
1115 /* configure rx filter */
1116 rfilt = sc->filter_flags;
1117 ath5k_hw_set_rx_filter(ah, rfilt);
1119 if (ath5k_hw_hasbssidmask(ah))
1120 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1122 /* configure operational mode */
1123 ath5k_hw_set_opmode(ah);
1125 ath5k_hw_set_mcast_filter(ah, 0, 0);
1126 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1130 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1134 /* return base rate on errors */
1135 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1136 "hw_rix out of bounds: %x\n", hw_rix))
1139 rix = sc->rate_idx[sc->curband->band][hw_rix];
1140 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1151 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1153 struct sk_buff *skb;
1157 * Allocate buffer with headroom_needed space for the
1158 * fake physical layer header at the start.
1160 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1163 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1164 sc->rxbufsize + sc->cachelsz - 1);
1168 * Cache-line-align. This is important (for the
1169 * 5210 at least) as not doing so causes bogus data
1172 off = ((unsigned long)skb->data) % sc->cachelsz;
1174 skb_reserve(skb, sc->cachelsz - off);
1176 *skb_addr = pci_map_single(sc->pdev,
1177 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1178 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1179 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1187 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1189 struct ath5k_hw *ah = sc->ah;
1190 struct sk_buff *skb = bf->skb;
1191 struct ath5k_desc *ds;
1194 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1201 * Setup descriptors. For receive we always terminate
1202 * the descriptor list with a self-linked entry so we'll
1203 * not get overrun under high load (as can happen with a
1204 * 5212 when ANI processing enables PHY error frames).
1206 * To insure the last descriptor is self-linked we create
1207 * each descriptor as self-linked and add it to the end. As
1208 * each additional descriptor is added the previous self-linked
1209 * entry is ``fixed'' naturally. This should be safe even
1210 * if DMA is happening. When processing RX interrupts we
1211 * never remove/process the last, self-linked, entry on the
1212 * descriptor list. This insures the hardware always has
1213 * someplace to write a new frame.
1216 ds->ds_link = bf->daddr; /* link to self */
1217 ds->ds_data = bf->skbaddr;
1218 ah->ah_setup_rx_desc(ah, ds,
1219 skb_tailroom(skb), /* buffer size */
1222 if (sc->rxlink != NULL)
1223 *sc->rxlink = bf->daddr;
1224 sc->rxlink = &ds->ds_link;
1229 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1231 struct ath5k_hw *ah = sc->ah;
1232 struct ath5k_txq *txq = sc->txq;
1233 struct ath5k_desc *ds = bf->desc;
1234 struct sk_buff *skb = bf->skb;
1235 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1236 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1237 struct ieee80211_rate *rate;
1238 unsigned int mrr_rate[3], mrr_tries[3];
1245 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1247 /* XXX endianness */
1248 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1251 rate = ieee80211_get_tx_rate(sc->hw, info);
1253 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1254 flags |= AR5K_TXDESC_NOACK;
1256 rc_flags = info->control.rates[0].flags;
1257 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1258 rate->hw_value_short : rate->hw_value;
1262 /* FIXME: If we are in g mode and rate is a CCK rate
1263 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1264 * from tx power (value is in dB units already) */
1265 if (info->control.hw_key) {
1266 keyidx = info->control.hw_key->hw_key_idx;
1267 pktlen += info->control.hw_key->icv_len;
1269 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1270 flags |= AR5K_TXDESC_RTSENA;
1271 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1272 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1273 sc->vif, pktlen, info));
1275 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1276 flags |= AR5K_TXDESC_CTSENA;
1277 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1278 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1279 sc->vif, pktlen, info));
1281 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1282 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1283 (sc->power_level * 2),
1285 info->control.rates[0].count, keyidx, 0, flags,
1286 cts_rate, duration);
1290 memset(mrr_rate, 0, sizeof(mrr_rate));
1291 memset(mrr_tries, 0, sizeof(mrr_tries));
1292 for (i = 0; i < 3; i++) {
1293 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1297 mrr_rate[i] = rate->hw_value;
1298 mrr_tries[i] = info->control.rates[i + 1].count;
1301 ah->ah_setup_mrr_tx_desc(ah, ds,
1302 mrr_rate[0], mrr_tries[0],
1303 mrr_rate[1], mrr_tries[1],
1304 mrr_rate[2], mrr_tries[2]);
1307 ds->ds_data = bf->skbaddr;
1309 spin_lock_bh(&txq->lock);
1310 list_add_tail(&bf->list, &txq->q);
1311 sc->tx_stats[txq->qnum].len++;
1312 if (txq->link == NULL) /* is this first packet? */
1313 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1314 else /* no, so only link it */
1315 *txq->link = bf->daddr;
1317 txq->link = &ds->ds_link;
1318 ath5k_hw_start_tx_dma(ah, txq->qnum);
1320 spin_unlock_bh(&txq->lock);
1324 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1328 /*******************\
1329 * Descriptors setup *
1330 \*******************/
1333 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1335 struct ath5k_desc *ds;
1336 struct ath5k_buf *bf;
1341 /* allocate descriptors */
1342 sc->desc_len = sizeof(struct ath5k_desc) *
1343 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1344 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1345 if (sc->desc == NULL) {
1346 ATH5K_ERR(sc, "can't allocate descriptors\n");
1351 da = sc->desc_daddr;
1352 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1353 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1355 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1356 sizeof(struct ath5k_buf), GFP_KERNEL);
1358 ATH5K_ERR(sc, "can't allocate bufptr\n");
1364 INIT_LIST_HEAD(&sc->rxbuf);
1365 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1368 list_add_tail(&bf->list, &sc->rxbuf);
1371 INIT_LIST_HEAD(&sc->txbuf);
1372 sc->txbuf_len = ATH_TXBUF;
1373 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1374 da += sizeof(*ds)) {
1377 list_add_tail(&bf->list, &sc->txbuf);
1387 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1394 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1396 struct ath5k_buf *bf;
1398 ath5k_txbuf_free(sc, sc->bbuf);
1399 list_for_each_entry(bf, &sc->txbuf, list)
1400 ath5k_txbuf_free(sc, bf);
1401 list_for_each_entry(bf, &sc->rxbuf, list)
1402 ath5k_rxbuf_free(sc, bf);
1404 /* Free memory associated with all descriptors */
1405 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1419 static struct ath5k_txq *
1420 ath5k_txq_setup(struct ath5k_softc *sc,
1421 int qtype, int subtype)
1423 struct ath5k_hw *ah = sc->ah;
1424 struct ath5k_txq *txq;
1425 struct ath5k_txq_info qi = {
1426 .tqi_subtype = subtype,
1427 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1428 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1429 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1434 * Enable interrupts only for EOL and DESC conditions.
1435 * We mark tx descriptors to receive a DESC interrupt
1436 * when a tx queue gets deep; otherwise waiting for the
1437 * EOL to reap descriptors. Note that this is done to
1438 * reduce interrupt load and this only defers reaping
1439 * descriptors, never transmitting frames. Aside from
1440 * reducing interrupts this also permits more concurrency.
1441 * The only potential downside is if the tx queue backs
1442 * up in which case the top half of the kernel may backup
1443 * due to a lack of tx descriptors.
1445 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1446 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1447 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1450 * NB: don't print a message, this happens
1451 * normally on parts with too few tx queues
1453 return ERR_PTR(qnum);
1455 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1456 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1457 qnum, ARRAY_SIZE(sc->txqs));
1458 ath5k_hw_release_tx_queue(ah, qnum);
1459 return ERR_PTR(-EINVAL);
1461 txq = &sc->txqs[qnum];
1465 INIT_LIST_HEAD(&txq->q);
1466 spin_lock_init(&txq->lock);
1469 return &sc->txqs[qnum];
1473 ath5k_beaconq_setup(struct ath5k_hw *ah)
1475 struct ath5k_txq_info qi = {
1476 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1477 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1478 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1479 /* NB: for dynamic turbo, don't enable any other interrupts */
1480 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1483 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1487 ath5k_beaconq_config(struct ath5k_softc *sc)
1489 struct ath5k_hw *ah = sc->ah;
1490 struct ath5k_txq_info qi;
1493 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1496 if (sc->opmode == NL80211_IFTYPE_AP ||
1497 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1499 * Always burst out beacon and CAB traffic
1500 * (aifs = cwmin = cwmax = 0)
1505 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1507 * Adhoc mode; backoff between 0 and (2 * cw_min).
1511 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1514 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1515 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1516 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1518 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1520 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1521 "hardware queue!\n", __func__);
1525 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1529 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1531 struct ath5k_buf *bf, *bf0;
1534 * NB: this assumes output has been stopped and
1535 * we do not need to block ath5k_tx_tasklet
1537 spin_lock_bh(&txq->lock);
1538 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1539 ath5k_debug_printtxbuf(sc, bf);
1541 ath5k_txbuf_free(sc, bf);
1543 spin_lock_bh(&sc->txbuflock);
1544 sc->tx_stats[txq->qnum].len--;
1545 list_move_tail(&bf->list, &sc->txbuf);
1547 spin_unlock_bh(&sc->txbuflock);
1550 spin_unlock_bh(&txq->lock);
1554 * Drain the transmit queues and reclaim resources.
1557 ath5k_txq_cleanup(struct ath5k_softc *sc)
1559 struct ath5k_hw *ah = sc->ah;
1562 /* XXX return value */
1563 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1564 /* don't touch the hardware if marked invalid */
1565 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1566 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1567 ath5k_hw_get_txdp(ah, sc->bhalq));
1568 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1569 if (sc->txqs[i].setup) {
1570 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1571 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1574 ath5k_hw_get_txdp(ah,
1579 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1581 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1582 if (sc->txqs[i].setup)
1583 ath5k_txq_drainq(sc, &sc->txqs[i]);
1587 ath5k_txq_release(struct ath5k_softc *sc)
1589 struct ath5k_txq *txq = sc->txqs;
1592 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1594 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1607 * Enable the receive h/w following a reset.
1610 ath5k_rx_start(struct ath5k_softc *sc)
1612 struct ath5k_hw *ah = sc->ah;
1613 struct ath5k_buf *bf;
1616 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1618 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1619 sc->cachelsz, sc->rxbufsize);
1621 spin_lock_bh(&sc->rxbuflock);
1623 list_for_each_entry(bf, &sc->rxbuf, list) {
1624 ret = ath5k_rxbuf_setup(sc, bf);
1626 spin_unlock_bh(&sc->rxbuflock);
1630 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1631 ath5k_hw_set_rxdp(ah, bf->daddr);
1632 spin_unlock_bh(&sc->rxbuflock);
1634 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1635 ath5k_mode_setup(sc); /* set filters, etc. */
1636 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1644 * Disable the receive h/w in preparation for a reset.
1647 ath5k_rx_stop(struct ath5k_softc *sc)
1649 struct ath5k_hw *ah = sc->ah;
1651 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1652 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1653 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1655 ath5k_debug_printrxbuffs(sc, ah);
1657 sc->rxlink = NULL; /* just in case */
1661 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1662 struct sk_buff *skb, struct ath5k_rx_status *rs)
1664 struct ieee80211_hdr *hdr = (void *)skb->data;
1665 unsigned int keyix, hlen;
1667 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1668 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1669 return RX_FLAG_DECRYPTED;
1671 /* Apparently when a default key is used to decrypt the packet
1672 the hw does not set the index used to decrypt. In such cases
1673 get the index from the packet. */
1674 hlen = ieee80211_hdrlen(hdr->frame_control);
1675 if (ieee80211_has_protected(hdr->frame_control) &&
1676 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1677 skb->len >= hlen + 4) {
1678 keyix = skb->data[hlen + 3] >> 6;
1680 if (test_bit(keyix, sc->keymap))
1681 return RX_FLAG_DECRYPTED;
1689 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1690 struct ieee80211_rx_status *rxs)
1694 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1696 if (ieee80211_is_beacon(mgmt->frame_control) &&
1697 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1698 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1700 * Received an IBSS beacon with the same BSSID. Hardware *must*
1701 * have updated the local TSF. We have to work around various
1702 * hardware bugs, though...
1704 tsf = ath5k_hw_get_tsf64(sc->ah);
1705 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1706 hw_tu = TSF_TO_TU(tsf);
1708 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1709 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1710 (unsigned long long)bc_tstamp,
1711 (unsigned long long)rxs->mactime,
1712 (unsigned long long)(rxs->mactime - bc_tstamp),
1713 (unsigned long long)tsf);
1716 * Sometimes the HW will give us a wrong tstamp in the rx
1717 * status, causing the timestamp extension to go wrong.
1718 * (This seems to happen especially with beacon frames bigger
1719 * than 78 byte (incl. FCS))
1720 * But we know that the receive timestamp must be later than the
1721 * timestamp of the beacon since HW must have synced to that.
1723 * NOTE: here we assume mactime to be after the frame was
1724 * received, not like mac80211 which defines it at the start.
1726 if (bc_tstamp > rxs->mactime) {
1727 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1728 "fixing mactime from %llx to %llx\n",
1729 (unsigned long long)rxs->mactime,
1730 (unsigned long long)tsf);
1735 * Local TSF might have moved higher than our beacon timers,
1736 * in that case we have to update them to continue sending
1737 * beacons. This also takes care of synchronizing beacon sending
1738 * times with other stations.
1740 if (hw_tu >= sc->nexttbtt)
1741 ath5k_beacon_update_timers(sc, bc_tstamp);
1745 static void ath5k_tasklet_beacon(unsigned long data)
1747 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1750 * Software beacon alert--time to send a beacon.
1752 * In IBSS mode we use this interrupt just to
1753 * keep track of the next TBTT (target beacon
1754 * transmission time) in order to detect wether
1755 * automatic TSF updates happened.
1757 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1758 /* XXX: only if VEOL suppported */
1759 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1760 sc->nexttbtt += sc->bintval;
1761 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1762 "SWBA nexttbtt: %x hw_tu: %x "
1766 (unsigned long long) tsf);
1768 spin_lock(&sc->block);
1769 ath5k_beacon_send(sc);
1770 spin_unlock(&sc->block);
1775 ath5k_tasklet_rx(unsigned long data)
1777 struct ieee80211_rx_status rxs = {};
1778 struct ath5k_rx_status rs = {};
1779 struct sk_buff *skb, *next_skb;
1780 dma_addr_t next_skb_addr;
1781 struct ath5k_softc *sc = (void *)data;
1782 struct ath5k_buf *bf;
1783 struct ath5k_desc *ds;
1788 spin_lock(&sc->rxbuflock);
1789 if (list_empty(&sc->rxbuf)) {
1790 ATH5K_WARN(sc, "empty rx buf pool\n");
1796 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1797 BUG_ON(bf->skb == NULL);
1801 /* bail if HW is still using self-linked descriptor */
1802 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1805 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1806 if (unlikely(ret == -EINPROGRESS))
1808 else if (unlikely(ret)) {
1809 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1810 spin_unlock(&sc->rxbuflock);
1814 if (unlikely(rs.rs_more)) {
1815 ATH5K_WARN(sc, "unsupported jumbo\n");
1819 if (unlikely(rs.rs_status)) {
1820 if (rs.rs_status & AR5K_RXERR_PHY)
1822 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1824 * Decrypt error. If the error occurred
1825 * because there was no hardware key, then
1826 * let the frame through so the upper layers
1827 * can process it. This is necessary for 5210
1828 * parts which have no way to setup a ``clear''
1831 * XXX do key cache faulting
1833 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1834 !(rs.rs_status & AR5K_RXERR_CRC))
1837 if (rs.rs_status & AR5K_RXERR_MIC) {
1838 rxs.flag |= RX_FLAG_MMIC_ERROR;
1842 /* let crypto-error packets fall through in MNTR */
1844 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1845 sc->opmode != NL80211_IFTYPE_MONITOR)
1849 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1852 * If we can't replace bf->skb with a new skb under memory
1853 * pressure, just skip this packet
1858 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1859 PCI_DMA_FROMDEVICE);
1860 skb_put(skb, rs.rs_datalen);
1862 /* The MAC header is padded to have 32-bit boundary if the
1863 * packet payload is non-zero. The general calculation for
1864 * padsize would take into account odd header lengths:
1865 * padsize = (4 - hdrlen % 4) % 4; However, since only
1866 * even-length headers are used, padding can only be 0 or 2
1867 * bytes and we can optimize this a bit. In addition, we must
1868 * not try to remove padding from short control frames that do
1869 * not have payload. */
1870 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1871 padsize = ath5k_pad_size(hdrlen);
1873 memmove(skb->data + padsize, skb->data, hdrlen);
1874 skb_pull(skb, padsize);
1878 * always extend the mac timestamp, since this information is
1879 * also needed for proper IBSS merging.
1881 * XXX: it might be too late to do it here, since rs_tstamp is
1882 * 15bit only. that means TSF extension has to be done within
1883 * 32768usec (about 32ms). it might be necessary to move this to
1884 * the interrupt handler, like it is done in madwifi.
1886 * Unfortunately we don't know when the hardware takes the rx
1887 * timestamp (beginning of phy frame, data frame, end of rx?).
1888 * The only thing we know is that it is hardware specific...
1889 * On AR5213 it seems the rx timestamp is at the end of the
1890 * frame, but i'm not sure.
1892 * NOTE: mac80211 defines mactime at the beginning of the first
1893 * data symbol. Since we don't have any time references it's
1894 * impossible to comply to that. This affects IBSS merge only
1895 * right now, so it's not too bad...
1897 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1898 rxs.flag |= RX_FLAG_TSFT;
1900 rxs.freq = sc->curchan->center_freq;
1901 rxs.band = sc->curband->band;
1903 rxs.noise = sc->ah->ah_noise_floor;
1904 rxs.signal = rxs.noise + rs.rs_rssi;
1906 /* An rssi of 35 indicates you should be able use
1907 * 54 Mbps reliably. A more elaborate scheme can be used
1908 * here but it requires a map of SNR/throughput for each
1909 * possible mode used */
1910 rxs.qual = rs.rs_rssi * 100 / 35;
1912 /* rssi can be more than 35 though, anything above that
1913 * should be considered at 100% */
1917 rxs.antenna = rs.rs_antenna;
1918 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1919 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1921 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1922 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1923 rxs.flag |= RX_FLAG_SHORTPRE;
1925 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1927 /* check beacons in IBSS mode */
1928 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1929 ath5k_check_ibss_tsf(sc, skb, &rxs);
1931 __ieee80211_rx(sc->hw, skb, &rxs);
1934 bf->skbaddr = next_skb_addr;
1936 list_move_tail(&bf->list, &sc->rxbuf);
1937 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1939 spin_unlock(&sc->rxbuflock);
1950 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1952 struct ath5k_tx_status ts = {};
1953 struct ath5k_buf *bf, *bf0;
1954 struct ath5k_desc *ds;
1955 struct sk_buff *skb;
1956 struct ieee80211_tx_info *info;
1959 spin_lock(&txq->lock);
1960 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1963 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1964 if (unlikely(ret == -EINPROGRESS))
1966 else if (unlikely(ret)) {
1967 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1973 info = IEEE80211_SKB_CB(skb);
1976 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1979 ieee80211_tx_info_clear_status(info);
1980 for (i = 0; i < 4; i++) {
1981 struct ieee80211_tx_rate *r =
1982 &info->status.rates[i];
1984 if (ts.ts_rate[i]) {
1985 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1986 r->count = ts.ts_retry[i];
1993 /* count the successful attempt as well */
1994 info->status.rates[ts.ts_final_idx].count++;
1996 if (unlikely(ts.ts_status)) {
1997 sc->ll_stats.dot11ACKFailureCount++;
1998 if (ts.ts_status & AR5K_TXERR_FILT)
1999 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2001 info->flags |= IEEE80211_TX_STAT_ACK;
2002 info->status.ack_signal = ts.ts_rssi;
2005 ieee80211_tx_status(sc->hw, skb);
2006 sc->tx_stats[txq->qnum].count++;
2008 spin_lock(&sc->txbuflock);
2009 sc->tx_stats[txq->qnum].len--;
2010 list_move_tail(&bf->list, &sc->txbuf);
2012 spin_unlock(&sc->txbuflock);
2014 if (likely(list_empty(&txq->q)))
2016 spin_unlock(&txq->lock);
2017 if (sc->txbuf_len > ATH_TXBUF / 5)
2018 ieee80211_wake_queues(sc->hw);
2022 ath5k_tasklet_tx(unsigned long data)
2024 struct ath5k_softc *sc = (void *)data;
2026 ath5k_tx_processq(sc, sc->txq);
2035 * Setup the beacon frame for transmit.
2038 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2040 struct sk_buff *skb = bf->skb;
2041 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2042 struct ath5k_hw *ah = sc->ah;
2043 struct ath5k_desc *ds;
2044 int ret, antenna = 0;
2047 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2049 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2050 "skbaddr %llx\n", skb, skb->data, skb->len,
2051 (unsigned long long)bf->skbaddr);
2052 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2053 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2059 flags = AR5K_TXDESC_NOACK;
2060 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2061 ds->ds_link = bf->daddr; /* self-linked */
2062 flags |= AR5K_TXDESC_VEOL;
2064 * Let hardware handle antenna switching if txantenna is not set
2069 * Switch antenna every 4 beacons if txantenna is not set
2070 * XXX assumes two antennas
2073 antenna = sc->bsent & 4 ? 2 : 1;
2076 /* FIXME: If we are in g mode and rate is a CCK rate
2077 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2078 * from tx power (value is in dB units already) */
2079 ds->ds_data = bf->skbaddr;
2080 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2081 ieee80211_get_hdrlen_from_skb(skb),
2082 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2083 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2084 1, AR5K_TXKEYIX_INVALID,
2085 antenna, flags, 0, 0);
2091 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2096 * Transmit a beacon frame at SWBA. Dynamic updates to the
2097 * frame contents are done as needed and the slot time is
2098 * also adjusted based on current state.
2100 * This is called from software irq context (beacontq or restq
2101 * tasklets) or user context from ath5k_beacon_config.
2104 ath5k_beacon_send(struct ath5k_softc *sc)
2106 struct ath5k_buf *bf = sc->bbuf;
2107 struct ath5k_hw *ah = sc->ah;
2109 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2111 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2112 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2113 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2117 * Check if the previous beacon has gone out. If
2118 * not don't don't try to post another, skip this
2119 * period and wait for the next. Missed beacons
2120 * indicate a problem and should not occur. If we
2121 * miss too many consecutive beacons reset the device.
2123 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2125 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2126 "missed %u consecutive beacons\n", sc->bmisscount);
2127 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2128 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2129 "stuck beacon time (%u missed)\n",
2131 tasklet_schedule(&sc->restq);
2135 if (unlikely(sc->bmisscount != 0)) {
2136 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2137 "resume beacon xmit after %u misses\n",
2143 * Stop any current dma and put the new frame on the queue.
2144 * This should never fail since we check above that no frames
2145 * are still pending on the queue.
2147 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2148 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2149 /* NB: hw still stops DMA, so proceed */
2152 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2153 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2154 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2155 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2162 * ath5k_beacon_update_timers - update beacon timers
2164 * @sc: struct ath5k_softc pointer we are operating on
2165 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2166 * beacon timer update based on the current HW TSF.
2168 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2169 * of a received beacon or the current local hardware TSF and write it to the
2170 * beacon timer registers.
2172 * This is called in a variety of situations, e.g. when a beacon is received,
2173 * when a TSF update has been detected, but also when an new IBSS is created or
2174 * when we otherwise know we have to update the timers, but we keep it in this
2175 * function to have it all together in one place.
2178 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2180 struct ath5k_hw *ah = sc->ah;
2181 u32 nexttbtt, intval, hw_tu, bc_tu;
2184 intval = sc->bintval & AR5K_BEACON_PERIOD;
2185 if (WARN_ON(!intval))
2188 /* beacon TSF converted to TU */
2189 bc_tu = TSF_TO_TU(bc_tsf);
2191 /* current TSF converted to TU */
2192 hw_tsf = ath5k_hw_get_tsf64(ah);
2193 hw_tu = TSF_TO_TU(hw_tsf);
2196 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2199 * no beacons received, called internally.
2200 * just need to refresh timers based on HW TSF.
2202 nexttbtt = roundup(hw_tu + FUDGE, intval);
2203 } else if (bc_tsf == 0) {
2205 * no beacon received, probably called by ath5k_reset_tsf().
2206 * reset TSF to start with 0.
2209 intval |= AR5K_BEACON_RESET_TSF;
2210 } else if (bc_tsf > hw_tsf) {
2212 * beacon received, SW merge happend but HW TSF not yet updated.
2213 * not possible to reconfigure timers yet, but next time we
2214 * receive a beacon with the same BSSID, the hardware will
2215 * automatically update the TSF and then we need to reconfigure
2218 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2219 "need to wait for HW TSF sync\n");
2223 * most important case for beacon synchronization between STA.
2225 * beacon received and HW TSF has been already updated by HW.
2226 * update next TBTT based on the TSF of the beacon, but make
2227 * sure it is ahead of our local TSF timer.
2229 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2233 sc->nexttbtt = nexttbtt;
2235 intval |= AR5K_BEACON_ENA;
2236 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2239 * debugging output last in order to preserve the time critical aspect
2243 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2244 "reconfigured timers based on HW TSF\n");
2245 else if (bc_tsf == 0)
2246 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2247 "reset HW TSF and timers\n");
2249 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2250 "updated timers based on beacon TSF\n");
2252 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2253 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2254 (unsigned long long) bc_tsf,
2255 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2256 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2257 intval & AR5K_BEACON_PERIOD,
2258 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2259 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2264 * ath5k_beacon_config - Configure the beacon queues and interrupts
2266 * @sc: struct ath5k_softc pointer we are operating on
2268 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2269 * interrupts to detect TSF updates only.
2272 ath5k_beacon_config(struct ath5k_softc *sc)
2274 struct ath5k_hw *ah = sc->ah;
2275 unsigned long flags;
2277 ath5k_hw_set_imr(ah, 0);
2279 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2281 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2282 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2283 sc->opmode == NL80211_IFTYPE_AP) {
2285 * In IBSS mode we use a self-linked tx descriptor and let the
2286 * hardware send the beacons automatically. We have to load it
2288 * We use the SWBA interrupt only to keep track of the beacon
2289 * timers in order to detect automatic TSF updates.
2291 ath5k_beaconq_config(sc);
2293 sc->imask |= AR5K_INT_SWBA;
2295 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2296 if (ath5k_hw_hasveol(ah)) {
2297 spin_lock_irqsave(&sc->block, flags);
2298 ath5k_beacon_send(sc);
2299 spin_unlock_irqrestore(&sc->block, flags);
2302 ath5k_beacon_update_timers(sc, -1);
2305 ath5k_hw_set_imr(ah, sc->imask);
2309 /********************\
2310 * Interrupt handling *
2311 \********************/
2314 ath5k_init(struct ath5k_softc *sc)
2316 struct ath5k_hw *ah = sc->ah;
2319 mutex_lock(&sc->lock);
2321 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2324 * Stop anything previously setup. This is safe
2325 * no matter this is the first time through or not.
2327 ath5k_stop_locked(sc);
2330 * The basic interface to setting the hardware in a good
2331 * state is ``reset''. On return the hardware is known to
2332 * be powered up and with interrupts disabled. This must
2333 * be followed by initialization of the appropriate bits
2334 * and then setup of the interrupt mask.
2336 sc->curchan = sc->hw->conf.channel;
2337 sc->curband = &sc->sbands[sc->curchan->band];
2338 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2339 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2340 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2341 ret = ath5k_reset(sc, false, false);
2346 * Reset the key cache since some parts do not reset the
2347 * contents on initial power up or resume from suspend.
2349 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2350 ath5k_hw_reset_key(ah, i);
2352 /* Set ack to be sent at low bit-rates */
2353 ath5k_hw_set_ack_bitrate_high(ah, false);
2355 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2356 msecs_to_jiffies(ath5k_calinterval * 1000)));
2361 mutex_unlock(&sc->lock);
2366 ath5k_stop_locked(struct ath5k_softc *sc)
2368 struct ath5k_hw *ah = sc->ah;
2370 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2371 test_bit(ATH_STAT_INVALID, sc->status));
2374 * Shutdown the hardware and driver:
2375 * stop output from above
2376 * disable interrupts
2378 * turn off the radio
2379 * clear transmit machinery
2380 * clear receive machinery
2381 * drain and release tx queues
2382 * reclaim beacon resources
2383 * power down hardware
2385 * Note that some of this work is not possible if the
2386 * hardware is gone (invalid).
2388 ieee80211_stop_queues(sc->hw);
2390 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2392 ath5k_hw_set_imr(ah, 0);
2393 synchronize_irq(sc->pdev->irq);
2395 ath5k_txq_cleanup(sc);
2396 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2398 ath5k_hw_phy_disable(ah);
2406 * Stop the device, grabbing the top-level lock to protect
2407 * against concurrent entry through ath5k_init (which can happen
2408 * if another thread does a system call and the thread doing the
2409 * stop is preempted).
2412 ath5k_stop_hw(struct ath5k_softc *sc)
2416 mutex_lock(&sc->lock);
2417 ret = ath5k_stop_locked(sc);
2418 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2420 * Set the chip in full sleep mode. Note that we are
2421 * careful to do this only when bringing the interface
2422 * completely to a stop. When the chip is in this state
2423 * it must be carefully woken up or references to
2424 * registers in the PCI clock domain may freeze the bus
2425 * (and system). This varies by chip and is mostly an
2426 * issue with newer parts that go to sleep more quickly.
2428 if (sc->ah->ah_mac_srev >= 0x78) {
2431 * don't put newer MAC revisions > 7.8 to sleep because
2432 * of the above mentioned problems
2434 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2435 "not putting device to sleep\n");
2437 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2438 "putting device to full sleep\n");
2439 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2442 ath5k_txbuf_free(sc, sc->bbuf);
2445 mutex_unlock(&sc->lock);
2447 del_timer_sync(&sc->calib_tim);
2448 tasklet_kill(&sc->rxtq);
2449 tasklet_kill(&sc->txtq);
2450 tasklet_kill(&sc->restq);
2451 tasklet_kill(&sc->beacontq);
2457 ath5k_intr(int irq, void *dev_id)
2459 struct ath5k_softc *sc = dev_id;
2460 struct ath5k_hw *ah = sc->ah;
2461 enum ath5k_int status;
2462 unsigned int counter = 1000;
2464 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2465 !ath5k_hw_is_intr_pending(ah)))
2469 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2470 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2472 if (unlikely(status & AR5K_INT_FATAL)) {
2474 * Fatal errors are unrecoverable.
2475 * Typically these are caused by DMA errors.
2477 tasklet_schedule(&sc->restq);
2478 } else if (unlikely(status & AR5K_INT_RXORN)) {
2479 tasklet_schedule(&sc->restq);
2481 if (status & AR5K_INT_SWBA) {
2482 tasklet_hi_schedule(&sc->beacontq);
2484 if (status & AR5K_INT_RXEOL) {
2486 * NB: the hardware should re-read the link when
2487 * RXE bit is written, but it doesn't work at
2488 * least on older hardware revs.
2492 if (status & AR5K_INT_TXURN) {
2493 /* bump tx trigger level */
2494 ath5k_hw_update_tx_triglevel(ah, true);
2496 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2497 tasklet_schedule(&sc->rxtq);
2498 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2499 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2500 tasklet_schedule(&sc->txtq);
2501 if (status & AR5K_INT_BMISS) {
2504 if (status & AR5K_INT_MIB) {
2506 * These stats are also used for ANI i think
2507 * so how about updating them more often ?
2509 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2512 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2514 if (unlikely(!counter))
2515 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2521 ath5k_tasklet_reset(unsigned long data)
2523 struct ath5k_softc *sc = (void *)data;
2525 ath5k_reset_wake(sc);
2529 * Periodically recalibrate the PHY to account
2530 * for temperature/environment changes.
2533 ath5k_calibrate(unsigned long data)
2535 struct ath5k_softc *sc = (void *)data;
2536 struct ath5k_hw *ah = sc->ah;
2538 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2539 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2540 sc->curchan->hw_value);
2542 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2544 * Rfgain is out of bounds, reset the chip
2545 * to load new gain values.
2547 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2548 ath5k_reset_wake(sc);
2550 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2551 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2552 ieee80211_frequency_to_channel(
2553 sc->curchan->center_freq));
2555 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2556 msecs_to_jiffies(ath5k_calinterval * 1000)));
2560 /********************\
2561 * Mac80211 functions *
2562 \********************/
2565 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2567 struct ath5k_softc *sc = hw->priv;
2568 struct ath5k_buf *bf;
2569 unsigned long flags;
2573 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2575 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2576 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2579 * the hardware expects the header padded to 4 byte boundaries
2580 * if this is not the case we add the padding after the header
2582 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2583 padsize = ath5k_pad_size(hdrlen);
2586 if (skb_headroom(skb) < padsize) {
2587 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2588 " headroom to pad %d\n", hdrlen, padsize);
2591 skb_push(skb, padsize);
2592 memmove(skb->data, skb->data+padsize, hdrlen);
2595 spin_lock_irqsave(&sc->txbuflock, flags);
2596 if (list_empty(&sc->txbuf)) {
2597 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2598 spin_unlock_irqrestore(&sc->txbuflock, flags);
2599 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2602 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2603 list_del(&bf->list);
2605 if (list_empty(&sc->txbuf))
2606 ieee80211_stop_queues(hw);
2607 spin_unlock_irqrestore(&sc->txbuflock, flags);
2611 if (ath5k_txbuf_setup(sc, bf)) {
2613 spin_lock_irqsave(&sc->txbuflock, flags);
2614 list_add_tail(&bf->list, &sc->txbuf);
2616 spin_unlock_irqrestore(&sc->txbuflock, flags);
2619 return NETDEV_TX_OK;
2622 dev_kfree_skb_any(skb);
2623 return NETDEV_TX_OK;
2627 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2629 struct ath5k_hw *ah = sc->ah;
2632 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2635 ath5k_hw_set_imr(ah, 0);
2636 ath5k_txq_cleanup(sc);
2639 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2641 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2645 ret = ath5k_rx_start(sc);
2647 ATH5K_ERR(sc, "can't start recv logic\n");
2652 * Change channels and update the h/w rate map if we're switching;
2653 * e.g. 11a to 11b/g.
2655 * We may be doing a reset in response to an ioctl that changes the
2656 * channel so update any state that might change as a result.
2660 /* ath5k_chan_change(sc, c); */
2662 ath5k_beacon_config(sc);
2663 /* intrs are enabled by ath5k_beacon_config */
2671 ath5k_reset_wake(struct ath5k_softc *sc)
2675 ret = ath5k_reset(sc, true, true);
2677 ieee80211_wake_queues(sc->hw);
2682 static int ath5k_start(struct ieee80211_hw *hw)
2684 return ath5k_init(hw->priv);
2687 static void ath5k_stop(struct ieee80211_hw *hw)
2689 ath5k_stop_hw(hw->priv);
2692 static int ath5k_add_interface(struct ieee80211_hw *hw,
2693 struct ieee80211_if_init_conf *conf)
2695 struct ath5k_softc *sc = hw->priv;
2698 mutex_lock(&sc->lock);
2704 sc->vif = conf->vif;
2706 switch (conf->type) {
2707 case NL80211_IFTYPE_AP:
2708 case NL80211_IFTYPE_STATION:
2709 case NL80211_IFTYPE_ADHOC:
2710 case NL80211_IFTYPE_MESH_POINT:
2711 case NL80211_IFTYPE_MONITOR:
2712 sc->opmode = conf->type;
2719 /* Set to a reasonable value. Note that this will
2720 * be set to mac80211's value at ath5k_config(). */
2722 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2726 mutex_unlock(&sc->lock);
2731 ath5k_remove_interface(struct ieee80211_hw *hw,
2732 struct ieee80211_if_init_conf *conf)
2734 struct ath5k_softc *sc = hw->priv;
2735 u8 mac[ETH_ALEN] = {};
2737 mutex_lock(&sc->lock);
2738 if (sc->vif != conf->vif)
2741 ath5k_hw_set_lladdr(sc->ah, mac);
2744 mutex_unlock(&sc->lock);
2748 * TODO: Phy disable/diversity etc
2751 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2753 struct ath5k_softc *sc = hw->priv;
2754 struct ieee80211_conf *conf = &hw->conf;
2757 mutex_lock(&sc->lock);
2759 sc->bintval = conf->beacon_int;
2760 sc->power_level = conf->power_level;
2762 ret = ath5k_chan_set(sc, conf->channel);
2764 mutex_unlock(&sc->lock);
2769 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2770 struct ieee80211_if_conf *conf)
2772 struct ath5k_softc *sc = hw->priv;
2773 struct ath5k_hw *ah = sc->ah;
2776 mutex_lock(&sc->lock);
2777 if (sc->vif != vif) {
2781 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2782 /* Cache for later use during resets */
2783 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2784 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2785 * a clean way of letting us retrieve this yet. */
2786 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2789 if (conf->changed & IEEE80211_IFCC_BEACON &&
2790 (vif->type == NL80211_IFTYPE_ADHOC ||
2791 vif->type == NL80211_IFTYPE_MESH_POINT ||
2792 vif->type == NL80211_IFTYPE_AP)) {
2793 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2798 ath5k_beacon_update(sc, beacon);
2802 mutex_unlock(&sc->lock);
2806 #define SUPPORTED_FIF_FLAGS \
2807 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2808 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2809 FIF_BCN_PRBRESP_PROMISC
2811 * o always accept unicast, broadcast, and multicast traffic
2812 * o multicast traffic for all BSSIDs will be enabled if mac80211
2814 * o maintain current state of phy ofdm or phy cck error reception.
2815 * If the hardware detects any of these type of errors then
2816 * ath5k_hw_get_rx_filter() will pass to us the respective
2817 * hardware filters to be able to receive these type of frames.
2818 * o probe request frames are accepted only when operating in
2819 * hostap, adhoc, or monitor modes
2820 * o enable promiscuous mode according to the interface state
2822 * - when operating in adhoc mode so the 802.11 layer creates
2823 * node table entries for peers,
2824 * - when operating in station mode for collecting rssi data when
2825 * the station is otherwise quiet, or
2828 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2829 unsigned int changed_flags,
2830 unsigned int *new_flags,
2831 int mc_count, struct dev_mc_list *mclist)
2833 struct ath5k_softc *sc = hw->priv;
2834 struct ath5k_hw *ah = sc->ah;
2835 u32 mfilt[2], val, rfilt;
2842 /* Only deal with supported flags */
2843 changed_flags &= SUPPORTED_FIF_FLAGS;
2844 *new_flags &= SUPPORTED_FIF_FLAGS;
2846 /* If HW detects any phy or radar errors, leave those filters on.
2847 * Also, always enable Unicast, Broadcasts and Multicast
2848 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2849 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2850 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2851 AR5K_RX_FILTER_MCAST);
2853 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2854 if (*new_flags & FIF_PROMISC_IN_BSS) {
2855 rfilt |= AR5K_RX_FILTER_PROM;
2856 __set_bit(ATH_STAT_PROMISC, sc->status);
2858 __clear_bit(ATH_STAT_PROMISC, sc->status);
2862 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2863 if (*new_flags & FIF_ALLMULTI) {
2867 for (i = 0; i < mc_count; i++) {
2870 /* calculate XOR of eight 6-bit values */
2871 val = get_unaligned_le32(mclist->dmi_addr + 0);
2872 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2873 val = get_unaligned_le32(mclist->dmi_addr + 3);
2874 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2876 mfilt[pos / 32] |= (1 << (pos % 32));
2877 /* XXX: we might be able to just do this instead,
2878 * but not sure, needs testing, if we do use this we'd
2879 * neet to inform below to not reset the mcast */
2880 /* ath5k_hw_set_mcast_filterindex(ah,
2881 * mclist->dmi_addr[5]); */
2882 mclist = mclist->next;
2886 /* This is the best we can do */
2887 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2888 rfilt |= AR5K_RX_FILTER_PHYERR;
2890 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2891 * and probes for any BSSID, this needs testing */
2892 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2893 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2895 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2896 * set we should only pass on control frames for this
2897 * station. This needs testing. I believe right now this
2898 * enables *all* control frames, which is OK.. but
2899 * but we should see if we can improve on granularity */
2900 if (*new_flags & FIF_CONTROL)
2901 rfilt |= AR5K_RX_FILTER_CONTROL;
2903 /* Additional settings per mode -- this is per ath5k */
2905 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2907 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2908 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2909 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2910 if (sc->opmode != NL80211_IFTYPE_STATION)
2911 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2912 if (sc->opmode != NL80211_IFTYPE_AP &&
2913 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2914 test_bit(ATH_STAT_PROMISC, sc->status))
2915 rfilt |= AR5K_RX_FILTER_PROM;
2916 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2917 sc->opmode == NL80211_IFTYPE_ADHOC ||
2918 sc->opmode == NL80211_IFTYPE_AP)
2919 rfilt |= AR5K_RX_FILTER_BEACON;
2920 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2921 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2922 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2925 ath5k_hw_set_rx_filter(ah, rfilt);
2927 /* Set multicast bits */
2928 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2929 /* Set the cached hw filter flags, this will alter actually
2931 sc->filter_flags = rfilt;
2935 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2936 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2937 struct ieee80211_key_conf *key)
2939 struct ath5k_softc *sc = hw->priv;
2942 if (modparam_nohwcrypt)
2956 mutex_lock(&sc->lock);
2960 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2961 sta ? sta->addr : NULL);
2963 ATH5K_ERR(sc, "can't set the key\n");
2966 __set_bit(key->keyidx, sc->keymap);
2967 key->hw_key_idx = key->keyidx;
2968 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2969 IEEE80211_KEY_FLAG_GENERATE_MMIC);
2972 ath5k_hw_reset_key(sc->ah, key->keyidx);
2973 __clear_bit(key->keyidx, sc->keymap);
2982 mutex_unlock(&sc->lock);
2987 ath5k_get_stats(struct ieee80211_hw *hw,
2988 struct ieee80211_low_level_stats *stats)
2990 struct ath5k_softc *sc = hw->priv;
2991 struct ath5k_hw *ah = sc->ah;
2994 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2996 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3002 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3003 struct ieee80211_tx_queue_stats *stats)
3005 struct ath5k_softc *sc = hw->priv;
3007 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3013 ath5k_get_tsf(struct ieee80211_hw *hw)
3015 struct ath5k_softc *sc = hw->priv;
3017 return ath5k_hw_get_tsf64(sc->ah);
3021 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3023 struct ath5k_softc *sc = hw->priv;
3025 ath5k_hw_set_tsf64(sc->ah, tsf);
3029 ath5k_reset_tsf(struct ieee80211_hw *hw)
3031 struct ath5k_softc *sc = hw->priv;
3034 * in IBSS mode we need to update the beacon timers too.
3035 * this will also reset the TSF if we call it with 0
3037 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3038 ath5k_beacon_update_timers(sc, 0);
3040 ath5k_hw_reset_tsf(sc->ah);
3044 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3046 unsigned long flags;
3049 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3051 spin_lock_irqsave(&sc->block, flags);
3052 ath5k_txbuf_free(sc, sc->bbuf);
3053 sc->bbuf->skb = skb;
3054 ret = ath5k_beacon_setup(sc, sc->bbuf);
3056 sc->bbuf->skb = NULL;
3057 spin_unlock_irqrestore(&sc->block, flags);
3059 ath5k_beacon_config(sc);
3066 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3068 struct ath5k_softc *sc = hw->priv;
3069 struct ath5k_hw *ah = sc->ah;
3071 rfilt = ath5k_hw_get_rx_filter(ah);
3073 rfilt |= AR5K_RX_FILTER_BEACON;
3075 rfilt &= ~AR5K_RX_FILTER_BEACON;
3076 ath5k_hw_set_rx_filter(ah, rfilt);
3077 sc->filter_flags = rfilt;
3080 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3081 struct ieee80211_vif *vif,
3082 struct ieee80211_bss_conf *bss_conf,
3085 struct ath5k_softc *sc = hw->priv;
3086 if (changes & BSS_CHANGED_ASSOC) {
3087 mutex_lock(&sc->lock);
3088 sc->assoc = bss_conf->assoc;
3089 if (sc->opmode == NL80211_IFTYPE_STATION)
3090 set_beacon_filter(hw, sc->assoc);
3091 mutex_unlock(&sc->lock);
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