4 * (C) Copyright IBM Corp. 2005
6 * Author: Mark Nutter <mnutter@us.ibm.com>
8 * Host-side part of SPU context switch sequence outlined in
9 * Synergistic Processor Element, Book IV.
11 * A fully premptive switch of an SPE is very expensive in terms
12 * of time and system resources. SPE Book IV indicates that SPE
13 * allocation should follow a "serially reusable device" model,
14 * in which the SPE is assigned a task until it completes. When
15 * this is not possible, this sequence may be used to premptively
16 * save, and then later (optionally) restore the context of a
17 * program executing on an SPE.
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/module.h>
36 #include <linux/errno.h>
37 #include <linux/sched.h>
38 #include <linux/kernel.h>
40 #include <linux/vmalloc.h>
41 #include <linux/smp.h>
42 #include <linux/stddef.h>
43 #include <linux/unistd.h>
47 #include <asm/spu_priv1.h>
48 #include <asm/spu_csa.h>
49 #include <asm/mmu_context.h>
51 #include "spu_save_dump.h"
52 #include "spu_restore_dump.h"
55 #define POLL_WHILE_TRUE(_c) { \
60 #define RELAX_SPIN_COUNT 1000
61 #define POLL_WHILE_TRUE(_c) { \
64 for (_i=0; _i<RELAX_SPIN_COUNT && (_c); _i++) { \
67 if (unlikely(_c)) yield(); \
73 #define POLL_WHILE_FALSE(_c) POLL_WHILE_TRUE(!(_c))
75 static inline void acquire_spu_lock(struct spu *spu)
79 * Acquire SPU-specific mutual exclusion lock.
84 static inline void release_spu_lock(struct spu *spu)
87 * Release SPU-specific mutual exclusion lock.
92 static inline int check_spu_isolate(struct spu_state *csa, struct spu *spu)
94 struct spu_problem __iomem *prob = spu->problem;
99 * If SPU_Status[E,L,IS] any field is '1', this
100 * SPU is in isolate state and cannot be context
101 * saved at this time.
103 isolate_state = SPU_STATUS_ISOLATED_STATE |
104 SPU_STATUS_ISOLATED_LOAD_STATUS | SPU_STATUS_ISOLATED_EXIT_STATUS;
105 return (in_be32(&prob->spu_status_R) & isolate_state) ? 1 : 0;
108 static inline void disable_interrupts(struct spu_state *csa, struct spu *spu)
112 * Save INT_Mask_class0 in CSA.
113 * Write INT_MASK_class0 with value of 0.
114 * Save INT_Mask_class1 in CSA.
115 * Write INT_MASK_class1 with value of 0.
116 * Save INT_Mask_class2 in CSA.
117 * Write INT_MASK_class2 with value of 0.
119 spin_lock_irq(&spu->register_lock);
121 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
122 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
123 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
125 spu_int_mask_set(spu, 0, 0ul);
126 spu_int_mask_set(spu, 1, 0ul);
127 spu_int_mask_set(spu, 2, 0ul);
129 spin_unlock_irq(&spu->register_lock);
132 static inline void set_watchdog_timer(struct spu_state *csa, struct spu *spu)
136 * Set a software watchdog timer, which specifies the
137 * maximum allowable time for a context save sequence.
139 * For present, this implementation will not set a global
140 * watchdog timer, as virtualization & variable system load
141 * may cause unpredictable execution times.
145 static inline void inhibit_user_access(struct spu_state *csa, struct spu *spu)
149 * Inhibit user-space access (if provided) to this
150 * SPU by unmapping the virtual pages assigned to
151 * the SPU memory-mapped I/O (MMIO) for problem
156 static inline void set_switch_pending(struct spu_state *csa, struct spu *spu)
160 * Set a software context switch pending flag.
162 set_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
166 static inline void save_mfc_cntl(struct spu_state *csa, struct spu *spu)
168 struct spu_priv2 __iomem *priv2 = spu->priv2;
171 * Suspend DMA and save MFC_CNTL.
173 switch (in_be64(&priv2->mfc_control_RW) &
174 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) {
175 case MFC_CNTL_SUSPEND_IN_PROGRESS:
176 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
177 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
178 MFC_CNTL_SUSPEND_COMPLETE);
180 case MFC_CNTL_SUSPEND_COMPLETE:
182 csa->priv2.mfc_control_RW =
183 in_be64(&priv2->mfc_control_RW) |
184 MFC_CNTL_SUSPEND_DMA_QUEUE;
187 case MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION:
188 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
189 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
190 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
191 MFC_CNTL_SUSPEND_COMPLETE);
193 csa->priv2.mfc_control_RW =
194 in_be64(&priv2->mfc_control_RW) &
195 ~MFC_CNTL_SUSPEND_DMA_QUEUE;
201 static inline void save_spu_runcntl(struct spu_state *csa, struct spu *spu)
203 struct spu_problem __iomem *prob = spu->problem;
206 * Save SPU_Runcntl in the CSA. This value contains
207 * the "Application Desired State".
209 csa->prob.spu_runcntl_RW = in_be32(&prob->spu_runcntl_RW);
212 static inline void save_mfc_sr1(struct spu_state *csa, struct spu *spu)
215 * Save MFC_SR1 in the CSA.
217 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
220 static inline void save_spu_status(struct spu_state *csa, struct spu *spu)
222 struct spu_problem __iomem *prob = spu->problem;
225 * Read SPU_Status[R], and save to CSA.
227 if ((in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) == 0) {
228 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
232 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
234 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
237 SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
238 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
239 if ((in_be32(&prob->spu_status_R) & stopped) == 0)
240 csa->prob.spu_status_R = SPU_STATUS_RUNNING;
242 csa->prob.spu_status_R = in_be32(&prob->spu_status_R);
246 static inline void save_mfc_decr(struct spu_state *csa, struct spu *spu)
248 struct spu_priv2 __iomem *priv2 = spu->priv2;
251 * Read MFC_CNTL[Ds]. Update saved copy of
254 if (in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DECREMENTER_RUNNING) {
255 csa->priv2.mfc_control_RW |= MFC_CNTL_DECREMENTER_RUNNING;
256 csa->suspend_time = get_cycles();
257 out_be64(&priv2->spu_chnlcntptr_RW, 7ULL);
259 csa->spu_chnldata_RW[7] = in_be64(&priv2->spu_chnldata_RW);
262 csa->priv2.mfc_control_RW &= ~MFC_CNTL_DECREMENTER_RUNNING;
266 static inline void halt_mfc_decr(struct spu_state *csa, struct spu *spu)
268 struct spu_priv2 __iomem *priv2 = spu->priv2;
271 * Write MFC_CNTL[Dh] set to a '1' to halt
274 out_be64(&priv2->mfc_control_RW,
275 MFC_CNTL_DECREMENTER_HALTED | MFC_CNTL_SUSPEND_MASK);
279 static inline void save_timebase(struct spu_state *csa, struct spu *spu)
282 * Read PPE Timebase High and Timebase low registers
283 * and save in CSA. TBD.
285 csa->suspend_time = get_cycles();
288 static inline void remove_other_spu_access(struct spu_state *csa,
292 * Remove other SPU access to this SPU by unmapping
293 * this SPU's pages from their address space. TBD.
297 static inline void do_mfc_mssync(struct spu_state *csa, struct spu *spu)
299 struct spu_problem __iomem *prob = spu->problem;
303 * Write SPU_MSSync register. Poll SPU_MSSync[P]
306 out_be64(&prob->spc_mssync_RW, 1UL);
307 POLL_WHILE_TRUE(in_be64(&prob->spc_mssync_RW) & MS_SYNC_PENDING);
310 static inline void issue_mfc_tlbie(struct spu_state *csa, struct spu *spu)
315 * Write TLB_Invalidate_Entry[IS,VPN,L,Lp]=0 register.
316 * Then issue a PPE sync instruction.
318 spu_tlb_invalidate(spu);
322 static inline void handle_pending_interrupts(struct spu_state *csa,
326 * Handle any pending interrupts from this SPU
327 * here. This is OS or hypervisor specific. One
328 * option is to re-enable interrupts to handle any
329 * pending interrupts, with the interrupt handlers
330 * recognizing the software Context Switch Pending
331 * flag, to ensure the SPU execution or MFC command
332 * queue is not restarted. TBD.
336 static inline void save_mfc_queues(struct spu_state *csa, struct spu *spu)
338 struct spu_priv2 __iomem *priv2 = spu->priv2;
342 * If MFC_Cntl[Se]=0 then save
343 * MFC command queues.
345 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
346 for (i = 0; i < 8; i++) {
347 csa->priv2.puq[i].mfc_cq_data0_RW =
348 in_be64(&priv2->puq[i].mfc_cq_data0_RW);
349 csa->priv2.puq[i].mfc_cq_data1_RW =
350 in_be64(&priv2->puq[i].mfc_cq_data1_RW);
351 csa->priv2.puq[i].mfc_cq_data2_RW =
352 in_be64(&priv2->puq[i].mfc_cq_data2_RW);
353 csa->priv2.puq[i].mfc_cq_data3_RW =
354 in_be64(&priv2->puq[i].mfc_cq_data3_RW);
356 for (i = 0; i < 16; i++) {
357 csa->priv2.spuq[i].mfc_cq_data0_RW =
358 in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
359 csa->priv2.spuq[i].mfc_cq_data1_RW =
360 in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
361 csa->priv2.spuq[i].mfc_cq_data2_RW =
362 in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
363 csa->priv2.spuq[i].mfc_cq_data3_RW =
364 in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
369 static inline void save_ppu_querymask(struct spu_state *csa, struct spu *spu)
371 struct spu_problem __iomem *prob = spu->problem;
374 * Save the PPU_QueryMask register
377 csa->prob.dma_querymask_RW = in_be32(&prob->dma_querymask_RW);
380 static inline void save_ppu_querytype(struct spu_state *csa, struct spu *spu)
382 struct spu_problem __iomem *prob = spu->problem;
385 * Save the PPU_QueryType register
388 csa->prob.dma_querytype_RW = in_be32(&prob->dma_querytype_RW);
391 static inline void save_ppu_tagstatus(struct spu_state *csa, struct spu *spu)
393 struct spu_problem __iomem *prob = spu->problem;
395 /* Save the Prxy_TagStatus register in the CSA.
397 * It is unnecessary to restore dma_tagstatus_R, however,
398 * dma_tagstatus_R in the CSA is accessed via backing_ops, so
401 csa->prob.dma_tagstatus_R = in_be32(&prob->dma_tagstatus_R);
404 static inline void save_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
406 struct spu_priv2 __iomem *priv2 = spu->priv2;
409 * Save the MFC_CSR_TSQ register
412 csa->priv2.spu_tag_status_query_RW =
413 in_be64(&priv2->spu_tag_status_query_RW);
416 static inline void save_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
418 struct spu_priv2 __iomem *priv2 = spu->priv2;
421 * Save the MFC_CSR_CMD1 and MFC_CSR_CMD2
422 * registers in the CSA.
424 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
425 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
428 static inline void save_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
430 struct spu_priv2 __iomem *priv2 = spu->priv2;
433 * Save the MFC_CSR_ATO register in
436 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
439 static inline void save_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
442 * Save the MFC_TCLASS_ID register in
445 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
448 static inline void set_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
452 * Write the MFC_TCLASS_ID register with
453 * the value 0x10000000.
455 spu_mfc_tclass_id_set(spu, 0x10000000);
459 static inline void purge_mfc_queue(struct spu_state *csa, struct spu *spu)
461 struct spu_priv2 __iomem *priv2 = spu->priv2;
465 * Write MFC_CNTL[Pc]=1 (purge queue).
467 out_be64(&priv2->mfc_control_RW, MFC_CNTL_PURGE_DMA_REQUEST);
471 static inline void wait_purge_complete(struct spu_state *csa, struct spu *spu)
473 struct spu_priv2 __iomem *priv2 = spu->priv2;
476 * Poll MFC_CNTL[Ps] until value '11' is read
479 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
480 MFC_CNTL_PURGE_DMA_STATUS_MASK) ==
481 MFC_CNTL_PURGE_DMA_COMPLETE);
484 static inline void setup_mfc_sr1(struct spu_state *csa, struct spu *spu)
488 * Write MFC_SR1 with MFC_SR1[D=0,S=1] and
489 * MFC_SR1[TL,R,Pr,T] set correctly for the
490 * OS specific environment.
492 * Implementation note: The SPU-side code
493 * for save/restore is privileged, so the
494 * MFC_SR1[Pr] bit is not set.
497 spu_mfc_sr1_set(spu, (MFC_STATE1_MASTER_RUN_CONTROL_MASK |
498 MFC_STATE1_RELOCATE_MASK |
499 MFC_STATE1_BUS_TLBIE_MASK));
502 static inline void save_spu_npc(struct spu_state *csa, struct spu *spu)
504 struct spu_problem __iomem *prob = spu->problem;
507 * Save SPU_NPC in the CSA.
509 csa->prob.spu_npc_RW = in_be32(&prob->spu_npc_RW);
512 static inline void save_spu_privcntl(struct spu_state *csa, struct spu *spu)
514 struct spu_priv2 __iomem *priv2 = spu->priv2;
517 * Save SPU_PrivCntl in the CSA.
519 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
522 static inline void reset_spu_privcntl(struct spu_state *csa, struct spu *spu)
524 struct spu_priv2 __iomem *priv2 = spu->priv2;
528 * Write SPU_PrivCntl[S,Le,A] fields reset to 0.
530 out_be64(&priv2->spu_privcntl_RW, 0UL);
534 static inline void save_spu_lslr(struct spu_state *csa, struct spu *spu)
536 struct spu_priv2 __iomem *priv2 = spu->priv2;
539 * Save SPU_LSLR in the CSA.
541 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
544 static inline void reset_spu_lslr(struct spu_state *csa, struct spu *spu)
546 struct spu_priv2 __iomem *priv2 = spu->priv2;
552 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
556 static inline void save_spu_cfg(struct spu_state *csa, struct spu *spu)
558 struct spu_priv2 __iomem *priv2 = spu->priv2;
561 * Save SPU_Cfg in the CSA.
563 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
566 static inline void save_pm_trace(struct spu_state *csa, struct spu *spu)
569 * Save PM_Trace_Tag_Wait_Mask in the CSA.
570 * Not performed by this implementation.
574 static inline void save_mfc_rag(struct spu_state *csa, struct spu *spu)
577 * Save RA_GROUP_ID register and the
578 * RA_ENABLE reigster in the CSA.
580 csa->priv1.resource_allocation_groupID_RW =
581 spu_resource_allocation_groupID_get(spu);
582 csa->priv1.resource_allocation_enable_RW =
583 spu_resource_allocation_enable_get(spu);
586 static inline void save_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
588 struct spu_problem __iomem *prob = spu->problem;
591 * Save MB_Stat register in the CSA.
593 csa->prob.mb_stat_R = in_be32(&prob->mb_stat_R);
596 static inline void save_ppu_mb(struct spu_state *csa, struct spu *spu)
598 struct spu_problem __iomem *prob = spu->problem;
601 * Save the PPU_MB register in the CSA.
603 csa->prob.pu_mb_R = in_be32(&prob->pu_mb_R);
606 static inline void save_ppuint_mb(struct spu_state *csa, struct spu *spu)
608 struct spu_priv2 __iomem *priv2 = spu->priv2;
611 * Save the PPUINT_MB register in the CSA.
613 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
616 static inline void save_ch_part1(struct spu_state *csa, struct spu *spu)
618 struct spu_priv2 __iomem *priv2 = spu->priv2;
619 u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
625 /* Save CH 1, without channel count */
626 out_be64(&priv2->spu_chnlcntptr_RW, 1);
627 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
629 /* Save the following CH: [0,3,4,24,25,27] */
630 for (i = 0; i < 7; i++) {
632 out_be64(&priv2->spu_chnlcntptr_RW, idx);
634 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
635 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
636 out_be64(&priv2->spu_chnldata_RW, 0UL);
637 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
642 static inline void save_spu_mb(struct spu_state *csa, struct spu *spu)
644 struct spu_priv2 __iomem *priv2 = spu->priv2;
648 * Save SPU Read Mailbox Channel.
650 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
652 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
653 for (i = 0; i < 4; i++) {
654 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
656 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
660 static inline void save_mfc_cmd(struct spu_state *csa, struct spu *spu)
662 struct spu_priv2 __iomem *priv2 = spu->priv2;
665 * Save MFC_CMD Channel.
667 out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
669 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
673 static inline void reset_ch(struct spu_state *csa, struct spu *spu)
675 struct spu_priv2 __iomem *priv2 = spu->priv2;
676 u64 ch_indices[4] = { 21UL, 23UL, 28UL, 30UL };
677 u64 ch_counts[4] = { 16UL, 1UL, 1UL, 1UL };
682 * Reset the following CH: [21, 23, 28, 30]
684 for (i = 0; i < 4; i++) {
686 out_be64(&priv2->spu_chnlcntptr_RW, idx);
688 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
693 static inline void resume_mfc_queue(struct spu_state *csa, struct spu *spu)
695 struct spu_priv2 __iomem *priv2 = spu->priv2;
699 * Write MFC_CNTL[Sc]=0 (resume queue processing).
701 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
704 static inline void get_kernel_slb(u64 ea, u64 slb[2])
708 if (REGION_ID(ea) == KERNEL_REGION_ID)
709 llp = mmu_psize_defs[mmu_linear_psize].sllp;
711 llp = mmu_psize_defs[mmu_virtual_psize].sllp;
712 slb[0] = (get_kernel_vsid(ea) << SLB_VSID_SHIFT) |
713 SLB_VSID_KERNEL | llp;
714 slb[1] = (ea & ESID_MASK) | SLB_ESID_V;
717 static inline void load_mfc_slb(struct spu *spu, u64 slb[2], int slbe)
719 struct spu_priv2 __iomem *priv2 = spu->priv2;
721 out_be64(&priv2->slb_index_W, slbe);
723 out_be64(&priv2->slb_vsid_RW, slb[0]);
724 out_be64(&priv2->slb_esid_RW, slb[1]);
728 static inline void setup_mfc_slbs(struct spu_state *csa, struct spu *spu)
735 * If MFC_SR1[R]=1, write 0 to SLB_Invalidate_All
736 * register, then initialize SLB_VSID and SLB_ESID
737 * to provide access to SPU context save code and
740 * This implementation places both the context
741 * switch code and LSCSA in kernel address space.
743 * Further this implementation assumes that the
744 * MFC_SR1[R]=1 (in other words, assume that
745 * translation is desired by OS environment).
747 spu_invalidate_slbs(spu);
748 get_kernel_slb((unsigned long)&spu_save_code[0], code_slb);
749 get_kernel_slb((unsigned long)csa->lscsa, lscsa_slb);
750 load_mfc_slb(spu, code_slb, 0);
751 if ((lscsa_slb[0] != code_slb[0]) || (lscsa_slb[1] != code_slb[1]))
752 load_mfc_slb(spu, lscsa_slb, 1);
755 static inline void set_switch_active(struct spu_state *csa, struct spu *spu)
759 * Change the software context switch pending flag
760 * to context switch active.
762 set_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
763 clear_bit(SPU_CONTEXT_SWITCH_PENDING, &spu->flags);
767 static inline void enable_interrupts(struct spu_state *csa, struct spu *spu)
769 unsigned long class1_mask = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
770 CLASS1_ENABLE_STORAGE_FAULT_INTR;
774 * Reset and then enable interrupts, as
777 * This implementation enables only class1
778 * (translation) interrupts.
780 spin_lock_irq(&spu->register_lock);
781 spu_int_stat_clear(spu, 0, ~0ul);
782 spu_int_stat_clear(spu, 1, ~0ul);
783 spu_int_stat_clear(spu, 2, ~0ul);
784 spu_int_mask_set(spu, 0, 0ul);
785 spu_int_mask_set(spu, 1, class1_mask);
786 spu_int_mask_set(spu, 2, 0ul);
787 spin_unlock_irq(&spu->register_lock);
790 static inline int send_mfc_dma(struct spu *spu, unsigned long ea,
791 unsigned int ls_offset, unsigned int size,
792 unsigned int tag, unsigned int rclass,
795 struct spu_problem __iomem *prob = spu->problem;
796 union mfc_tag_size_class_cmd command;
797 unsigned int transfer_size;
798 volatile unsigned int status = 0x0;
802 (size > MFC_MAX_DMA_SIZE) ? MFC_MAX_DMA_SIZE : size;
803 command.u.mfc_size = transfer_size;
804 command.u.mfc_tag = tag;
805 command.u.mfc_rclassid = rclass;
806 command.u.mfc_cmd = cmd;
808 out_be32(&prob->mfc_lsa_W, ls_offset);
809 out_be64(&prob->mfc_ea_W, ea);
810 out_be64(&prob->mfc_union_W.all64, command.all64);
812 in_be32(&prob->mfc_union_W.by32.mfc_class_cmd32);
813 if (unlikely(status & 0x2)) {
816 } while (status & 0x3);
817 size -= transfer_size;
819 ls_offset += transfer_size;
824 static inline void save_ls_16kb(struct spu_state *csa, struct spu *spu)
826 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
827 unsigned int ls_offset = 0x0;
828 unsigned int size = 16384;
829 unsigned int tag = 0;
830 unsigned int rclass = 0;
831 unsigned int cmd = MFC_PUT_CMD;
834 * Issue a DMA command to copy the first 16K bytes
835 * of local storage to the CSA.
837 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
840 static inline void set_spu_npc(struct spu_state *csa, struct spu *spu)
842 struct spu_problem __iomem *prob = spu->problem;
846 * Write SPU_NPC[IE]=0 and SPU_NPC[LSA] to entry
847 * point address of context save code in local
850 * This implementation uses SPU-side save/restore
851 * programs with entry points at LSA of 0.
853 out_be32(&prob->spu_npc_RW, 0);
857 static inline void set_signot1(struct spu_state *csa, struct spu *spu)
859 struct spu_problem __iomem *prob = spu->problem;
867 * Write SPU_Sig_Notify_1 register with upper 32-bits
868 * of the CSA.LSCSA effective address.
870 addr64.ull = (u64) csa->lscsa;
871 out_be32(&prob->signal_notify1, addr64.ui[0]);
875 static inline void set_signot2(struct spu_state *csa, struct spu *spu)
877 struct spu_problem __iomem *prob = spu->problem;
885 * Write SPU_Sig_Notify_2 register with lower 32-bits
886 * of the CSA.LSCSA effective address.
888 addr64.ull = (u64) csa->lscsa;
889 out_be32(&prob->signal_notify2, addr64.ui[1]);
893 static inline void send_save_code(struct spu_state *csa, struct spu *spu)
895 unsigned long addr = (unsigned long)&spu_save_code[0];
896 unsigned int ls_offset = 0x0;
897 unsigned int size = sizeof(spu_save_code);
898 unsigned int tag = 0;
899 unsigned int rclass = 0;
900 unsigned int cmd = MFC_GETFS_CMD;
903 * Issue a DMA command to copy context save code
904 * to local storage and start SPU.
906 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
909 static inline void set_ppu_querymask(struct spu_state *csa, struct spu *spu)
911 struct spu_problem __iomem *prob = spu->problem;
915 * Write PPU_QueryMask=1 (enable Tag Group 0)
916 * and issue eieio instruction.
918 out_be32(&prob->dma_querymask_RW, MFC_TAGID_TO_TAGMASK(0));
922 static inline void wait_tag_complete(struct spu_state *csa, struct spu *spu)
924 struct spu_problem __iomem *prob = spu->problem;
925 u32 mask = MFC_TAGID_TO_TAGMASK(0);
932 * Poll PPU_TagStatus[gn] until 01 (Tag group 0 complete)
933 * or write PPU_QueryType[TS]=01 and wait for Tag Group
934 * Complete Interrupt. Write INT_Stat_Class0 or
935 * INT_Stat_Class2 with value of 'handled'.
937 POLL_WHILE_FALSE(in_be32(&prob->dma_tagstatus_R) & mask);
939 local_irq_save(flags);
940 spu_int_stat_clear(spu, 0, ~(0ul));
941 spu_int_stat_clear(spu, 2, ~(0ul));
942 local_irq_restore(flags);
945 static inline void wait_spu_stopped(struct spu_state *csa, struct spu *spu)
947 struct spu_problem __iomem *prob = spu->problem;
952 * Poll until SPU_Status[R]=0 or wait for SPU Class 0
953 * or SPU Class 2 interrupt. Write INT_Stat_class0
954 * or INT_Stat_class2 with value of handled.
956 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
958 local_irq_save(flags);
959 spu_int_stat_clear(spu, 0, ~(0ul));
960 spu_int_stat_clear(spu, 2, ~(0ul));
961 local_irq_restore(flags);
964 static inline int check_save_status(struct spu_state *csa, struct spu *spu)
966 struct spu_problem __iomem *prob = spu->problem;
970 * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
971 * context save succeeded, otherwise context save
974 complete = ((SPU_SAVE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
975 SPU_STATUS_STOPPED_BY_STOP);
976 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
979 static inline void terminate_spu_app(struct spu_state *csa, struct spu *spu)
982 * If required, notify the "using application" that
983 * the SPU task has been terminated. TBD.
987 static inline void suspend_mfc(struct spu_state *csa, struct spu *spu)
989 struct spu_priv2 __iomem *priv2 = spu->priv2;
993 * Write MFC_Cntl[Dh,Sc]='1','1' to suspend
994 * the queue and halt the decrementer.
996 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
997 MFC_CNTL_DECREMENTER_HALTED);
1001 static inline void wait_suspend_mfc_complete(struct spu_state *csa,
1004 struct spu_priv2 __iomem *priv2 = spu->priv2;
1008 * Poll MFC_CNTL[Ss] until 11 is returned.
1010 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1011 MFC_CNTL_SUSPEND_DMA_STATUS_MASK) ==
1012 MFC_CNTL_SUSPEND_COMPLETE);
1015 static inline int suspend_spe(struct spu_state *csa, struct spu *spu)
1017 struct spu_problem __iomem *prob = spu->problem;
1020 * If SPU_Status[R]=1, stop SPU execution
1021 * and wait for stop to complete.
1023 * Returns 1 if SPU_Status[R]=1 on entry.
1026 if (in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING) {
1027 if (in_be32(&prob->spu_status_R) &
1028 SPU_STATUS_ISOLATED_EXIT_STATUS) {
1029 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1030 SPU_STATUS_RUNNING);
1032 if ((in_be32(&prob->spu_status_R) &
1033 SPU_STATUS_ISOLATED_LOAD_STATUS)
1034 || (in_be32(&prob->spu_status_R) &
1035 SPU_STATUS_ISOLATED_STATE)) {
1036 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1038 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1039 SPU_STATUS_RUNNING);
1040 out_be32(&prob->spu_runcntl_RW, 0x2);
1042 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1043 SPU_STATUS_RUNNING);
1045 if (in_be32(&prob->spu_status_R) &
1046 SPU_STATUS_WAITING_FOR_CHANNEL) {
1047 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1049 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1050 SPU_STATUS_RUNNING);
1057 static inline void clear_spu_status(struct spu_state *csa, struct spu *spu)
1059 struct spu_problem __iomem *prob = spu->problem;
1061 /* Restore, Step 10:
1062 * If SPU_Status[R]=0 and SPU_Status[E,L,IS]=1,
1063 * release SPU from isolate state.
1065 if (!(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING)) {
1066 if (in_be32(&prob->spu_status_R) &
1067 SPU_STATUS_ISOLATED_EXIT_STATUS) {
1068 spu_mfc_sr1_set(spu,
1069 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1071 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1073 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1074 SPU_STATUS_RUNNING);
1076 if ((in_be32(&prob->spu_status_R) &
1077 SPU_STATUS_ISOLATED_LOAD_STATUS)
1078 || (in_be32(&prob->spu_status_R) &
1079 SPU_STATUS_ISOLATED_STATE)) {
1080 spu_mfc_sr1_set(spu,
1081 MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1083 out_be32(&prob->spu_runcntl_RW, 0x2);
1085 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1086 SPU_STATUS_RUNNING);
1091 static inline void reset_ch_part1(struct spu_state *csa, struct spu *spu)
1093 struct spu_priv2 __iomem *priv2 = spu->priv2;
1094 u64 ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1098 /* Restore, Step 20:
1102 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1103 out_be64(&priv2->spu_chnldata_RW, 0UL);
1105 /* Reset the following CH: [0,3,4,24,25,27] */
1106 for (i = 0; i < 7; i++) {
1107 idx = ch_indices[i];
1108 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1110 out_be64(&priv2->spu_chnldata_RW, 0UL);
1111 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1116 static inline void reset_ch_part2(struct spu_state *csa, struct spu *spu)
1118 struct spu_priv2 __iomem *priv2 = spu->priv2;
1119 u64 ch_indices[5] = { 21UL, 23UL, 28UL, 29UL, 30UL };
1120 u64 ch_counts[5] = { 16UL, 1UL, 1UL, 0UL, 1UL };
1124 /* Restore, Step 21:
1125 * Reset the following CH: [21, 23, 28, 29, 30]
1127 for (i = 0; i < 5; i++) {
1128 idx = ch_indices[i];
1129 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1131 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1136 static inline void setup_spu_status_part1(struct spu_state *csa,
1139 u32 status_P = SPU_STATUS_STOPPED_BY_STOP;
1140 u32 status_I = SPU_STATUS_INVALID_INSTR;
1141 u32 status_H = SPU_STATUS_STOPPED_BY_HALT;
1142 u32 status_S = SPU_STATUS_SINGLE_STEP;
1143 u32 status_S_I = SPU_STATUS_SINGLE_STEP | SPU_STATUS_INVALID_INSTR;
1144 u32 status_S_P = SPU_STATUS_SINGLE_STEP | SPU_STATUS_STOPPED_BY_STOP;
1145 u32 status_P_H = SPU_STATUS_STOPPED_BY_HALT |SPU_STATUS_STOPPED_BY_STOP;
1146 u32 status_P_I = SPU_STATUS_STOPPED_BY_STOP |SPU_STATUS_INVALID_INSTR;
1149 /* Restore, Step 27:
1150 * If the CSA.SPU_Status[I,S,H,P]=1 then add the correct
1151 * instruction sequence to the end of the SPU based restore
1152 * code (after the "context restored" stop and signal) to
1153 * restore the correct SPU status.
1155 * NOTE: Rather than modifying the SPU executable, we
1156 * instead add a new 'stopped_status' field to the
1157 * LSCSA. The SPU-side restore reads this field and
1158 * takes the appropriate action when exiting.
1162 (csa->prob.spu_status_R >> SPU_STOP_STATUS_SHIFT) & 0xFFFF;
1163 if ((csa->prob.spu_status_R & status_P_I) == status_P_I) {
1165 /* SPU_Status[P,I]=1 - Illegal Instruction followed
1166 * by Stop and Signal instruction, followed by 'br -4'.
1169 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_I;
1170 csa->lscsa->stopped_status.slot[1] = status_code;
1172 } else if ((csa->prob.spu_status_R & status_P_H) == status_P_H) {
1174 /* SPU_Status[P,H]=1 - Halt Conditional, followed
1175 * by Stop and Signal instruction, followed by
1178 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P_H;
1179 csa->lscsa->stopped_status.slot[1] = status_code;
1181 } else if ((csa->prob.spu_status_R & status_S_P) == status_S_P) {
1183 /* SPU_Status[S,P]=1 - Stop and Signal instruction
1184 * followed by 'br -4'.
1186 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_P;
1187 csa->lscsa->stopped_status.slot[1] = status_code;
1189 } else if ((csa->prob.spu_status_R & status_S_I) == status_S_I) {
1191 /* SPU_Status[S,I]=1 - Illegal instruction followed
1194 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S_I;
1195 csa->lscsa->stopped_status.slot[1] = status_code;
1197 } else if ((csa->prob.spu_status_R & status_P) == status_P) {
1199 /* SPU_Status[P]=1 - Stop and Signal instruction
1200 * followed by 'br -4'.
1202 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_P;
1203 csa->lscsa->stopped_status.slot[1] = status_code;
1205 } else if ((csa->prob.spu_status_R & status_H) == status_H) {
1207 /* SPU_Status[H]=1 - Halt Conditional, followed
1210 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_H;
1212 } else if ((csa->prob.spu_status_R & status_S) == status_S) {
1214 /* SPU_Status[S]=1 - Two nop instructions.
1216 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_S;
1218 } else if ((csa->prob.spu_status_R & status_I) == status_I) {
1220 /* SPU_Status[I]=1 - Illegal instruction followed
1223 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_I;
1228 static inline void setup_spu_status_part2(struct spu_state *csa,
1233 /* Restore, Step 28:
1234 * If the CSA.SPU_Status[I,S,H,P,R]=0 then
1235 * add a 'br *' instruction to the end of
1236 * the SPU based restore code.
1238 * NOTE: Rather than modifying the SPU executable, we
1239 * instead add a new 'stopped_status' field to the
1240 * LSCSA. The SPU-side restore reads this field and
1241 * takes the appropriate action when exiting.
1243 mask = SPU_STATUS_INVALID_INSTR |
1244 SPU_STATUS_SINGLE_STEP |
1245 SPU_STATUS_STOPPED_BY_HALT |
1246 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1247 if (!(csa->prob.spu_status_R & mask)) {
1248 csa->lscsa->stopped_status.slot[0] = SPU_STOPPED_STATUS_R;
1252 static inline void restore_mfc_rag(struct spu_state *csa, struct spu *spu)
1254 /* Restore, Step 29:
1255 * Restore RA_GROUP_ID register and the
1256 * RA_ENABLE reigster from the CSA.
1258 spu_resource_allocation_groupID_set(spu,
1259 csa->priv1.resource_allocation_groupID_RW);
1260 spu_resource_allocation_enable_set(spu,
1261 csa->priv1.resource_allocation_enable_RW);
1264 static inline void send_restore_code(struct spu_state *csa, struct spu *spu)
1266 unsigned long addr = (unsigned long)&spu_restore_code[0];
1267 unsigned int ls_offset = 0x0;
1268 unsigned int size = sizeof(spu_restore_code);
1269 unsigned int tag = 0;
1270 unsigned int rclass = 0;
1271 unsigned int cmd = MFC_GETFS_CMD;
1273 /* Restore, Step 37:
1274 * Issue MFC DMA command to copy context
1275 * restore code to local storage.
1277 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1280 static inline void setup_decr(struct spu_state *csa, struct spu *spu)
1282 /* Restore, Step 34:
1283 * If CSA.MFC_CNTL[Ds]=1 (decrementer was
1284 * running) then adjust decrementer, set
1285 * decrementer running status in LSCSA,
1286 * and set decrementer "wrapped" status
1289 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1290 cycles_t resume_time = get_cycles();
1291 cycles_t delta_time = resume_time - csa->suspend_time;
1293 csa->lscsa->decr.slot[0] -= delta_time;
1297 static inline void setup_ppu_mb(struct spu_state *csa, struct spu *spu)
1299 /* Restore, Step 35:
1300 * Copy the CSA.PU_MB data into the LSCSA.
1302 csa->lscsa->ppu_mb.slot[0] = csa->prob.pu_mb_R;
1305 static inline void setup_ppuint_mb(struct spu_state *csa, struct spu *spu)
1307 /* Restore, Step 36:
1308 * Copy the CSA.PUINT_MB data into the LSCSA.
1310 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1313 static inline int check_restore_status(struct spu_state *csa, struct spu *spu)
1315 struct spu_problem __iomem *prob = spu->problem;
1318 /* Restore, Step 40:
1319 * If SPU_Status[P]=1 and SPU_Status[SC] = "success",
1320 * context restore succeeded, otherwise context restore
1323 complete = ((SPU_RESTORE_COMPLETE << SPU_STOP_STATUS_SHIFT) |
1324 SPU_STATUS_STOPPED_BY_STOP);
1325 return (in_be32(&prob->spu_status_R) != complete) ? 1 : 0;
1328 static inline void restore_spu_privcntl(struct spu_state *csa, struct spu *spu)
1330 struct spu_priv2 __iomem *priv2 = spu->priv2;
1332 /* Restore, Step 41:
1333 * Restore SPU_PrivCntl from the CSA.
1335 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1339 static inline void restore_status_part1(struct spu_state *csa, struct spu *spu)
1341 struct spu_problem __iomem *prob = spu->problem;
1344 /* Restore, Step 42:
1345 * If any CSA.SPU_Status[I,S,H,P]=1, then
1346 * restore the error or single step state.
1348 mask = SPU_STATUS_INVALID_INSTR |
1349 SPU_STATUS_SINGLE_STEP |
1350 SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
1351 if (csa->prob.spu_status_R & mask) {
1352 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1354 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1355 SPU_STATUS_RUNNING);
1359 static inline void restore_status_part2(struct spu_state *csa, struct spu *spu)
1361 struct spu_problem __iomem *prob = spu->problem;
1364 /* Restore, Step 43:
1365 * If all CSA.SPU_Status[I,S,H,P,R]=0 then write
1366 * SPU_RunCntl[R0R1]='01', wait for SPU_Status[R]=1,
1367 * then write '00' to SPU_RunCntl[R0R1] and wait
1368 * for SPU_Status[R]=0.
1370 mask = SPU_STATUS_INVALID_INSTR |
1371 SPU_STATUS_SINGLE_STEP |
1372 SPU_STATUS_STOPPED_BY_HALT |
1373 SPU_STATUS_STOPPED_BY_STOP | SPU_STATUS_RUNNING;
1374 if (!(csa->prob.spu_status_R & mask)) {
1375 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1377 POLL_WHILE_FALSE(in_be32(&prob->spu_status_R) &
1378 SPU_STATUS_RUNNING);
1379 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1381 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) &
1382 SPU_STATUS_RUNNING);
1386 static inline void restore_ls_16kb(struct spu_state *csa, struct spu *spu)
1388 unsigned long addr = (unsigned long)&csa->lscsa->ls[0];
1389 unsigned int ls_offset = 0x0;
1390 unsigned int size = 16384;
1391 unsigned int tag = 0;
1392 unsigned int rclass = 0;
1393 unsigned int cmd = MFC_GET_CMD;
1395 /* Restore, Step 44:
1396 * Issue a DMA command to restore the first
1397 * 16kb of local storage from CSA.
1399 send_mfc_dma(spu, addr, ls_offset, size, tag, rclass, cmd);
1402 static inline void clear_interrupts(struct spu_state *csa, struct spu *spu)
1404 /* Restore, Step 49:
1405 * Write INT_MASK_class0 with value of 0.
1406 * Write INT_MASK_class1 with value of 0.
1407 * Write INT_MASK_class2 with value of 0.
1408 * Write INT_STAT_class0 with value of -1.
1409 * Write INT_STAT_class1 with value of -1.
1410 * Write INT_STAT_class2 with value of -1.
1412 spin_lock_irq(&spu->register_lock);
1413 spu_int_mask_set(spu, 0, 0ul);
1414 spu_int_mask_set(spu, 1, 0ul);
1415 spu_int_mask_set(spu, 2, 0ul);
1416 spu_int_stat_clear(spu, 0, ~0ul);
1417 spu_int_stat_clear(spu, 1, ~0ul);
1418 spu_int_stat_clear(spu, 2, ~0ul);
1419 spin_unlock_irq(&spu->register_lock);
1422 static inline void restore_mfc_queues(struct spu_state *csa, struct spu *spu)
1424 struct spu_priv2 __iomem *priv2 = spu->priv2;
1427 /* Restore, Step 50:
1428 * If MFC_Cntl[Se]!=0 then restore
1429 * MFC command queues.
1431 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1432 for (i = 0; i < 8; i++) {
1433 out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1434 csa->priv2.puq[i].mfc_cq_data0_RW);
1435 out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1436 csa->priv2.puq[i].mfc_cq_data1_RW);
1437 out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1438 csa->priv2.puq[i].mfc_cq_data2_RW);
1439 out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1440 csa->priv2.puq[i].mfc_cq_data3_RW);
1442 for (i = 0; i < 16; i++) {
1443 out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1444 csa->priv2.spuq[i].mfc_cq_data0_RW);
1445 out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1446 csa->priv2.spuq[i].mfc_cq_data1_RW);
1447 out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1448 csa->priv2.spuq[i].mfc_cq_data2_RW);
1449 out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1450 csa->priv2.spuq[i].mfc_cq_data3_RW);
1456 static inline void restore_ppu_querymask(struct spu_state *csa, struct spu *spu)
1458 struct spu_problem __iomem *prob = spu->problem;
1460 /* Restore, Step 51:
1461 * Restore the PPU_QueryMask register from CSA.
1463 out_be32(&prob->dma_querymask_RW, csa->prob.dma_querymask_RW);
1467 static inline void restore_ppu_querytype(struct spu_state *csa, struct spu *spu)
1469 struct spu_problem __iomem *prob = spu->problem;
1471 /* Restore, Step 52:
1472 * Restore the PPU_QueryType register from CSA.
1474 out_be32(&prob->dma_querytype_RW, csa->prob.dma_querytype_RW);
1478 static inline void restore_mfc_csr_tsq(struct spu_state *csa, struct spu *spu)
1480 struct spu_priv2 __iomem *priv2 = spu->priv2;
1482 /* Restore, Step 53:
1483 * Restore the MFC_CSR_TSQ register from CSA.
1485 out_be64(&priv2->spu_tag_status_query_RW,
1486 csa->priv2.spu_tag_status_query_RW);
1490 static inline void restore_mfc_csr_cmd(struct spu_state *csa, struct spu *spu)
1492 struct spu_priv2 __iomem *priv2 = spu->priv2;
1494 /* Restore, Step 54:
1495 * Restore the MFC_CSR_CMD1 and MFC_CSR_CMD2
1496 * registers from CSA.
1498 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1499 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1503 static inline void restore_mfc_csr_ato(struct spu_state *csa, struct spu *spu)
1505 struct spu_priv2 __iomem *priv2 = spu->priv2;
1507 /* Restore, Step 55:
1508 * Restore the MFC_CSR_ATO register from CSA.
1510 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1513 static inline void restore_mfc_tclass_id(struct spu_state *csa, struct spu *spu)
1515 /* Restore, Step 56:
1516 * Restore the MFC_TCLASS_ID register from CSA.
1518 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1522 static inline void set_llr_event(struct spu_state *csa, struct spu *spu)
1524 u64 ch0_cnt, ch0_data;
1527 /* Restore, Step 57:
1528 * Set the Lock Line Reservation Lost Event by:
1529 * 1. OR CSA.SPU_Event_Status with bit 21 (Lr) set to 1.
1530 * 2. If CSA.SPU_Channel_0_Count=0 and
1531 * CSA.SPU_Wr_Event_Mask[Lr]=1 and
1532 * CSA.SPU_Event_Status[Lr]=0 then set
1533 * CSA.SPU_Event_Status_Count=1.
1535 ch0_cnt = csa->spu_chnlcnt_RW[0];
1536 ch0_data = csa->spu_chnldata_RW[0];
1537 ch1_data = csa->spu_chnldata_RW[1];
1538 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT;
1539 if ((ch0_cnt == 0) && !(ch0_data & MFC_LLR_LOST_EVENT) &&
1540 (ch1_data & MFC_LLR_LOST_EVENT)) {
1541 csa->spu_chnlcnt_RW[0] = 1;
1545 static inline void restore_decr_wrapped(struct spu_state *csa, struct spu *spu)
1547 /* Restore, Step 58:
1548 * If the status of the CSA software decrementer
1549 * "wrapped" flag is set, OR in a '1' to
1550 * CSA.SPU_Event_Status[Tm].
1552 if (csa->lscsa->decr_status.slot[0] == 1) {
1553 csa->spu_chnldata_RW[0] |= 0x20;
1555 if ((csa->lscsa->decr_status.slot[0] == 1) &&
1556 (csa->spu_chnlcnt_RW[0] == 0 &&
1557 ((csa->spu_chnldata_RW[2] & 0x20) == 0x0) &&
1558 ((csa->spu_chnldata_RW[0] & 0x20) != 0x1))) {
1559 csa->spu_chnlcnt_RW[0] = 1;
1563 static inline void restore_ch_part1(struct spu_state *csa, struct spu *spu)
1565 struct spu_priv2 __iomem *priv2 = spu->priv2;
1566 u64 idx, ch_indices[7] = { 0UL, 3UL, 4UL, 24UL, 25UL, 27UL };
1569 /* Restore, Step 59:
1572 /* Restore CH 1 without count */
1573 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1574 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[1]);
1576 /* Restore the following CH: [0,3,4,24,25,27] */
1577 for (i = 0; i < 7; i++) {
1578 idx = ch_indices[i];
1579 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1581 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1582 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1587 static inline void restore_ch_part2(struct spu_state *csa, struct spu *spu)
1589 struct spu_priv2 __iomem *priv2 = spu->priv2;
1590 u64 ch_indices[3] = { 9UL, 21UL, 23UL };
1591 u64 ch_counts[3] = { 1UL, 16UL, 1UL };
1595 /* Restore, Step 60:
1596 * Restore the following CH: [9,21,23].
1599 ch_counts[1] = csa->spu_chnlcnt_RW[21];
1601 for (i = 0; i < 3; i++) {
1602 idx = ch_indices[i];
1603 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1605 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1610 static inline void restore_spu_lslr(struct spu_state *csa, struct spu *spu)
1612 struct spu_priv2 __iomem *priv2 = spu->priv2;
1614 /* Restore, Step 61:
1615 * Restore the SPU_LSLR register from CSA.
1617 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1621 static inline void restore_spu_cfg(struct spu_state *csa, struct spu *spu)
1623 struct spu_priv2 __iomem *priv2 = spu->priv2;
1625 /* Restore, Step 62:
1626 * Restore the SPU_Cfg register from CSA.
1628 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1632 static inline void restore_pm_trace(struct spu_state *csa, struct spu *spu)
1634 /* Restore, Step 63:
1635 * Restore PM_Trace_Tag_Wait_Mask from CSA.
1636 * Not performed by this implementation.
1640 static inline void restore_spu_npc(struct spu_state *csa, struct spu *spu)
1642 struct spu_problem __iomem *prob = spu->problem;
1644 /* Restore, Step 64:
1645 * Restore SPU_NPC from CSA.
1647 out_be32(&prob->spu_npc_RW, csa->prob.spu_npc_RW);
1651 static inline void restore_spu_mb(struct spu_state *csa, struct spu *spu)
1653 struct spu_priv2 __iomem *priv2 = spu->priv2;
1656 /* Restore, Step 65:
1657 * Restore MFC_RdSPU_MB from CSA.
1659 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1661 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1662 for (i = 0; i < 4; i++) {
1663 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1668 static inline void check_ppu_mb_stat(struct spu_state *csa, struct spu *spu)
1670 struct spu_problem __iomem *prob = spu->problem;
1673 /* Restore, Step 66:
1674 * If CSA.MB_Stat[P]=0 (mailbox empty) then
1675 * read from the PPU_MB register.
1677 if ((csa->prob.mb_stat_R & 0xFF) == 0) {
1678 dummy = in_be32(&prob->pu_mb_R);
1683 static inline void check_ppuint_mb_stat(struct spu_state *csa, struct spu *spu)
1685 struct spu_priv2 __iomem *priv2 = spu->priv2;
1688 /* Restore, Step 66:
1689 * If CSA.MB_Stat[I]=0 (mailbox empty) then
1690 * read from the PPUINT_MB register.
1692 if ((csa->prob.mb_stat_R & 0xFF0000) == 0) {
1693 dummy = in_be64(&priv2->puint_mb_R);
1695 spu_int_stat_clear(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
1700 static inline void restore_mfc_sr1(struct spu_state *csa, struct spu *spu)
1702 /* Restore, Step 69:
1703 * Restore the MFC_SR1 register from CSA.
1705 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1709 static inline void restore_other_spu_access(struct spu_state *csa,
1712 /* Restore, Step 70:
1713 * Restore other SPU mappings to this SPU. TBD.
1717 static inline void restore_spu_runcntl(struct spu_state *csa, struct spu *spu)
1719 struct spu_problem __iomem *prob = spu->problem;
1721 /* Restore, Step 71:
1722 * If CSA.SPU_Status[R]=1 then write
1723 * SPU_RunCntl[R0R1]='01'.
1725 if (csa->prob.spu_status_R & SPU_STATUS_RUNNING) {
1726 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_RUNNABLE);
1731 static inline void restore_mfc_cntl(struct spu_state *csa, struct spu *spu)
1733 struct spu_priv2 __iomem *priv2 = spu->priv2;
1735 /* Restore, Step 72:
1736 * Restore the MFC_CNTL register for the CSA.
1738 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1741 * FIXME: this is to restart a DMA that we were processing
1742 * before the save. better remember the fault information
1743 * in the csa instead.
1745 if ((csa->priv2.mfc_control_RW & MFC_CNTL_SUSPEND_DMA_QUEUE_MASK)) {
1746 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
1751 static inline void enable_user_access(struct spu_state *csa, struct spu *spu)
1753 /* Restore, Step 73:
1754 * Enable user-space access (if provided) to this
1755 * SPU by mapping the virtual pages assigned to
1756 * the SPU memory-mapped I/O (MMIO) for problem
1761 static inline void reset_switch_active(struct spu_state *csa, struct spu *spu)
1763 /* Restore, Step 74:
1764 * Reset the "context switch active" flag.
1766 clear_bit(SPU_CONTEXT_SWITCH_ACTIVE, &spu->flags);
1770 static inline void reenable_interrupts(struct spu_state *csa, struct spu *spu)
1772 /* Restore, Step 75:
1773 * Re-enable SPU interrupts.
1775 spin_lock_irq(&spu->register_lock);
1776 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1777 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1778 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
1779 spin_unlock_irq(&spu->register_lock);
1782 static int quiece_spu(struct spu_state *prev, struct spu *spu)
1785 * Combined steps 2-18 of SPU context save sequence, which
1786 * quiesce the SPU state (disable SPU execution, MFC command
1787 * queues, decrementer, SPU interrupts, etc.).
1789 * Returns 0 on success.
1790 * 2 if failed step 2.
1791 * 6 if failed step 6.
1794 if (check_spu_isolate(prev, spu)) { /* Step 2. */
1797 disable_interrupts(prev, spu); /* Step 3. */
1798 set_watchdog_timer(prev, spu); /* Step 4. */
1799 inhibit_user_access(prev, spu); /* Step 5. */
1800 if (check_spu_isolate(prev, spu)) { /* Step 6. */
1803 set_switch_pending(prev, spu); /* Step 7. */
1804 save_mfc_cntl(prev, spu); /* Step 8. */
1805 save_spu_runcntl(prev, spu); /* Step 9. */
1806 save_mfc_sr1(prev, spu); /* Step 10. */
1807 save_spu_status(prev, spu); /* Step 11. */
1808 save_mfc_decr(prev, spu); /* Step 12. */
1809 halt_mfc_decr(prev, spu); /* Step 13. */
1810 save_timebase(prev, spu); /* Step 14. */
1811 remove_other_spu_access(prev, spu); /* Step 15. */
1812 do_mfc_mssync(prev, spu); /* Step 16. */
1813 issue_mfc_tlbie(prev, spu); /* Step 17. */
1814 handle_pending_interrupts(prev, spu); /* Step 18. */
1819 static void save_csa(struct spu_state *prev, struct spu *spu)
1822 * Combine steps 19-44 of SPU context save sequence, which
1823 * save regions of the privileged & problem state areas.
1826 save_mfc_queues(prev, spu); /* Step 19. */
1827 save_ppu_querymask(prev, spu); /* Step 20. */
1828 save_ppu_querytype(prev, spu); /* Step 21. */
1829 save_ppu_tagstatus(prev, spu); /* NEW. */
1830 save_mfc_csr_tsq(prev, spu); /* Step 22. */
1831 save_mfc_csr_cmd(prev, spu); /* Step 23. */
1832 save_mfc_csr_ato(prev, spu); /* Step 24. */
1833 save_mfc_tclass_id(prev, spu); /* Step 25. */
1834 set_mfc_tclass_id(prev, spu); /* Step 26. */
1835 purge_mfc_queue(prev, spu); /* Step 27. */
1836 wait_purge_complete(prev, spu); /* Step 28. */
1837 setup_mfc_sr1(prev, spu); /* Step 30. */
1838 save_spu_npc(prev, spu); /* Step 31. */
1839 save_spu_privcntl(prev, spu); /* Step 32. */
1840 reset_spu_privcntl(prev, spu); /* Step 33. */
1841 save_spu_lslr(prev, spu); /* Step 34. */
1842 reset_spu_lslr(prev, spu); /* Step 35. */
1843 save_spu_cfg(prev, spu); /* Step 36. */
1844 save_pm_trace(prev, spu); /* Step 37. */
1845 save_mfc_rag(prev, spu); /* Step 38. */
1846 save_ppu_mb_stat(prev, spu); /* Step 39. */
1847 save_ppu_mb(prev, spu); /* Step 40. */
1848 save_ppuint_mb(prev, spu); /* Step 41. */
1849 save_ch_part1(prev, spu); /* Step 42. */
1850 save_spu_mb(prev, spu); /* Step 43. */
1851 save_mfc_cmd(prev, spu); /* Step 44. */
1852 reset_ch(prev, spu); /* Step 45. */
1855 static void save_lscsa(struct spu_state *prev, struct spu *spu)
1858 * Perform steps 46-57 of SPU context save sequence,
1859 * which save regions of the local store and register
1863 resume_mfc_queue(prev, spu); /* Step 46. */
1864 setup_mfc_slbs(prev, spu); /* Step 47. */
1865 set_switch_active(prev, spu); /* Step 48. */
1866 enable_interrupts(prev, spu); /* Step 49. */
1867 save_ls_16kb(prev, spu); /* Step 50. */
1868 set_spu_npc(prev, spu); /* Step 51. */
1869 set_signot1(prev, spu); /* Step 52. */
1870 set_signot2(prev, spu); /* Step 53. */
1871 send_save_code(prev, spu); /* Step 54. */
1872 set_ppu_querymask(prev, spu); /* Step 55. */
1873 wait_tag_complete(prev, spu); /* Step 56. */
1874 wait_spu_stopped(prev, spu); /* Step 57. */
1877 static void force_spu_isolate_exit(struct spu *spu)
1879 struct spu_problem __iomem *prob = spu->problem;
1880 struct spu_priv2 __iomem *priv2 = spu->priv2;
1882 /* Stop SPE execution and wait for completion. */
1883 out_be32(&prob->spu_runcntl_RW, SPU_RUNCNTL_STOP);
1885 POLL_WHILE_TRUE(in_be32(&prob->spu_status_R) & SPU_STATUS_RUNNING);
1887 /* Restart SPE master runcntl. */
1888 spu_mfc_sr1_set(spu, MFC_STATE1_MASTER_RUN_CONTROL_MASK);
1891 /* Initiate isolate exit request and wait for completion. */
1892 out_be64(&priv2->spu_privcntl_RW, 4LL);
1894 out_be32(&prob->spu_runcntl_RW, 2);
1896 POLL_WHILE_FALSE((in_be32(&prob->spu_status_R)
1897 & SPU_STATUS_STOPPED_BY_STOP));
1899 /* Reset load request to normal. */
1900 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
1906 * Check SPU run-control state and force isolated
1907 * exit function as necessary.
1909 static void stop_spu_isolate(struct spu *spu)
1911 struct spu_problem __iomem *prob = spu->problem;
1913 if (in_be32(&prob->spu_status_R) & SPU_STATUS_ISOLATED_STATE) {
1914 /* The SPU is in isolated state; the only way
1915 * to get it out is to perform an isolated
1916 * exit (clean) operation.
1918 force_spu_isolate_exit(spu);
1922 static void harvest(struct spu_state *prev, struct spu *spu)
1925 * Perform steps 2-25 of SPU context restore sequence,
1926 * which resets an SPU either after a failed save, or
1927 * when using SPU for first time.
1930 disable_interrupts(prev, spu); /* Step 2. */
1931 inhibit_user_access(prev, spu); /* Step 3. */
1932 terminate_spu_app(prev, spu); /* Step 4. */
1933 set_switch_pending(prev, spu); /* Step 5. */
1934 stop_spu_isolate(spu); /* NEW. */
1935 remove_other_spu_access(prev, spu); /* Step 6. */
1936 suspend_mfc(prev, spu); /* Step 7. */
1937 wait_suspend_mfc_complete(prev, spu); /* Step 8. */
1938 if (!suspend_spe(prev, spu)) /* Step 9. */
1939 clear_spu_status(prev, spu); /* Step 10. */
1940 do_mfc_mssync(prev, spu); /* Step 11. */
1941 issue_mfc_tlbie(prev, spu); /* Step 12. */
1942 handle_pending_interrupts(prev, spu); /* Step 13. */
1943 purge_mfc_queue(prev, spu); /* Step 14. */
1944 wait_purge_complete(prev, spu); /* Step 15. */
1945 reset_spu_privcntl(prev, spu); /* Step 16. */
1946 reset_spu_lslr(prev, spu); /* Step 17. */
1947 setup_mfc_sr1(prev, spu); /* Step 18. */
1948 spu_invalidate_slbs(spu); /* Step 19. */
1949 reset_ch_part1(prev, spu); /* Step 20. */
1950 reset_ch_part2(prev, spu); /* Step 21. */
1951 enable_interrupts(prev, spu); /* Step 22. */
1952 set_switch_active(prev, spu); /* Step 23. */
1953 set_mfc_tclass_id(prev, spu); /* Step 24. */
1954 resume_mfc_queue(prev, spu); /* Step 25. */
1957 static void restore_lscsa(struct spu_state *next, struct spu *spu)
1960 * Perform steps 26-40 of SPU context restore sequence,
1961 * which restores regions of the local store and register
1965 set_watchdog_timer(next, spu); /* Step 26. */
1966 setup_spu_status_part1(next, spu); /* Step 27. */
1967 setup_spu_status_part2(next, spu); /* Step 28. */
1968 restore_mfc_rag(next, spu); /* Step 29. */
1969 setup_mfc_slbs(next, spu); /* Step 30. */
1970 set_spu_npc(next, spu); /* Step 31. */
1971 set_signot1(next, spu); /* Step 32. */
1972 set_signot2(next, spu); /* Step 33. */
1973 setup_decr(next, spu); /* Step 34. */
1974 setup_ppu_mb(next, spu); /* Step 35. */
1975 setup_ppuint_mb(next, spu); /* Step 36. */
1976 send_restore_code(next, spu); /* Step 37. */
1977 set_ppu_querymask(next, spu); /* Step 38. */
1978 wait_tag_complete(next, spu); /* Step 39. */
1979 wait_spu_stopped(next, spu); /* Step 40. */
1982 static void restore_csa(struct spu_state *next, struct spu *spu)
1985 * Combine steps 41-76 of SPU context restore sequence, which
1986 * restore regions of the privileged & problem state areas.
1989 restore_spu_privcntl(next, spu); /* Step 41. */
1990 restore_status_part1(next, spu); /* Step 42. */
1991 restore_status_part2(next, spu); /* Step 43. */
1992 restore_ls_16kb(next, spu); /* Step 44. */
1993 wait_tag_complete(next, spu); /* Step 45. */
1994 suspend_mfc(next, spu); /* Step 46. */
1995 wait_suspend_mfc_complete(next, spu); /* Step 47. */
1996 issue_mfc_tlbie(next, spu); /* Step 48. */
1997 clear_interrupts(next, spu); /* Step 49. */
1998 restore_mfc_queues(next, spu); /* Step 50. */
1999 restore_ppu_querymask(next, spu); /* Step 51. */
2000 restore_ppu_querytype(next, spu); /* Step 52. */
2001 restore_mfc_csr_tsq(next, spu); /* Step 53. */
2002 restore_mfc_csr_cmd(next, spu); /* Step 54. */
2003 restore_mfc_csr_ato(next, spu); /* Step 55. */
2004 restore_mfc_tclass_id(next, spu); /* Step 56. */
2005 set_llr_event(next, spu); /* Step 57. */
2006 restore_decr_wrapped(next, spu); /* Step 58. */
2007 restore_ch_part1(next, spu); /* Step 59. */
2008 restore_ch_part2(next, spu); /* Step 60. */
2009 restore_spu_lslr(next, spu); /* Step 61. */
2010 restore_spu_cfg(next, spu); /* Step 62. */
2011 restore_pm_trace(next, spu); /* Step 63. */
2012 restore_spu_npc(next, spu); /* Step 64. */
2013 restore_spu_mb(next, spu); /* Step 65. */
2014 check_ppu_mb_stat(next, spu); /* Step 66. */
2015 check_ppuint_mb_stat(next, spu); /* Step 67. */
2016 spu_invalidate_slbs(spu); /* Modified Step 68. */
2017 restore_mfc_sr1(next, spu); /* Step 69. */
2018 restore_other_spu_access(next, spu); /* Step 70. */
2019 restore_spu_runcntl(next, spu); /* Step 71. */
2020 restore_mfc_cntl(next, spu); /* Step 72. */
2021 enable_user_access(next, spu); /* Step 73. */
2022 reset_switch_active(next, spu); /* Step 74. */
2023 reenable_interrupts(next, spu); /* Step 75. */
2026 static int __do_spu_save(struct spu_state *prev, struct spu *spu)
2031 * SPU context save can be broken into three phases:
2033 * (a) quiesce [steps 2-16].
2034 * (b) save of CSA, performed by PPE [steps 17-42]
2035 * (c) save of LSCSA, mostly performed by SPU [steps 43-52].
2037 * Returns 0 on success.
2038 * 2,6 if failed to quiece SPU
2039 * 53 if SPU-side of save failed.
2042 rc = quiece_spu(prev, spu); /* Steps 2-16. */
2053 save_csa(prev, spu); /* Steps 17-43. */
2054 save_lscsa(prev, spu); /* Steps 44-53. */
2055 return check_save_status(prev, spu); /* Step 54. */
2058 static int __do_spu_restore(struct spu_state *next, struct spu *spu)
2063 * SPU context restore can be broken into three phases:
2065 * (a) harvest (or reset) SPU [steps 2-24].
2066 * (b) restore LSCSA [steps 25-40], mostly performed by SPU.
2067 * (c) restore CSA [steps 41-76], performed by PPE.
2069 * The 'harvest' step is not performed here, but rather
2073 restore_lscsa(next, spu); /* Steps 24-39. */
2074 rc = check_restore_status(next, spu); /* Step 40. */
2077 /* Failed. Return now. */
2081 /* Fall through to next step. */
2084 restore_csa(next, spu);
2090 * spu_save - SPU context save, with locking.
2091 * @prev: pointer to SPU context save area, to be saved.
2092 * @spu: pointer to SPU iomem structure.
2094 * Acquire locks, perform the save operation then return.
2096 int spu_save(struct spu_state *prev, struct spu *spu)
2100 acquire_spu_lock(spu); /* Step 1. */
2101 prev->dar = spu->dar;
2102 prev->dsisr = spu->dsisr;
2105 rc = __do_spu_save(prev, spu); /* Steps 2-53. */
2106 release_spu_lock(spu);
2107 if (rc != 0 && rc != 2 && rc != 6) {
2108 panic("%s failed on SPU[%d], rc=%d.\n",
2109 __func__, spu->number, rc);
2113 EXPORT_SYMBOL_GPL(spu_save);
2116 * spu_restore - SPU context restore, with harvest and locking.
2117 * @new: pointer to SPU context save area, to be restored.
2118 * @spu: pointer to SPU iomem structure.
2120 * Perform harvest + restore, as we may not be coming
2121 * from a previous successful save operation, and the
2122 * hardware state is unknown.
2124 int spu_restore(struct spu_state *new, struct spu *spu)
2128 acquire_spu_lock(spu);
2130 spu->slb_replace = 0;
2133 spu->class_0_pending = 0;
2134 rc = __do_spu_restore(new, spu);
2135 release_spu_lock(spu);
2137 panic("%s failed on SPU[%d] rc=%d.\n",
2138 __func__, spu->number, rc);
2142 EXPORT_SYMBOL_GPL(spu_restore);
2145 * spu_harvest - SPU harvest (reset) operation
2146 * @spu: pointer to SPU iomem structure.
2148 * Perform SPU harvest (reset) operation.
2150 void spu_harvest(struct spu *spu)
2152 acquire_spu_lock(spu);
2154 release_spu_lock(spu);
2157 static void init_prob(struct spu_state *csa)
2159 csa->spu_chnlcnt_RW[9] = 1;
2160 csa->spu_chnlcnt_RW[21] = 16;
2161 csa->spu_chnlcnt_RW[23] = 1;
2162 csa->spu_chnlcnt_RW[28] = 1;
2163 csa->spu_chnlcnt_RW[30] = 1;
2164 csa->prob.spu_runcntl_RW = SPU_RUNCNTL_STOP;
2165 csa->prob.mb_stat_R = 0x000400;
2168 static void init_priv1(struct spu_state *csa)
2170 /* Enable decode, relocate, tlbie response, master runcntl. */
2171 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2172 MFC_STATE1_MASTER_RUN_CONTROL_MASK |
2173 MFC_STATE1_PROBLEM_STATE_MASK |
2174 MFC_STATE1_RELOCATE_MASK | MFC_STATE1_BUS_TLBIE_MASK;
2176 /* Enable OS-specific set of interrupts. */
2177 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2178 CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR |
2179 CLASS0_ENABLE_SPU_ERROR_INTR;
2180 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2181 CLASS1_ENABLE_STORAGE_FAULT_INTR;
2182 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
2183 CLASS2_ENABLE_SPU_HALT_INTR |
2184 CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR;
2187 static void init_priv2(struct spu_state *csa)
2189 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2190 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |
2191 MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION |
2192 MFC_CNTL_DMA_QUEUES_EMPTY_MASK;
2196 * spu_alloc_csa - allocate and initialize an SPU context save area.
2198 * Allocate and initialize the contents of an SPU context save area.
2199 * This includes enabling address translation, interrupt masks, etc.,
2200 * as appropriate for the given OS environment.
2202 * Note that storage for the 'lscsa' is allocated separately,
2203 * as it is by far the largest of the context save regions,
2204 * and may need to be pinned or otherwise specially aligned.
2206 int spu_init_csa(struct spu_state *csa)
2212 memset(csa, 0, sizeof(struct spu_state));
2214 rc = spu_alloc_lscsa(csa);
2218 spin_lock_init(&csa->register_lock);
2226 EXPORT_SYMBOL_GPL(spu_init_csa);
2228 void spu_fini_csa(struct spu_state *csa)
2230 spu_free_lscsa(csa);
2232 EXPORT_SYMBOL_GPL(spu_fini_csa);