git.oblomov.eu Git - linux-2.6/blob - arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/string.h>
  91 #include <linux/bootmem.h>
  92
  93 #include <asm/delay.h>
  94 #include <asm/hw_irq.h>
  95 #include <asm/io.h>
  96 #include <asm/iosapic.h>
  97 #include <asm/machvec.h>
  98 #include <asm/processor.h>
  99 #include <asm/ptrace.h>
 100 #include <asm/system.h>
 101
 102 #undef DEBUG_INTERRUPT_ROUTING
 103
 104 #ifdef DEBUG_INTERRUPT_ROUTING
 105 #define DBG(fmt...)     printk(fmt)
 106 #else
 107 #define DBG(fmt...)
 108 #endif
 109
 110 #define NR_PREALLOCATE_RTE_ENTRIES \
 111         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 112 #define RTE_PREALLOCATED        (1)
 113
 114 static DEFINE_SPINLOCK(iosapic_lock);
 115
 116 /*
 117  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 118  * vector.
 119  */
 120
 121 #define NO_REF_RTE      0
 122
 123 static struct iosapic {
 124         char __iomem    *addr;          /* base address of IOSAPIC */
 125         unsigned int    gsi_base;       /* GSI base */
 126         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 127         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 128 #ifdef CONFIG_NUMA
 129         unsigned short  node;           /* numa node association via pxm */
 130 #endif
 131         spinlock_t      lock;           /* lock for indirect reg access */
 132 } iosapic_lists[NR_IOSAPICS];
 133
 134 struct iosapic_rte_info {
 135         struct list_head rte_list;      /* RTEs sharing the same vector */
 136         char            rte_index;      /* IOSAPIC RTE index */
 137         int             refcnt;         /* reference counter */
 138         unsigned int    flags;          /* flags */
 139         struct iosapic  *iosapic;
 140 } ____cacheline_aligned;
 141
 142 static struct iosapic_intr_info {
 143         struct list_head rtes;          /* RTEs using this vector (empty =>
 144                                          * not an IOSAPIC interrupt) */
 145         int             count;          /* # of RTEs that shares this vector */
 146         u32             low32;          /* current value of low word of
 147                                          * Redirection table entry */
 148         unsigned int    dest;           /* destination CPU physical ID */
 149         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 150         unsigned char   polarity: 1;    /* interrupt polarity
 151                                          * (see iosapic.h) */
 152         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 153 } iosapic_intr_info[NR_IRQS];
 154
 155 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 156
 157 static int iosapic_kmalloc_ok;
 158 static LIST_HEAD(free_rte_list);
 159
 160 static inline void
 161 iosapic_write(struct iosapic *iosapic, unsigned int reg, u32 val)
 162 {
 163         unsigned long flags;
 164
 165         spin_lock_irqsave(&iosapic->lock, flags);
 166         __iosapic_write(iosapic->addr, reg, val);
 167         spin_unlock_irqrestore(&iosapic->lock, flags);
 168 }
 169
 170 /*
 171  * Find an IOSAPIC associated with a GSI
 172  */
 173 static inline int
 174 find_iosapic (unsigned int gsi)
 175 {
 176         int i;
 177
 178         for (i = 0; i < NR_IOSAPICS; i++) {
 179                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 180                     iosapic_lists[i].num_rte)
 181                         return i;
 182         }
 183
 184         return -1;
 185 }
 186
 187 static inline int __gsi_to_irq(unsigned int gsi)
 188 {
 189         int irq;
 190         struct iosapic_intr_info *info;
 191         struct iosapic_rte_info *rte;
 192
 193         for (irq = 0; irq < NR_IRQS; irq++) {
 194                 info = &iosapic_intr_info[irq];
 195                 list_for_each_entry(rte, &info->rtes, rte_list)
 196                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 197                                 return irq;
 198         }
 199         return -1;
 200 }
 201
 202 /*
 203  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 204  * entry exists, return -1.
 205  */
 206 inline int
 207 gsi_to_vector (unsigned int gsi)
 208 {
 209         int irq = __gsi_to_irq(gsi);
 210         if (check_irq_used(irq) < 0)
 211                 return -1;
 212         return irq_to_vector(irq);
 213 }
 214
 215 int
 216 gsi_to_irq (unsigned int gsi)
 217 {
 218         unsigned long flags;
 219         int irq;
 220
 221         spin_lock_irqsave(&iosapic_lock, flags);
 222         irq = __gsi_to_irq(gsi);
 223         spin_unlock_irqrestore(&iosapic_lock, flags);
 224         return irq;
 225 }
 226
 227 static struct iosapic_rte_info *find_rte(unsigned int irq, unsigned int gsi)
 228 {
 229         struct iosapic_rte_info *rte;
 230
 231         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 232                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 233                         return rte;
 234         return NULL;
 235 }
 236
 237 static void
 238 set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 239 {
 240         unsigned long pol, trigger, dmode;
 241         u32 low32, high32;
 242         int rte_index;
 243         char redir;
 244         struct iosapic_rte_info *rte;
 245         ia64_vector vector = irq_to_vector(irq);
 246
 247         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 248
 249         rte = find_rte(irq, gsi);
 250         if (!rte)
 251                 return;         /* not an IOSAPIC interrupt */
 252
 253         rte_index = rte->rte_index;
 254         pol     = iosapic_intr_info[irq].polarity;
 255         trigger = iosapic_intr_info[irq].trigger;
 256         dmode   = iosapic_intr_info[irq].dmode;
 257
 258         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 259
 260 #ifdef CONFIG_SMP
 261         set_irq_affinity_info(irq, (int)(dest & 0xffff), redir);
 262 #endif
 263
 264         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 265                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 266                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 267                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 268                  vector);
 269
 270         /* dest contains both id and eid */
 271         high32 = (dest << IOSAPIC_DEST_SHIFT);
 272
 273         iosapic_write(rte->iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 274         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 275         iosapic_intr_info[irq].low32 = low32;
 276         iosapic_intr_info[irq].dest = dest;
 277 }
 278
 279 static void
 280 nop (unsigned int irq)
 281 {
 282         /* do nothing... */
 283 }
 284
 285
 286 #ifdef CONFIG_KEXEC
 287 void
 288 kexec_disable_iosapic(void)
 289 {
 290         struct iosapic_intr_info *info;
 291         struct iosapic_rte_info *rte;
 292         ia64_vector vec;
 293         int irq;
 294
 295         for (irq = 0; irq < NR_IRQS; irq++) {
 296                 info = &iosapic_intr_info[irq];
 297                 vec = irq_to_vector(irq);
 298                 list_for_each_entry(rte, &info->rtes,
 299                                 rte_list) {
 300                         iosapic_write(rte->iosapic,
 301                                         IOSAPIC_RTE_LOW(rte->rte_index),
 302                                         IOSAPIC_MASK|vec);
 303                         iosapic_eoi(rte->iosapic->addr, vec);
 304                 }
 305         }
 306 }
 307 #endif
 308
 309 static void
 310 mask_irq (unsigned int irq)
 311 {
 312         u32 low32;
 313         int rte_index;
 314         struct iosapic_rte_info *rte;
 315
 316         if (list_empty(&iosapic_intr_info[irq].rtes))
 317                 return;                 /* not an IOSAPIC interrupt! */
 318
 319         /* set only the mask bit */
 320         low32 = iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 321         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 322                 rte_index = rte->rte_index;
 323                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 324         }
 325 }
 326
 327 static void
 328 unmask_irq (unsigned int irq)
 329 {
 330         u32 low32;
 331         int rte_index;
 332         struct iosapic_rte_info *rte;
 333
 334         if (list_empty(&iosapic_intr_info[irq].rtes))
 335                 return;                 /* not an IOSAPIC interrupt! */
 336
 337         low32 = iosapic_intr_info[irq].low32 &= ~IOSAPIC_MASK;
 338         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 339                 rte_index = rte->rte_index;
 340                 iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 341         }
 342 }
 343
 344
 345 static void
 346 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 347 {
 348 #ifdef CONFIG_SMP
 349         u32 high32, low32;
 350         int dest, rte_index;
 351         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 352         struct iosapic_rte_info *rte;
 353         struct iosapic *iosapic;
 354
 355         irq &= (~IA64_IRQ_REDIRECTED);
 356
 357         /* IRQ migration across domain is not supported yet */
 358         cpus_and(mask, mask, irq_to_domain(irq));
 359         if (cpus_empty(mask))
 360                 return;
 361
 362         dest = cpu_physical_id(first_cpu(mask));
 363
 364         if (list_empty(&iosapic_intr_info[irq].rtes))
 365                 return;                 /* not an IOSAPIC interrupt */
 366
 367         set_irq_affinity_info(irq, dest, redir);
 368
 369         /* dest contains both id and eid */
 370         high32 = dest << IOSAPIC_DEST_SHIFT;
 371
 372         low32 = iosapic_intr_info[irq].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 373         if (redir)
 374                 /* change delivery mode to lowest priority */
 375                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 376         else
 377                 /* change delivery mode to fixed */
 378                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 379
 380         iosapic_intr_info[irq].low32 = low32;
 381         iosapic_intr_info[irq].dest = dest;
 382         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list) {
 383                 iosapic = rte->iosapic;
 384                 rte_index = rte->rte_index;
 385                 iosapic_write(iosapic, IOSAPIC_RTE_HIGH(rte_index), high32);
 386                 iosapic_write(iosapic, IOSAPIC_RTE_LOW(rte_index), low32);
 387         }
 388 #endif
 389 }
 390
 391 /*
 392  * Handlers for level-triggered interrupts.
 393  */
 394
 395 static unsigned int
 396 iosapic_startup_level_irq (unsigned int irq)
 397 {
 398         unmask_irq(irq);
 399         return 0;
 400 }
 401
 402 static void
 403 iosapic_end_level_irq (unsigned int irq)
 404 {
 405         ia64_vector vec = irq_to_vector(irq);
 406         struct iosapic_rte_info *rte;
 407
 408         move_native_irq(irq);
 409         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
 410                 iosapic_eoi(rte->iosapic->addr, vec);
 411 }
 412
 413 #define iosapic_shutdown_level_irq      mask_irq
 414 #define iosapic_enable_level_irq        unmask_irq
 415 #define iosapic_disable_level_irq       mask_irq
 416 #define iosapic_ack_level_irq           nop
 417
 418 struct irq_chip irq_type_iosapic_level = {
 419         .name =         "IO-SAPIC-level",
 420         .startup =      iosapic_startup_level_irq,
 421         .shutdown =     iosapic_shutdown_level_irq,
 422         .enable =       iosapic_enable_level_irq,
 423         .disable =      iosapic_disable_level_irq,
 424         .ack =          iosapic_ack_level_irq,
 425         .end =          iosapic_end_level_irq,
 426         .mask =         mask_irq,
 427         .unmask =       unmask_irq,
 428         .set_affinity = iosapic_set_affinity
 429 };
 430
 431 /*
 432  * Handlers for edge-triggered interrupts.
 433  */
 434
 435 static unsigned int
 436 iosapic_startup_edge_irq (unsigned int irq)
 437 {
 438         unmask_irq(irq);
 439         /*
 440          * IOSAPIC simply drops interrupts pended while the
 441          * corresponding pin was masked, so we can't know if an
 442          * interrupt is pending already.  Let's hope not...
 443          */
 444         return 0;
 445 }
 446
 447 static void
 448 iosapic_ack_edge_irq (unsigned int irq)
 449 {
 450         irq_desc_t *idesc = irq_desc + irq;
 451
 452         move_native_irq(irq);
 453         /*
 454          * Once we have recorded IRQ_PENDING already, we can mask the
 455          * interrupt for real. This prevents IRQ storms from unhandled
 456          * devices.
 457          */
 458         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 459             (IRQ_PENDING|IRQ_DISABLED))
 460                 mask_irq(irq);
 461 }
 462
 463 #define iosapic_enable_edge_irq         unmask_irq
 464 #define iosapic_disable_edge_irq        nop
 465 #define iosapic_end_edge_irq            nop
 466
 467 struct irq_chip irq_type_iosapic_edge = {
 468         .name =         "IO-SAPIC-edge",
 469         .startup =      iosapic_startup_edge_irq,
 470         .shutdown =     iosapic_disable_edge_irq,
 471         .enable =       iosapic_enable_edge_irq,
 472         .disable =      iosapic_disable_edge_irq,
 473         .ack =          iosapic_ack_edge_irq,
 474         .end =          iosapic_end_edge_irq,
 475         .mask =         mask_irq,
 476         .unmask =       unmask_irq,
 477         .set_affinity = iosapic_set_affinity
 478 };
 479
 480 unsigned int
 481 iosapic_version (char __iomem *addr)
 482 {
 483         /*
 484          * IOSAPIC Version Register return 32 bit structure like:
 485          * {
 486          *      unsigned int version   : 8;
 487          *      unsigned int reserved1 : 8;
 488          *      unsigned int max_redir : 8;
 489          *      unsigned int reserved2 : 8;
 490          * }
 491          */
 492         return __iosapic_read(addr, IOSAPIC_VERSION);
 493 }
 494
 495 static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
 496 {
 497         int i, irq = -ENOSPC, min_count = -1;
 498         struct iosapic_intr_info *info;
 499
 500         /*
 501          * shared vectors for edge-triggered interrupts are not
 502          * supported yet
 503          */
 504         if (trigger == IOSAPIC_EDGE)
 505                 return -EINVAL;
 506
 507         for (i = 0; i <= NR_IRQS; i++) {
 508                 info = &iosapic_intr_info[i];
 509                 if (info->trigger == trigger && info->polarity == pol &&
 510                     (info->dmode == IOSAPIC_FIXED ||
 511                      info->dmode == IOSAPIC_LOWEST_PRIORITY) &&
 512                     can_request_irq(i, IRQF_SHARED)) {
 513                         if (min_count == -1 || info->count < min_count) {
 514                                 irq = i;
 515                                 min_count = info->count;
 516                         }
 517                 }
 518         }
 519         return irq;
 520 }
 521
 522 /*
 523  * if the given vector is already owned by other,
 524  *  assign a new vector for the other and make the vector available
 525  */
 526 static void __init
 527 iosapic_reassign_vector (int irq)
 528 {
 529         int new_irq;
 530
 531         if (!list_empty(&iosapic_intr_info[irq].rtes)) {
 532                 new_irq = create_irq();
 533                 if (new_irq < 0)
 534                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 535                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 536                        irq_to_vector(irq), irq_to_vector(new_irq));
 537                 memcpy(&iosapic_intr_info[new_irq], &iosapic_intr_info[irq],
 538                        sizeof(struct iosapic_intr_info));
 539                 INIT_LIST_HEAD(&iosapic_intr_info[new_irq].rtes);
 540                 list_move(iosapic_intr_info[irq].rtes.next,
 541                           &iosapic_intr_info[new_irq].rtes);
 542                 memset(&iosapic_intr_info[irq], 0,
 543                        sizeof(struct iosapic_intr_info));
 544                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 545                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 546         }
 547 }
 548
 549 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 550 {
 551         int i;
 552         struct iosapic_rte_info *rte;
 553         int preallocated = 0;
 554
 555         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 556                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 557                                     NR_PREALLOCATE_RTE_ENTRIES);
 558                 if (!rte)
 559                         return NULL;
 560                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 561                         list_add(&rte->rte_list, &free_rte_list);
 562         }
 563
 564         if (!list_empty(&free_rte_list)) {
 565                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 566                                  rte_list);
 567                 list_del(&rte->rte_list);
 568                 preallocated++;
 569         } else {
 570                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 571                 if (!rte)
 572                         return NULL;
 573         }
 574
 575         memset(rte, 0, sizeof(struct iosapic_rte_info));
 576         if (preallocated)
 577                 rte->flags |= RTE_PREALLOCATED;
 578
 579         return rte;
 580 }
 581
 582 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 583 {
 584         if (rte->flags & RTE_PREALLOCATED)
 585                 list_add_tail(&rte->rte_list, &free_rte_list);
 586         else
 587                 kfree(rte);
 588 }
 589
 590 static inline int irq_is_shared (int irq)
 591 {
 592         return (iosapic_intr_info[irq].count > 1);
 593 }
 594
 595 static int
 596 register_intr (unsigned int gsi, int irq, unsigned char delivery,
 597                unsigned long polarity, unsigned long trigger)
 598 {
 599         irq_desc_t *idesc;
 600         struct hw_interrupt_type *irq_type;
 601         int index;
 602         struct iosapic_rte_info *rte;
 603
 604         index = find_iosapic(gsi);
 605         if (index < 0) {
 606                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 607                        __FUNCTION__, gsi);
 608                 return -ENODEV;
 609         }
 610
 611         rte = find_rte(irq, gsi);
 612         if (!rte) {
 613                 rte = iosapic_alloc_rte();
 614                 if (!rte) {
 615                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 616                                __FUNCTION__);
 617                         return -ENOMEM;
 618                 }
 619
 620                 rte->iosapic    = &iosapic_lists[index];
 621                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
 622                 rte->refcnt++;
 623                 list_add_tail(&rte->rte_list, &iosapic_intr_info[irq].rtes);
 624                 iosapic_intr_info[irq].count++;
 625                 iosapic_lists[index].rtes_inuse++;
 626         }
 627         else if (rte->refcnt == NO_REF_RTE) {
 628                 struct iosapic_intr_info *info = &iosapic_intr_info[irq];
 629                 if (info->count > 0 &&
 630                     (info->trigger != trigger || info->polarity != polarity)){
 631                         printk (KERN_WARNING
 632                                 "%s: cannot override the interrupt\n",
 633                                 __FUNCTION__);
 634                         return -EINVAL;
 635                 }
 636                 rte->refcnt++;
 637                 iosapic_intr_info[irq].count++;
 638                 iosapic_lists[index].rtes_inuse++;
 639         }
 640
 641         iosapic_intr_info[irq].polarity = polarity;
 642         iosapic_intr_info[irq].dmode    = delivery;
 643         iosapic_intr_info[irq].trigger  = trigger;
 644
 645         if (trigger == IOSAPIC_EDGE)
 646                 irq_type = &irq_type_iosapic_edge;
 647         else
 648                 irq_type = &irq_type_iosapic_level;
 649
 650         idesc = irq_desc + irq;
 651         if (idesc->chip != irq_type) {
 652                 if (idesc->chip != &no_irq_type)
 653                         printk(KERN_WARNING
 654                                "%s: changing vector %d from %s to %s\n",
 655                                __FUNCTION__, irq_to_vector(irq),
 656                                idesc->chip->name, irq_type->name);
 657                 idesc->chip = irq_type;
 658         }
 659         return 0;
 660 }
 661
 662 static unsigned int
 663 get_target_cpu (unsigned int gsi, int irq)
 664 {
 665 #ifdef CONFIG_SMP
 666         static int cpu = -1;
 667         extern int cpe_vector;
 668         cpumask_t domain = irq_to_domain(irq);
 669
 670         /*
 671          * In case of vector shared by multiple RTEs, all RTEs that
 672          * share the vector need to use the same destination CPU.
 673          */
 674         if (!list_empty(&iosapic_intr_info[irq].rtes))
 675                 return iosapic_intr_info[irq].dest;
 676
 677         /*
 678          * If the platform supports redirection via XTP, let it
 679          * distribute interrupts.
 680          */
 681         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 682                 return cpu_physical_id(smp_processor_id());
 683
 684         /*
 685          * Some interrupts (ACPI SCI, for instance) are registered
 686          * before the BSP is marked as online.
 687          */
 688         if (!cpu_online(smp_processor_id()))
 689                 return cpu_physical_id(smp_processor_id());
 690
 691 #ifdef CONFIG_ACPI
 692         if (cpe_vector > 0 && irq_to_vector(irq) == IA64_CPEP_VECTOR)
 693                 return get_cpei_target_cpu();
 694 #endif
 695
 696 #ifdef CONFIG_NUMA
 697         {
 698                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 699                 cpumask_t cpu_mask;
 700
 701                 iosapic_index = find_iosapic(gsi);
 702                 if (iosapic_index < 0 ||
 703                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 704                         goto skip_numa_setup;
 705
 706                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 707                 cpus_and(cpu_mask, cpu_mask, domain);
 708                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 709                         if (!cpu_online(numa_cpu))
 710                                 cpu_clear(numa_cpu, cpu_mask);
 711                 }
 712
 713                 num_cpus = cpus_weight(cpu_mask);
 714
 715                 if (!num_cpus)
 716                         goto skip_numa_setup;
 717
 718                 /* Use irq assignment to distribute across cpus in node */
 719                 cpu_index = irq % num_cpus;
 720
 721                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 722                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 723
 724                 if (numa_cpu != NR_CPUS)
 725                         return cpu_physical_id(numa_cpu);
 726         }
 727 skip_numa_setup:
 728 #endif
 729         /*
 730          * Otherwise, round-robin interrupt vectors across all the
 731          * processors.  (It'd be nice if we could be smarter in the
 732          * case of NUMA.)
 733          */
 734         do {
 735                 if (++cpu >= NR_CPUS)
 736                         cpu = 0;
 737         } while (!cpu_online(cpu) || !cpu_isset(cpu, domain));
 738
 739         return cpu_physical_id(cpu);
 740 #else  /* CONFIG_SMP */
 741         return cpu_physical_id(smp_processor_id());
 742 #endif
 743 }
 744
 745 /*
 746  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 747  * methods.  This provides an interface to register those interrupts and
 748  * program the IOSAPIC RTE.
 749  */
 750 int
 751 iosapic_register_intr (unsigned int gsi,
 752                        unsigned long polarity, unsigned long trigger)
 753 {
 754         int irq, mask = 1, err;
 755         unsigned int dest;
 756         unsigned long flags;
 757         struct iosapic_rte_info *rte;
 758         u32 low32;
 759
 760         /*
 761          * If this GSI has already been registered (i.e., it's a
 762          * shared interrupt, or we lost a race to register it),
 763          * don't touch the RTE.
 764          */
 765         spin_lock_irqsave(&iosapic_lock, flags);
 766         irq = __gsi_to_irq(gsi);
 767         if (irq > 0) {
 768                 rte = find_rte(irq, gsi);
 769                 if(iosapic_intr_info[irq].count == 0) {
 770                         assign_irq_vector(irq);
 771                         dynamic_irq_init(irq);
 772                 } else if (rte->refcnt != NO_REF_RTE) {
 773                         rte->refcnt++;
 774                         goto unlock_iosapic_lock;
 775                 }
 776         } else
 777                 irq = create_irq();
 778
 779         /* If vector is running out, we try to find a sharable vector */
 780         if (irq < 0) {
 781                 irq = iosapic_find_sharable_irq(trigger, polarity);
 782                 if (irq < 0)
 783                         goto unlock_iosapic_lock;
 784         }
 785
 786         spin_lock(&irq_desc[irq].lock);
 787         dest = get_target_cpu(gsi, irq);
 788         err = register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY,
 789                             polarity, trigger);
 790         if (err < 0) {
 791                 irq = err;
 792                 goto unlock_all;
 793         }
 794
 795         /*
 796          * If the vector is shared and already unmasked for other
 797          * interrupt sources, don't mask it.
 798          */
 799         low32 = iosapic_intr_info[irq].low32;
 800         if (irq_is_shared(irq) && !(low32 & IOSAPIC_MASK))
 801                 mask = 0;
 802         set_rte(gsi, irq, dest, mask);
 803
 804         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 805                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 806                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 807                cpu_logical_id(dest), dest, irq_to_vector(irq));
 808  unlock_all:
 809         spin_unlock(&irq_desc[irq].lock);
 810  unlock_iosapic_lock:
 811         spin_unlock_irqrestore(&iosapic_lock, flags);
 812         return irq;
 813 }
 814
 815 void
 816 iosapic_unregister_intr (unsigned int gsi)
 817 {
 818         unsigned long flags;
 819         int irq, index;
 820         irq_desc_t *idesc;
 821         u32 low32;
 822         unsigned long trigger, polarity;
 823         unsigned int dest;
 824         struct iosapic_rte_info *rte;
 825
 826         /*
 827          * If the irq associated with the gsi is not found,
 828          * iosapic_unregister_intr() is unbalanced. We need to check
 829          * this again after getting locks.
 830          */
 831         irq = gsi_to_irq(gsi);
 832         if (irq < 0) {
 833                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 834                        gsi);
 835                 WARN_ON(1);
 836                 return;
 837         }
 838
 839         spin_lock_irqsave(&iosapic_lock, flags);
 840         if ((rte = find_rte(irq, gsi)) == NULL) {
 841                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 842                        gsi);
 843                 WARN_ON(1);
 844                 goto out;
 845         }
 846
 847         if (--rte->refcnt > 0)
 848                 goto out;
 849
 850         idesc = irq_desc + irq;
 851         rte->refcnt = NO_REF_RTE;
 852
 853         /* Mask the interrupt */
 854         low32 = iosapic_intr_info[irq].low32 | IOSAPIC_MASK;
 855         iosapic_write(rte->iosapic, IOSAPIC_RTE_LOW(rte->rte_index), low32);
 856
 857         iosapic_intr_info[irq].count--;
 858         index = find_iosapic(gsi);
 859         iosapic_lists[index].rtes_inuse--;
 860         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 861
 862         trigger  = iosapic_intr_info[irq].trigger;
 863         polarity = iosapic_intr_info[irq].polarity;
 864         dest     = iosapic_intr_info[irq].dest;
 865         printk(KERN_INFO
 866                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 867                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 868                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 869                cpu_logical_id(dest), dest, irq_to_vector(irq));
 870
 871         if (iosapic_intr_info[irq].count == 0) {
 872 #ifdef CONFIG_SMP
 873                 /* Clear affinity */
 874                 cpus_setall(idesc->affinity);
 875 #endif
 876                 /* Clear the interrupt information */
 877                 iosapic_intr_info[irq].dest = 0;
 878                 iosapic_intr_info[irq].dmode = 0;
 879                 iosapic_intr_info[irq].polarity = 0;
 880                 iosapic_intr_info[irq].trigger = 0;
 881                 iosapic_intr_info[irq].low32 |= IOSAPIC_MASK;
 882
 883                 /* Destroy and reserve IRQ */
 884                 destroy_and_reserve_irq(irq);
 885         }
 886  out:
 887         spin_unlock_irqrestore(&iosapic_lock, flags);
 888 }
 889
 890 /*
 891  * ACPI calls this when it finds an entry for a platform interrupt.
 892  */
 893 int __init
 894 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 895                                 int iosapic_vector, u16 eid, u16 id,
 896                                 unsigned long polarity, unsigned long trigger)
 897 {
 898         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 899         unsigned char delivery;
 900         int irq, vector, mask = 0;
 901         unsigned int dest = ((id << 8) | eid) & 0xffff;
 902
 903         switch (int_type) {
 904               case ACPI_INTERRUPT_PMI:
 905                 irq = vector = iosapic_vector;
 906                 bind_irq_vector(irq, vector, CPU_MASK_ALL);
 907                 /*
 908                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 909                  * we need to make sure the vector is available
 910                  */
 911                 iosapic_reassign_vector(irq);
 912                 delivery = IOSAPIC_PMI;
 913                 break;
 914               case ACPI_INTERRUPT_INIT:
 915                 irq = create_irq();
 916                 if (irq < 0)
 917                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 918                 vector = irq_to_vector(irq);
 919                 delivery = IOSAPIC_INIT;
 920                 break;
 921               case ACPI_INTERRUPT_CPEI:
 922                 irq = vector = IA64_CPE_VECTOR;
 923                 BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
 924                 delivery = IOSAPIC_LOWEST_PRIORITY;
 925                 mask = 1;
 926                 break;
 927               default:
 928                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
 929                        int_type);
 930                 return -1;
 931         }
 932
 933         register_intr(gsi, irq, delivery, polarity, trigger);
 934
 935         printk(KERN_INFO
 936                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
 937                " vector %d\n",
 938                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 939                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 940                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 941                cpu_logical_id(dest), dest, vector);
 942
 943         set_rte(gsi, irq, dest, mask);
 944         return vector;
 945 }
 946
 947 /*
 948  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 949  */
 950 void __devinit
 951 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 952                           unsigned long polarity,
 953                           unsigned long trigger)
 954 {
 955         int vector, irq;
 956         unsigned int dest = cpu_physical_id(smp_processor_id());
 957
 958         irq = vector = isa_irq_to_vector(isa_irq);
 959         BUG_ON(bind_irq_vector(irq, vector, CPU_MASK_ALL));
 960         register_intr(gsi, irq, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
 961
 962         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 963             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 964             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 965             cpu_logical_id(dest), dest, vector);
 966
 967         set_rte(gsi, irq, dest, 1);
 968 }
 969
 970 void __init
 971 iosapic_system_init (int system_pcat_compat)
 972 {
 973         int irq;
 974
 975         for (irq = 0; irq < NR_IRQS; ++irq) {
 976                 iosapic_intr_info[irq].low32 = IOSAPIC_MASK;
 977                 /* mark as unused */
 978                 INIT_LIST_HEAD(&iosapic_intr_info[irq].rtes);
 979
 980                 iosapic_intr_info[irq].count = 0;
 981         }
 982
 983         pcat_compat = system_pcat_compat;
 984         if (pcat_compat) {
 985                 /*
 986                  * Disable the compatibility mode interrupts (8259 style),
 987                  * needs IN/OUT support enabled.
 988                  */
 989                 printk(KERN_INFO
 990                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
 991                        __FUNCTION__);
 992                 outb(0xff, 0xA1);
 993                 outb(0xff, 0x21);
 994         }
 995 }
 996
 997 static inline int
 998 iosapic_alloc (void)
 999 {
1000         int index;
1001
1002         for (index = 0; index < NR_IOSAPICS; index++)
1003                 if (!iosapic_lists[index].addr)
1004                         return index;
1005
1006         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
1007         return -1;
1008 }
1009
1010 static inline void
1011 iosapic_free (int index)
1012 {
1013         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1014 }
1015
1016 static inline int
1017 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1018 {
1019         int index;
1020         unsigned int gsi_end, base, end;
1021
1022         /* check gsi range */
1023         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1024         for (index = 0; index < NR_IOSAPICS; index++) {
1025                 if (!iosapic_lists[index].addr)
1026                         continue;
1027
1028                 base = iosapic_lists[index].gsi_base;
1029                 end  = base + iosapic_lists[index].num_rte - 1;
1030
1031                 if (gsi_end < base || end < gsi_base)
1032                         continue; /* OK */
1033
1034                 return -EBUSY;
1035         }
1036         return 0;
1037 }
1038
1039 int __devinit
1040 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1041 {
1042         int num_rte, err, index;
1043         unsigned int isa_irq, ver;
1044         char __iomem *addr;
1045         unsigned long flags;
1046
1047         spin_lock_irqsave(&iosapic_lock, flags);
1048         index = find_iosapic(gsi_base);
1049         if (index >= 0) {
1050                 spin_unlock_irqrestore(&iosapic_lock, flags);
1051                 return -EBUSY;
1052         }
1053
1054         addr = ioremap(phys_addr, 0);
1055         ver = iosapic_version(addr);
1056         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1057                 iounmap(addr);
1058                 spin_unlock_irqrestore(&iosapic_lock, flags);
1059                 return err;
1060         }
1061
1062         /*
1063          * The MAX_REDIR register holds the highest input pin number
1064          * (starting from 0).  We add 1 so that we can use it for
1065          * number of pins (= RTEs)
1066          */
1067         num_rte = ((ver >> 16) & 0xff) + 1;
1068
1069         index = iosapic_alloc();
1070         iosapic_lists[index].addr = addr;
1071         iosapic_lists[index].gsi_base = gsi_base;
1072         iosapic_lists[index].num_rte = num_rte;
1073 #ifdef CONFIG_NUMA
1074         iosapic_lists[index].node = MAX_NUMNODES;
1075 #endif
1076         spin_lock_init(&iosapic_lists[index].lock);
1077         spin_unlock_irqrestore(&iosapic_lock, flags);
1078
1079         if ((gsi_base == 0) && pcat_compat) {
1080                 /*
1081                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1082                  * these may get reprogrammed later on with data from the ACPI
1083                  * Interrupt Source Override table.
1084                  */
1085                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1086                         iosapic_override_isa_irq(isa_irq, isa_irq,
1087                                                  IOSAPIC_POL_HIGH,
1088                                                  IOSAPIC_EDGE);
1089         }
1090         return 0;
1091 }
1092
1093 #ifdef CONFIG_HOTPLUG
1094 int
1095 iosapic_remove (unsigned int gsi_base)
1096 {
1097         int index, err = 0;
1098         unsigned long flags;
1099
1100         spin_lock_irqsave(&iosapic_lock, flags);
1101         index = find_iosapic(gsi_base);
1102         if (index < 0) {
1103                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1104                        __FUNCTION__, gsi_base);
1105                 goto out;
1106         }
1107
1108         if (iosapic_lists[index].rtes_inuse) {
1109                 err = -EBUSY;
1110                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1111                        __FUNCTION__, gsi_base);
1112                 goto out;
1113         }
1114
1115         iounmap(iosapic_lists[index].addr);
1116         iosapic_free(index);
1117  out:
1118         spin_unlock_irqrestore(&iosapic_lock, flags);
1119         return err;
1120 }
1121 #endif /* CONFIG_HOTPLUG */
1122
1123 #ifdef CONFIG_NUMA
1124 void __devinit
1125 map_iosapic_to_node(unsigned int gsi_base, int node)
1126 {
1127         int index;
1128
1129         index = find_iosapic(gsi_base);
1130         if (index < 0) {
1131                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1132                        __FUNCTION__, gsi_base);
1133                 return;
1134         }
1135         iosapic_lists[index].node = node;
1136         return;
1137 }
1138 #endif
1139
1140 static int __init iosapic_enable_kmalloc (void)
1141 {
1142         iosapic_kmalloc_ok = 1;
1143         return 0;
1144 }
1145 core_initcall (iosapic_enable_kmalloc);