git.oblomov.eu Git - linux-2.6/blob - arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/config.h>
  29 #include <linux/smp_lock.h>
  30 #include <linux/mc146818rtc.h>
  31 #include <linux/acpi.h>
  32 #include <linux/sysdev.h>
  33 #ifdef CONFIG_ACPI
  34 #include <acpi/acpi_bus.h>
  35 #endif
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/proto.h>
  41 #include <asm/mach_apic.h>
  42 #include <asm/acpi.h>
  43 #include <asm/dma.h>
  44
  45 #define __apicdebuginit  __init
  46
  47 int sis_apic_bug; /* not actually supported, dummy for compile */
  48
  49 static int no_timer_check;
  50
  51 int disable_timer_pin_1 __initdata;
  52
  53 int timer_over_8254 __initdata = 0;
  54
  55 /* Where if anywhere is the i8259 connect in external int mode */
  56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
  57
  58 static DEFINE_SPINLOCK(ioapic_lock);
  59
  60 /*
  61  * # of IRQ routing registers
  62  */
  63 int nr_ioapic_registers[MAX_IO_APICS];
  64
  65 /*
  66  * Rough estimation of how many shared IRQs there are, can
  67  * be changed anytime.
  68  */
  69 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
  70 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  71
  72 /*
  73  * This is performance-critical, we want to do it O(1)
  74  *
  75  * the indexing order of this array favors 1:1 mappings
  76  * between pins and IRQs.
  77  */
  78
  79 static struct irq_pin_list {
  80         short apic, pin, next;
  81 } irq_2_pin[PIN_MAP_SIZE];
  82
  83 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  84 #ifdef CONFIG_PCI_MSI
  85 #define vector_to_irq(vector)   \
  86         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  87 #else
  88 #define vector_to_irq(vector)   (vector)
  89 #endif
  90
  91 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  92                                                                         \
  93 {                                                                       \
  94         int pin;                                                        \
  95         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  96                                                                         \
  97         BUG_ON(irq >= NR_IRQS);                                         \
  98         for (;;) {                                                      \
  99                 unsigned int reg;                                       \
 100                 pin = entry->pin;                                       \
 101                 if (pin == -1)                                          \
 102                         break;                                          \
 103                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 104                 reg ACTION;                                             \
 105                 io_apic_modify(entry->apic, reg);                       \
 106                 if (!entry->next)                                       \
 107                         break;                                          \
 108                 entry = irq_2_pin + entry->next;                        \
 109         }                                                               \
 110         FINAL;                                                          \
 111 }
 112
 113 #ifdef CONFIG_SMP
 114 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 115 {
 116         unsigned long flags;
 117         unsigned int dest;
 118         cpumask_t tmp;
 119
 120         cpus_and(tmp, mask, cpu_online_map);
 121         if (cpus_empty(tmp))
 122                 tmp = TARGET_CPUS;
 123
 124         cpus_and(mask, tmp, CPU_MASK_ALL);
 125
 126         dest = cpu_mask_to_apicid(mask);
 127
 128         /*
 129          * Only the high 8 bits are valid.
 130          */
 131         dest = SET_APIC_LOGICAL_ID(dest);
 132
 133         spin_lock_irqsave(&ioapic_lock, flags);
 134         __DO_ACTION(1, = dest, )
 135         set_irq_info(irq, mask);
 136         spin_unlock_irqrestore(&ioapic_lock, flags);
 137 }
 138 #endif
 139
 140 static u8 gsi_2_irq[NR_IRQ_VECTORS] = { [0 ... NR_IRQ_VECTORS-1] = 0xFF };
 141
 142 /*
 143  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 144  * shared ISA-space IRQs, so we have to support them. We are super
 145  * fast in the common case, and fast for shared ISA-space IRQs.
 146  */
 147 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 148 {
 149         static int first_free_entry = NR_IRQS;
 150         struct irq_pin_list *entry = irq_2_pin + irq;
 151
 152         BUG_ON(irq >= NR_IRQS);
 153         while (entry->next)
 154                 entry = irq_2_pin + entry->next;
 155
 156         if (entry->pin != -1) {
 157                 entry->next = first_free_entry;
 158                 entry = irq_2_pin + entry->next;
 159                 if (++first_free_entry >= PIN_MAP_SIZE)
 160                         panic("io_apic.c: ran out of irq_2_pin entries!");
 161         }
 162         entry->apic = apic;
 163         entry->pin = pin;
 164 }
 165
 166
 167 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 168                                                                         \
 169         static void name##_IO_APIC_irq (unsigned int irq)               \
 170         __DO_ACTION(R, ACTION, FINAL)
 171
 172 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 173                                                 /* mask = 1 */
 174 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 175                                                 /* mask = 0 */
 176
 177 static void mask_IO_APIC_irq (unsigned int irq)
 178 {
 179         unsigned long flags;
 180
 181         spin_lock_irqsave(&ioapic_lock, flags);
 182         __mask_IO_APIC_irq(irq);
 183         spin_unlock_irqrestore(&ioapic_lock, flags);
 184 }
 185
 186 static void unmask_IO_APIC_irq (unsigned int irq)
 187 {
 188         unsigned long flags;
 189
 190         spin_lock_irqsave(&ioapic_lock, flags);
 191         __unmask_IO_APIC_irq(irq);
 192         spin_unlock_irqrestore(&ioapic_lock, flags);
 193 }
 194
 195 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 196 {
 197         struct IO_APIC_route_entry entry;
 198         unsigned long flags;
 199
 200         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 201         spin_lock_irqsave(&ioapic_lock, flags);
 202         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 203         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 204         spin_unlock_irqrestore(&ioapic_lock, flags);
 205         if (entry.delivery_mode == dest_SMI)
 206                 return;
 207         /*
 208          * Disable it in the IO-APIC irq-routing table:
 209          */
 210         memset(&entry, 0, sizeof(entry));
 211         entry.mask = 1;
 212         spin_lock_irqsave(&ioapic_lock, flags);
 213         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 214         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 215         spin_unlock_irqrestore(&ioapic_lock, flags);
 216 }
 217
 218 static void clear_IO_APIC (void)
 219 {
 220         int apic, pin;
 221
 222         for (apic = 0; apic < nr_ioapics; apic++)
 223                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 224                         clear_IO_APIC_pin(apic, pin);
 225 }
 226
 227 /*
 228  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 229  * specific CPU-side IRQs.
 230  */
 231
 232 #define MAX_PIRQS 8
 233 static int pirq_entries [MAX_PIRQS];
 234 static int pirqs_enabled;
 235 int skip_ioapic_setup;
 236 int ioapic_force;
 237
 238 /* dummy parsing: see setup.c */
 239
 240 static int __init disable_ioapic_setup(char *str)
 241 {
 242         skip_ioapic_setup = 1;
 243         return 1;
 244 }
 245
 246 static int __init enable_ioapic_setup(char *str)
 247 {
 248         ioapic_force = 1;
 249         skip_ioapic_setup = 0;
 250         return 1;
 251 }
 252
 253 __setup("noapic", disable_ioapic_setup);
 254 __setup("apic", enable_ioapic_setup);
 255
 256 static int __init setup_disable_8254_timer(char *s)
 257 {
 258         timer_over_8254 = -1;
 259         return 1;
 260 }
 261 static int __init setup_enable_8254_timer(char *s)
 262 {
 263         timer_over_8254 = 2;
 264         return 1;
 265 }
 266
 267 __setup("disable_8254_timer", setup_disable_8254_timer);
 268 __setup("enable_8254_timer", setup_enable_8254_timer);
 269
 270 #include <asm/pci-direct.h>
 271 #include <linux/pci_ids.h>
 272 #include <linux/pci.h>
 273
 274 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 275    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 276    Use pci direct infrastructure because this runs before the PCI subsystem.
 277
 278    Can be overwritten with "apic"
 279
 280    And another hack to disable the IOMMU on VIA chipsets.
 281
 282    ... and others. Really should move this somewhere else.
 283
 284    Kludge-O-Rama. */
 285 void __init check_ioapic(void)
 286 {
 287         int num,slot,func;
 288         /* Poor man's PCI discovery */
 289         for (num = 0; num < 32; num++) {
 290                 for (slot = 0; slot < 32; slot++) {
 291                         for (func = 0; func < 8; func++) {
 292                                 u32 class;
 293                                 u32 vendor;
 294                                 u8 type;
 295                                 class = read_pci_config(num,slot,func,
 296                                                         PCI_CLASS_REVISION);
 297                                 if (class == 0xffffffff)
 298                                         break;
 299
 300                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 301                                         continue;
 302
 303                                 vendor = read_pci_config(num, slot, func,
 304                                                          PCI_VENDOR_ID);
 305                                 vendor &= 0xffff;
 306                                 switch (vendor) {
 307                                 case PCI_VENDOR_ID_VIA:
 308 #ifdef CONFIG_GART_IOMMU
 309                                         if ((end_pfn > MAX_DMA32_PFN ||
 310                                              force_iommu) &&
 311                                             !iommu_aperture_allowed) {
 312                                                 printk(KERN_INFO
 313     "Looks like a VIA chipset. Disabling IOMMU. Override with \"iommu=allowed\"\n");
 314                                                 iommu_aperture_disabled = 1;
 315                                         }
 316 #endif
 317                                         return;
 318                                 case PCI_VENDOR_ID_NVIDIA:
 319 #ifdef CONFIG_ACPI
 320                                         /* All timer overrides on Nvidia
 321                                            seem to be wrong. Skip them. */
 322                                         acpi_skip_timer_override = 1;
 323                                         printk(KERN_INFO
 324              "Nvidia board detected. Ignoring ACPI timer override.\n");
 325 #endif
 326                                         /* RED-PEN skip them on mptables too? */
 327                                         return;
 328
 329                                 /* This should be actually default, but
 330                                    for 2.6.16 let's do it for ATI only where
 331                                    it's really needed. */
 332                                 case PCI_VENDOR_ID_ATI:
 333                                         if (timer_over_8254 == 1) {
 334                                                 timer_over_8254 = 0;
 335                                         printk(KERN_INFO
 336                 "ATI board detected. Disabling timer routing over 8254.\n");
 337                                         }
 338                                         return;
 339                                 }
 340
 341
 342                                 /* No multi-function device? */
 343                                 type = read_pci_config_byte(num,slot,func,
 344                                                             PCI_HEADER_TYPE);
 345                                 if (!(type & 0x80))
 346                                         break;
 347                         }
 348                 }
 349         }
 350 }
 351
 352 static int __init ioapic_pirq_setup(char *str)
 353 {
 354         int i, max;
 355         int ints[MAX_PIRQS+1];
 356
 357         get_options(str, ARRAY_SIZE(ints), ints);
 358
 359         for (i = 0; i < MAX_PIRQS; i++)
 360                 pirq_entries[i] = -1;
 361
 362         pirqs_enabled = 1;
 363         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 364         max = MAX_PIRQS;
 365         if (ints[0] < MAX_PIRQS)
 366                 max = ints[0];
 367
 368         for (i = 0; i < max; i++) {
 369                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 370                 /*
 371                  * PIRQs are mapped upside down, usually.
 372                  */
 373                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 374         }
 375         return 1;
 376 }
 377
 378 __setup("pirq=", ioapic_pirq_setup);
 379
 380 /*
 381  * Find the IRQ entry number of a certain pin.
 382  */
 383 static int find_irq_entry(int apic, int pin, int type)
 384 {
 385         int i;
 386
 387         for (i = 0; i < mp_irq_entries; i++)
 388                 if (mp_irqs[i].mpc_irqtype == type &&
 389                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 390                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 391                     mp_irqs[i].mpc_dstirq == pin)
 392                         return i;
 393
 394         return -1;
 395 }
 396
 397 /*
 398  * Find the pin to which IRQ[irq] (ISA) is connected
 399  */
 400 static int __init find_isa_irq_pin(int irq, int type)
 401 {
 402         int i;
 403
 404         for (i = 0; i < mp_irq_entries; i++) {
 405                 int lbus = mp_irqs[i].mpc_srcbus;
 406
 407                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 408                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 409                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 410                     (mp_irqs[i].mpc_irqtype == type) &&
 411                     (mp_irqs[i].mpc_srcbusirq == irq))
 412
 413                         return mp_irqs[i].mpc_dstirq;
 414         }
 415         return -1;
 416 }
 417
 418 static int __init find_isa_irq_apic(int irq, int type)
 419 {
 420         int i;
 421
 422         for (i = 0; i < mp_irq_entries; i++) {
 423                 int lbus = mp_irqs[i].mpc_srcbus;
 424
 425                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 426                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 427                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 428                     (mp_irqs[i].mpc_irqtype == type) &&
 429                     (mp_irqs[i].mpc_srcbusirq == irq))
 430                         break;
 431         }
 432         if (i < mp_irq_entries) {
 433                 int apic;
 434                 for(apic = 0; apic < nr_ioapics; apic++) {
 435                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
 436                                 return apic;
 437                 }
 438         }
 439
 440         return -1;
 441 }
 442
 443 /*
 444  * Find a specific PCI IRQ entry.
 445  * Not an __init, possibly needed by modules
 446  */
 447 static int pin_2_irq(int idx, int apic, int pin);
 448
 449 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 450 {
 451         int apic, i, best_guess = -1;
 452
 453         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 454                 bus, slot, pin);
 455         if (mp_bus_id_to_pci_bus[bus] == -1) {
 456                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 457                 return -1;
 458         }
 459         for (i = 0; i < mp_irq_entries; i++) {
 460                 int lbus = mp_irqs[i].mpc_srcbus;
 461
 462                 for (apic = 0; apic < nr_ioapics; apic++)
 463                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 464                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 465                                 break;
 466
 467                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 468                     !mp_irqs[i].mpc_irqtype &&
 469                     (bus == lbus) &&
 470                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 471                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 472
 473                         if (!(apic || IO_APIC_IRQ(irq)))
 474                                 continue;
 475
 476                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 477                                 return irq;
 478                         /*
 479                          * Use the first all-but-pin matching entry as a
 480                          * best-guess fuzzy result for broken mptables.
 481                          */
 482                         if (best_guess < 0)
 483                                 best_guess = irq;
 484                 }
 485         }
 486         BUG_ON(best_guess >= NR_IRQS);
 487         return best_guess;
 488 }
 489
 490 /*
 491  * EISA Edge/Level control register, ELCR
 492  */
 493 static int EISA_ELCR(unsigned int irq)
 494 {
 495         if (irq < 16) {
 496                 unsigned int port = 0x4d0 + (irq >> 3);
 497                 return (inb(port) >> (irq & 7)) & 1;
 498         }
 499         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 500         return 0;
 501 }
 502
 503 /* EISA interrupts are always polarity zero and can be edge or level
 504  * trigger depending on the ELCR value.  If an interrupt is listed as
 505  * EISA conforming in the MP table, that means its trigger type must
 506  * be read in from the ELCR */
 507
 508 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 509 #define default_EISA_polarity(idx)      (0)
 510
 511 /* ISA interrupts are always polarity zero edge triggered,
 512  * when listed as conforming in the MP table. */
 513
 514 #define default_ISA_trigger(idx)        (0)
 515 #define default_ISA_polarity(idx)       (0)
 516
 517 /* PCI interrupts are always polarity one level triggered,
 518  * when listed as conforming in the MP table. */
 519
 520 #define default_PCI_trigger(idx)        (1)
 521 #define default_PCI_polarity(idx)       (1)
 522
 523 /* MCA interrupts are always polarity zero level triggered,
 524  * when listed as conforming in the MP table. */
 525
 526 #define default_MCA_trigger(idx)        (1)
 527 #define default_MCA_polarity(idx)       (0)
 528
 529 static int __init MPBIOS_polarity(int idx)
 530 {
 531         int bus = mp_irqs[idx].mpc_srcbus;
 532         int polarity;
 533
 534         /*
 535          * Determine IRQ line polarity (high active or low active):
 536          */
 537         switch (mp_irqs[idx].mpc_irqflag & 3)
 538         {
 539                 case 0: /* conforms, ie. bus-type dependent polarity */
 540                 {
 541                         switch (mp_bus_id_to_type[bus])
 542                         {
 543                                 case MP_BUS_ISA: /* ISA pin */
 544                                 {
 545                                         polarity = default_ISA_polarity(idx);
 546                                         break;
 547                                 }
 548                                 case MP_BUS_EISA: /* EISA pin */
 549                                 {
 550                                         polarity = default_EISA_polarity(idx);
 551                                         break;
 552                                 }
 553                                 case MP_BUS_PCI: /* PCI pin */
 554                                 {
 555                                         polarity = default_PCI_polarity(idx);
 556                                         break;
 557                                 }
 558                                 case MP_BUS_MCA: /* MCA pin */
 559                                 {
 560                                         polarity = default_MCA_polarity(idx);
 561                                         break;
 562                                 }
 563                                 default:
 564                                 {
 565                                         printk(KERN_WARNING "broken BIOS!!\n");
 566                                         polarity = 1;
 567                                         break;
 568                                 }
 569                         }
 570                         break;
 571                 }
 572                 case 1: /* high active */
 573                 {
 574                         polarity = 0;
 575                         break;
 576                 }
 577                 case 2: /* reserved */
 578                 {
 579                         printk(KERN_WARNING "broken BIOS!!\n");
 580                         polarity = 1;
 581                         break;
 582                 }
 583                 case 3: /* low active */
 584                 {
 585                         polarity = 1;
 586                         break;
 587                 }
 588                 default: /* invalid */
 589                 {
 590                         printk(KERN_WARNING "broken BIOS!!\n");
 591                         polarity = 1;
 592                         break;
 593                 }
 594         }
 595         return polarity;
 596 }
 597
 598 static int MPBIOS_trigger(int idx)
 599 {
 600         int bus = mp_irqs[idx].mpc_srcbus;
 601         int trigger;
 602
 603         /*
 604          * Determine IRQ trigger mode (edge or level sensitive):
 605          */
 606         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 607         {
 608                 case 0: /* conforms, ie. bus-type dependent */
 609                 {
 610                         switch (mp_bus_id_to_type[bus])
 611                         {
 612                                 case MP_BUS_ISA: /* ISA pin */
 613                                 {
 614                                         trigger = default_ISA_trigger(idx);
 615                                         break;
 616                                 }
 617                                 case MP_BUS_EISA: /* EISA pin */
 618                                 {
 619                                         trigger = default_EISA_trigger(idx);
 620                                         break;
 621                                 }
 622                                 case MP_BUS_PCI: /* PCI pin */
 623                                 {
 624                                         trigger = default_PCI_trigger(idx);
 625                                         break;
 626                                 }
 627                                 case MP_BUS_MCA: /* MCA pin */
 628                                 {
 629                                         trigger = default_MCA_trigger(idx);
 630                                         break;
 631                                 }
 632                                 default:
 633                                 {
 634                                         printk(KERN_WARNING "broken BIOS!!\n");
 635                                         trigger = 1;
 636                                         break;
 637                                 }
 638                         }
 639                         break;
 640                 }
 641                 case 1: /* edge */
 642                 {
 643                         trigger = 0;
 644                         break;
 645                 }
 646                 case 2: /* reserved */
 647                 {
 648                         printk(KERN_WARNING "broken BIOS!!\n");
 649                         trigger = 1;
 650                         break;
 651                 }
 652                 case 3: /* level */
 653                 {
 654                         trigger = 1;
 655                         break;
 656                 }
 657                 default: /* invalid */
 658                 {
 659                         printk(KERN_WARNING "broken BIOS!!\n");
 660                         trigger = 0;
 661                         break;
 662                 }
 663         }
 664         return trigger;
 665 }
 666
 667 static inline int irq_polarity(int idx)
 668 {
 669         return MPBIOS_polarity(idx);
 670 }
 671
 672 static inline int irq_trigger(int idx)
 673 {
 674         return MPBIOS_trigger(idx);
 675 }
 676
 677 static int next_irq = 16;
 678
 679 /*
 680  * gsi_irq_sharing -- Name overload!  "irq" can be either a legacy IRQ
 681  * in the range 0-15, a linux IRQ in the range 0-223, or a GSI number
 682  * from ACPI, which can reach 800 in large boxen.
 683  *
 684  * Compact the sparse GSI space into a sequential IRQ series and reuse
 685  * vectors if possible.
 686  */
 687 int gsi_irq_sharing(int gsi)
 688 {
 689         int i, tries, vector;
 690
 691         BUG_ON(gsi >= NR_IRQ_VECTORS);
 692
 693         if (platform_legacy_irq(gsi))
 694                 return gsi;
 695
 696         if (gsi_2_irq[gsi] != 0xFF)
 697                 return (int)gsi_2_irq[gsi];
 698
 699         tries = NR_IRQS;
 700   try_again:
 701         vector = assign_irq_vector(gsi);
 702
 703         /*
 704          * Sharing vectors means sharing IRQs, so scan irq_vectors for previous
 705          * use of vector and if found, return that IRQ.  However, we never want
 706          * to share legacy IRQs, which usually have a different trigger mode
 707          * than PCI.
 708          */
 709         for (i = 0; i < NR_IRQS; i++)
 710                 if (IO_APIC_VECTOR(i) == vector)
 711                         break;
 712         if (platform_legacy_irq(i)) {
 713                 if (--tries >= 0) {
 714                         IO_APIC_VECTOR(i) = 0;
 715                         goto try_again;
 716                 }
 717                 panic("gsi_irq_sharing: didn't find an IRQ using vector 0x%02X for GSI %d", vector, gsi);
 718         }
 719         if (i < NR_IRQS) {
 720                 gsi_2_irq[gsi] = i;
 721                 printk(KERN_INFO "GSI %d sharing vector 0x%02X and IRQ %d\n",
 722                                 gsi, vector, i);
 723                 return i;
 724         }
 725
 726         i = next_irq++;
 727         BUG_ON(i >= NR_IRQS);
 728         gsi_2_irq[gsi] = i;
 729         IO_APIC_VECTOR(i) = vector;
 730         printk(KERN_INFO "GSI %d assigned vector 0x%02X and IRQ %d\n",
 731                         gsi, vector, i);
 732         return i;
 733 }
 734
 735 static int pin_2_irq(int idx, int apic, int pin)
 736 {
 737         int irq, i;
 738         int bus = mp_irqs[idx].mpc_srcbus;
 739
 740         /*
 741          * Debugging check, we are in big trouble if this message pops up!
 742          */
 743         if (mp_irqs[idx].mpc_dstirq != pin)
 744                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 745
 746         switch (mp_bus_id_to_type[bus])
 747         {
 748                 case MP_BUS_ISA: /* ISA pin */
 749                 case MP_BUS_EISA:
 750                 case MP_BUS_MCA:
 751                 {
 752                         irq = mp_irqs[idx].mpc_srcbusirq;
 753                         break;
 754                 }
 755                 case MP_BUS_PCI: /* PCI pin */
 756                 {
 757                         /*
 758                          * PCI IRQs are mapped in order
 759                          */
 760                         i = irq = 0;
 761                         while (i < apic)
 762                                 irq += nr_ioapic_registers[i++];
 763                         irq += pin;
 764                         irq = gsi_irq_sharing(irq);
 765                         break;
 766                 }
 767                 default:
 768                 {
 769                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 770                         irq = 0;
 771                         break;
 772                 }
 773         }
 774         BUG_ON(irq >= NR_IRQS);
 775
 776         /*
 777          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 778          */
 779         if ((pin >= 16) && (pin <= 23)) {
 780                 if (pirq_entries[pin-16] != -1) {
 781                         if (!pirq_entries[pin-16]) {
 782                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 783                         } else {
 784                                 irq = pirq_entries[pin-16];
 785                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 786                                                 pin-16, irq);
 787                         }
 788                 }
 789         }
 790         BUG_ON(irq >= NR_IRQS);
 791         return irq;
 792 }
 793
 794 static inline int IO_APIC_irq_trigger(int irq)
 795 {
 796         int apic, idx, pin;
 797
 798         for (apic = 0; apic < nr_ioapics; apic++) {
 799                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 800                         idx = find_irq_entry(apic,pin,mp_INT);
 801                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 802                                 return irq_trigger(idx);
 803                 }
 804         }
 805         /*
 806          * nonexistent IRQs are edge default
 807          */
 808         return 0;
 809 }
 810
 811 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 812 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 813
 814 int assign_irq_vector(int irq)
 815 {
 816         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 817
 818         BUG_ON(irq != AUTO_ASSIGN && (unsigned)irq >= NR_IRQ_VECTORS);
 819         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
 820                 return IO_APIC_VECTOR(irq);
 821 next:
 822         current_vector += 8;
 823         if (current_vector == IA32_SYSCALL_VECTOR)
 824                 goto next;
 825
 826         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 827                 /* If we run out of vectors on large boxen, must share them. */
 828                 offset = (offset + 1) % 8;
 829                 current_vector = FIRST_DEVICE_VECTOR + offset;
 830         }
 831
 832         vector_irq[current_vector] = irq;
 833         if (irq != AUTO_ASSIGN)
 834                 IO_APIC_VECTOR(irq) = current_vector;
 835
 836         return current_vector;
 837 }
 838
 839 extern void (*interrupt[NR_IRQS])(void);
 840 static struct hw_interrupt_type ioapic_level_type;
 841 static struct hw_interrupt_type ioapic_edge_type;
 842
 843 #define IOAPIC_AUTO     -1
 844 #define IOAPIC_EDGE     0
 845 #define IOAPIC_LEVEL    1
 846
 847 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 848 {
 849         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 850                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 851                                 trigger == IOAPIC_LEVEL)
 852                         irq_desc[vector].handler = &ioapic_level_type;
 853                 else
 854                         irq_desc[vector].handler = &ioapic_edge_type;
 855                 set_intr_gate(vector, interrupt[vector]);
 856         } else  {
 857                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 858                                 trigger == IOAPIC_LEVEL)
 859                         irq_desc[irq].handler = &ioapic_level_type;
 860                 else
 861                         irq_desc[irq].handler = &ioapic_edge_type;
 862                 set_intr_gate(vector, interrupt[irq]);
 863         }
 864 }
 865
 866 static void __init setup_IO_APIC_irqs(void)
 867 {
 868         struct IO_APIC_route_entry entry;
 869         int apic, pin, idx, irq, first_notcon = 1, vector;
 870         unsigned long flags;
 871
 872         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 873
 874         for (apic = 0; apic < nr_ioapics; apic++) {
 875         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 876
 877                 /*
 878                  * add it to the IO-APIC irq-routing table:
 879                  */
 880                 memset(&entry,0,sizeof(entry));
 881
 882                 entry.delivery_mode = INT_DELIVERY_MODE;
 883                 entry.dest_mode = INT_DEST_MODE;
 884                 entry.mask = 0;                         /* enable IRQ */
 885                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 886
 887                 idx = find_irq_entry(apic,pin,mp_INT);
 888                 if (idx == -1) {
 889                         if (first_notcon) {
 890                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 891                                 first_notcon = 0;
 892                         } else
 893                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 894                         continue;
 895                 }
 896
 897                 entry.trigger = irq_trigger(idx);
 898                 entry.polarity = irq_polarity(idx);
 899
 900                 if (irq_trigger(idx)) {
 901                         entry.trigger = 1;
 902                         entry.mask = 1;
 903                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 904                 }
 905
 906                 irq = pin_2_irq(idx, apic, pin);
 907                 add_pin_to_irq(irq, apic, pin);
 908
 909                 if (!apic && !IO_APIC_IRQ(irq))
 910                         continue;
 911
 912                 if (IO_APIC_IRQ(irq)) {
 913                         vector = assign_irq_vector(irq);
 914                         entry.vector = vector;
 915
 916                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 917                         if (!apic && (irq < 16))
 918                                 disable_8259A_irq(irq);
 919                 }
 920                 spin_lock_irqsave(&ioapic_lock, flags);
 921                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 922                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 923                 set_native_irq_info(irq, TARGET_CPUS);
 924                 spin_unlock_irqrestore(&ioapic_lock, flags);
 925         }
 926         }
 927
 928         if (!first_notcon)
 929                 apic_printk(APIC_VERBOSE," not connected.\n");
 930 }
 931
 932 /*
 933  * Set up the 8259A-master output pin as broadcast to all
 934  * CPUs.
 935  */
 936 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
 937 {
 938         struct IO_APIC_route_entry entry;
 939         unsigned long flags;
 940
 941         memset(&entry,0,sizeof(entry));
 942
 943         disable_8259A_irq(0);
 944
 945         /* mask LVT0 */
 946         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 947
 948         /*
 949          * We use logical delivery to get the timer IRQ
 950          * to the first CPU.
 951          */
 952         entry.dest_mode = INT_DEST_MODE;
 953         entry.mask = 0;                                 /* unmask IRQ now */
 954         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 955         entry.delivery_mode = INT_DELIVERY_MODE;
 956         entry.polarity = 0;
 957         entry.trigger = 0;
 958         entry.vector = vector;
 959
 960         /*
 961          * The timer IRQ doesn't have to know that behind the
 962          * scene we have a 8259A-master in AEOI mode ...
 963          */
 964         irq_desc[0].handler = &ioapic_edge_type;
 965
 966         /*
 967          * Add it to the IO-APIC irq-routing table:
 968          */
 969         spin_lock_irqsave(&ioapic_lock, flags);
 970         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 971         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 972         spin_unlock_irqrestore(&ioapic_lock, flags);
 973
 974         enable_8259A_irq(0);
 975 }
 976
 977 void __init UNEXPECTED_IO_APIC(void)
 978 {
 979 }
 980
 981 void __apicdebuginit print_IO_APIC(void)
 982 {
 983         int apic, i;
 984         union IO_APIC_reg_00 reg_00;
 985         union IO_APIC_reg_01 reg_01;
 986         union IO_APIC_reg_02 reg_02;
 987         unsigned long flags;
 988
 989         if (apic_verbosity == APIC_QUIET)
 990                 return;
 991
 992         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 993         for (i = 0; i < nr_ioapics; i++)
 994                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 995                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 996
 997         /*
 998          * We are a bit conservative about what we expect.  We have to
 999          * know about every hardware change ASAP.
1000          */
1001         printk(KERN_INFO "testing the IO APIC.......................\n");
1002
1003         for (apic = 0; apic < nr_ioapics; apic++) {
1004
1005         spin_lock_irqsave(&ioapic_lock, flags);
1006         reg_00.raw = io_apic_read(apic, 0);
1007         reg_01.raw = io_apic_read(apic, 1);
1008         if (reg_01.bits.version >= 0x10)
1009                 reg_02.raw = io_apic_read(apic, 2);
1010         spin_unlock_irqrestore(&ioapic_lock, flags);
1011
1012         printk("\n");
1013         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1014         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1015         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1016         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1017                 UNEXPECTED_IO_APIC();
1018
1019         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1020         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1021         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1022                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1023                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1024                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1025                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1026                 (reg_01.bits.entries != 0x2E) &&
1027                 (reg_01.bits.entries != 0x3F) &&
1028                 (reg_01.bits.entries != 0x03)
1029         )
1030                 UNEXPECTED_IO_APIC();
1031
1032         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1033         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1034         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1035                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
1036                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1037                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1038                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1039                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1040         )
1041                 UNEXPECTED_IO_APIC();
1042         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1043                 UNEXPECTED_IO_APIC();
1044
1045         if (reg_01.bits.version >= 0x10) {
1046                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1047                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1048                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1049                         UNEXPECTED_IO_APIC();
1050         }
1051
1052         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1053
1054         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1055                           " Stat Dest Deli Vect:   \n");
1056
1057         for (i = 0; i <= reg_01.bits.entries; i++) {
1058                 struct IO_APIC_route_entry entry;
1059
1060                 spin_lock_irqsave(&ioapic_lock, flags);
1061                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1062                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1063                 spin_unlock_irqrestore(&ioapic_lock, flags);
1064
1065                 printk(KERN_DEBUG " %02x %03X %02X  ",
1066                         i,
1067                         entry.dest.logical.logical_dest,
1068                         entry.dest.physical.physical_dest
1069                 );
1070
1071                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1072                         entry.mask,
1073                         entry.trigger,
1074                         entry.irr,
1075                         entry.polarity,
1076                         entry.delivery_status,
1077                         entry.dest_mode,
1078                         entry.delivery_mode,
1079                         entry.vector
1080                 );
1081         }
1082         }
1083         if (use_pci_vector())
1084                 printk(KERN_INFO "Using vector-based indexing\n");
1085         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1086         for (i = 0; i < NR_IRQS; i++) {
1087                 struct irq_pin_list *entry = irq_2_pin + i;
1088                 if (entry->pin < 0)
1089                         continue;
1090                 if (use_pci_vector() && !platform_legacy_irq(i))
1091                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1092                 else
1093                         printk(KERN_DEBUG "IRQ%d ", i);
1094                 for (;;) {
1095                         printk("-> %d:%d", entry->apic, entry->pin);
1096                         if (!entry->next)
1097                                 break;
1098                         entry = irq_2_pin + entry->next;
1099                 }
1100                 printk("\n");
1101         }
1102
1103         printk(KERN_INFO ".................................... done.\n");
1104
1105         return;
1106 }
1107
1108 #if 0
1109
1110 static __apicdebuginit void print_APIC_bitfield (int base)
1111 {
1112         unsigned int v;
1113         int i, j;
1114
1115         if (apic_verbosity == APIC_QUIET)
1116                 return;
1117
1118         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1119         for (i = 0; i < 8; i++) {
1120                 v = apic_read(base + i*0x10);
1121                 for (j = 0; j < 32; j++) {
1122                         if (v & (1<<j))
1123                                 printk("1");
1124                         else
1125                                 printk("0");
1126                 }
1127                 printk("\n");
1128         }
1129 }
1130
1131 void __apicdebuginit print_local_APIC(void * dummy)
1132 {
1133         unsigned int v, ver, maxlvt;
1134
1135         if (apic_verbosity == APIC_QUIET)
1136                 return;
1137
1138         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1139                 smp_processor_id(), hard_smp_processor_id());
1140         v = apic_read(APIC_ID);
1141         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1142         v = apic_read(APIC_LVR);
1143         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1144         ver = GET_APIC_VERSION(v);
1145         maxlvt = get_maxlvt();
1146
1147         v = apic_read(APIC_TASKPRI);
1148         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1149
1150         v = apic_read(APIC_ARBPRI);
1151         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1152                 v & APIC_ARBPRI_MASK);
1153         v = apic_read(APIC_PROCPRI);
1154         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1155
1156         v = apic_read(APIC_EOI);
1157         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1158         v = apic_read(APIC_RRR);
1159         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1160         v = apic_read(APIC_LDR);
1161         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1162         v = apic_read(APIC_DFR);
1163         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1164         v = apic_read(APIC_SPIV);
1165         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1166
1167         printk(KERN_DEBUG "... APIC ISR field:\n");
1168         print_APIC_bitfield(APIC_ISR);
1169         printk(KERN_DEBUG "... APIC TMR field:\n");
1170         print_APIC_bitfield(APIC_TMR);
1171         printk(KERN_DEBUG "... APIC IRR field:\n");
1172         print_APIC_bitfield(APIC_IRR);
1173
1174         v = apic_read(APIC_ESR);
1175         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1176
1177         v = apic_read(APIC_ICR);
1178         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1179         v = apic_read(APIC_ICR2);
1180         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1181
1182         v = apic_read(APIC_LVTT);
1183         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1184
1185         if (maxlvt > 3) {                       /* PC is LVT#4. */
1186                 v = apic_read(APIC_LVTPC);
1187                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1188         }
1189         v = apic_read(APIC_LVT0);
1190         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1191         v = apic_read(APIC_LVT1);
1192         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1193
1194         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1195                 v = apic_read(APIC_LVTERR);
1196                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1197         }
1198
1199         v = apic_read(APIC_TMICT);
1200         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1201         v = apic_read(APIC_TMCCT);
1202         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1203         v = apic_read(APIC_TDCR);
1204         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1205         printk("\n");
1206 }
1207
1208 void print_all_local_APICs (void)
1209 {
1210         on_each_cpu(print_local_APIC, NULL, 1, 1);
1211 }
1212
1213 void __apicdebuginit print_PIC(void)
1214 {
1215         unsigned int v;
1216         unsigned long flags;
1217
1218         if (apic_verbosity == APIC_QUIET)
1219                 return;
1220
1221         printk(KERN_DEBUG "\nprinting PIC contents\n");
1222
1223         spin_lock_irqsave(&i8259A_lock, flags);
1224
1225         v = inb(0xa1) << 8 | inb(0x21);
1226         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1227
1228         v = inb(0xa0) << 8 | inb(0x20);
1229         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1230
1231         outb(0x0b,0xa0);
1232         outb(0x0b,0x20);
1233         v = inb(0xa0) << 8 | inb(0x20);
1234         outb(0x0a,0xa0);
1235         outb(0x0a,0x20);
1236
1237         spin_unlock_irqrestore(&i8259A_lock, flags);
1238
1239         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1240
1241         v = inb(0x4d1) << 8 | inb(0x4d0);
1242         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1243 }
1244
1245 #endif  /*  0  */
1246
1247 static void __init enable_IO_APIC(void)
1248 {
1249         union IO_APIC_reg_01 reg_01;
1250         int i8259_apic, i8259_pin;
1251         int i, apic;
1252         unsigned long flags;
1253
1254         for (i = 0; i < PIN_MAP_SIZE; i++) {
1255                 irq_2_pin[i].pin = -1;
1256                 irq_2_pin[i].next = 0;
1257         }
1258         if (!pirqs_enabled)
1259                 for (i = 0; i < MAX_PIRQS; i++)
1260                         pirq_entries[i] = -1;
1261
1262         /*
1263          * The number of IO-APIC IRQ registers (== #pins):
1264          */
1265         for (apic = 0; apic < nr_ioapics; apic++) {
1266                 spin_lock_irqsave(&ioapic_lock, flags);
1267                 reg_01.raw = io_apic_read(apic, 1);
1268                 spin_unlock_irqrestore(&ioapic_lock, flags);
1269                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1270         }
1271         for(apic = 0; apic < nr_ioapics; apic++) {
1272                 int pin;
1273                 /* See if any of the pins is in ExtINT mode */
1274                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1275                         struct IO_APIC_route_entry entry;
1276                         spin_lock_irqsave(&ioapic_lock, flags);
1277                         *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1278                         *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1279                         spin_unlock_irqrestore(&ioapic_lock, flags);
1280
1281
1282                         /* If the interrupt line is enabled and in ExtInt mode
1283                          * I have found the pin where the i8259 is connected.
1284                          */
1285                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1286                                 ioapic_i8259.apic = apic;
1287                                 ioapic_i8259.pin  = pin;
1288                                 goto found_i8259;
1289                         }
1290                 }
1291         }
1292  found_i8259:
1293         /* Look to see what if the MP table has reported the ExtINT */
1294         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1295         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1296         /* Trust the MP table if nothing is setup in the hardware */
1297         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1298                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1299                 ioapic_i8259.pin  = i8259_pin;
1300                 ioapic_i8259.apic = i8259_apic;
1301         }
1302         /* Complain if the MP table and the hardware disagree */
1303         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1304                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1305         {
1306                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1307         }
1308
1309         /*
1310          * Do not trust the IO-APIC being empty at bootup
1311          */
1312         clear_IO_APIC();
1313 }
1314
1315 /*
1316  * Not an __init, needed by the reboot code
1317  */
1318 void disable_IO_APIC(void)
1319 {
1320         /*
1321          * Clear the IO-APIC before rebooting:
1322          */
1323         clear_IO_APIC();
1324
1325         /*
1326          * If the i8259 is routed through an IOAPIC
1327          * Put that IOAPIC in virtual wire mode
1328          * so legacy interrupts can be delivered.
1329          */
1330         if (ioapic_i8259.pin != -1) {
1331                 struct IO_APIC_route_entry entry;
1332                 unsigned long flags;
1333
1334                 memset(&entry, 0, sizeof(entry));
1335                 entry.mask            = 0; /* Enabled */
1336                 entry.trigger         = 0; /* Edge */
1337                 entry.irr             = 0;
1338                 entry.polarity        = 0; /* High */
1339                 entry.delivery_status = 0;
1340                 entry.dest_mode       = 0; /* Physical */
1341                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1342                 entry.vector          = 0;
1343                 entry.dest.physical.physical_dest =
1344                                         GET_APIC_ID(apic_read(APIC_ID));
1345
1346                 /*
1347                  * Add it to the IO-APIC irq-routing table:
1348                  */
1349                 spin_lock_irqsave(&ioapic_lock, flags);
1350                 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1351                         *(((int *)&entry)+1));
1352                 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1353                         *(((int *)&entry)+0));
1354                 spin_unlock_irqrestore(&ioapic_lock, flags);
1355         }
1356
1357         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1358 }
1359
1360 /*
1361  * function to set the IO-APIC physical IDs based on the
1362  * values stored in the MPC table.
1363  *
1364  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1365  */
1366
1367 static void __init setup_ioapic_ids_from_mpc (void)
1368 {
1369         union IO_APIC_reg_00 reg_00;
1370         int apic;
1371         int i;
1372         unsigned char old_id;
1373         unsigned long flags;
1374
1375         /*
1376          * Set the IOAPIC ID to the value stored in the MPC table.
1377          */
1378         for (apic = 0; apic < nr_ioapics; apic++) {
1379
1380                 /* Read the register 0 value */
1381                 spin_lock_irqsave(&ioapic_lock, flags);
1382                 reg_00.raw = io_apic_read(apic, 0);
1383                 spin_unlock_irqrestore(&ioapic_lock, flags);
1384
1385                 old_id = mp_ioapics[apic].mpc_apicid;
1386
1387
1388                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1389
1390
1391                 /*
1392                  * We need to adjust the IRQ routing table
1393                  * if the ID changed.
1394                  */
1395                 if (old_id != mp_ioapics[apic].mpc_apicid)
1396                         for (i = 0; i < mp_irq_entries; i++)
1397                                 if (mp_irqs[i].mpc_dstapic == old_id)
1398                                         mp_irqs[i].mpc_dstapic
1399                                                 = mp_ioapics[apic].mpc_apicid;
1400
1401                 /*
1402                  * Read the right value from the MPC table and
1403                  * write it into the ID register.
1404                  */
1405                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1406                                 mp_ioapics[apic].mpc_apicid);
1407
1408                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1409                 spin_lock_irqsave(&ioapic_lock, flags);
1410                 io_apic_write(apic, 0, reg_00.raw);
1411                 spin_unlock_irqrestore(&ioapic_lock, flags);
1412
1413                 /*
1414                  * Sanity check
1415                  */
1416                 spin_lock_irqsave(&ioapic_lock, flags);
1417                 reg_00.raw = io_apic_read(apic, 0);
1418                 spin_unlock_irqrestore(&ioapic_lock, flags);
1419                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1420                         printk("could not set ID!\n");
1421                 else
1422                         apic_printk(APIC_VERBOSE," ok.\n");
1423         }
1424 }
1425
1426 /*
1427  * There is a nasty bug in some older SMP boards, their mptable lies
1428  * about the timer IRQ. We do the following to work around the situation:
1429  *
1430  *      - timer IRQ defaults to IO-APIC IRQ
1431  *      - if this function detects that timer IRQs are defunct, then we fall
1432  *        back to ISA timer IRQs
1433  */
1434 static int __init timer_irq_works(void)
1435 {
1436         unsigned long t1 = jiffies;
1437
1438         local_irq_enable();
1439         /* Let ten ticks pass... */
1440         mdelay((10 * 1000) / HZ);
1441
1442         /*
1443          * Expect a few ticks at least, to be sure some possible
1444          * glue logic does not lock up after one or two first
1445          * ticks in a non-ExtINT mode.  Also the local APIC
1446          * might have cached one ExtINT interrupt.  Finally, at
1447          * least one tick may be lost due to delays.
1448          */
1449
1450         /* jiffies wrap? */
1451         if (jiffies - t1 > 4)
1452                 return 1;
1453         return 0;
1454 }
1455
1456 /*
1457  * In the SMP+IOAPIC case it might happen that there are an unspecified
1458  * number of pending IRQ events unhandled. These cases are very rare,
1459  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1460  * better to do it this way as thus we do not have to be aware of
1461  * 'pending' interrupts in the IRQ path, except at this point.
1462  */
1463 /*
1464  * Edge triggered needs to resend any interrupt
1465  * that was delayed but this is now handled in the device
1466  * independent code.
1467  */
1468
1469 /*
1470  * Starting up a edge-triggered IO-APIC interrupt is
1471  * nasty - we need to make sure that we get the edge.
1472  * If it is already asserted for some reason, we need
1473  * return 1 to indicate that is was pending.
1474  *
1475  * This is not complete - we should be able to fake
1476  * an edge even if it isn't on the 8259A...
1477  */
1478
1479 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1480 {
1481         int was_pending = 0;
1482         unsigned long flags;
1483
1484         spin_lock_irqsave(&ioapic_lock, flags);
1485         if (irq < 16) {
1486                 disable_8259A_irq(irq);
1487                 if (i8259A_irq_pending(irq))
1488                         was_pending = 1;
1489         }
1490         __unmask_IO_APIC_irq(irq);
1491         spin_unlock_irqrestore(&ioapic_lock, flags);
1492
1493         return was_pending;
1494 }
1495
1496 /*
1497  * Once we have recorded IRQ_PENDING already, we can mask the
1498  * interrupt for real. This prevents IRQ storms from unhandled
1499  * devices.
1500  */
1501 static void ack_edge_ioapic_irq(unsigned int irq)
1502 {
1503         move_irq(irq);
1504         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1505                                         == (IRQ_PENDING | IRQ_DISABLED))
1506                 mask_IO_APIC_irq(irq);
1507         ack_APIC_irq();
1508 }
1509
1510 /*
1511  * Level triggered interrupts can just be masked,
1512  * and shutting down and starting up the interrupt
1513  * is the same as enabling and disabling them -- except
1514  * with a startup need to return a "was pending" value.
1515  *
1516  * Level triggered interrupts are special because we
1517  * do not touch any IO-APIC register while handling
1518  * them. We ack the APIC in the end-IRQ handler, not
1519  * in the start-IRQ-handler. Protection against reentrance
1520  * from the same interrupt is still provided, both by the
1521  * generic IRQ layer and by the fact that an unacked local
1522  * APIC does not accept IRQs.
1523  */
1524 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1525 {
1526         unmask_IO_APIC_irq(irq);
1527
1528         return 0; /* don't check for pending */
1529 }
1530
1531 static void end_level_ioapic_irq (unsigned int irq)
1532 {
1533         move_irq(irq);
1534         ack_APIC_irq();
1535 }
1536
1537 #ifdef CONFIG_PCI_MSI
1538 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1539 {
1540         int irq = vector_to_irq(vector);
1541
1542         return startup_edge_ioapic_irq(irq);
1543 }
1544
1545 static void ack_edge_ioapic_vector(unsigned int vector)
1546 {
1547         int irq = vector_to_irq(vector);
1548
1549         move_native_irq(vector);
1550         ack_edge_ioapic_irq(irq);
1551 }
1552
1553 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1554 {
1555         int irq = vector_to_irq(vector);
1556
1557         return startup_level_ioapic_irq (irq);
1558 }
1559
1560 static void end_level_ioapic_vector (unsigned int vector)
1561 {
1562         int irq = vector_to_irq(vector);
1563
1564         move_native_irq(vector);
1565         end_level_ioapic_irq(irq);
1566 }
1567
1568 static void mask_IO_APIC_vector (unsigned int vector)
1569 {
1570         int irq = vector_to_irq(vector);
1571
1572         mask_IO_APIC_irq(irq);
1573 }
1574
1575 static void unmask_IO_APIC_vector (unsigned int vector)
1576 {
1577         int irq = vector_to_irq(vector);
1578
1579         unmask_IO_APIC_irq(irq);
1580 }
1581
1582 #ifdef CONFIG_SMP
1583 static void set_ioapic_affinity_vector (unsigned int vector,
1584                                         cpumask_t cpu_mask)
1585 {
1586         int irq = vector_to_irq(vector);
1587
1588         set_native_irq_info(vector, cpu_mask);
1589         set_ioapic_affinity_irq(irq, cpu_mask);
1590 }
1591 #endif // CONFIG_SMP
1592 #endif // CONFIG_PCI_MSI
1593
1594 /*
1595  * Level and edge triggered IO-APIC interrupts need different handling,
1596  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1597  * handled with the level-triggered descriptor, but that one has slightly
1598  * more overhead. Level-triggered interrupts cannot be handled with the
1599  * edge-triggered handler, without risking IRQ storms and other ugly
1600  * races.
1601  */
1602
1603 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1604         .typename = "IO-APIC-edge",
1605         .startup        = startup_edge_ioapic,
1606         .shutdown       = shutdown_edge_ioapic,
1607         .enable         = enable_edge_ioapic,
1608         .disable        = disable_edge_ioapic,
1609         .ack            = ack_edge_ioapic,
1610         .end            = end_edge_ioapic,
1611 #ifdef CONFIG_SMP
1612         .set_affinity = set_ioapic_affinity,
1613 #endif
1614 };
1615
1616 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1617         .typename = "IO-APIC-level",
1618         .startup        = startup_level_ioapic,
1619         .shutdown       = shutdown_level_ioapic,
1620         .enable         = enable_level_ioapic,
1621         .disable        = disable_level_ioapic,
1622         .ack            = mask_and_ack_level_ioapic,
1623         .end            = end_level_ioapic,
1624 #ifdef CONFIG_SMP
1625         .set_affinity = set_ioapic_affinity,
1626 #endif
1627 };
1628
1629 static inline void init_IO_APIC_traps(void)
1630 {
1631         int irq;
1632
1633         /*
1634          * NOTE! The local APIC isn't very good at handling
1635          * multiple interrupts at the same interrupt level.
1636          * As the interrupt level is determined by taking the
1637          * vector number and shifting that right by 4, we
1638          * want to spread these out a bit so that they don't
1639          * all fall in the same interrupt level.
1640          *
1641          * Also, we've got to be careful not to trash gate
1642          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1643          */
1644         for (irq = 0; irq < NR_IRQS ; irq++) {
1645                 int tmp = irq;
1646                 if (use_pci_vector()) {
1647                         if (!platform_legacy_irq(tmp))
1648                                 if ((tmp = vector_to_irq(tmp)) == -1)
1649                                         continue;
1650                 }
1651                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1652                         /*
1653                          * Hmm.. We don't have an entry for this,
1654                          * so default to an old-fashioned 8259
1655                          * interrupt if we can..
1656                          */
1657                         if (irq < 16)
1658                                 make_8259A_irq(irq);
1659                         else
1660                                 /* Strange. Oh, well.. */
1661                                 irq_desc[irq].handler = &no_irq_type;
1662                 }
1663         }
1664 }
1665
1666 static void enable_lapic_irq (unsigned int irq)
1667 {
1668         unsigned long v;
1669
1670         v = apic_read(APIC_LVT0);
1671         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1672 }
1673
1674 static void disable_lapic_irq (unsigned int irq)
1675 {
1676         unsigned long v;
1677
1678         v = apic_read(APIC_LVT0);
1679         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1680 }
1681
1682 static void ack_lapic_irq (unsigned int irq)
1683 {
1684         ack_APIC_irq();
1685 }
1686
1687 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1688
1689 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1690         .typename = "local-APIC-edge",
1691         .startup = NULL, /* startup_irq() not used for IRQ0 */
1692         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1693         .enable = enable_lapic_irq,
1694         .disable = disable_lapic_irq,
1695         .ack = ack_lapic_irq,
1696         .end = end_lapic_irq,
1697 };
1698
1699 static void setup_nmi (void)
1700 {
1701         /*
1702          * Dirty trick to enable the NMI watchdog ...
1703          * We put the 8259A master into AEOI mode and
1704          * unmask on all local APICs LVT0 as NMI.
1705          *
1706          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1707          * is from Maciej W. Rozycki - so we do not have to EOI from
1708          * the NMI handler or the timer interrupt.
1709          */
1710         printk(KERN_INFO "activating NMI Watchdog ...");
1711
1712         enable_NMI_through_LVT0(NULL);
1713
1714         printk(" done.\n");
1715 }
1716
1717 /*
1718  * This looks a bit hackish but it's about the only one way of sending
1719  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1720  * not support the ExtINT mode, unfortunately.  We need to send these
1721  * cycles as some i82489DX-based boards have glue logic that keeps the
1722  * 8259A interrupt line asserted until INTA.  --macro
1723  */
1724 static inline void unlock_ExtINT_logic(void)
1725 {
1726         int apic, pin, i;
1727         struct IO_APIC_route_entry entry0, entry1;
1728         unsigned char save_control, save_freq_select;
1729         unsigned long flags;
1730
1731         pin  = find_isa_irq_pin(8, mp_INT);
1732         apic = find_isa_irq_apic(8, mp_INT);
1733         if (pin == -1)
1734                 return;
1735
1736         spin_lock_irqsave(&ioapic_lock, flags);
1737         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1738         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1739         spin_unlock_irqrestore(&ioapic_lock, flags);
1740         clear_IO_APIC_pin(apic, pin);
1741
1742         memset(&entry1, 0, sizeof(entry1));
1743
1744         entry1.dest_mode = 0;                   /* physical delivery */
1745         entry1.mask = 0;                        /* unmask IRQ now */
1746         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1747         entry1.delivery_mode = dest_ExtINT;
1748         entry1.polarity = entry0.polarity;
1749         entry1.trigger = 0;
1750         entry1.vector = 0;
1751
1752         spin_lock_irqsave(&ioapic_lock, flags);
1753         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1754         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1755         spin_unlock_irqrestore(&ioapic_lock, flags);
1756
1757         save_control = CMOS_READ(RTC_CONTROL);
1758         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1759         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1760                    RTC_FREQ_SELECT);
1761         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1762
1763         i = 100;
1764         while (i-- > 0) {
1765                 mdelay(10);
1766                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1767                         i -= 10;
1768         }
1769
1770         CMOS_WRITE(save_control, RTC_CONTROL);
1771         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1772         clear_IO_APIC_pin(apic, pin);
1773
1774         spin_lock_irqsave(&ioapic_lock, flags);
1775         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1776         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1777         spin_unlock_irqrestore(&ioapic_lock, flags);
1778 }
1779
1780 /*
1781  * This code may look a bit paranoid, but it's supposed to cooperate with
1782  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1783  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1784  * fanatically on his truly buggy board.
1785  *
1786  * FIXME: really need to revamp this for modern platforms only.
1787  */
1788 static inline void check_timer(void)
1789 {
1790         int apic1, pin1, apic2, pin2;
1791         int vector;
1792
1793         /*
1794          * get/set the timer IRQ vector:
1795          */
1796         disable_8259A_irq(0);
1797         vector = assign_irq_vector(0);
1798         set_intr_gate(vector, interrupt[0]);
1799
1800         /*
1801          * Subtle, code in do_timer_interrupt() expects an AEOI
1802          * mode for the 8259A whenever interrupts are routed
1803          * through I/O APICs.  Also IRQ0 has to be enabled in
1804          * the 8259A which implies the virtual wire has to be
1805          * disabled in the local APIC.
1806          */
1807         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1808         init_8259A(1);
1809         if (timer_over_8254 > 0)
1810                 enable_8259A_irq(0);
1811
1812         pin1  = find_isa_irq_pin(0, mp_INT);
1813         apic1 = find_isa_irq_apic(0, mp_INT);
1814         pin2  = ioapic_i8259.pin;
1815         apic2 = ioapic_i8259.apic;
1816
1817         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1818                 vector, apic1, pin1, apic2, pin2);
1819
1820         if (pin1 != -1) {
1821                 /*
1822                  * Ok, does IRQ0 through the IOAPIC work?
1823                  */
1824                 unmask_IO_APIC_irq(0);
1825                 if (!no_timer_check && timer_irq_works()) {
1826                         nmi_watchdog_default();
1827                         if (nmi_watchdog == NMI_IO_APIC) {
1828                                 disable_8259A_irq(0);
1829                                 setup_nmi();
1830                                 enable_8259A_irq(0);
1831                         }
1832                         if (disable_timer_pin_1 > 0)
1833                                 clear_IO_APIC_pin(0, pin1);
1834                         return;
1835                 }
1836                 clear_IO_APIC_pin(apic1, pin1);
1837                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1838                                 "connected to IO-APIC\n");
1839         }
1840
1841         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1842                                 "through the 8259A ... ");
1843         if (pin2 != -1) {
1844                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1845                         apic2, pin2);
1846                 /*
1847                  * legacy devices should be connected to IO APIC #0
1848                  */
1849                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1850                 if (timer_irq_works()) {
1851                         apic_printk(APIC_VERBOSE," works.\n");
1852                         nmi_watchdog_default();
1853                         if (nmi_watchdog == NMI_IO_APIC) {
1854                                 setup_nmi();
1855                         }
1856                         return;
1857                 }
1858                 /*
1859                  * Cleanup, just in case ...
1860                  */
1861                 clear_IO_APIC_pin(apic2, pin2);
1862         }
1863         apic_printk(APIC_VERBOSE," failed.\n");
1864
1865         if (nmi_watchdog == NMI_IO_APIC) {
1866                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1867                 nmi_watchdog = 0;
1868         }
1869
1870         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1871
1872         disable_8259A_irq(0);
1873         irq_desc[0].handler = &lapic_irq_type;
1874         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1875         enable_8259A_irq(0);
1876
1877         if (timer_irq_works()) {
1878                 apic_printk(APIC_VERBOSE," works.\n");
1879                 return;
1880         }
1881         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1882         apic_printk(APIC_VERBOSE," failed.\n");
1883
1884         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1885
1886         init_8259A(0);
1887         make_8259A_irq(0);
1888         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1889
1890         unlock_ExtINT_logic();
1891
1892         if (timer_irq_works()) {
1893                 apic_printk(APIC_VERBOSE," works.\n");
1894                 return;
1895         }
1896         apic_printk(APIC_VERBOSE," failed :(.\n");
1897         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1898 }
1899
1900 static int __init notimercheck(char *s)
1901 {
1902         no_timer_check = 1;
1903         return 1;
1904 }
1905 __setup("no_timer_check", notimercheck);
1906
1907 /*
1908  *
1909  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1910  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1911  *   Linux doesn't really care, as it's not actually used
1912  *   for any interrupt handling anyway.
1913  */
1914 #define PIC_IRQS        (1<<2)
1915
1916 void __init setup_IO_APIC(void)
1917 {
1918         enable_IO_APIC();
1919
1920         if (acpi_ioapic)
1921                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1922         else
1923                 io_apic_irqs = ~PIC_IRQS;
1924
1925         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1926
1927         /*
1928          * Set up the IO-APIC IRQ routing table.
1929          */
1930         if (!acpi_ioapic)
1931                 setup_ioapic_ids_from_mpc();
1932         sync_Arb_IDs();
1933         setup_IO_APIC_irqs();
1934         init_IO_APIC_traps();
1935         check_timer();
1936         if (!acpi_ioapic)
1937                 print_IO_APIC();
1938 }
1939
1940 struct sysfs_ioapic_data {
1941         struct sys_device dev;
1942         struct IO_APIC_route_entry entry[0];
1943 };
1944 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1945
1946 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1947 {
1948         struct IO_APIC_route_entry *entry;
1949         struct sysfs_ioapic_data *data;
1950         unsigned long flags;
1951         int i;
1952
1953         data = container_of(dev, struct sysfs_ioapic_data, dev);
1954         entry = data->entry;
1955         spin_lock_irqsave(&ioapic_lock, flags);
1956         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1957                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1958                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1959         }
1960         spin_unlock_irqrestore(&ioapic_lock, flags);
1961
1962         return 0;
1963 }
1964
1965 static int ioapic_resume(struct sys_device *dev)
1966 {
1967         struct IO_APIC_route_entry *entry;
1968         struct sysfs_ioapic_data *data;
1969         unsigned long flags;
1970         union IO_APIC_reg_00 reg_00;
1971         int i;
1972
1973         data = container_of(dev, struct sysfs_ioapic_data, dev);
1974         entry = data->entry;
1975
1976         spin_lock_irqsave(&ioapic_lock, flags);
1977         reg_00.raw = io_apic_read(dev->id, 0);
1978         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1979                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1980                 io_apic_write(dev->id, 0, reg_00.raw);
1981         }
1982         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1983                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1984                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1985         }
1986         spin_unlock_irqrestore(&ioapic_lock, flags);
1987
1988         return 0;
1989 }
1990
1991 static struct sysdev_class ioapic_sysdev_class = {
1992         set_kset_name("ioapic"),
1993         .suspend = ioapic_suspend,
1994         .resume = ioapic_resume,
1995 };
1996
1997 static int __init ioapic_init_sysfs(void)
1998 {
1999         struct sys_device * dev;
2000         int i, size, error = 0;
2001
2002         error = sysdev_class_register(&ioapic_sysdev_class);
2003         if (error)
2004                 return error;
2005
2006         for (i = 0; i < nr_ioapics; i++ ) {
2007                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2008                         * sizeof(struct IO_APIC_route_entry);
2009                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2010                 if (!mp_ioapic_data[i]) {
2011                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2012                         continue;
2013                 }
2014                 memset(mp_ioapic_data[i], 0, size);
2015                 dev = &mp_ioapic_data[i]->dev;
2016                 dev->id = i;
2017                 dev->cls = &ioapic_sysdev_class;
2018                 error = sysdev_register(dev);
2019                 if (error) {
2020                         kfree(mp_ioapic_data[i]);
2021                         mp_ioapic_data[i] = NULL;
2022                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2023                         continue;
2024                 }
2025         }
2026
2027         return 0;
2028 }
2029
2030 device_initcall(ioapic_init_sysfs);
2031
2032 /* --------------------------------------------------------------------------
2033                           ACPI-based IOAPIC Configuration
2034    -------------------------------------------------------------------------- */
2035
2036 #ifdef CONFIG_ACPI
2037
2038 #define IO_APIC_MAX_ID          0xFE
2039
2040 int __init io_apic_get_version (int ioapic)
2041 {
2042         union IO_APIC_reg_01    reg_01;
2043         unsigned long flags;
2044
2045         spin_lock_irqsave(&ioapic_lock, flags);
2046         reg_01.raw = io_apic_read(ioapic, 1);
2047         spin_unlock_irqrestore(&ioapic_lock, flags);
2048
2049         return reg_01.bits.version;
2050 }
2051
2052
2053 int __init io_apic_get_redir_entries (int ioapic)
2054 {
2055         union IO_APIC_reg_01    reg_01;
2056         unsigned long flags;
2057
2058         spin_lock_irqsave(&ioapic_lock, flags);
2059         reg_01.raw = io_apic_read(ioapic, 1);
2060         spin_unlock_irqrestore(&ioapic_lock, flags);
2061
2062         return reg_01.bits.entries;
2063 }
2064
2065
2066 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2067 {
2068         struct IO_APIC_route_entry entry;
2069         unsigned long flags;
2070
2071         if (!IO_APIC_IRQ(irq)) {
2072                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2073                         ioapic);
2074                 return -EINVAL;
2075         }
2076
2077         /*
2078          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2079          * Note that we mask (disable) IRQs now -- these get enabled when the
2080          * corresponding device driver registers for this IRQ.
2081          */
2082
2083         memset(&entry,0,sizeof(entry));
2084
2085         entry.delivery_mode = INT_DELIVERY_MODE;
2086         entry.dest_mode = INT_DEST_MODE;
2087         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2088         entry.trigger = triggering;
2089         entry.polarity = polarity;
2090         entry.mask = 1;                                  /* Disabled (masked) */
2091
2092         irq = gsi_irq_sharing(irq);
2093         /*
2094          * IRQs < 16 are already in the irq_2_pin[] map
2095          */
2096         if (irq >= 16)
2097                 add_pin_to_irq(irq, ioapic, pin);
2098
2099         entry.vector = assign_irq_vector(irq);
2100
2101         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
2102                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
2103                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2104                triggering, polarity);
2105
2106         ioapic_register_intr(irq, entry.vector, triggering);
2107
2108         if (!ioapic && (irq < 16))
2109                 disable_8259A_irq(irq);
2110
2111         spin_lock_irqsave(&ioapic_lock, flags);
2112         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2113         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2114         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
2115         spin_unlock_irqrestore(&ioapic_lock, flags);
2116
2117         return 0;
2118 }
2119
2120 #endif /* CONFIG_ACPI */
2121
2122
2123 /*
2124  * This function currently is only a helper for the i386 smp boot process where
2125  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2126  * so mask in all cases should simply be TARGET_CPUS
2127  */
2128 #ifdef CONFIG_SMP
2129 void __init setup_ioapic_dest(void)
2130 {
2131         int pin, ioapic, irq, irq_entry;
2132
2133         if (skip_ioapic_setup == 1)
2134                 return;
2135
2136         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2137                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2138                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2139                         if (irq_entry == -1)
2140                                 continue;
2141                         irq = pin_2_irq(irq_entry, ioapic, pin);
2142                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
2143                 }
2144
2145         }
2146 }
2147 #endif