git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/b43/dma.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "b43.h"
  31 #include "dma.h"
  32 #include "main.h"
  33 #include "debugfs.h"
  34 #include "xmit.h"
  35
  36 #include <linux/dma-mapping.h>
  37 #include <linux/pci.h>
  38 #include <linux/delay.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/etherdevice.h>
  41 #include <asm/div64.h>
  42
  43
  44 /* 32bit DMA ops. */
  45 static
  46 struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring,
  47                                           int slot,
  48                                           struct b43_dmadesc_meta **meta)
  49 {
  50         struct b43_dmadesc32 *desc;
  51
  52         *meta = &(ring->meta[slot]);
  53         desc = ring->descbase;
  54         desc = &(desc[slot]);
  55
  56         return (struct b43_dmadesc_generic *)desc;
  57 }
  58
  59 static void op32_fill_descriptor(struct b43_dmaring *ring,
  60                                  struct b43_dmadesc_generic *desc,
  61                                  dma_addr_t dmaaddr, u16 bufsize,
  62                                  int start, int end, int irq)
  63 {
  64         struct b43_dmadesc32 *descbase = ring->descbase;
  65         int slot;
  66         u32 ctl;
  67         u32 addr;
  68         u32 addrext;
  69
  70         slot = (int)(&(desc->dma32) - descbase);
  71         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
  72
  73         addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
  74         addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK)
  75             >> SSB_DMA_TRANSLATION_SHIFT;
  76         addr |= ssb_dma_translation(ring->dev->dev);
  77         ctl = (bufsize - ring->frameoffset)
  78             & B43_DMA32_DCTL_BYTECNT;
  79         if (slot == ring->nr_slots - 1)
  80                 ctl |= B43_DMA32_DCTL_DTABLEEND;
  81         if (start)
  82                 ctl |= B43_DMA32_DCTL_FRAMESTART;
  83         if (end)
  84                 ctl |= B43_DMA32_DCTL_FRAMEEND;
  85         if (irq)
  86                 ctl |= B43_DMA32_DCTL_IRQ;
  87         ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT)
  88             & B43_DMA32_DCTL_ADDREXT_MASK;
  89
  90         desc->dma32.control = cpu_to_le32(ctl);
  91         desc->dma32.address = cpu_to_le32(addr);
  92 }
  93
  94 static void op32_poke_tx(struct b43_dmaring *ring, int slot)
  95 {
  96         b43_dma_write(ring, B43_DMA32_TXINDEX,
  97                       (u32) (slot * sizeof(struct b43_dmadesc32)));
  98 }
  99
 100 static void op32_tx_suspend(struct b43_dmaring *ring)
 101 {
 102         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 103                       | B43_DMA32_TXSUSPEND);
 104 }
 105
 106 static void op32_tx_resume(struct b43_dmaring *ring)
 107 {
 108         b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL)
 109                       & ~B43_DMA32_TXSUSPEND);
 110 }
 111
 112 static int op32_get_current_rxslot(struct b43_dmaring *ring)
 113 {
 114         u32 val;
 115
 116         val = b43_dma_read(ring, B43_DMA32_RXSTATUS);
 117         val &= B43_DMA32_RXDPTR;
 118
 119         return (val / sizeof(struct b43_dmadesc32));
 120 }
 121
 122 static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot)
 123 {
 124         b43_dma_write(ring, B43_DMA32_RXINDEX,
 125                       (u32) (slot * sizeof(struct b43_dmadesc32)));
 126 }
 127
 128 static const struct b43_dma_ops dma32_ops = {
 129         .idx2desc = op32_idx2desc,
 130         .fill_descriptor = op32_fill_descriptor,
 131         .poke_tx = op32_poke_tx,
 132         .tx_suspend = op32_tx_suspend,
 133         .tx_resume = op32_tx_resume,
 134         .get_current_rxslot = op32_get_current_rxslot,
 135         .set_current_rxslot = op32_set_current_rxslot,
 136 };
 137
 138 /* 64bit DMA ops. */
 139 static
 140 struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring,
 141                                           int slot,
 142                                           struct b43_dmadesc_meta **meta)
 143 {
 144         struct b43_dmadesc64 *desc;
 145
 146         *meta = &(ring->meta[slot]);
 147         desc = ring->descbase;
 148         desc = &(desc[slot]);
 149
 150         return (struct b43_dmadesc_generic *)desc;
 151 }
 152
 153 static void op64_fill_descriptor(struct b43_dmaring *ring,
 154                                  struct b43_dmadesc_generic *desc,
 155                                  dma_addr_t dmaaddr, u16 bufsize,
 156                                  int start, int end, int irq)
 157 {
 158         struct b43_dmadesc64 *descbase = ring->descbase;
 159         int slot;
 160         u32 ctl0 = 0, ctl1 = 0;
 161         u32 addrlo, addrhi;
 162         u32 addrext;
 163
 164         slot = (int)(&(desc->dma64) - descbase);
 165         B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
 166
 167         addrlo = (u32) (dmaaddr & 0xFFFFFFFF);
 168         addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
 169         addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
 170             >> SSB_DMA_TRANSLATION_SHIFT;
 171         addrhi |= (ssb_dma_translation(ring->dev->dev) << 1);
 172         if (slot == ring->nr_slots - 1)
 173                 ctl0 |= B43_DMA64_DCTL0_DTABLEEND;
 174         if (start)
 175                 ctl0 |= B43_DMA64_DCTL0_FRAMESTART;
 176         if (end)
 177                 ctl0 |= B43_DMA64_DCTL0_FRAMEEND;
 178         if (irq)
 179                 ctl0 |= B43_DMA64_DCTL0_IRQ;
 180         ctl1 |= (bufsize - ring->frameoffset)
 181             & B43_DMA64_DCTL1_BYTECNT;
 182         ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT)
 183             & B43_DMA64_DCTL1_ADDREXT_MASK;
 184
 185         desc->dma64.control0 = cpu_to_le32(ctl0);
 186         desc->dma64.control1 = cpu_to_le32(ctl1);
 187         desc->dma64.address_low = cpu_to_le32(addrlo);
 188         desc->dma64.address_high = cpu_to_le32(addrhi);
 189 }
 190
 191 static void op64_poke_tx(struct b43_dmaring *ring, int slot)
 192 {
 193         b43_dma_write(ring, B43_DMA64_TXINDEX,
 194                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 195 }
 196
 197 static void op64_tx_suspend(struct b43_dmaring *ring)
 198 {
 199         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 200                       | B43_DMA64_TXSUSPEND);
 201 }
 202
 203 static void op64_tx_resume(struct b43_dmaring *ring)
 204 {
 205         b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL)
 206                       & ~B43_DMA64_TXSUSPEND);
 207 }
 208
 209 static int op64_get_current_rxslot(struct b43_dmaring *ring)
 210 {
 211         u32 val;
 212
 213         val = b43_dma_read(ring, B43_DMA64_RXSTATUS);
 214         val &= B43_DMA64_RXSTATDPTR;
 215
 216         return (val / sizeof(struct b43_dmadesc64));
 217 }
 218
 219 static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot)
 220 {
 221         b43_dma_write(ring, B43_DMA64_RXINDEX,
 222                       (u32) (slot * sizeof(struct b43_dmadesc64)));
 223 }
 224
 225 static const struct b43_dma_ops dma64_ops = {
 226         .idx2desc = op64_idx2desc,
 227         .fill_descriptor = op64_fill_descriptor,
 228         .poke_tx = op64_poke_tx,
 229         .tx_suspend = op64_tx_suspend,
 230         .tx_resume = op64_tx_resume,
 231         .get_current_rxslot = op64_get_current_rxslot,
 232         .set_current_rxslot = op64_set_current_rxslot,
 233 };
 234
 235 static inline int free_slots(struct b43_dmaring *ring)
 236 {
 237         return (ring->nr_slots - ring->used_slots);
 238 }
 239
 240 static inline int next_slot(struct b43_dmaring *ring, int slot)
 241 {
 242         B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
 243         if (slot == ring->nr_slots - 1)
 244                 return 0;
 245         return slot + 1;
 246 }
 247
 248 static inline int prev_slot(struct b43_dmaring *ring, int slot)
 249 {
 250         B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
 251         if (slot == 0)
 252                 return ring->nr_slots - 1;
 253         return slot - 1;
 254 }
 255
 256 #ifdef CONFIG_B43_DEBUG
 257 static void update_max_used_slots(struct b43_dmaring *ring,
 258                                   int current_used_slots)
 259 {
 260         if (current_used_slots <= ring->max_used_slots)
 261                 return;
 262         ring->max_used_slots = current_used_slots;
 263         if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) {
 264                 b43dbg(ring->dev->wl,
 265                        "max_used_slots increased to %d on %s ring %d\n",
 266                        ring->max_used_slots,
 267                        ring->tx ? "TX" : "RX", ring->index);
 268         }
 269 }
 270 #else
 271 static inline
 272     void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots)
 273 {
 274 }
 275 #endif /* DEBUG */
 276
 277 /* Request a slot for usage. */
 278 static inline int request_slot(struct b43_dmaring *ring)
 279 {
 280         int slot;
 281
 282         B43_WARN_ON(!ring->tx);
 283         B43_WARN_ON(ring->stopped);
 284         B43_WARN_ON(free_slots(ring) == 0);
 285
 286         slot = next_slot(ring, ring->current_slot);
 287         ring->current_slot = slot;
 288         ring->used_slots++;
 289
 290         update_max_used_slots(ring, ring->used_slots);
 291
 292         return slot;
 293 }
 294
 295 static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx)
 296 {
 297         static const u16 map64[] = {
 298                 B43_MMIO_DMA64_BASE0,
 299                 B43_MMIO_DMA64_BASE1,
 300                 B43_MMIO_DMA64_BASE2,
 301                 B43_MMIO_DMA64_BASE3,
 302                 B43_MMIO_DMA64_BASE4,
 303                 B43_MMIO_DMA64_BASE5,
 304         };
 305         static const u16 map32[] = {
 306                 B43_MMIO_DMA32_BASE0,
 307                 B43_MMIO_DMA32_BASE1,
 308                 B43_MMIO_DMA32_BASE2,
 309                 B43_MMIO_DMA32_BASE3,
 310                 B43_MMIO_DMA32_BASE4,
 311                 B43_MMIO_DMA32_BASE5,
 312         };
 313
 314         if (type == B43_DMA_64BIT) {
 315                 B43_WARN_ON(!(controller_idx >= 0 &&
 316                               controller_idx < ARRAY_SIZE(map64)));
 317                 return map64[controller_idx];
 318         }
 319         B43_WARN_ON(!(controller_idx >= 0 &&
 320                       controller_idx < ARRAY_SIZE(map32)));
 321         return map32[controller_idx];
 322 }
 323
 324 static inline
 325     dma_addr_t map_descbuffer(struct b43_dmaring *ring,
 326                               unsigned char *buf, size_t len, int tx)
 327 {
 328         dma_addr_t dmaaddr;
 329
 330         if (tx) {
 331                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 332                                          buf, len, DMA_TO_DEVICE);
 333         } else {
 334                 dmaaddr = dma_map_single(ring->dev->dev->dev,
 335                                          buf, len, DMA_FROM_DEVICE);
 336         }
 337
 338         return dmaaddr;
 339 }
 340
 341 static inline
 342     void unmap_descbuffer(struct b43_dmaring *ring,
 343                           dma_addr_t addr, size_t len, int tx)
 344 {
 345         if (tx) {
 346                 dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE);
 347         } else {
 348                 dma_unmap_single(ring->dev->dev->dev,
 349                                  addr, len, DMA_FROM_DEVICE);
 350         }
 351 }
 352
 353 static inline
 354     void sync_descbuffer_for_cpu(struct b43_dmaring *ring,
 355                                  dma_addr_t addr, size_t len)
 356 {
 357         B43_WARN_ON(ring->tx);
 358         dma_sync_single_for_cpu(ring->dev->dev->dev,
 359                                 addr, len, DMA_FROM_DEVICE);
 360 }
 361
 362 static inline
 363     void sync_descbuffer_for_device(struct b43_dmaring *ring,
 364                                     dma_addr_t addr, size_t len)
 365 {
 366         B43_WARN_ON(ring->tx);
 367         dma_sync_single_for_device(ring->dev->dev->dev,
 368                                    addr, len, DMA_FROM_DEVICE);
 369 }
 370
 371 static inline
 372     void free_descriptor_buffer(struct b43_dmaring *ring,
 373                                 struct b43_dmadesc_meta *meta)
 374 {
 375         if (meta->skb) {
 376                 dev_kfree_skb_any(meta->skb);
 377                 meta->skb = NULL;
 378         }
 379 }
 380
 381 static int alloc_ringmemory(struct b43_dmaring *ring)
 382 {
 383         struct device *dev = ring->dev->dev->dev;
 384         gfp_t flags = GFP_KERNEL;
 385
 386         /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
 387          * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
 388          * has shown that 4K is sufficient for the latter as long as the buffer
 389          * does not cross an 8K boundary.
 390          *
 391          * For unknown reasons - possibly a hardware error - the BCM4311 rev
 392          * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
 393          * which accounts for the GFP_DMA flag below.
 394          */
 395         if (ring->type == B43_DMA_64BIT)
 396                 flags |= GFP_DMA;
 397         ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE,
 398                                             &(ring->dmabase), flags);
 399         if (!ring->descbase) {
 400                 b43err(ring->dev->wl, "DMA ringmemory allocation failed\n");
 401                 return -ENOMEM;
 402         }
 403         memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE);
 404
 405         return 0;
 406 }
 407
 408 static void free_ringmemory(struct b43_dmaring *ring)
 409 {
 410         struct device *dev = ring->dev->dev->dev;
 411
 412         dma_free_coherent(dev, B43_DMA_RINGMEMSIZE,
 413                           ring->descbase, ring->dmabase);
 414 }
 415
 416 /* Reset the RX DMA channel */
 417 static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base,
 418                                       enum b43_dmatype type)
 419 {
 420         int i;
 421         u32 value;
 422         u16 offset;
 423
 424         might_sleep();
 425
 426         offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL;
 427         b43_write32(dev, mmio_base + offset, 0);
 428         for (i = 0; i < 10; i++) {
 429                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS :
 430                                                    B43_DMA32_RXSTATUS;
 431                 value = b43_read32(dev, mmio_base + offset);
 432                 if (type == B43_DMA_64BIT) {
 433                         value &= B43_DMA64_RXSTAT;
 434                         if (value == B43_DMA64_RXSTAT_DISABLED) {
 435                                 i = -1;
 436                                 break;
 437                         }
 438                 } else {
 439                         value &= B43_DMA32_RXSTATE;
 440                         if (value == B43_DMA32_RXSTAT_DISABLED) {
 441                                 i = -1;
 442                                 break;
 443                         }
 444                 }
 445                 msleep(1);
 446         }
 447         if (i != -1) {
 448                 b43err(dev->wl, "DMA RX reset timed out\n");
 449                 return -ENODEV;
 450         }
 451
 452         return 0;
 453 }
 454
 455 /* Reset the TX DMA channel */
 456 static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base,
 457                                       enum b43_dmatype type)
 458 {
 459         int i;
 460         u32 value;
 461         u16 offset;
 462
 463         might_sleep();
 464
 465         for (i = 0; i < 10; i++) {
 466                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 467                                                    B43_DMA32_TXSTATUS;
 468                 value = b43_read32(dev, mmio_base + offset);
 469                 if (type == B43_DMA_64BIT) {
 470                         value &= B43_DMA64_TXSTAT;
 471                         if (value == B43_DMA64_TXSTAT_DISABLED ||
 472                             value == B43_DMA64_TXSTAT_IDLEWAIT ||
 473                             value == B43_DMA64_TXSTAT_STOPPED)
 474                                 break;
 475                 } else {
 476                         value &= B43_DMA32_TXSTATE;
 477                         if (value == B43_DMA32_TXSTAT_DISABLED ||
 478                             value == B43_DMA32_TXSTAT_IDLEWAIT ||
 479                             value == B43_DMA32_TXSTAT_STOPPED)
 480                                 break;
 481                 }
 482                 msleep(1);
 483         }
 484         offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL;
 485         b43_write32(dev, mmio_base + offset, 0);
 486         for (i = 0; i < 10; i++) {
 487                 offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS :
 488                                                    B43_DMA32_TXSTATUS;
 489                 value = b43_read32(dev, mmio_base + offset);
 490                 if (type == B43_DMA_64BIT) {
 491                         value &= B43_DMA64_TXSTAT;
 492                         if (value == B43_DMA64_TXSTAT_DISABLED) {
 493                                 i = -1;
 494                                 break;
 495                         }
 496                 } else {
 497                         value &= B43_DMA32_TXSTATE;
 498                         if (value == B43_DMA32_TXSTAT_DISABLED) {
 499                                 i = -1;
 500                                 break;
 501                         }
 502                 }
 503                 msleep(1);
 504         }
 505         if (i != -1) {
 506                 b43err(dev->wl, "DMA TX reset timed out\n");
 507                 return -ENODEV;
 508         }
 509         /* ensure the reset is completed. */
 510         msleep(1);
 511
 512         return 0;
 513 }
 514
 515 /* Check if a DMA mapping address is invalid. */
 516 static bool b43_dma_mapping_error(struct b43_dmaring *ring,
 517                                   dma_addr_t addr,
 518                                   size_t buffersize, bool dma_to_device)
 519 {
 520         if (unlikely(dma_mapping_error(addr)))
 521                 return 1;
 522
 523         switch (ring->type) {
 524         case B43_DMA_30BIT:
 525                 if ((u64)addr + buffersize > (1ULL << 30))
 526                         goto address_error;
 527                 break;
 528         case B43_DMA_32BIT:
 529                 if ((u64)addr + buffersize > (1ULL << 32))
 530                         goto address_error;
 531                 break;
 532         case B43_DMA_64BIT:
 533                 /* Currently we can't have addresses beyond
 534                  * 64bit in the kernel. */
 535                 break;
 536         }
 537
 538         /* The address is OK. */
 539         return 0;
 540
 541 address_error:
 542         /* We can't support this address. Unmap it again. */
 543         unmap_descbuffer(ring, addr, buffersize, dma_to_device);
 544
 545         return 1;
 546 }
 547
 548 static int setup_rx_descbuffer(struct b43_dmaring *ring,
 549                                struct b43_dmadesc_generic *desc,
 550                                struct b43_dmadesc_meta *meta, gfp_t gfp_flags)
 551 {
 552         struct b43_rxhdr_fw4 *rxhdr;
 553         dma_addr_t dmaaddr;
 554         struct sk_buff *skb;
 555
 556         B43_WARN_ON(ring->tx);
 557
 558         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 559         if (unlikely(!skb))
 560                 return -ENOMEM;
 561         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 562         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 563                 /* ugh. try to realloc in zone_dma */
 564                 gfp_flags |= GFP_DMA;
 565
 566                 dev_kfree_skb_any(skb);
 567
 568                 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 569                 if (unlikely(!skb))
 570                         return -ENOMEM;
 571                 dmaaddr = map_descbuffer(ring, skb->data,
 572                                          ring->rx_buffersize, 0);
 573         }
 574
 575         if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
 576                 b43err(ring->dev->wl, "RX DMA buffer allocation failed\n");
 577                 dev_kfree_skb_any(skb);
 578                 return -EIO;
 579         }
 580
 581         meta->skb = skb;
 582         meta->dmaaddr = dmaaddr;
 583         ring->ops->fill_descriptor(ring, desc, dmaaddr,
 584                                    ring->rx_buffersize, 0, 0, 0);
 585
 586         rxhdr = (struct b43_rxhdr_fw4 *)(skb->data);
 587         rxhdr->frame_len = 0;
 588
 589         return 0;
 590 }
 591
 592 /* Allocate the initial descbuffers.
 593  * This is used for an RX ring only.
 594  */
 595 static int alloc_initial_descbuffers(struct b43_dmaring *ring)
 596 {
 597         int i, err = -ENOMEM;
 598         struct b43_dmadesc_generic *desc;
 599         struct b43_dmadesc_meta *meta;
 600
 601         for (i = 0; i < ring->nr_slots; i++) {
 602                 desc = ring->ops->idx2desc(ring, i, &meta);
 603
 604                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 605                 if (err) {
 606                         b43err(ring->dev->wl,
 607                                "Failed to allocate initial descbuffers\n");
 608                         goto err_unwind;
 609                 }
 610         }
 611         mb();
 612         ring->used_slots = ring->nr_slots;
 613         err = 0;
 614       out:
 615         return err;
 616
 617       err_unwind:
 618         for (i--; i >= 0; i--) {
 619                 desc = ring->ops->idx2desc(ring, i, &meta);
 620
 621                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 622                 dev_kfree_skb(meta->skb);
 623         }
 624         goto out;
 625 }
 626
 627 /* Do initial setup of the DMA controller.
 628  * Reset the controller, write the ring busaddress
 629  * and switch the "enable" bit on.
 630  */
 631 static int dmacontroller_setup(struct b43_dmaring *ring)
 632 {
 633         int err = 0;
 634         u32 value;
 635         u32 addrext;
 636         u32 trans = ssb_dma_translation(ring->dev->dev);
 637
 638         if (ring->tx) {
 639                 if (ring->type == B43_DMA_64BIT) {
 640                         u64 ringbase = (u64) (ring->dmabase);
 641
 642                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 643                             >> SSB_DMA_TRANSLATION_SHIFT;
 644                         value = B43_DMA64_TXENABLE;
 645                         value |= (addrext << B43_DMA64_TXADDREXT_SHIFT)
 646                             & B43_DMA64_TXADDREXT_MASK;
 647                         b43_dma_write(ring, B43_DMA64_TXCTL, value);
 648                         b43_dma_write(ring, B43_DMA64_TXRINGLO,
 649                                       (ringbase & 0xFFFFFFFF));
 650                         b43_dma_write(ring, B43_DMA64_TXRINGHI,
 651                                       ((ringbase >> 32) &
 652                                        ~SSB_DMA_TRANSLATION_MASK)
 653                                       | (trans << 1));
 654                 } else {
 655                         u32 ringbase = (u32) (ring->dmabase);
 656
 657                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 658                             >> SSB_DMA_TRANSLATION_SHIFT;
 659                         value = B43_DMA32_TXENABLE;
 660                         value |= (addrext << B43_DMA32_TXADDREXT_SHIFT)
 661                             & B43_DMA32_TXADDREXT_MASK;
 662                         b43_dma_write(ring, B43_DMA32_TXCTL, value);
 663                         b43_dma_write(ring, B43_DMA32_TXRING,
 664                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 665                                       | trans);
 666                 }
 667         } else {
 668                 err = alloc_initial_descbuffers(ring);
 669                 if (err)
 670                         goto out;
 671                 if (ring->type == B43_DMA_64BIT) {
 672                         u64 ringbase = (u64) (ring->dmabase);
 673
 674                         addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
 675                             >> SSB_DMA_TRANSLATION_SHIFT;
 676                         value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT);
 677                         value |= B43_DMA64_RXENABLE;
 678                         value |= (addrext << B43_DMA64_RXADDREXT_SHIFT)
 679                             & B43_DMA64_RXADDREXT_MASK;
 680                         b43_dma_write(ring, B43_DMA64_RXCTL, value);
 681                         b43_dma_write(ring, B43_DMA64_RXRINGLO,
 682                                       (ringbase & 0xFFFFFFFF));
 683                         b43_dma_write(ring, B43_DMA64_RXRINGHI,
 684                                       ((ringbase >> 32) &
 685                                        ~SSB_DMA_TRANSLATION_MASK)
 686                                       | (trans << 1));
 687                         b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots *
 688                                       sizeof(struct b43_dmadesc64));
 689                 } else {
 690                         u32 ringbase = (u32) (ring->dmabase);
 691
 692                         addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
 693                             >> SSB_DMA_TRANSLATION_SHIFT;
 694                         value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT);
 695                         value |= B43_DMA32_RXENABLE;
 696                         value |= (addrext << B43_DMA32_RXADDREXT_SHIFT)
 697                             & B43_DMA32_RXADDREXT_MASK;
 698                         b43_dma_write(ring, B43_DMA32_RXCTL, value);
 699                         b43_dma_write(ring, B43_DMA32_RXRING,
 700                                       (ringbase & ~SSB_DMA_TRANSLATION_MASK)
 701                                       | trans);
 702                         b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots *
 703                                       sizeof(struct b43_dmadesc32));
 704                 }
 705         }
 706
 707 out:
 708         return err;
 709 }
 710
 711 /* Shutdown the DMA controller. */
 712 static void dmacontroller_cleanup(struct b43_dmaring *ring)
 713 {
 714         if (ring->tx) {
 715                 b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
 716                                            ring->type);
 717                 if (ring->type == B43_DMA_64BIT) {
 718                         b43_dma_write(ring, B43_DMA64_TXRINGLO, 0);
 719                         b43_dma_write(ring, B43_DMA64_TXRINGHI, 0);
 720                 } else
 721                         b43_dma_write(ring, B43_DMA32_TXRING, 0);
 722         } else {
 723                 b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
 724                                            ring->type);
 725                 if (ring->type == B43_DMA_64BIT) {
 726                         b43_dma_write(ring, B43_DMA64_RXRINGLO, 0);
 727                         b43_dma_write(ring, B43_DMA64_RXRINGHI, 0);
 728                 } else
 729                         b43_dma_write(ring, B43_DMA32_RXRING, 0);
 730         }
 731 }
 732
 733 static void free_all_descbuffers(struct b43_dmaring *ring)
 734 {
 735         struct b43_dmadesc_generic *desc;
 736         struct b43_dmadesc_meta *meta;
 737         int i;
 738
 739         if (!ring->used_slots)
 740                 return;
 741         for (i = 0; i < ring->nr_slots; i++) {
 742                 desc = ring->ops->idx2desc(ring, i, &meta);
 743
 744                 if (!meta->skb) {
 745                         B43_WARN_ON(!ring->tx);
 746                         continue;
 747                 }
 748                 if (ring->tx) {
 749                         unmap_descbuffer(ring, meta->dmaaddr,
 750                                          meta->skb->len, 1);
 751                 } else {
 752                         unmap_descbuffer(ring, meta->dmaaddr,
 753                                          ring->rx_buffersize, 0);
 754                 }
 755                 free_descriptor_buffer(ring, meta);
 756         }
 757 }
 758
 759 static u64 supported_dma_mask(struct b43_wldev *dev)
 760 {
 761         u32 tmp;
 762         u16 mmio_base;
 763
 764         tmp = b43_read32(dev, SSB_TMSHIGH);
 765         if (tmp & SSB_TMSHIGH_DMA64)
 766                 return DMA_64BIT_MASK;
 767         mmio_base = b43_dmacontroller_base(0, 0);
 768         b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK);
 769         tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL);
 770         if (tmp & B43_DMA32_TXADDREXT_MASK)
 771                 return DMA_32BIT_MASK;
 772
 773         return DMA_30BIT_MASK;
 774 }
 775
 776 static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask)
 777 {
 778         if (dmamask == DMA_30BIT_MASK)
 779                 return B43_DMA_30BIT;
 780         if (dmamask == DMA_32BIT_MASK)
 781                 return B43_DMA_32BIT;
 782         if (dmamask == DMA_64BIT_MASK)
 783                 return B43_DMA_64BIT;
 784         B43_WARN_ON(1);
 785         return B43_DMA_30BIT;
 786 }
 787
 788 /* Main initialization function. */
 789 static
 790 struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev,
 791                                       int controller_index,
 792                                       int for_tx,
 793                                       enum b43_dmatype type)
 794 {
 795         struct b43_dmaring *ring;
 796         int err;
 797         int nr_slots;
 798         dma_addr_t dma_test;
 799
 800         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 801         if (!ring)
 802                 goto out;
 803         ring->type = type;
 804
 805         nr_slots = B43_RXRING_SLOTS;
 806         if (for_tx)
 807                 nr_slots = B43_TXRING_SLOTS;
 808
 809         ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta),
 810                              GFP_KERNEL);
 811         if (!ring->meta)
 812                 goto err_kfree_ring;
 813         if (for_tx) {
 814                 ring->txhdr_cache = kcalloc(nr_slots,
 815                                             b43_txhdr_size(dev),
 816                                             GFP_KERNEL);
 817                 if (!ring->txhdr_cache)
 818                         goto err_kfree_meta;
 819
 820                 /* test for ability to dma to txhdr_cache */
 821                 dma_test = dma_map_single(dev->dev->dev,
 822                                           ring->txhdr_cache,
 823                                           b43_txhdr_size(dev),
 824                                           DMA_TO_DEVICE);
 825
 826                 if (b43_dma_mapping_error(ring, dma_test,
 827                                           b43_txhdr_size(dev), 1)) {
 828                         /* ugh realloc */
 829                         kfree(ring->txhdr_cache);
 830                         ring->txhdr_cache = kcalloc(nr_slots,
 831                                                     b43_txhdr_size(dev),
 832                                                     GFP_KERNEL | GFP_DMA);
 833                         if (!ring->txhdr_cache)
 834                                 goto err_kfree_meta;
 835
 836                         dma_test = dma_map_single(dev->dev->dev,
 837                                                   ring->txhdr_cache,
 838                                                   b43_txhdr_size(dev),
 839                                                   DMA_TO_DEVICE);
 840
 841                         if (b43_dma_mapping_error(ring, dma_test,
 842                                                   b43_txhdr_size(dev), 1)) {
 843
 844                                 b43err(dev->wl,
 845                                        "TXHDR DMA allocation failed\n");
 846                                 goto err_kfree_txhdr_cache;
 847                         }
 848                 }
 849
 850                 dma_unmap_single(dev->dev->dev,
 851                                  dma_test, b43_txhdr_size(dev),
 852                                  DMA_TO_DEVICE);
 853         }
 854
 855         ring->dev = dev;
 856         ring->nr_slots = nr_slots;
 857         ring->mmio_base = b43_dmacontroller_base(type, controller_index);
 858         ring->index = controller_index;
 859         if (type == B43_DMA_64BIT)
 860                 ring->ops = &dma64_ops;
 861         else
 862                 ring->ops = &dma32_ops;
 863         if (for_tx) {
 864                 ring->tx = 1;
 865                 ring->current_slot = -1;
 866         } else {
 867                 if (ring->index == 0) {
 868                         ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE;
 869                         ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET;
 870                 } else if (ring->index == 3) {
 871                         ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE;
 872                         ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET;
 873                 } else
 874                         B43_WARN_ON(1);
 875         }
 876         spin_lock_init(&ring->lock);
 877 #ifdef CONFIG_B43_DEBUG
 878         ring->last_injected_overflow = jiffies;
 879 #endif
 880
 881         err = alloc_ringmemory(ring);
 882         if (err)
 883                 goto err_kfree_txhdr_cache;
 884         err = dmacontroller_setup(ring);
 885         if (err)
 886                 goto err_free_ringmemory;
 887
 888       out:
 889         return ring;
 890
 891       err_free_ringmemory:
 892         free_ringmemory(ring);
 893       err_kfree_txhdr_cache:
 894         kfree(ring->txhdr_cache);
 895       err_kfree_meta:
 896         kfree(ring->meta);
 897       err_kfree_ring:
 898         kfree(ring);
 899         ring = NULL;
 900         goto out;
 901 }
 902
 903 #define divide(a, b)    ({      \
 904         typeof(a) __a = a;      \
 905         do_div(__a, b);         \
 906         __a;                    \
 907   })
 908
 909 #define modulo(a, b)    ({      \
 910         typeof(a) __a = a;      \
 911         do_div(__a, b);         \
 912   })
 913
 914 /* Main cleanup function. */
 915 static void b43_destroy_dmaring(struct b43_dmaring *ring,
 916                                 const char *ringname)
 917 {
 918         if (!ring)
 919                 return;
 920
 921 #ifdef CONFIG_B43_DEBUG
 922         {
 923                 /* Print some statistics. */
 924                 u64 failed_packets = ring->nr_failed_tx_packets;
 925                 u64 succeed_packets = ring->nr_succeed_tx_packets;
 926                 u64 nr_packets = failed_packets + succeed_packets;
 927                 u64 permille_failed = 0, average_tries = 0;
 928
 929                 if (nr_packets)
 930                         permille_failed = divide(failed_packets * 1000, nr_packets);
 931                 if (nr_packets)
 932                         average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets);
 933
 934                 b43dbg(ring->dev->wl, "DMA-%u %s: "
 935                        "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
 936                        "Average tries %llu.%02llu\n",
 937                        (unsigned int)(ring->type), ringname,
 938                        ring->max_used_slots,
 939                        ring->nr_slots,
 940                        (unsigned long long)failed_packets,
 941                        (unsigned long long)nr_packets,
 942                        (unsigned long long)divide(permille_failed, 10),
 943                        (unsigned long long)modulo(permille_failed, 10),
 944                        (unsigned long long)divide(average_tries, 100),
 945                        (unsigned long long)modulo(average_tries, 100));
 946         }
 947 #endif /* DEBUG */
 948
 949         /* Device IRQs are disabled prior entering this function,
 950          * so no need to take care of concurrency with rx handler stuff.
 951          */
 952         dmacontroller_cleanup(ring);
 953         free_all_descbuffers(ring);
 954         free_ringmemory(ring);
 955
 956         kfree(ring->txhdr_cache);
 957         kfree(ring->meta);
 958         kfree(ring);
 959 }
 960
 961 #define destroy_ring(dma, ring) do {                            \
 962         b43_destroy_dmaring((dma)->ring, __stringify(ring));    \
 963         (dma)->ring = NULL;                                     \
 964     } while (0)
 965
 966 void b43_dma_free(struct b43_wldev *dev)
 967 {
 968         struct b43_dma *dma;
 969
 970         if (b43_using_pio_transfers(dev))
 971                 return;
 972         dma = &dev->dma;
 973
 974         destroy_ring(dma, rx_ring);
 975         destroy_ring(dma, tx_ring_AC_BK);
 976         destroy_ring(dma, tx_ring_AC_BE);
 977         destroy_ring(dma, tx_ring_AC_VI);
 978         destroy_ring(dma, tx_ring_AC_VO);
 979         destroy_ring(dma, tx_ring_mcast);
 980 }
 981
 982 int b43_dma_init(struct b43_wldev *dev)
 983 {
 984         struct b43_dma *dma = &dev->dma;
 985         int err;
 986         u64 dmamask;
 987         enum b43_dmatype type;
 988
 989         dmamask = supported_dma_mask(dev);
 990         type = dma_mask_to_engine_type(dmamask);
 991         err = ssb_dma_set_mask(dev->dev, dmamask);
 992         if (err) {
 993                 b43err(dev->wl, "The machine/kernel does not support "
 994                        "the required DMA mask (0x%08X%08X)\n",
 995                        (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32),
 996                        (unsigned int)(dmamask & 0x00000000FFFFFFFFULL));
 997                 return -EOPNOTSUPP;
 998         }
 999
1000         err = -ENOMEM;
1001         /* setup TX DMA channels. */
1002         dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type);
1003         if (!dma->tx_ring_AC_BK)
1004                 goto out;
1005
1006         dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type);
1007         if (!dma->tx_ring_AC_BE)
1008                 goto err_destroy_bk;
1009
1010         dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type);
1011         if (!dma->tx_ring_AC_VI)
1012                 goto err_destroy_be;
1013
1014         dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type);
1015         if (!dma->tx_ring_AC_VO)
1016                 goto err_destroy_vi;
1017
1018         dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type);
1019         if (!dma->tx_ring_mcast)
1020                 goto err_destroy_vo;
1021
1022         /* setup RX DMA channel. */
1023         dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type);
1024         if (!dma->rx_ring)
1025                 goto err_destroy_mcast;
1026
1027         /* No support for the TX status DMA ring. */
1028         B43_WARN_ON(dev->dev->id.revision < 5);
1029
1030         b43dbg(dev->wl, "%u-bit DMA initialized\n",
1031                (unsigned int)type);
1032         err = 0;
1033 out:
1034         return err;
1035
1036 err_destroy_mcast:
1037         destroy_ring(dma, tx_ring_mcast);
1038 err_destroy_vo:
1039         destroy_ring(dma, tx_ring_AC_VO);
1040 err_destroy_vi:
1041         destroy_ring(dma, tx_ring_AC_VI);
1042 err_destroy_be:
1043         destroy_ring(dma, tx_ring_AC_BE);
1044 err_destroy_bk:
1045         destroy_ring(dma, tx_ring_AC_BK);
1046         return err;
1047 }
1048
1049 /* Generate a cookie for the TX header. */
1050 static u16 generate_cookie(struct b43_dmaring *ring, int slot)
1051 {
1052         u16 cookie;
1053
1054         /* Use the upper 4 bits of the cookie as
1055          * DMA controller ID and store the slot number
1056          * in the lower 12 bits.
1057          * Note that the cookie must never be 0, as this
1058          * is a special value used in RX path.
1059          * It can also not be 0xFFFF because that is special
1060          * for multicast frames.
1061          */
1062         cookie = (((u16)ring->index + 1) << 12);
1063         B43_WARN_ON(slot & ~0x0FFF);
1064         cookie |= (u16)slot;
1065
1066         return cookie;
1067 }
1068
1069 /* Inspect a cookie and find out to which controller/slot it belongs. */
1070 static
1071 struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot)
1072 {
1073         struct b43_dma *dma = &dev->dma;
1074         struct b43_dmaring *ring = NULL;
1075
1076         switch (cookie & 0xF000) {
1077         case 0x1000:
1078                 ring = dma->tx_ring_AC_BK;
1079                 break;
1080         case 0x2000:
1081                 ring = dma->tx_ring_AC_BE;
1082                 break;
1083         case 0x3000:
1084                 ring = dma->tx_ring_AC_VI;
1085                 break;
1086         case 0x4000:
1087                 ring = dma->tx_ring_AC_VO;
1088                 break;
1089         case 0x5000:
1090                 ring = dma->tx_ring_mcast;
1091                 break;
1092         default:
1093                 B43_WARN_ON(1);
1094         }
1095         *slot = (cookie & 0x0FFF);
1096         B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1097
1098         return ring;
1099 }
1100
1101 static int dma_tx_fragment(struct b43_dmaring *ring,
1102                            struct sk_buff *skb,
1103                            struct ieee80211_tx_control *ctl)
1104 {
1105         const struct b43_dma_ops *ops = ring->ops;
1106         u8 *header;
1107         int slot, old_top_slot, old_used_slots;
1108         int err;
1109         struct b43_dmadesc_generic *desc;
1110         struct b43_dmadesc_meta *meta;
1111         struct b43_dmadesc_meta *meta_hdr;
1112         struct sk_buff *bounce_skb;
1113         u16 cookie;
1114         size_t hdrsize = b43_txhdr_size(ring->dev);
1115
1116 #define SLOTS_PER_PACKET  2
1117
1118         old_top_slot = ring->current_slot;
1119         old_used_slots = ring->used_slots;
1120
1121         /* Get a slot for the header. */
1122         slot = request_slot(ring);
1123         desc = ops->idx2desc(ring, slot, &meta_hdr);
1124         memset(meta_hdr, 0, sizeof(*meta_hdr));
1125
1126         header = &(ring->txhdr_cache[slot * hdrsize]);
1127         cookie = generate_cookie(ring, slot);
1128         err = b43_generate_txhdr(ring->dev, header,
1129                                  skb->data, skb->len, ctl, cookie);
1130         if (unlikely(err)) {
1131                 ring->current_slot = old_top_slot;
1132                 ring->used_slots = old_used_slots;
1133                 return err;
1134         }
1135
1136         meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1137                                            hdrsize, 1);
1138         if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) {
1139                 ring->current_slot = old_top_slot;
1140                 ring->used_slots = old_used_slots;
1141                 return -EIO;
1142         }
1143         ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1144                              hdrsize, 1, 0, 0);
1145
1146         /* Get a slot for the payload. */
1147         slot = request_slot(ring);
1148         desc = ops->idx2desc(ring, slot, &meta);
1149         memset(meta, 0, sizeof(*meta));
1150
1151         memcpy(&meta->txstat.control, ctl, sizeof(*ctl));
1152         meta->skb = skb;
1153         meta->is_last_fragment = 1;
1154
1155         meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1156         /* create a bounce buffer in zone_dma on mapping failure. */
1157         if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1158                 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1159                 if (!bounce_skb) {
1160                         ring->current_slot = old_top_slot;
1161                         ring->used_slots = old_used_slots;
1162                         err = -ENOMEM;
1163                         goto out_unmap_hdr;
1164                 }
1165
1166                 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1167                 dev_kfree_skb_any(skb);
1168                 skb = bounce_skb;
1169                 meta->skb = skb;
1170                 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1171                 if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1172                         ring->current_slot = old_top_slot;
1173                         ring->used_slots = old_used_slots;
1174                         err = -EIO;
1175                         goto out_free_bounce;
1176                 }
1177         }
1178
1179         ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1);
1180
1181         if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1182                 /* Tell the firmware about the cookie of the last
1183                  * mcast frame, so it can clear the more-data bit in it. */
1184                 b43_shm_write16(ring->dev, B43_SHM_SHARED,
1185                                 B43_SHM_SH_MCASTCOOKIE, cookie);
1186         }
1187         /* Now transfer the whole frame. */
1188         wmb();
1189         ops->poke_tx(ring, next_slot(ring, slot));
1190         return 0;
1191
1192 out_free_bounce:
1193         dev_kfree_skb_any(skb);
1194 out_unmap_hdr:
1195         unmap_descbuffer(ring, meta_hdr->dmaaddr,
1196                          hdrsize, 1);
1197         return err;
1198 }
1199
1200 static inline int should_inject_overflow(struct b43_dmaring *ring)
1201 {
1202 #ifdef CONFIG_B43_DEBUG
1203         if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) {
1204                 /* Check if we should inject another ringbuffer overflow
1205                  * to test handling of this situation in the stack. */
1206                 unsigned long next_overflow;
1207
1208                 next_overflow = ring->last_injected_overflow + HZ;
1209                 if (time_after(jiffies, next_overflow)) {
1210                         ring->last_injected_overflow = jiffies;
1211                         b43dbg(ring->dev->wl,
1212                                "Injecting TX ring overflow on "
1213                                "DMA controller %d\n", ring->index);
1214                         return 1;
1215                 }
1216         }
1217 #endif /* CONFIG_B43_DEBUG */
1218         return 0;
1219 }
1220
1221 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1222 static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev,
1223                                                     u8 queue_prio)
1224 {
1225         struct b43_dmaring *ring;
1226
1227         if (b43_modparam_qos) {
1228                 /* 0 = highest priority */
1229                 switch (queue_prio) {
1230                 default:
1231                         B43_WARN_ON(1);
1232                         /* fallthrough */
1233                 case 0:
1234                         ring = dev->dma.tx_ring_AC_VO;
1235                         break;
1236                 case 1:
1237                         ring = dev->dma.tx_ring_AC_VI;
1238                         break;
1239                 case 2:
1240                         ring = dev->dma.tx_ring_AC_BE;
1241                         break;
1242                 case 3:
1243                         ring = dev->dma.tx_ring_AC_BK;
1244                         break;
1245                 }
1246         } else
1247                 ring = dev->dma.tx_ring_AC_BE;
1248
1249         return ring;
1250 }
1251
1252 int b43_dma_tx(struct b43_wldev *dev,
1253                struct sk_buff *skb, struct ieee80211_tx_control *ctl)
1254 {
1255         struct b43_dmaring *ring;
1256         struct ieee80211_hdr *hdr;
1257         int err = 0;
1258         unsigned long flags;
1259
1260         hdr = (struct ieee80211_hdr *)skb->data;
1261         if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) {
1262                 /* The multicast ring will be sent after the DTIM */
1263                 ring = dev->dma.tx_ring_mcast;
1264                 /* Set the more-data bit. Ucode will clear it on
1265                  * the last frame for us. */
1266                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
1267         } else {
1268                 /* Decide by priority where to put this frame. */
1269                 ring = select_ring_by_priority(dev, ctl->queue);
1270         }
1271
1272         spin_lock_irqsave(&ring->lock, flags);
1273         B43_WARN_ON(!ring->tx);
1274         if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) {
1275                 b43warn(dev->wl, "DMA queue overflow\n");
1276                 err = -ENOSPC;
1277                 goto out_unlock;
1278         }
1279         /* Check if the queue was stopped in mac80211,
1280          * but we got called nevertheless.
1281          * That would be a mac80211 bug. */
1282         B43_WARN_ON(ring->stopped);
1283
1284         /* Assign the queue number to the ring (if not already done before)
1285          * so TX status handling can use it. The queue to ring mapping is
1286          * static, so we don't need to store it per frame. */
1287         ring->queue_prio = ctl->queue;
1288
1289         err = dma_tx_fragment(ring, skb, ctl);
1290         if (unlikely(err == -ENOKEY)) {
1291                 /* Drop this packet, as we don't have the encryption key
1292                  * anymore and must not transmit it unencrypted. */
1293                 dev_kfree_skb_any(skb);
1294                 err = 0;
1295                 goto out_unlock;
1296         }
1297         if (unlikely(err)) {
1298                 b43err(dev->wl, "DMA tx mapping failure\n");
1299                 goto out_unlock;
1300         }
1301         ring->nr_tx_packets++;
1302         if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1303             should_inject_overflow(ring)) {
1304                 /* This TX ring is full. */
1305                 ieee80211_stop_queue(dev->wl->hw, ctl->queue);
1306                 ring->stopped = 1;
1307                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1308                         b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index);
1309                 }
1310         }
1311 out_unlock:
1312         spin_unlock_irqrestore(&ring->lock, flags);
1313
1314         return err;
1315 }
1316
1317 /* Called with IRQs disabled. */
1318 void b43_dma_handle_txstatus(struct b43_wldev *dev,
1319                              const struct b43_txstatus *status)
1320 {
1321         const struct b43_dma_ops *ops;
1322         struct b43_dmaring *ring;
1323         struct b43_dmadesc_generic *desc;
1324         struct b43_dmadesc_meta *meta;
1325         int slot;
1326         bool frame_succeed;
1327
1328         ring = parse_cookie(dev, status->cookie, &slot);
1329         if (unlikely(!ring))
1330                 return;
1331
1332         spin_lock(&ring->lock); /* IRQs are already disabled. */
1333
1334         B43_WARN_ON(!ring->tx);
1335         ops = ring->ops;
1336         while (1) {
1337                 B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1338                 desc = ops->idx2desc(ring, slot, &meta);
1339
1340                 if (meta->skb)
1341                         unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len,
1342                                          1);
1343                 else
1344                         unmap_descbuffer(ring, meta->dmaaddr,
1345                                          b43_txhdr_size(dev), 1);
1346
1347                 if (meta->is_last_fragment) {
1348                         B43_WARN_ON(!meta->skb);
1349                         /* Call back to inform the ieee80211 subsystem about the
1350                          * status of the transmission.
1351                          * Some fields of txstat are already filled in dma_tx().
1352                          */
1353                         frame_succeed = b43_fill_txstatus_report(
1354                                                 &(meta->txstat), status);
1355 #ifdef CONFIG_B43_DEBUG
1356                         if (frame_succeed)
1357                                 ring->nr_succeed_tx_packets++;
1358                         else
1359                                 ring->nr_failed_tx_packets++;
1360                         ring->nr_total_packet_tries += status->frame_count;
1361 #endif /* DEBUG */
1362                         ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb,
1363                                                     &(meta->txstat));
1364                         /* skb is freed by ieee80211_tx_status_irqsafe() */
1365                         meta->skb = NULL;
1366                 } else {
1367                         /* No need to call free_descriptor_buffer here, as
1368                          * this is only the txhdr, which is not allocated.
1369                          */
1370                         B43_WARN_ON(meta->skb);
1371                 }
1372
1373                 /* Everything unmapped and free'd. So it's not used anymore. */
1374                 ring->used_slots--;
1375
1376                 if (meta->is_last_fragment)
1377                         break;
1378                 slot = next_slot(ring, slot);
1379         }
1380         dev->stats.last_tx = jiffies;
1381         if (ring->stopped) {
1382                 B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1383                 ieee80211_wake_queue(dev->wl->hw, ring->queue_prio);
1384                 ring->stopped = 0;
1385                 if (b43_debug(dev, B43_DBG_DMAVERBOSE)) {
1386                         b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index);
1387                 }
1388         }
1389
1390         spin_unlock(&ring->lock);
1391 }
1392
1393 void b43_dma_get_tx_stats(struct b43_wldev *dev,
1394                           struct ieee80211_tx_queue_stats *stats)
1395 {
1396         const int nr_queues = dev->wl->hw->queues;
1397         struct b43_dmaring *ring;
1398         struct ieee80211_tx_queue_stats_data *data;
1399         unsigned long flags;
1400         int i;
1401
1402         for (i = 0; i < nr_queues; i++) {
1403                 data = &(stats->data[i]);
1404                 ring = select_ring_by_priority(dev, i);
1405
1406                 spin_lock_irqsave(&ring->lock, flags);
1407                 data->len = ring->used_slots / SLOTS_PER_PACKET;
1408                 data->limit = ring->nr_slots / SLOTS_PER_PACKET;
1409                 data->count = ring->nr_tx_packets;
1410                 spin_unlock_irqrestore(&ring->lock, flags);
1411         }
1412 }
1413
1414 static void dma_rx(struct b43_dmaring *ring, int *slot)
1415 {
1416         const struct b43_dma_ops *ops = ring->ops;
1417         struct b43_dmadesc_generic *desc;
1418         struct b43_dmadesc_meta *meta;
1419         struct b43_rxhdr_fw4 *rxhdr;
1420         struct sk_buff *skb;
1421         u16 len;
1422         int err;
1423         dma_addr_t dmaaddr;
1424
1425         desc = ops->idx2desc(ring, *slot, &meta);
1426
1427         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1428         skb = meta->skb;
1429
1430         rxhdr = (struct b43_rxhdr_fw4 *)skb->data;
1431         len = le16_to_cpu(rxhdr->frame_len);
1432         if (len == 0) {
1433                 int i = 0;
1434
1435                 do {
1436                         udelay(2);
1437                         barrier();
1438                         len = le16_to_cpu(rxhdr->frame_len);
1439                 } while (len == 0 && i++ < 5);
1440                 if (unlikely(len == 0)) {
1441                         /* recycle the descriptor buffer. */
1442                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1443                                                    ring->rx_buffersize);
1444                         goto drop;
1445                 }
1446         }
1447         if (unlikely(len > ring->rx_buffersize)) {
1448                 /* The data did not fit into one descriptor buffer
1449                  * and is split over multiple buffers.
1450                  * This should never happen, as we try to allocate buffers
1451                  * big enough. So simply ignore this packet.
1452                  */
1453                 int cnt = 0;
1454                 s32 tmp = len;
1455
1456                 while (1) {
1457                         desc = ops->idx2desc(ring, *slot, &meta);
1458                         /* recycle the descriptor buffer. */
1459                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1460                                                    ring->rx_buffersize);
1461                         *slot = next_slot(ring, *slot);
1462                         cnt++;
1463                         tmp -= ring->rx_buffersize;
1464                         if (tmp <= 0)
1465                                 break;
1466                 }
1467                 b43err(ring->dev->wl, "DMA RX buffer too small "
1468                        "(len: %u, buffer: %u, nr-dropped: %d)\n",
1469                        len, ring->rx_buffersize, cnt);
1470                 goto drop;
1471         }
1472
1473         dmaaddr = meta->dmaaddr;
1474         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1475         if (unlikely(err)) {
1476                 b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n");
1477                 sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize);
1478                 goto drop;
1479         }
1480
1481         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1482         skb_put(skb, len + ring->frameoffset);
1483         skb_pull(skb, ring->frameoffset);
1484
1485         b43_rx(ring->dev, skb, rxhdr);
1486 drop:
1487         return;
1488 }
1489
1490 void b43_dma_rx(struct b43_dmaring *ring)
1491 {
1492         const struct b43_dma_ops *ops = ring->ops;
1493         int slot, current_slot;
1494         int used_slots = 0;
1495
1496         B43_WARN_ON(ring->tx);
1497         current_slot = ops->get_current_rxslot(ring);
1498         B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots));
1499
1500         slot = ring->current_slot;
1501         for (; slot != current_slot; slot = next_slot(ring, slot)) {
1502                 dma_rx(ring, &slot);
1503                 update_max_used_slots(ring, ++used_slots);
1504         }
1505         ops->set_current_rxslot(ring, slot);
1506         ring->current_slot = slot;
1507 }
1508
1509 static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring)
1510 {
1511         unsigned long flags;
1512
1513         spin_lock_irqsave(&ring->lock, flags);
1514         B43_WARN_ON(!ring->tx);
1515         ring->ops->tx_suspend(ring);
1516         spin_unlock_irqrestore(&ring->lock, flags);
1517 }
1518
1519 static void b43_dma_tx_resume_ring(struct b43_dmaring *ring)
1520 {
1521         unsigned long flags;
1522
1523         spin_lock_irqsave(&ring->lock, flags);
1524         B43_WARN_ON(!ring->tx);
1525         ring->ops->tx_resume(ring);
1526         spin_unlock_irqrestore(&ring->lock, flags);
1527 }
1528
1529 void b43_dma_tx_suspend(struct b43_wldev *dev)
1530 {
1531         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1532         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK);
1533         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE);
1534         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI);
1535         b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO);
1536         b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast);
1537 }
1538
1539 void b43_dma_tx_resume(struct b43_wldev *dev)
1540 {
1541         b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast);
1542         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO);
1543         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI);
1544         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE);
1545         b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK);
1546         b43_power_saving_ctl_bits(dev, 0);
1547 }
1548
1549 #ifdef CONFIG_B43_PIO
1550 static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type,
1551                            u16 mmio_base, bool enable)
1552 {
1553         u32 ctl;
1554
1555         if (type == B43_DMA_64BIT) {
1556                 ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL);
1557                 ctl &= ~B43_DMA64_RXDIRECTFIFO;
1558                 if (enable)
1559                         ctl |= B43_DMA64_RXDIRECTFIFO;
1560                 b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl);
1561         } else {
1562                 ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL);
1563                 ctl &= ~B43_DMA32_RXDIRECTFIFO;
1564                 if (enable)
1565                         ctl |= B43_DMA32_RXDIRECTFIFO;
1566                 b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl);
1567         }
1568 }
1569
1570 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1571  * This is called from PIO code, so DMA structures are not available. */
1572 void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
1573                             unsigned int engine_index, bool enable)
1574 {
1575         enum b43_dmatype type;
1576         u16 mmio_base;
1577
1578         type = dma_mask_to_engine_type(supported_dma_mask(dev));
1579
1580         mmio_base = b43_dmacontroller_base(type, engine_index);
1581         direct_fifo_rx(dev, type, mmio_base, enable);
1582 }
1583 #endif /* CONFIG_B43_PIO */