1 /* linux/arch/arm/mach-s3c2412/s3c2412-irq.c
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/ptrace.h>
27 #include <linux/sysdev.h>
29 #include <asm/hardware.h>
33 #include <asm/mach/irq.h>
35 #include <asm/arch/regs-irq.h>
36 #include <asm/arch/regs-gpio.h>
41 /* the s3c2412 changes the behaviour of IRQ_EINT0 through IRQ_EINT3 by
42 * having them turn up in both the INT* and the EINT* registers. Whilst
43 * both show the status, they both now need to be acked when the IRQs
48 s3c2412_irq_mask(unsigned int irqno)
50 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
53 mask = __raw_readl(S3C2410_INTMSK);
54 __raw_writel(mask | bitval, S3C2410_INTMSK);
56 mask = __raw_readl(S3C2412_EINTMASK);
57 __raw_writel(mask | bitval, S3C2412_EINTMASK);
61 s3c2412_irq_ack(unsigned int irqno)
63 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
65 __raw_writel(bitval, S3C2412_EINTPEND);
66 __raw_writel(bitval, S3C2410_SRCPND);
67 __raw_writel(bitval, S3C2410_INTPND);
71 s3c2412_irq_maskack(unsigned int irqno)
73 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
76 mask = __raw_readl(S3C2410_INTMSK);
77 __raw_writel(mask|bitval, S3C2410_INTMSK);
79 mask = __raw_readl(S3C2412_EINTMASK);
80 __raw_writel(mask | bitval, S3C2412_EINTMASK);
82 __raw_writel(bitval, S3C2412_EINTPEND);
83 __raw_writel(bitval, S3C2410_SRCPND);
84 __raw_writel(bitval, S3C2410_INTPND);
88 s3c2412_irq_unmask(unsigned int irqno)
90 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
93 mask = __raw_readl(S3C2412_EINTMASK);
94 __raw_writel(mask & ~bitval, S3C2412_EINTMASK);
96 mask = __raw_readl(S3C2410_INTMSK);
97 __raw_writel(mask & ~bitval, S3C2410_INTMSK);
100 static struct irqchip s3c2412_irq_eint0t4 = {
101 .ack = s3c2412_irq_ack,
102 .mask = s3c2412_irq_mask,
103 .unmask = s3c2412_irq_unmask,
104 .set_wake = s3c_irq_wake,
105 .set_type = s3c_irqext_type,
108 static int s3c2412_irq_add(struct sys_device *sysdev)
112 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
113 set_irq_chip(irqno, &s3c2412_irq_eint0t4);
114 set_irq_handler(irqno, do_edge_IRQ);
115 set_irq_flags(irqno, IRQF_VALID);
121 static struct sysdev_driver s3c2412_irq_driver = {
122 .add = s3c2412_irq_add,
125 static int s3c2412_irq_init(void)
127 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
130 arch_initcall(s3c2412_irq_init);