2 * arch/sh/kernel/cpu/init.c
6 * Copyright (C) 2002 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/kernel.h>
16 #include <linux/log2.h>
17 #include <asm/mmu_context.h>
18 #include <asm/processor.h>
19 #include <asm/uaccess.h>
21 #include <asm/system.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cache.h>
27 #ifdef CONFIG_SUPERH32
32 * Generic wrapper for command line arguments to disable on-chip
33 * peripherals (nofpu, nodsp, and so forth).
35 #define onchip_setup(x) \
36 static int x##_disabled __initdata = 0; \
38 static int __init x##_setup(char *opts) \
43 __setup("no" __stringify(x), x##_setup);
48 #ifdef CONFIG_SPECULATIVE_EXECUTION
49 #define CPUOPM 0xff2f0000
50 #define CPUOPM_RABD (1 << 5)
52 static void __init speculative_execution_init(void)
55 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
57 /* Flush the update */
58 (void)ctrl_inl(CPUOPM);
62 #define speculative_execution_init() do { } while (0)
66 * Generic first-level cache init
68 #ifdef CONFIG_SUPERH32
69 static void __uses_jump_to_uncached cache_init(void)
71 unsigned long ccr, flags;
77 * At this point we don't know whether the cache is enabled or not - a
78 * bootloader may have enabled it. There are at least 2 things that
79 * could be dirty in the cache at this point:
80 * 1. kernel command line set up by boot loader
81 * 2. spilled registers from the prolog of this function
82 * => before re-initialising the cache, we must do a purge of the whole
83 * cache out to memory for safety. As long as nothing is spilled
84 * during the loop to lines that have already been done, this is safe.
87 if (ccr & CCR_CACHE_ENABLE) {
88 unsigned long ways, waysize, addrstart;
90 waysize = current_cpu_data.dcache.sets;
94 * If the OC is already in RAM mode, we only have
95 * half of the entries to flush..
97 if (ccr & CCR_CACHE_ORA)
101 waysize <<= current_cpu_data.dcache.entry_shift;
103 #ifdef CCR_CACHE_EMODE
104 /* If EMODE is not set, we only have 1 way to flush. */
105 if (!(ccr & CCR_CACHE_EMODE))
109 ways = current_cpu_data.dcache.ways;
111 addrstart = CACHE_OC_ADDRESS_ARRAY;
115 for (addr = addrstart;
116 addr < addrstart + waysize;
117 addr += current_cpu_data.dcache.linesz)
120 addrstart += current_cpu_data.dcache.way_incr;
125 * Default CCR values .. enable the caches
126 * and invalidate them immediately..
128 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
130 #ifdef CCR_CACHE_EMODE
131 /* Force EMODE if possible */
132 if (current_cpu_data.dcache.ways > 1)
133 flags |= CCR_CACHE_EMODE;
135 flags &= ~CCR_CACHE_EMODE;
138 #if defined(CONFIG_CACHE_WRITETHROUGH)
140 flags |= CCR_CACHE_WT;
141 #elif defined(CONFIG_CACHE_WRITEBACK)
143 flags |= CCR_CACHE_CB;
146 flags &= ~CCR_CACHE_ENABLE;
149 ctrl_outl(flags, CCR);
153 #define cache_init() do { } while (0)
156 #define CSHAPE(totalsize, linesize, assoc) \
157 ((totalsize & ~0xff) | (linesize << 4) | assoc)
159 #define CACHE_DESC_SHAPE(desc) \
160 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
162 static void detect_cache_shape(void)
164 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
166 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
167 l1i_cache_shape = l1d_cache_shape;
169 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
171 if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
172 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
174 l2_cache_shape = -1; /* No S-cache */
178 static void __init release_dsp(void)
182 /* Clear SR.DSP bit */
183 __asm__ __volatile__ (
192 static void __init dsp_init(void)
197 * Set the SR.DSP bit, wait for one instruction, and then read
200 __asm__ __volatile__ (
210 /* If the DSP bit is still set, this CPU has a DSP */
212 current_cpu_data.flags |= CPU_HAS_DSP;
214 /* Now that we've determined the DSP status, clear the DSP bit. */
217 #endif /* CONFIG_SH_DSP */
222 * This is our initial entry point for each CPU, and is invoked on the boot
223 * CPU prior to calling start_kernel(). For SMP, a combination of this and
224 * start_secondary() will bring up each processor to a ready state prior
225 * to hand forking the idle loop.
227 * We do all of the basic processor init here, including setting up the
228 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
229 * hit (and subsequently platform_setup()) things like determining the
230 * CPU subtype and initial configuration will all be done.
232 * Each processor family is still responsible for doing its own probing
233 * and cache configuration in detect_cpu_and_cache_system().
236 asmlinkage void __init sh_cpu_init(void)
238 current_thread_info()->cpu = hard_smp_processor_id();
240 /* First, probe the CPU */
241 detect_cpu_and_cache_system();
243 if (current_cpu_data.type == CPU_SH_NONE)
244 panic("Unknown CPU");
246 /* First setup the rest of the I-cache info */
247 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
248 current_cpu_data.icache.linesz;
250 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
251 current_cpu_data.icache.linesz;
253 /* And the D-cache too */
254 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
255 current_cpu_data.dcache.linesz;
257 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
258 current_cpu_data.dcache.linesz;
263 if (raw_smp_processor_id() == 0) {
265 shm_align_mask = max_t(unsigned long,
266 current_cpu_data.dcache.way_size - 1,
270 /* Boot CPU sets the cache shape */
271 detect_cache_shape();
274 /* Disable the FPU */
276 printk("FPU Disabled\n");
277 current_cpu_data.flags &= ~CPU_HAS_FPU;
281 /* FPU initialization */
282 if ((current_cpu_data.flags & CPU_HAS_FPU)) {
283 clear_thread_flag(TIF_USEDFPU);
288 * Initialize the per-CPU ASID cache very early, since the
289 * TLB flushing routines depend on this being setup.
291 current_cpu_data.asid_cache = NO_CONTEXT;
297 /* Disable the DSP */
299 printk("DSP Disabled\n");
300 current_cpu_data.flags &= ~CPU_HAS_DSP;
306 * Some brain-damaged loaders decided it would be a good idea to put
307 * the UBC to sleep. This causes some issues when it comes to things
308 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
309 * we wake it up and hope that all is well.
311 #ifdef CONFIG_SUPERH32
312 if (raw_smp_processor_id() == 0)
316 speculative_execution_init();