2 * Adaptec U320 device driver firmware for Linux and FreeBSD.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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38 * POSSIBILITY OF SUCH DAMAGES.
43 VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#119 $"
44 PATCH_ARG_LIST = "struct ahd_softc *ahd"
47 #include "aic79xx.reg"
48 #include "scsi_message.h"
51 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
52 test SEQINTCODE, 0xFF jz idle_loop;
53 SET_SEQINTCODE(NO_SEQINT)
58 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60 * Convert ERROR status into a sequencer
61 * interrupt to handle the case of an
62 * interrupt collision on the hardware
65 test ERROR, 0xFF jz no_error_set;
66 SET_SEQINTCODE(SAW_HWERR)
69 SET_MODE(M_SCSI, M_SCSI)
70 test SCSISEQ0, ENSELO|ENARBO jnz idle_loop_checkbus;
71 test SEQ_FLAGS2, SELECTOUT_QFROZEN jz check_waiting_list;
73 * If the kernel has caught up with us, thaw the queue.
75 mov A, KERNEL_QFREEZE_COUNT;
76 cmp QFREEZE_COUNT, A jne check_frozen_completions;
77 mov A, KERNEL_QFREEZE_COUNT[1];
78 cmp QFREEZE_COUNT[1], A jne check_frozen_completions;
79 and SEQ_FLAGS2, ~SELECTOUT_QFROZEN;
80 jmp check_waiting_list;
81 check_frozen_completions:
82 test SSTAT0, SELDO|SELINGO jnz idle_loop_checkbus;
85 * If we have completions stalled waiting for the qfreeze
86 * to take effect, move them over to the complete_scb list
87 * now that no selections are pending.
89 cmp COMPLETE_ON_QFREEZE_HEAD[1],SCB_LIST_NULL je idle_loop_checkbus;
91 * Find the end of the qfreeze list. The first element has
92 * to be treated specially.
94 bmov SCBPTR, COMPLETE_ON_QFREEZE_HEAD, 2;
95 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je join_lists;
97 * Now the normal loop.
99 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
100 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
102 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
103 bmov COMPLETE_SCB_HEAD, COMPLETE_ON_QFREEZE_HEAD, 2;
104 mvi COMPLETE_ON_QFREEZE_HEAD[1], SCB_LIST_NULL;
105 jmp idle_loop_checkbus;
107 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je idle_loop_checkbus;
109 * ENSELO is cleared by a SELDO, so we must test for SELDO
112 test SSTAT0, SELDO jnz select_out;
114 call start_selection;
117 test SSTAT0, SELDO jnz select_out;
119 test SSTAT0, SELDI jnz select_in;
120 test SCSIPHASE, ~DATA_PHASE_MASK jz idle_loop_check_nonpackreq;
121 test SCSISIGO, ATNO jz idle_loop_check_nonpackreq;
122 call unexpected_nonpkt_phase_find_ctxt;
123 idle_loop_check_nonpackreq:
124 test SSTAT2, NONPACKREQ jz . + 2;
125 call unexpected_nonpkt_phase_find_ctxt;
126 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
128 * On Rev A. hardware, the busy LED is only
129 * turned on automaically during selections
130 * and re-selections. Make the LED status
131 * more useful by forcing it to be on so
132 * long as one of our data FIFOs is active.
134 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
135 cmp A, FIFO0FREE|FIFO1FREE jne . + 3;
136 and SBLKCTL, ~DIAGLEDEN|DIAGLEDON;
138 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
140 call idle_loop_gsfifo_in_scsi_mode;
141 call idle_loop_service_fifos;
142 call idle_loop_cchan;
146 SET_MODE(M_SCSI, M_SCSI)
148 idle_loop_gsfifo_in_scsi_mode:
149 test LQISTAT2, LQIGSAVAIL jz return;
151 * We have received good status for this transaction. There may
152 * still be data in our FIFOs draining to the host. Complete
153 * the SCB only if all data has transferred to the host.
156 bmov SCBPTR, GSFIFO, 2;
159 * If a command completed before an attempted task management
160 * function completed, notify the host after disabling any
161 * pending select-outs.
163 test SCB_TASK_MANAGEMENT, 0xFF jz gsfifo_complete_normally;
164 test SSTAT0, SELDO|SELINGO jnz . + 2;
165 and SCSISEQ0, ~ENSELO;
166 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
167 gsfifo_complete_normally:
168 or SCB_CONTROL, STATUS_RCVD;
171 * Since this status did not consume a FIFO, we have to
172 * be a bit more dilligent in how we check for FIFOs pertaining
173 * to this transaction. There are two states that a FIFO still
174 * transferring data may be in.
176 * 1) Configured and draining to the host, with a FIFO handler.
177 * 2) Pending cfg4data, fifo not empty.
179 * Case 1 can be detected by noticing a non-zero FIFO active
180 * count in the SCB. In this case, we allow the routine servicing
181 * the FIFO to complete the SCB.
183 * Case 2 implies either a pending or yet to occur save data
184 * pointers for this same context in the other FIFO. So, if
185 * we detect case 1, we will properly defer the post of the SCB
186 * and achieve the desired result. The pending cfg4data will
187 * notice that status has been received and complete the SCB.
189 test SCB_FIFO_USE_COUNT, 0xFF jnz idle_loop_gsfifo_in_scsi_mode;
192 jmp idle_loop_gsfifo_in_scsi_mode;
194 idle_loop_service_fifos:
195 SET_MODE(M_DFF0, M_DFF0)
197 test LONGJMP_ADDR[1], INVALID_ADDR jnz idle_loop_next_fifo;
201 SET_MODE(M_DFF1, M_DFF1)
203 test LONGJMP_ADDR[1], INVALID_ADDR jz longjmp;
209 SET_MODE(M_CCHAN, M_CCHAN)
210 test QOFF_CTLSTA, HS_MAILBOX_ACT jz hs_mailbox_empty;
211 or QOFF_CTLSTA, HS_MAILBOX_ACT;
212 mov LOCAL_HS_MAILBOX, HS_MAILBOX;
215 test CCSCBCTL, CCARREN|CCSCBEN jz scbdma_idle;
216 test CCSCBCTL, CCSCBDIR jnz fetch_new_scb_inprog;
217 test CCSCBCTL, CCSCBDONE jz return;
220 test CCSCBCTL, CCARREN jz fill_qoutfifo_dmadone;
222 * An SCB has been succesfully uploaded to the host.
223 * If the SCB was uploaded for some reason other than
224 * bad SCSI status (currently only for underruns), we
225 * queue the SCB for normal completion. Otherwise, we
226 * wait until any select-out activity has halted, and
227 * then queue the completion.
229 and CCSCBCTL, ~(CCARREN|CCSCBEN);
230 bmov COMPLETE_DMA_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
231 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . + 2;
232 mvi COMPLETE_DMA_SCB_TAIL[1], SCB_LIST_NULL;
233 test SCB_SCSI_STATUS, 0xff jz scbdma_queue_completion;
234 bmov SCB_NEXT_COMPLETE, COMPLETE_ON_QFREEZE_HEAD, 2;
235 bmov COMPLETE_ON_QFREEZE_HEAD, SCBPTR, 2 ret;
236 scbdma_queue_completion:
237 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
238 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
239 fill_qoutfifo_dmadone:
240 and CCSCBCTL, ~(CCARREN|CCSCBEN);
241 call qoutfifo_updated;
242 mvi COMPLETE_SCB_DMAINPROG_HEAD[1], SCB_LIST_NULL;
243 bmov QOUTFIFO_NEXT_ADDR, SCBHADDR, 4;
244 test QOFF_CTLSTA, SDSCB_ROLLOVR jz return;
245 bmov QOUTFIFO_NEXT_ADDR, SHARED_DATA_ADDR, 4;
246 xor QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID_TOGGLE ret;
251 * If there are more commands waiting to be dma'ed
252 * to the host, always coalesce. Otherwise honor the
255 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
256 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL jne coalesce_by_count;
257 test LOCAL_HS_MAILBOX, ENINT_COALESCE jz issue_cmdcmplt;
260 * If we have relatively few commands outstanding, don't
261 * bother waiting for another command to complete.
263 test CMDS_PENDING[1], 0xFF jnz coalesce_by_count;
264 /* Add -1 so that jnc means <= not just < */
265 add A, -1, INT_COALESCING_MINCMDS;
266 add NONE, A, CMDS_PENDING;
270 * If coalescing, only coalesce up to the limit
271 * provided by the host driver.
274 mov A, INT_COALESCING_MAXCMDS;
275 add NONE, A, INT_COALESCING_CMDCOUNT;
278 * If the timer is not currently active,
281 test INTCTL, SWTMINTMASK jz return;
282 bmov SWTIMER, INT_COALESCING_TIMER, 2;
283 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
284 or INTCTL, SWTMINTEN|SWTIMER_START;
285 and INTCTL, ~SWTMINTMASK ret;
288 mvi INTSTAT, CMDCMPLT;
289 clr INT_COALESCING_CMDCOUNT;
290 or INTCTL, SWTMINTMASK ret;
293 fetch_new_scb_inprog:
294 test CCSCBCTL, ARRDONE jz return;
296 and CCSCBCTL, ~(CCARREN|CCSCBEN);
297 bmov REG0, SCBPTR, 2;
300 adc CMDS_PENDING[1], A;
301 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
303 * "Short Luns" are not placed into outgoing LQ
304 * packets in the correct byte order. Use a full
305 * sized lun field instead and fill it with the
306 * one byte of lun information we support.
308 mov SCB_PKT_LUN[6], SCB_LUN;
311 * The FIFO use count field is shared with the
312 * tag set by the host so that our SCB dma engine
313 * knows the correct location to store the SCB.
314 * Set it to zero before processing the SCB.
316 clr SCB_FIFO_USE_COUNT;
317 /* Update the next SCB address to download. */
318 bmov NEXT_QUEUED_SCB_ADDR, SCB_NEXT_SCB_BUSADDR, 4;
319 mvi SCB_NEXT[1], SCB_LIST_NULL;
320 mvi SCB_NEXT2[1], SCB_LIST_NULL;
321 /* Increment our position in the QINFIFO. */
322 mov NONE, SNSCB_QOFF;
324 * SCBs that want to send messages are always
325 * queued independently. This ensures that they
326 * are at the head of the SCB list to select out
327 * to a target and we will see the MK_MESSAGE flag.
329 test SCB_CONTROL, MK_MESSAGE jnz first_new_target_scb;
330 shr SINDEX, 3, SCB_SCSIID;
332 mvi SINDEX[1], (WAITING_SCB_TAILS >> 8);
333 bmov DINDEX, SINDEX, 2;
334 bmov SCBPTR, SINDIR, 2;
335 bmov DINDIR, REG0, 2;
336 cmp SCBPTR[1], SCB_LIST_NULL je first_new_target_scb;
337 bmov SCB_NEXT, REG0, 2 ret;
338 first_new_target_scb:
339 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL je first_new_scb;
340 bmov SCBPTR, WAITING_TID_TAIL, 2;
341 bmov SCB_NEXT2, REG0, 2;
342 bmov WAITING_TID_TAIL, REG0, 2 ret;
344 bmov WAITING_TID_HEAD, REG0, 2;
345 bmov WAITING_TID_TAIL, REG0, 2 ret;
350 * Give precedence to downloading new SCBs to execute
351 * unless select-outs are currently frozen.
353 test SEQ_FLAGS2, SELECTOUT_QFROZEN jnz . + 2;
355 test QOFF_CTLSTA, NEW_SCB_AVAIL jnz fetch_new_scb;
356 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne dma_complete_scb;
357 cmp COMPLETE_SCB_HEAD[1], SCB_LIST_NULL je return;
361 * Keep track of the SCBs we are dmaing just
362 * in case the DMA fails or is aborted.
364 bmov COMPLETE_SCB_DMAINPROG_HEAD, COMPLETE_SCB_HEAD, 2;
365 mvi CCSCBCTL, CCSCBRESET;
366 bmov SCBHADDR, QOUTFIFO_NEXT_ADDR, 4;
367 mov A, QOUTFIFO_NEXT_ADDR;
368 bmov SCBPTR, COMPLETE_SCB_HEAD, 2;
370 bmov CCSCBRAM, SCBPTR, 2;
371 mov CCSCBRAM, SCB_SGPTR[0];
372 mov CCSCBRAM, QOUTFIFO_ENTRY_VALID_TAG;
373 mov NONE, SDSCB_QOFF;
374 inc INT_COALESCING_CMDCOUNT;
375 add CMDS_PENDING, -1;
376 adc CMDS_PENDING[1], -1;
377 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL je fill_qoutfifo_done;
378 cmp CCSCBADDR, CCSCBADDR_MAX je fill_qoutfifo_done;
379 test QOFF_CTLSTA, SDSCB_ROLLOVR jnz fill_qoutfifo_done;
381 * Don't cross an ADB or Cachline boundary when DMA'ing
382 * completion entries. In PCI mode, at least in 32/33
383 * configurations, the SCB DMA engine may lose its place
384 * in the data-stream should the target force a retry on
385 * something other than an 8byte aligned boundary. In
386 * PCI-X mode, we do this to avoid split transactions since
387 * many chipsets seem to be unable to format proper split
388 * completions to continue the data transfer.
390 add SINDEX, A, CCSCBADDR;
391 test SINDEX, CACHELINE_MASK jz fill_qoutfifo_done;
392 bmov SCBPTR, SCB_NEXT_COMPLETE, 2;
393 jmp fill_qoutfifo_loop;
395 mov SCBHCNT, CCSCBADDR;
396 mvi CCSCBCTL, CCSCBEN|CCSCBRESET;
397 bmov COMPLETE_SCB_HEAD, SCB_NEXT_COMPLETE, 2;
398 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL ret;
401 bmov SCBHADDR, NEXT_QUEUED_SCB_ADDR, 4;
402 mvi CCARREN|CCSCBEN|CCSCBDIR|CCSCBRESET jmp dma_scb;
404 bmov SCBPTR, COMPLETE_DMA_SCB_HEAD, 2;
405 bmov SCBHADDR, SCB_BUSADDR, 4;
406 mvi CCARREN|CCSCBEN|CCSCBRESET jmp dma_scb;
409 * Either post or fetch an SCB from host memory. The caller
410 * is responsible for polling for transfer completion.
412 * Prerequisits: Mode == M_CCHAN
413 * SINDEX contains CCSCBCTL flags
414 * SCBHADDR set to Host SCB address
415 * SCBPTR set to SCB src location on "push" operations
417 SET_SRC_MODE M_CCHAN;
418 SET_DST_MODE M_CCHAN;
420 mvi SCBHCNT, SCB_TRANSFER_SIZE;
421 mov CCSCBCTL, SINDEX ret;
425 * At least on the A, a return in the same
426 * instruction as the bmov results in a return
427 * to the caller, not to the new address at the
428 * top of the stack. Since we want the latter
429 * (we use setjmp to register a handler from an
430 * interrupt context but not invoke that handler
431 * until we return to our idle loop), use a
432 * separate ret instruction.
434 bmov LONGJMP_ADDR, STACK, 2;
437 bmov LONGJMP_ADDR, STACK, 2;
439 bmov STACK, LONGJMP_ADDR, 2 ret;
442 /*************************** Chip Bug Work Arounds ****************************/
444 * Must disable interrupts when setting the mode pointer
445 * register as an interrupt occurring mid update will
446 * fail to store the new mode value for restoration on
449 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
450 set_mode_work_around:
451 mvi SEQINTCTL, INTVEC1DSL;
452 mov MODE_PTR, SINDEX;
457 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
458 set_seqint_work_around:
459 mov SEQINTCODE, SINDEX;
460 mvi SEQINTCODE, NO_SEQINT ret;
463 /************************ Packetized LongJmp Routines *************************/
468 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
471 * Rev A hardware fails to update LAST/CURR/NEXTSCB
472 * correctly after a packetized selection in several
475 * 1) If only one command existed in the queue, the
476 * LAST/CURR/NEXTSCB are unchanged.
478 * 2) In a non QAS, protocol allowed phase change,
479 * the queue is shifted 1 too far. LASTSCB is
480 * the last SCB that was correctly processed.
482 * 3) In the QAS case, if the full list of commands
483 * was successfully sent, NEXTSCB is NULL and neither
484 * CURRSCB nor LASTSCB can be trusted. We must
485 * manually walk the list counting MAXCMDCNT elements
486 * to find the last SCB that was sent correctly.
488 * To simplify the workaround for this bug in SELDO
489 * handling, we initialize LASTSCB prior to enabling
490 * selection so we can rely on it even for case #1 above.
492 bmov LASTSCB, WAITING_TID_HEAD, 2;
494 bmov CURRSCB, WAITING_TID_HEAD, 2;
495 bmov SCBPTR, WAITING_TID_HEAD, 2;
496 shr SELOID, 4, SCB_SCSIID;
498 * If we want to send a message to the device, ensure
499 * we are selecting with atn irregardless of our packetized
500 * agreement. Since SPI4 only allows target reset or PPR
501 * messages if this is a packetized connection, the change
502 * to our negotiation table entry for this selection will
503 * be cleared when the message is acted on.
505 test SCB_CONTROL, MK_MESSAGE jz . + 3;
506 mov NEGOADDR, SELOID;
507 or NEGCONOPTS, ENAUTOATNO;
508 or SCSISEQ0, ENSELO ret;
512 * Allocate a FIFO for a non-packetized transaction.
513 * In RevA hardware, both FIFOs must be free before we
514 * can allocate a FIFO for a non-packetized transaction.
518 * Do whatever work is required to free a FIFO.
520 call idle_loop_service_fifos;
521 SET_MODE(M_SCSI, M_SCSI)
523 if ((ahd->bugs & AHD_NONPACKFIFO_BUG) != 0) {
524 and A, FIFO0FREE|FIFO1FREE, DFFSTAT;
525 cmp A, FIFO0FREE|FIFO1FREE jne allocate_fifo_loop;
527 test DFFSTAT, FIFO1FREE jnz allocate_fifo1;
528 test DFFSTAT, FIFO0FREE jz allocate_fifo_loop;
529 mvi DFFSTAT, B_CURRFIFO_0;
530 SET_MODE(M_DFF0, M_DFF0)
531 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
536 mvi DFFSTAT, CURRFIFO_1;
537 SET_MODE(M_DFF1, M_DFF1)
538 bmov SCBPTR, ALLOCFIFO_SCBPTR, 2 ret;
541 * We have been reselected as an initiator
542 * or selected as a target.
547 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
549 * On Rev A. hardware, the busy LED is only
550 * turned on automaically during selections
551 * and re-selections. Make the LED status
552 * more useful by forcing it to be on from
553 * the point of selection until our idle
554 * loop determines that neither of our FIFOs
555 * are busy. This handles the non-packetized
556 * case nicely as we will not return to the
557 * idle loop until the busfree at the end of
560 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
562 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
564 * Test to ensure that the bus has not
565 * already gone free prior to clearing
566 * any stale busfree status. This avoids
567 * a window whereby a busfree just after
568 * a selection could be missed.
570 test SCSISIGI, BSYI jz . + 2;
571 mvi CLRSINT1,CLRBUSFREE;
572 or SIMODE1, ENBUSFREE;
575 and SAVED_SCSIID, SELID_MASK, SELID;
578 mvi CLRSINT0, CLRSELDI;
582 * We have successfully selected out.
585 * Dequeue all SCBs sent from the waiting queue
586 * Requeue all SCBs *not* sent to the tail of the waiting queue
587 * Take Razor #494 into account for above.
589 * In Packetized Mode:
590 * Return to the idle loop. Our interrupt handler will take
591 * care of any incoming L_Qs.
593 * In Non-Packetize Mode:
594 * Continue to our normal state machine.
600 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
602 * On Rev A. hardware, the busy LED is only
603 * turned on automaically during selections
604 * and re-selections. Make the LED status
605 * more useful by forcing it to be on from
606 * the point of re-selection until our idle
607 * loop determines that neither of our FIFOs
608 * are busy. This handles the non-packetized
609 * case nicely as we will not return to the
610 * idle loop until the busfree at the end of
613 or SBLKCTL, DIAGLEDEN|DIAGLEDON;
615 /* Clear out all SCBs that have been successfully sent. */
616 if ((ahd->bugs & AHD_SENT_SCB_UPDATE_BUG) != 0) {
618 * For packetized, the LQO manager clears ENSELO on
619 * the assertion of SELDO. If we are non-packetized,
620 * LASTSCB and CURRSCB are accurate.
622 test SCSISEQ0, ENSELO jnz use_lastscb;
625 * The update is correct for LQOSTAT1 errors. All
626 * but LQOBUSFREE are handled by kernel interrupts.
627 * If we see LQOBUSFREE, return to the idle loop.
628 * Once we are out of the select_out critical section,
629 * the kernel will cleanup the LQOBUSFREE and we will
630 * eventually restart the selection if appropriate.
632 test LQOSTAT1, LQOBUSFREE jnz idle_loop;
635 * On a phase change oustside of packet boundaries,
636 * LASTSCB points to the currently active SCB context
639 test LQOSTAT2, LQOPHACHGOUTPKT jnz use_lastscb;
642 * If the hardware has traversed the whole list, NEXTSCB
643 * will be NULL, CURRSCB and LASTSCB cannot be trusted,
644 * but MAXCMDCNT is accurate. If we stop part way through
645 * the list or only had one command to issue, NEXTSCB[1] is
646 * not NULL and LASTSCB is the last command to go out.
648 cmp NEXTSCB[1], SCB_LIST_NULL jne use_lastscb;
653 bmov SCBPTR, WAITING_TID_HEAD, 2;
654 mvi SEQINTCTL, INTVEC1DSL;
655 mvi MODE_PTR, MK_MODE(M_CFG, M_CFG);
657 mvi MODE_PTR, MK_MODE(M_SCSI, M_SCSI);
661 test A, 0xFF jz found_last_sent_scb;
662 bmov SCBPTR, SCB_NEXT, 2;
663 jmp find_lastscb_loop;
665 bmov SCBPTR, LASTSCB, 2;
667 bmov CURRSCB, SCBPTR, 2;
670 bmov SCBPTR, CURRSCB, 2;
674 * Requeue any SCBs not sent, to the tail of the waiting Q.
676 cmp SCB_NEXT[1], SCB_LIST_NULL je select_out_list_done;
679 * We know that neither the per-TID list nor the list of
680 * TIDs is empty. Use this knowledge to our advantage.
682 bmov REG0, SCB_NEXT, 2;
683 bmov SCBPTR, WAITING_TID_TAIL, 2;
684 bmov SCB_NEXT2, REG0, 2;
685 bmov WAITING_TID_TAIL, REG0, 2;
686 jmp select_out_inc_tid_q;
688 select_out_list_done:
690 * The whole list made it. Just clear our TID's tail pointer
691 * unless we were queued independently due to our need to
694 test SCB_CONTROL, MK_MESSAGE jnz select_out_inc_tid_q;
695 shr DINDEX, 3, SCB_SCSIID;
696 or DINDEX, 1; /* Want only the second byte */
697 mvi DINDEX[1], ((WAITING_SCB_TAILS) >> 8);
698 mvi DINDIR, SCB_LIST_NULL;
699 select_out_inc_tid_q:
700 bmov SCBPTR, WAITING_TID_HEAD, 2;
701 bmov WAITING_TID_HEAD, SCB_NEXT2, 2;
702 cmp WAITING_TID_HEAD[1], SCB_LIST_NULL jne . + 2;
703 mvi WAITING_TID_TAIL[1], SCB_LIST_NULL;
704 bmov SCBPTR, CURRSCB, 2;
705 mvi CLRSINT0, CLRSELDO;
706 test LQOSTAT2, LQOPHACHGOUTPKT jnz unexpected_nonpkt_phase;
707 test LQOSTAT1, LQOPHACHGINPKT jnz unexpected_nonpkt_phase;
710 * If this is a packetized connection, return to our
711 * idle_loop and let our interrupt handler deal with
712 * any connection setup/teardown issues. The only
713 * exceptions are the case of MK_MESSAGE and task management
716 if ((ahd->bugs & AHD_LQO_ATNO_BUG) != 0) {
718 * In the A, the LQO manager transitions to LQOSTOP0 even if
719 * we have selected out with ATN asserted and the target
720 * REQs in a non-packet phase.
722 test SCB_CONTROL, MK_MESSAGE jz select_out_no_message;
723 test SCSISIGO, ATNO jnz select_out_non_packetized;
724 select_out_no_message:
726 test LQOSTAT2, LQOSTOP0 jz select_out_non_packetized;
727 test SCB_TASK_MANAGEMENT, 0xFF jz idle_loop;
728 SET_SEQINTCODE(TASKMGMT_FUNC_COMPLETE)
731 select_out_non_packetized:
732 /* Non packetized request. */
733 and SCSISEQ0, ~ENSELO;
734 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
736 * Test to ensure that the bus has not
737 * already gone free prior to clearing
738 * any stale busfree status. This avoids
739 * a window whereby a busfree just after
740 * a selection could be missed.
742 test SCSISIGI, BSYI jz . + 2;
743 mvi CLRSINT1,CLRBUSFREE;
744 or SIMODE1, ENBUSFREE;
746 mov SAVED_SCSIID, SCB_SCSIID;
747 mov SAVED_LUN, SCB_LUN;
748 mvi SEQ_FLAGS, NO_CDB_SENT;
753 * As soon as we get a successful selection, the target
754 * should go into the message out phase since we have ATN
757 mvi MSG_OUT, MSG_IDENTIFYFLAG;
760 * Main loop for information transfer phases. Wait for the
761 * target to assert REQ before checking MSG, C/D and I/O for
770 test A, ~P_DATAIN_DT jz p_data;
771 cmp A,P_COMMAND je p_command;
772 cmp A,P_MESGOUT je p_mesgout;
773 cmp A,P_STATUS je p_status;
774 cmp A,P_MESGIN je p_mesgin;
776 SET_SEQINTCODE(BAD_PHASE)
777 jmp ITloop; /* Try reading the bus again. */
780 * Command phase. Set up the DMA registers and let 'er rip.
783 test SEQ_FLAGS, NOT_IDENTIFIED jz p_command_okay;
784 SET_SEQINTCODE(PROTO_VIOLATION)
786 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
787 jnz p_command_allocate_fifo;
789 * Command retry. Free our current FIFO and
790 * re-allocate a FIFO so transfer state is
795 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
796 SET_MODE(M_SCSI, M_SCSI)
797 p_command_allocate_fifo:
798 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
802 add NONE, -17, SCB_CDB_LEN;
803 jnc p_command_embedded;
805 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
806 mvi SG_CACHE_PRE, LAST_SEG;
807 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
810 bmov SHCNT[0], SCB_CDB_LEN, 1;
811 bmov DFDAT, SCB_CDB_STORE, 16;
814 and SEQ_FLAGS, ~NO_CDB_SENT;
815 if ((ahd->features & AHD_FAST_CDB_DELIVERY) != 0) {
817 * To speed up CDB delivery in Rev B, all CDB acks
818 * are "released" to the output sync as soon as the
819 * command phase starts. There is only one problem
820 * with this approach. If the target changes phase
821 * before all data are sent, we have left over acks
822 * that can go out on the bus in a data phase. Due
823 * to other chip contraints, this only happens if
824 * the target goes to data-in, but if the acks go
825 * out before we can test SDONE, we'll think that
826 * the transfer has completed successfully. Work
827 * around this by taking advantage of the 400ns or
828 * 800ns dead time between command phase and the REQ
829 * of the new phase. If the transfer has completed
830 * successfully, SCSIEN should fall *long* before we
831 * see a phase change. We thus treat any phasemiss
832 * that occurs before SCSIEN falls as an incomplete
835 test SSTAT1, PHASEMIS jnz p_command_xfer_failed;
836 test DFCNTRL, SCSIEN jnz . - 1;
838 test DFCNTRL, SCSIEN jnz .;
841 * DMA Channel automatically disabled.
842 * Don't allow a data phase if the command
843 * was not fully transferred.
845 test SSTAT2, SDONE jnz ITloop;
846 p_command_xfer_failed:
847 or SEQ_FLAGS, NO_CDB_SENT;
852 * Status phase. Wait for the data byte to appear, then read it
853 * and store it into the SCB.
858 test SEQ_FLAGS,NOT_IDENTIFIED jnz mesgin_proto_violation;
860 mov SCB_SCSI_STATUS, SCSIDAT;
861 or SCB_CONTROL, STATUS_RCVD;
865 * Message out phase. If MSG_OUT is MSG_IDENTIFYFLAG, build a full
866 * indentify message sequence and send it to the target. The host may
867 * override this behavior by setting the MK_MESSAGE bit in the SCB
868 * control byte. This will cause us to interrupt the host and allow
869 * it to handle the message phase completely on its own. If the bit
870 * associated with this target is set, we will also interrupt the host,
871 * thereby allowing it to send a message on the next selection regardless
872 * of the transaction being sent.
874 * If MSG_OUT is == HOST_MSG, also interrupt the host and take a message.
875 * This is done to allow the host to send messages outside of an identify
876 * sequence while protecting the seqencer from testing the MK_MESSAGE bit
877 * on an SCB that might not be for the current nexus. (For example, a
878 * BDR message in responce to a bad reselection would leave us pointed to
879 * an SCB that doesn't have anything to do with the current target).
881 * Otherwise, treat MSG_OUT as a 1 byte message to send (abort, abort tag,
884 * When there are no messages to send, MSG_OUT should be set to MSG_NOOP,
885 * in case the target decides to put us in this phase for some strange
889 /* Turn on ATN for the retry */
893 cmp SINDEX, MSG_IDENTIFYFLAG jne p_mesgout_from_host;
894 test SCB_CONTROL,MK_MESSAGE jnz host_message_loop;
896 or SINDEX, MSG_IDENTIFYFLAG|DISCENB, SCB_LUN;
897 test SCB_CONTROL, DISCENB jnz . + 2;
898 and SINDEX, ~DISCENB;
900 * Send a tag message if TAG_ENB is set in the SCB control block.
901 * Use SCB_NONPACKET_TAG as the tag value.
904 test SCB_CONTROL,TAG_ENB jz p_mesgout_onebyte;
905 mov SCSIDAT, SINDEX; /* Send the identify message */
907 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
908 and SCSIDAT,TAG_ENB|SCB_TAG_TYPE,SCB_CONTROL;
910 cmp LASTPHASE, P_MESGOUT jne p_mesgout_done;
911 mov SCBPTR jmp p_mesgout_onebyte;
913 * Interrupt the driver, and allow it to handle this message
914 * phase and any required retries.
917 cmp SINDEX, HOST_MSG jne p_mesgout_onebyte;
918 jmp host_message_loop;
921 mvi CLRSINT1, CLRATNO;
925 * If the next bus phase after ATN drops is message out, it means
926 * that the target is requesting that the last message(s) be resent.
929 cmp LASTPHASE, P_MESGOUT je p_mesgout_retry;
932 mvi CLRSINT1,CLRATNO; /* Be sure to turn ATNO off */
933 mov LAST_MSG, MSG_OUT;
934 mvi MSG_OUT, MSG_NOOP; /* No message left */
938 * Message in phase. Bytes are read using Automatic PIO mode.
941 /* read the 1st message byte */
942 mvi ACCUM call inb_first;
944 test A,MSG_IDENTIFYFLAG jnz mesgin_identify;
945 cmp A,MSG_DISCONNECT je mesgin_disconnect;
946 cmp A,MSG_SAVEDATAPOINTER je mesgin_sdptrs;
947 cmp ALLZEROS,A je mesgin_complete;
948 cmp A,MSG_RESTOREPOINTERS je mesgin_rdptrs;
949 cmp A,MSG_IGN_WIDE_RESIDUE je mesgin_ign_wide_residue;
950 cmp A,MSG_NOOP je mesgin_done;
953 * Pushed message loop to allow the kernel to
954 * run it's own message state engine. To avoid an
955 * extra nop instruction after signaling the kernel,
956 * we perform the phase_lock before checking to see
957 * if we should exit the loop and skip the phase_lock
958 * in the ITloop. Performing back to back phase_locks
959 * shouldn't hurt, but why do it twice...
962 call phase_lock; /* Benign the first time through. */
963 SET_SEQINTCODE(HOST_MSG_LOOP)
964 cmp RETURN_1, EXIT_MSG_LOOP je ITloop;
965 cmp RETURN_1, CONT_MSG_LOOP_WRITE jne . + 3;
966 mov SCSIDAT, RETURN_2;
967 jmp host_message_loop;
968 /* Must be CONT_MSG_LOOP_READ */
969 mov NONE, SCSIDAT; /* ACK Byte */
970 jmp host_message_loop;
972 mesgin_ign_wide_residue:
973 mov SAVED_MODE, MODE_PTR;
974 SET_MODE(M_SCSI, M_SCSI)
975 shr NEGOADDR, 4, SAVED_SCSIID;
977 RESTORE_MODE(SAVED_MODE)
978 test A, WIDEXFER jz mesgin_reject;
979 /* Pull the residue byte */
980 mvi REG0 call inb_next;
981 cmp REG0, 0x01 jne mesgin_reject;
982 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz . + 2;
983 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jnz mesgin_done;
984 SET_SEQINTCODE(IGN_WIDE_RES)
987 mesgin_proto_violation:
988 SET_SEQINTCODE(PROTO_VIOLATION)
991 mvi MSG_MESSAGE_REJECT call mk_mesg;
993 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
996 #define INDEX_DISC_LIST(scsiid, lun) \
997 and A, 0xC0, scsiid; \
1000 and SINDEX, 0x30, scsiid; \
1001 shr SINDEX, 3; /* Multiply by 2 */ \
1002 add SINDEX, (SCB_DISCONNECTED_LISTS & 0xFF); \
1003 mvi SINDEX[1], ((SCB_DISCONNECTED_LISTS >> 8) & 0xFF)
1007 * Determine whether a target is using tagged or non-tagged
1008 * transactions by first looking at the transaction stored in
1009 * the per-device, disconnected array. If there is no untagged
1010 * transaction for this target, this must be a tagged transaction.
1012 and SAVED_LUN, MSG_IDENTIFY_LUNMASK, A;
1013 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1014 bmov DINDEX, SINDEX, 2;
1015 bmov REG0, SINDIR, 2;
1016 cmp REG0[1], SCB_LIST_NULL je snoop_tag;
1017 /* Untagged. Clear the busy table entry and setup the SCB. */
1018 bmov DINDIR, ALLONES, 2;
1019 bmov SCBPTR, REG0, 2;
1023 * Here we "snoop" the bus looking for a SIMPLE QUEUE TAG message.
1024 * If we get one, we use the tag returned to find the proper
1025 * SCB. After receiving the tag, look for the SCB at SCB locations tag and
1029 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1032 mov NONE, SCSIDAT; /* ACK Identify MSG */
1034 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1037 cmp LASTPHASE, P_MESGIN jne not_found_ITloop;
1038 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1041 cmp SCSIBUS, MSG_SIMPLE_Q_TAG jne not_found;
1044 mvi SCBPTR call inb_next; /* tag value */
1046 test SCB_CONTROL,DISCONNECTED jz verify_other_scb;
1047 mov A, SAVED_SCSIID;
1048 cmp SCB_SCSIID, A jne verify_other_scb;
1050 cmp SCB_LUN, A je setup_SCB_disconnected;
1053 test SCBPTR[1], 0xFF jnz verify_scb;
1057 * Ensure that the SCB the tag points to is for
1058 * an SCB transaction to the reconnecting target.
1061 if ((ahd->flags & AHD_SEQUENCER_DEBUG) != 0) {
1064 test SCB_CONTROL,DISCONNECTED jz not_found;
1065 setup_SCB_disconnected:
1066 and SCB_CONTROL,~DISCONNECTED;
1067 clr SEQ_FLAGS; /* make note of IDENTIFY */
1068 test SCB_SGPTR, SG_LIST_NULL jnz . + 3;
1069 bmov ALLOCFIFO_SCBPTR, SCBPTR, 2;
1071 /* See if the host wants to send a message upon reconnection */
1072 test SCB_CONTROL, MK_MESSAGE jz mesgin_done;
1073 mvi HOST_MSG call mk_mesg;
1077 SET_SEQINTCODE(NO_MATCH)
1081 SET_SEQINTCODE(NO_MATCH)
1085 * We received a "command complete" message. Put the SCB on the complete
1086 * queue and trigger a completion interrupt via the idle loop. Before doing
1087 * so, check to see if there is a residual or the status byte is something
1088 * other than STATUS_GOOD (0). In either of these conditions, we upload the
1089 * SCB back to the host so it can process this information.
1094 * If ATN is raised, we still want to give the target a message.
1095 * Perhaps there was a parity error on this last message byte.
1096 * Either way, the target should take us to message out phase
1097 * and then attempt to complete the command again. We should use a
1098 * critical section here to guard against a timeout triggering
1099 * for this command and setting ATN while we are still processing
1101 test SCSISIGI, ATNI jnz mesgin_done;
1105 * If we are identified and have successfully sent the CDB,
1106 * any status will do. Optimize this fast path.
1108 test SCB_CONTROL, STATUS_RCVD jz mesgin_proto_violation;
1109 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz complete_accepted;
1112 * If the target never sent an identify message but instead went
1113 * to mesgin to give an invalid message, let the host abort us.
1115 test SEQ_FLAGS, NOT_IDENTIFIED jnz mesgin_proto_violation;
1118 * If we recevied good status but never successfully sent the
1119 * cdb, abort the command.
1121 test SCB_SCSI_STATUS,0xff jnz complete_accepted;
1122 test SEQ_FLAGS, NO_CDB_SENT jnz mesgin_proto_violation;
1126 * See if we attempted to deliver a message but the target ingnored us.
1128 test SCB_CONTROL, MK_MESSAGE jz complete_nomsg;
1129 SET_SEQINTCODE(MKMSG_FAILED)
1131 call queue_scb_completion;
1136 /* Cancel any pending select-out. */
1137 test SSTAT0, SELDO|SELINGO jnz . + 2;
1138 and SCSISEQ0, ~ENSELO;
1141 add QFREEZE_COUNT, 1;
1142 adc QFREEZE_COUNT[1], A;
1143 or SEQ_FLAGS2, SELECTOUT_QFROZEN;
1144 mov A, ACCUM_SAVE ret;
1148 * Complete the current FIFO's SCB if data for this same
1149 * SCB is not transferring in the other FIFO.
1151 SET_SRC_MODE M_DFF1;
1152 SET_DST_MODE M_DFF1;
1153 pkt_complete_scb_if_fifos_idle:
1154 bmov ARG_1, SCBPTR, 2;
1155 mvi DFFSXFRCTL, CLRCHN;
1156 SET_MODE(M_SCSI, M_SCSI)
1157 bmov SCBPTR, ARG_1, 2;
1158 test SCB_FIFO_USE_COUNT, 0xFF jnz return;
1159 queue_scb_completion:
1160 test SCB_SCSI_STATUS,0xff jnz bad_status;
1162 * Check for residuals
1164 test SCB_SGPTR, SG_LIST_NULL jnz complete; /* No xfer */
1165 test SCB_SGPTR, SG_FULL_RESID jnz upload_scb;/* Never xfered */
1166 test SCB_RESIDUAL_SGPTR, SG_LIST_NULL jz upload_scb;
1169 bmov SCB_NEXT_COMPLETE, COMPLETE_SCB_HEAD, 2;
1170 bmov COMPLETE_SCB_HEAD, SCBPTR, 2 ret;
1173 cmp SCB_SCSI_STATUS, STATUS_PKT_SENSE je upload_scb;
1177 * Restore SCB TAG since we reuse this field
1178 * in the sequencer. We don't want to corrupt
1181 bmov SCB_TAG, SCBPTR, 2;
1183 or SCB_SGPTR, SG_STATUS_VALID;
1184 mvi SCB_NEXT_COMPLETE[1], SCB_LIST_NULL;
1185 cmp COMPLETE_DMA_SCB_HEAD[1], SCB_LIST_NULL jne add_dma_scb_tail;
1186 bmov COMPLETE_DMA_SCB_HEAD, SCBPTR, 2;
1187 bmov COMPLETE_DMA_SCB_TAIL, SCBPTR, 2 ret;
1189 bmov REG0, SCBPTR, 2;
1190 bmov SCBPTR, COMPLETE_DMA_SCB_TAIL, 2;
1191 bmov SCB_NEXT_COMPLETE, REG0, 2;
1192 bmov COMPLETE_DMA_SCB_TAIL, REG0, 2 ret;
1196 * Is it a disconnect message? Set a flag in the SCB to remind us
1197 * and await the bus going free. If this is an untagged transaction
1198 * store the SCB id for it in our untagged target table for lookup on
1203 * If ATN is raised, we still want to give the target a message.
1204 * Perhaps there was a parity error on this last message byte
1205 * or we want to abort this command. Either way, the target
1206 * should take us to message out phase and then attempt to
1208 * XXX - Wait for more testing.
1209 test SCSISIGI, ATNI jnz mesgin_done;
1211 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT
1212 jnz mesgin_proto_violation;
1213 or SCB_CONTROL,DISCONNECTED;
1214 test SCB_CONTROL, TAG_ENB jnz await_busfree;
1216 bmov REG0, SCBPTR, 2;
1217 INDEX_DISC_LIST(SAVED_SCSIID, SAVED_LUN);
1218 bmov DINDEX, SINDEX, 2;
1219 bmov DINDIR, REG0, 2;
1220 bmov SCBPTR, REG0, 2;
1223 and SIMODE1, ~ENBUSFREE;
1224 if ((ahd->bugs & AHD_BUSFREEREV_BUG) == 0) {
1226 * In the BUSFREEREV_BUG case, the
1227 * busfree status was cleared at the
1228 * beginning of the connection.
1230 mvi CLRSINT1,CLRBUSFREE;
1232 mov NONE, SCSIDAT; /* Ack the last byte */
1233 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1234 jnz await_busfree_not_m_dff;
1235 SET_SRC_MODE M_DFF1;
1236 SET_DST_MODE M_DFF1;
1237 await_busfree_clrchn:
1238 mvi DFFSXFRCTL, CLRCHN;
1239 await_busfree_not_m_dff:
1240 /* clear target specific flags */
1241 mvi SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT;
1242 test SSTAT1,REQINIT|BUSFREE jz .;
1244 * We only set BUSFREE status once either a new
1245 * phase has been detected or we are really
1246 * BUSFREE. This allows the driver to know
1247 * that we are active on the bus even though
1248 * no identified transaction exists should a
1249 * timeout occur while awaiting busfree.
1251 mvi LASTPHASE, P_BUSFREE;
1252 test SSTAT1, BUSFREE jnz idle_loop;
1253 SET_SEQINTCODE(MISSED_BUSFREE)
1257 * Save data pointers message:
1258 * Copying RAM values back to SCB, for Save Data Pointers message, but
1259 * only if we've actually been into a data phase to change them. This
1260 * protects against bogus data in scratch ram and the residual counts
1261 * since they are only initialized when we go into data_in or data_out.
1262 * Ack the message as soon as possible.
1264 SET_SRC_MODE M_DFF1;
1265 SET_DST_MODE M_DFF1;
1267 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1268 test SEQ_FLAGS, DPHASE jz ITloop;
1274 * If we are asked to save our position at the end of the
1275 * transfer, just mark us at the end rather than perform a
1278 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz save_pointers_full;
1279 or SCB_SGPTR, SG_LIST_NULL ret;
1283 * The SCB_DATAPTR becomes the current SHADDR.
1284 * All other information comes directly from our residual
1287 bmov SCB_DATAPTR, SHADDR, 8;
1288 bmov SCB_DATACNT, SCB_RESIDUAL_DATACNT, 8 ret;
1291 * Restore pointers message? Data pointers are recopied from the
1292 * SCB anytime we enter a data phase for the first time, so all
1293 * we need to do is clear the DPHASE flag and let the data phase
1294 * code do the rest. We also reset/reallocate the FIFO to make
1295 * sure we have a clean start for the next data or command phase.
1298 and SEQ_FLAGS, ~DPHASE;
1299 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1)) jnz msgin_rdptrs_get_fifo;
1300 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1301 SET_MODE(M_SCSI, M_SCSI)
1302 msgin_rdptrs_get_fifo:
1307 if ((ahd->bugs & AHD_EARLY_REQ_BUG) != 0) {
1309 * Don't ignore persistent REQ assertions just because
1310 * they were asserted within the bus settle delay window.
1311 * This allows us to tolerate devices like the GEM318
1312 * that violate the SCSI spec. We are careful not to
1313 * count REQ while we are waiting for it to fall during
1314 * an async phase due to our asserted ACK. Each
1315 * sequencer instruction takes ~25ns, so the REQ must
1316 * last at least 100ns in order to be counted as a true
1319 test SCSIPHASE, 0xFF jnz phase_locked;
1320 test SCSISIGI, ACKI jnz phase_lock;
1321 test SCSISIGI, REQI jz phase_lock;
1322 test SCSIPHASE, 0xFF jnz phase_locked;
1323 test SCSISIGI, ACKI jnz phase_lock;
1324 test SCSISIGI, REQI jz phase_lock;
1327 test SCSIPHASE, 0xFF jz .;
1329 test SSTAT1, SCSIPERR jnz phase_lock;
1330 phase_lock_latch_phase:
1331 and LASTPHASE, PHASE_MASK, SCSISIGI ret;
1334 * Functions to read data in Automatic PIO mode.
1336 * An ACK is not sent on input from the target until SCSIDATL is read from.
1337 * So we wait until SCSIDATL is latched (the usual way), then read the data
1338 * byte directly off the bus using SCSIBUSL. When we have pulled the ATN
1339 * line, or we just want to acknowledge the byte, then we do a dummy read
1340 * from SCISDATL. The SCSI spec guarantees that the target will hold the
1341 * data byte on the bus until we send our ACK.
1343 * The assumption here is that these are called in a particular sequence,
1344 * and that REQ is already set when inb_first is called. inb_{first,next}
1345 * use the same calling convention as inb.
1348 mov NONE,SCSIDAT; /*dummy read from latch to ACK*/
1351 * If there is a parity error, wait for the kernel to
1352 * see the interrupt and prepare our message response
1353 * before continuing.
1355 test SCSIPHASE, 0xFF jz .;
1356 test SSTAT1, SCSIPERR jnz inb_next_wait;
1357 inb_next_check_phase:
1358 and LASTPHASE, PHASE_MASK, SCSISIGI;
1359 cmp LASTPHASE, P_MESGIN jne mesgin_phasemis;
1363 mov DINDIR,SCSIBUS ret; /*read byte directly from bus*/
1365 mov NONE,SCSIDAT ret; /*dummy read from latch to ACK*/
1369 mov MSG_OUT,SINDEX ret;
1371 SET_SRC_MODE M_DFF1;
1372 SET_DST_MODE M_DFF1;
1374 test SG_STATE, FETCH_INPROG jz disable_ccsgen_fetch_done;
1376 disable_ccsgen_fetch_done:
1381 * Do we have any prefetch left???
1383 test SG_STATE, SEGS_AVAIL jnz idle_sg_avail;
1386 * Can this FIFO have access to the S/G cache yet?
1388 test CCSGCTL, SG_CACHE_AVAIL jz return;
1390 /* Did we just finish fetching segs? */
1391 test CCSGCTL, CCSGDONE jnz idle_sgfetch_complete;
1393 /* Are we actively fetching segments? */
1394 test CCSGCTL, CCSGENACK jnz return;
1397 * Should the other FIFO get the S/G cache first? If
1398 * both FIFOs have been allocated since we last checked
1399 * any FIFO, it is important that we service a FIFO
1400 * that is not actively on the bus first. This guarantees
1401 * that a FIFO will be freed to handle snapshot requests for
1402 * any FIFO that is still on the bus. Chips with RTI do not
1403 * perform snapshots, so don't bother with this test there.
1405 if ((ahd->features & AHD_RTI) == 0) {
1407 * If we're not still receiving SCSI data,
1408 * it is safe to allocate the S/G cache to
1411 test DFCNTRL, SCSIEN jz idle_sgfetch_start;
1414 * Switch to the other FIFO. Non-RTI chips
1415 * also have the "set mode" bug, so we must
1416 * disable interrupts during the switch.
1418 mvi SEQINTCTL, INTVEC1DSL;
1419 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1422 * If the other FIFO needs loading, then it
1423 * must not have claimed the S/G cache yet
1424 * (SG_CACHE_AVAIL would have been cleared in
1425 * the orginal FIFO mode and we test this above).
1426 * Return to the idle loop so we can process the
1427 * FIFO not currently on the bus first.
1429 test SG_STATE, LOADING_NEEDED jz idle_sgfetch_okay;
1432 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1438 * We fetch a "cacheline aligned" and sized amount of data
1439 * so we don't end up referencing a non-existant page.
1440 * Cacheline aligned is in quotes because the kernel will
1441 * set the prefetch amount to a reasonable level if the
1442 * cacheline size is unknown.
1444 bmov SGHADDR, SCB_RESIDUAL_SGPTR, 4;
1445 mvi SGHCNT, SG_PREFETCH_CNT;
1446 if ((ahd->bugs & AHD_REG_SLOW_SETTLE_BUG) != 0) {
1448 * Need two instructions between "touches" of SGHADDR.
1452 and SGHADDR[0], SG_PREFETCH_ALIGN_MASK, SCB_RESIDUAL_SGPTR;
1453 mvi CCSGCTL, CCSGEN|CCSGRESET;
1454 or SG_STATE, FETCH_INPROG ret;
1455 idle_sgfetch_complete:
1457 * Guard against SG_CACHE_AVAIL activating during sg fetch
1458 * request in the other FIFO.
1460 test SG_STATE, FETCH_INPROG jz return;
1462 and CCSGADDR, SG_PREFETCH_ADDR_MASK, SCB_RESIDUAL_SGPTR;
1463 mvi SG_STATE, SEGS_AVAIL|LOADING_NEEDED;
1465 /* Does the hardware have space for another SG entry? */
1466 test DFSTATUS, PRELOAD_AVAIL jz return;
1468 * On the A, preloading a segment before HDMAENACK
1469 * comes true can clobber the shaddow address of the
1470 * first segment in the S/G FIFO. Wait until it is
1473 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) == 0) {
1474 test DFCNTRL, HDMAENACK jz return;
1476 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1477 bmov HADDR, CCSGRAM, 8;
1479 bmov HADDR, CCSGRAM, 4;
1481 bmov HCNT, CCSGRAM, 3;
1482 bmov SCB_RESIDUAL_DATACNT[3], CCSGRAM, 1;
1483 if ((ahd->flags & AHD_39BIT_ADDRESSING) != 0) {
1484 and HADDR[4], SG_HIGH_ADDR_BITS, SCB_RESIDUAL_DATACNT[3];
1486 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
1487 /* Skip 4 bytes of pad. */
1491 clr A; /* add sizeof(struct scatter) */
1492 add SCB_RESIDUAL_SGPTR[0],SG_SIZEOF;
1493 adc SCB_RESIDUAL_SGPTR[1],A;
1494 adc SCB_RESIDUAL_SGPTR[2],A;
1495 adc SCB_RESIDUAL_SGPTR[3],A;
1496 mov SINDEX, SCB_RESIDUAL_SGPTR[0];
1497 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 3;
1498 or SINDEX, LAST_SEG;
1500 mov SG_CACHE_PRE, SINDEX;
1501 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
1503 * Use SCSIENWRDIS so that SCSIEN is never
1504 * modified by this operation.
1506 or DFCNTRL, PRELOADEN|HDMAEN|SCSIENWRDIS;
1508 or DFCNTRL, PRELOADEN|HDMAEN;
1511 * Do we have another segment in the cache?
1513 add NONE, SG_PREFETCH_CNT_LIMIT, CCSGADDR;
1515 and SG_STATE, ~SEGS_AVAIL ret;
1518 * Initialize the DMA address and counter from the SCB.
1521 bmov HADDR, SCB_DATAPTR, 11;
1522 and REG_ISR, ~SG_FULL_RESID, SCB_SGPTR[0];
1523 test SCB_DATACNT[3], SG_LAST_SEG jz . + 2;
1524 or REG_ISR, LAST_SEG;
1525 mov SG_CACHE_PRE, REG_ISR;
1526 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1528 * Since we've are entering a data phase, we will
1529 * rely on the SCB_RESID* fields. Initialize the
1530 * residual and clear the full residual flag.
1532 and SCB_SGPTR[0], ~SG_FULL_RESID;
1533 bmov SCB_RESIDUAL_DATACNT[3], SCB_DATACNT[3], 5;
1534 /* If we need more S/G elements, tell the idle loop */
1535 test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jnz . + 2;
1536 mvi SG_STATE, LOADING_NEEDED ret;
1541 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1542 p_data_clear_handler:
1543 or LONGJMP_ADDR[1], INVALID_ADDR ret;
1546 test SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT jz p_data_allowed;
1547 SET_SEQINTCODE(PROTO_VIOLATION)
1550 test SEQ_FLAGS, DPHASE jz data_phase_initialize;
1553 * If we re-enter the data phase after going through another
1554 * phase, our transfer location has almost certainly been
1555 * corrupted by the interveining, non-data, transfers. Ask
1556 * the host driver to fix us up based on the transfer residual
1557 * unless we already know that we should be bitbucketing.
1559 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1560 SET_SEQINTCODE(PDATA_REINIT)
1561 jmp data_phase_inbounds;
1565 * Turn on `Bit Bucket' mode, wait until the target takes
1566 * us to another phase, and then notify the host.
1568 mov SAVED_MODE, MODE_PTR;
1569 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
1570 jnz bitbucket_not_m_dff;
1572 * Ensure that any FIFO contents are cleared out and the
1573 * FIFO free'd prior to starting the BITBUCKET. BITBUCKET
1574 * doesn't discard data already in the FIFO.
1576 mvi DFFSXFRCTL, RSTCHN|CLRSHCNT;
1577 SET_MODE(M_SCSI, M_SCSI)
1578 bitbucket_not_m_dff:
1579 or SXFRCTL1,BITBUCKET;
1580 /* Wait for non-data phase. */
1581 test SCSIPHASE, ~DATA_PHASE_MASK jz .;
1582 and SXFRCTL1, ~BITBUCKET;
1583 RESTORE_MODE(SAVED_MODE)
1584 SET_SRC_MODE M_DFF1;
1585 SET_DST_MODE M_DFF1;
1586 SET_SEQINTCODE(DATA_OVERRUN)
1589 data_phase_initialize:
1590 test SCB_SGPTR[0], SG_LIST_NULL jnz p_data_bitbucket;
1591 call load_first_seg;
1592 data_phase_inbounds:
1593 /* We have seen a data phase at least once. */
1594 or SEQ_FLAGS, DPHASE;
1595 mov SAVED_MODE, MODE_PTR;
1596 test SG_STATE, LOADING_NEEDED jz data_group_dma_loop;
1597 call p_data_handle_xfer;
1598 data_group_dma_loop:
1600 * The transfer is complete if either the last segment
1601 * completes or the target changes phase. Both conditions
1602 * will clear SCSIEN.
1604 call idle_loop_service_fifos;
1605 call idle_loop_cchan;
1606 call idle_loop_gsfifo;
1607 RESTORE_MODE(SAVED_MODE)
1608 test DFCNTRL, SCSIEN jnz data_group_dma_loop;
1610 data_group_dmafinish:
1612 * The transfer has terminated either due to a phase
1613 * change, and/or the completion of the last segment.
1614 * We have two goals here. Do as much other work
1615 * as possible while the data fifo drains on a read
1616 * and respond as quickly as possible to the standard
1617 * messages (save data pointers/disconnect and command
1618 * complete) that usually follow a data phase.
1623 * Go ahead and shut down the DMA engine now.
1625 test DFCNTRL, DIRECTION jnz data_phase_finish;
1626 data_group_fifoflush:
1627 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1628 or DFCNTRL, FIFOFLUSH;
1631 * We have enabled the auto-ack feature. This means
1632 * that the controller may have already transferred
1633 * some overrun bytes into the data FIFO and acked them
1634 * on the bus. The only way to detect this situation is
1635 * to wait for LAST_SEG_DONE to come true on a completed
1636 * transfer and then test to see if the data FIFO is
1637 * non-empty. We know there is more data yet to transfer
1638 * if SG_LIST_NULL is not yet set, thus there cannot be
1641 test SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL jz data_phase_finish;
1642 test SG_CACHE_SHADOW, LAST_SEG_DONE jz .;
1643 test DFSTATUS, FIFOEMP jnz data_phase_finish;
1648 * If the target has left us in data phase, loop through
1649 * the dma code again. We will only loop if there is a
1652 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1653 test SSTAT0, TARGET jnz data_phase_done;
1655 if ((ahd->flags & AHD_INITIATORROLE) != 0) {
1656 test SSTAT1, REQINIT jz .;
1657 test SCSIPHASE, DATA_PHASE_MASK jnz p_data;
1661 /* Kill off any pending prefetch */
1662 call disable_ccsgen;
1663 or LONGJMP_ADDR[1], INVALID_ADDR;
1665 if ((ahd->flags & AHD_TARGETROLE) != 0) {
1666 test SEQ_FLAGS, DPHASE_PENDING jz ITloop;
1668 and SEQ_FLAGS, ~DPHASE_PENDING;
1669 * For data-in phases, wait for any pending acks from the
1670 * initiator before changing phase. We only need to
1671 * send Ignore Wide Residue messages for data-in phases.
1672 test DFCNTRL, DIRECTION jz target_ITloop;
1673 test SSTAT1, REQINIT jnz .;
1674 test SCB_TASK_ATTRIBUTE, SCB_XFERLEN_ODD jz target_ITloop;
1675 SET_MODE(M_SCSI, M_SCSI)
1676 test NEGCONOPTS, WIDEXFER jz target_ITloop;
1679 * Issue an Ignore Wide Residue Message.
1680 mvi P_MESGIN|BSYO call change_phase;
1681 mvi MSG_IGN_WIDE_RESIDUE call target_outb;
1682 mvi 1 call target_outb;
1690 * We assume that, even though data may still be
1691 * transferring to the host, that the SCSI side of
1692 * the DMA engine is now in a static state. This
1693 * allows us to update our notion of where we are
1696 * If, by chance, we stopped before being able
1697 * to fetch additional segments for this transfer,
1698 * yet the last S/G was completely exhausted,
1699 * call our idle loop until it is able to load
1700 * another segment. This will allow us to immediately
1701 * pickup on the next segment on the next data phase.
1703 * If we happened to stop on the last segment, then
1704 * our residual information is still correct from
1705 * the idle loop and there is no need to perform
1708 residual_before_last_seg:
1709 test MDFFSTAT, SHVALID jnz sgptr_fixup;
1711 * Can never happen from an interrupt as the packetized
1712 * hardware will only interrupt us once SHVALID or
1715 call idle_loop_service_fifos;
1716 RESTORE_MODE(SAVED_MODE)
1719 test SG_CACHE_SHADOW, LAST_SEG jz residual_before_last_seg;
1720 /* Record if we've consumed all S/G entries */
1721 test MDFFSTAT, SHVALID jz . + 2;
1722 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1723 or SCB_RESIDUAL_SGPTR[0], SG_LIST_NULL ret;
1727 * Fixup the residual next S/G pointer. The S/G preload
1728 * feature of the chip allows us to load two elements
1729 * in addition to the currently active element. We
1730 * store the bottom byte of the next S/G pointer in
1731 * the SG_CACHE_PTR register so we can restore the
1732 * correct value when the DMA completes. If the next
1733 * sg ptr value has advanced to the point where higher
1734 * bytes in the address have been affected, fix them
1737 test SG_CACHE_SHADOW, 0x80 jz sgptr_fixup_done;
1738 test SCB_RESIDUAL_SGPTR[0], 0x80 jnz sgptr_fixup_done;
1739 add SCB_RESIDUAL_SGPTR[1], -1;
1740 adc SCB_RESIDUAL_SGPTR[2], -1;
1741 adc SCB_RESIDUAL_SGPTR[3], -1;
1743 and SCB_RESIDUAL_SGPTR[0], SG_ADDR_MASK, SG_CACHE_SHADOW;
1744 clr SCB_RESIDUAL_DATACNT[3]; /* We are not the last seg */
1745 bmov SCB_RESIDUAL_DATACNT, SHCNT, 3 ret;
1748 call issue_cmdcmplt;
1749 mvi CLRSEQINTSTAT, CLRSEQ_SWTMRTO;
1750 if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) {
1752 * In H2A4, the mode pointer is not saved
1753 * for intvec2, but is restored on iret.
1754 * This can lead to the restoration of a
1755 * bogus mode ptr. Manually clear the
1756 * intmask bits and do a normal return
1759 and SEQINTCTL, ~(INTMASK2|INTMASK1) ret;
1761 or SEQINTCTL, IRET ret;
1765 if ((ahd->features & AHD_RTI) == 0) {
1767 * On RevA Silicon, if the target returns us to data-out
1768 * after we have already trained for data-out, it is
1769 * possible for us to transition the free running clock to
1770 * data-valid before the required 100ns P1 setup time (8 P1
1771 * assertions in fast-160 mode). This will only happen if
1772 * this L-Q is a continuation of a data transfer for which
1773 * we have already prefetched data into our FIFO (LQ/Data
1774 * followed by LQ/Data for the same write transaction).
1775 * This can cause some target implementations to miss the
1776 * first few data transfers on the bus. We detect this
1777 * situation by noticing that this is the first data transfer
1778 * after an LQ (LQIWORKONLQ true), that the data transfer is
1779 * a continuation of a transfer already setup in our FIFO
1780 * (SAVEPTRS interrupt), and that the transaction is a write
1781 * (DIRECTION set in DFCNTRL). The delay is performed by
1782 * disabling SCSIEN until we see the first REQ from the
1785 * First instruction in an ISR cannot be a branch on
1786 * Rev A. Snapshot LQISTAT2 so the status is not missed
1787 * and deffer the test by one instruction.
1789 mov REG_ISR, LQISTAT2;
1790 test REG_ISR, LQIWORKONLQ jz main_isr;
1791 test SEQINTSRC, SAVEPTRS jz main_isr;
1792 test LONGJMP_ADDR[1], INVALID_ADDR jz saveptr_active_fifo;
1794 * Switch to the active FIFO after clearing the snapshot
1795 * savepointer in the current FIFO. We do this so that
1796 * a pending CTXTDONE or SAVEPTR is visible in the active
1797 * FIFO. This status is the only way we can detect if we
1798 * have lost the race (e.g. host paused us) and our attempts
1799 * to disable the channel occurred after all REQs were
1800 * already seen and acked (REQINIT never comes true).
1802 mvi DFFSXFRCTL, CLRCHN;
1803 xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1);
1804 test DFCNTRL, DIRECTION jz interrupt_return;
1805 and DFCNTRL, ~SCSIEN;
1806 snapshot_wait_data_valid:
1807 test SEQINTSRC, (CTXTDONE|SAVEPTRS) jnz interrupt_return;
1808 test SSTAT1, REQINIT jz snapshot_wait_data_valid;
1809 snapshot_data_valid:
1811 or SEQINTCTL, IRET ret;
1813 mvi DFFSXFRCTL, CLRCHN;
1814 or SEQINTCTL, IRET ret;
1817 test SEQINTSRC, CFG4DATA jnz cfg4data_intr;
1818 test SEQINTSRC, CFG4ISTAT jnz cfg4istat_intr;
1819 test SEQINTSRC, SAVEPTRS jnz saveptr_intr;
1820 test SEQINTSRC, CFG4ICMD jnz cfg4icmd_intr;
1821 SET_SEQINTCODE(INVALID_SEQINT)
1824 * There are two types of save pointers interrupts:
1825 * The first is a snapshot save pointers where the current FIFO is not
1826 * active and contains a snapshot of the current poniter information.
1827 * This happens between packets in a stream for a single L_Q. Since we
1828 * are not performing a pointer save, we can safely clear the channel
1829 * so it can be used for other transactions. On RTI capable controllers,
1830 * where snapshots can, and are, disabled, the code to handle this type
1831 * of snapshot is not active.
1833 * The second case is a save pointers on an active FIFO which occurs
1834 * if the target changes to a new L_Q or busfrees/QASes and the transfer
1835 * has a residual. This should occur coincident with a ctxtdone. We
1836 * disable the interrupt and allow our active routine to handle the
1840 if ((ahd->features & AHD_RTI) == 0) {
1841 test LONGJMP_ADDR[1], INVALID_ADDR jnz snapshot_saveptr;
1843 saveptr_active_fifo:
1844 and SEQIMODE, ~ENSAVEPTRS;
1845 or SEQINTCTL, IRET ret;
1848 test SCB_SGPTR[0], SG_LIST_NULL jnz pkt_handle_overrun_inc_use_count;
1849 call load_first_seg;
1850 call pkt_handle_xfer;
1851 inc SCB_FIFO_USE_COUNT;
1853 or SEQINTCTL, IRET ret;
1857 add NONE, -13, SCB_CDB_LEN;
1858 jnc cfg4istat_have_sense_addr;
1859 test SCB_CDB_LEN, SCB_CDB_LEN_PTR jnz cfg4istat_have_sense_addr;
1861 * Host sets up address/count and enables transfer.
1863 SET_SEQINTCODE(CFG4ISTAT_INTR)
1864 jmp cfg4istat_setup_handler;
1865 cfg4istat_have_sense_addr:
1866 bmov HADDR, SCB_SENSE_BUSADDR, 4;
1867 mvi HCNT[1], (AHD_SENSE_BUFSIZE >> 8);
1868 mvi SG_CACHE_PRE, LAST_SEG;
1869 mvi DFCNTRL, PRELOADEN|SCSIEN|HDMAEN;
1870 cfg4istat_setup_handler:
1872 * Status pkt is transferring to host.
1873 * Wait in idle loop for transfer to complete.
1874 * If a command completed before an attempted
1875 * task management function completed, notify the host.
1877 test SCB_TASK_MANAGEMENT, 0xFF jz cfg4istat_no_taskmgmt_func;
1878 SET_SEQINTCODE(TASKMGMT_CMD_CMPLT_OKAY)
1879 cfg4istat_no_taskmgmt_func:
1880 call pkt_handle_status;
1881 or SEQINTCTL, IRET ret;
1885 * In the case of DMAing a CDB from the host, the normal
1886 * CDB buffer is formatted with an 8 byte address followed
1887 * by a 1 byte count.
1889 bmov HADDR[0], SCB_HOST_CDB_PTR, 9;
1890 mvi SG_CACHE_PRE, LAST_SEG;
1891 mvi DFCNTRL, (PRELOADEN|SCSIEN|HDMAEN);
1892 call pkt_handle_cdb;
1893 or SEQINTCTL, IRET ret;
1896 * See if the target has gone on in this context creating an
1897 * overrun condition. For the write case, the hardware cannot
1898 * ack bytes until data are provided. So, if the target begins
1899 * another packet without changing contexts, implying we are
1900 * not sitting on a packet boundary, we are in an overrun
1901 * situation. For the read case, the hardware will continue to
1902 * ack bytes into the FIFO, and may even ack the last overrun packet
1903 * into the FIFO. If the FIFO should become non-empty, we are in
1904 * a read overrun case.
1906 #define check_overrun \
1907 /* Not on a packet boundary. */ \
1908 test MDFFSTAT, DLZERO jz pkt_handle_overrun; \
1909 test DFSTATUS, FIFOEMP jz pkt_handle_overrun
1912 test SG_STATE, LOADING_NEEDED jz pkt_last_seg;
1914 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1915 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1916 test SCSISIGO, ATNO jnz . + 2;
1917 test SSTAT2, NONPACKREQ jz pkt_service_fifo;
1919 * Defer handling of this NONPACKREQ until we
1920 * can be sure it pertains to this FIFO. SAVEPTRS
1921 * will not be asserted if the NONPACKREQ is for us,
1922 * so we must simulate it if shaddow is valid. If
1923 * shaddow is not valid, keep running this FIFO until we
1924 * have satisfied the transfer by loading segments and
1925 * waiting for either shaddow valid or last_seg_done.
1927 test MDFFSTAT, SHVALID jnz pkt_saveptrs;
1929 test SG_STATE, LOADING_NEEDED jnz service_fifo;
1932 test SEQINTSRC, SAVEPTRS jnz pkt_saveptrs;
1933 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_last_seg_done;
1934 test SCSIPHASE, ~DATA_PHASE_MASK jz . + 2;
1935 test SCSISIGO, ATNO jnz . + 2;
1936 test SSTAT2, NONPACKREQ jz return;
1937 test MDFFSTAT, SHVALID jz return;
1941 * Either a SAVEPTRS interrupt condition is pending for this FIFO
1942 * or we have a pending NONPACKREQ for this FIFO. We differentiate
1943 * between the two by capturing the state of the SAVEPTRS interrupt
1944 * prior to clearing this status and executing the common code for
1949 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
1950 or DFCNTRL, FIFOFLUSH;
1952 mov REG0, SEQINTSRC;
1955 mvi CLRSEQINTSRC, CLRSAVEPTRS;
1956 call disable_ccsgen;
1957 or SEQIMODE, ENSAVEPTRS;
1958 test DFCNTRL, DIRECTION jnz pkt_saveptrs_check_status;
1959 test DFSTATUS, FIFOEMP jnz pkt_saveptrs_check_status;
1961 * Keep a handler around for this FIFO until it drains
1962 * to the host to guarantee that we don't complete the
1963 * command to the host before the data arrives.
1965 pkt_saveptrs_wait_fifoemp:
1967 test DFSTATUS, FIFOEMP jz return;
1968 pkt_saveptrs_check_status:
1969 or LONGJMP_ADDR[1], INVALID_ADDR;
1970 test REG0, SAVEPTRS jz unexpected_nonpkt_phase;
1971 dec SCB_FIFO_USE_COUNT;
1972 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
1973 mvi DFFSXFRCTL, CLRCHN ret;
1976 * LAST_SEG_DONE status has been seen in the current FIFO.
1977 * This indicates that all of the allowed data for this
1978 * command has transferred across the SCSI and host buses.
1979 * Check for overrun and see if we can complete this command.
1983 * Mark transfer as completed.
1985 or SCB_SGPTR, SG_LIST_NULL;
1988 * Wait for the current context to finish to verify that
1989 * no overrun condition has occurred.
1991 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1993 pkt_wait_ctxt_done_loop:
1994 test SEQINTSRC, CTXTDONE jnz pkt_ctxt_done;
1996 * A sufficiently large overrun or a NONPACKREQ may
1997 * prevent CTXTDONE from ever asserting, so we must
1998 * poll for these statuses too.
2001 test SSTAT2, NONPACKREQ jz return;
2002 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2007 or LONGJMP_ADDR[1], INVALID_ADDR;
2009 * If status has been received, it is safe to skip
2010 * the check to see if another FIFO is active because
2011 * LAST_SEG_DONE has been observed. However, we check
2012 * the FIFO anyway since it costs us only one extra
2013 * instruction to leverage common code to perform the
2016 dec SCB_FIFO_USE_COUNT;
2017 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2018 mvi DFFSXFRCTL, CLRCHN ret;
2022 * Must wait until CDB xfer is over before issuing the
2027 test SG_CACHE_SHADOW, LAST_SEG_DONE jz return;
2028 or LONGJMP_ADDR[1], INVALID_ADDR;
2029 mvi DFFSXFRCTL, CLRCHN ret;
2032 * Watch over the status transfer. Our host sense buffer is
2033 * large enough to take the maximum allowed status packet.
2034 * None-the-less, we must still catch and report overruns to
2035 * the host. Additionally, properly catch unexpected non-packet
2036 * phases that are typically caused by CRC errors in status packet
2041 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2042 test SEQINTSRC, CTXTDONE jz pkt_status_check_nonpackreq;
2043 test SG_CACHE_SHADOW, LAST_SEG_DONE jnz pkt_status_check_overrun;
2045 if ((ahd->bugs & AHD_AUTOFLUSH_BUG) != 0) {
2046 or DFCNTRL, FIFOFLUSH;
2048 test DFSTATUS, FIFOEMP jz return;
2050 or LONGJMP_ADDR[1], INVALID_ADDR;
2051 mvi SCB_SCSI_STATUS, STATUS_PKT_SENSE;
2052 or SCB_CONTROL, STATUS_RCVD;
2053 jmp pkt_complete_scb_if_fifos_idle;
2055 pkt_status_check_overrun:
2057 * Status PKT overruns are uncerimoniously recovered with a
2058 * bus reset. If we've overrun, let the host know so that
2059 * recovery can be performed.
2061 * LAST_SEG_DONE has been observed. If either CTXTDONE or
2062 * a NONPACKREQ phase change have occurred and the FIFO is
2063 * empty, there is no overrun.
2065 test DFSTATUS, FIFOEMP jz pkt_status_report_overrun;
2066 test SEQINTSRC, CTXTDONE jz . + 2;
2067 test DFSTATUS, FIFOEMP jnz pkt_status_IU_done;
2068 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2069 test DFSTATUS, FIFOEMP jnz pkt_status_check_nonpackreq;
2070 pkt_status_report_overrun:
2071 SET_SEQINTCODE(STATUS_OVERRUN)
2072 /* SEQUENCER RESTARTED */
2073 pkt_status_check_nonpackreq:
2075 * CTXTDONE may be held off if a NONPACKREQ is associated with
2076 * the current context. If a NONPACKREQ is observed, decide
2077 * if it is for the current context. If it is for the current
2078 * context, we must defer NONPACKREQ processing until all data
2079 * has transferred to the host.
2081 test SCSIPHASE, ~DATA_PHASE_MASK jz return;
2082 test SCSISIGO, ATNO jnz . + 2;
2083 test SSTAT2, NONPACKREQ jz return;
2084 test SEQINTSRC, CTXTDONE jnz pkt_status_IU_done;
2085 test DFSTATUS, FIFOEMP jz return;
2087 * The unexpected nonpkt phase handler assumes that any
2088 * data channel use will have a FIFO reference count. It
2089 * turns out that the status handler doesn't need a refernce
2090 * count since the status received flag, and thus completion
2091 * processing, cannot be set until the handler is finished.
2092 * We increment the count here to make the nonpkt handler
2095 inc SCB_FIFO_USE_COUNT;
2099 * Nonpackreq is a polled status. It can come true in three situations:
2100 * we have received an L_Q, we have sent one or more L_Qs, or there is no
2101 * L_Q context associated with this REQ (REQ occurs immediately after a
2102 * (re)selection). Routines that know that the context responsible for this
2103 * nonpackreq call directly into unexpected_nonpkt_phase. In the case of the
2104 * top level idle loop, we exhaust all active contexts prior to determining that
2105 * we simply do not have the full I_T_L_Q for this phase.
2107 unexpected_nonpkt_phase_find_ctxt:
2109 * This nonpackreq is most likely associated with one of the tags
2110 * in a FIFO or an outgoing LQ. Only treat it as an I_T only
2111 * nonpackreq if we've cleared out the FIFOs and handled any
2114 SET_SRC_MODE M_SCSI;
2115 SET_DST_MODE M_SCSI;
2116 and A, FIFO1FREE|FIFO0FREE, DFFSTAT;
2117 cmp A, FIFO1FREE|FIFO0FREE jne return;
2118 test SSTAT0, SELDO jnz return;
2119 mvi SCBPTR[1], SCB_LIST_NULL;
2120 unexpected_nonpkt_phase:
2121 test MODE_PTR, ~(MK_MODE(M_DFF1, M_DFF1))
2122 jnz unexpected_nonpkt_mode_cleared;
2123 SET_SRC_MODE M_DFF0;
2124 SET_DST_MODE M_DFF0;
2125 or LONGJMP_ADDR[1], INVALID_ADDR;
2126 dec SCB_FIFO_USE_COUNT;
2127 mvi DFFSXFRCTL, CLRCHN;
2128 unexpected_nonpkt_mode_cleared:
2129 mvi CLRSINT2, CLRNONPACKREQ;
2130 test SCSIPHASE, ~(MSG_IN_PHASE|MSG_OUT_PHASE) jnz illegal_phase;
2131 SET_SEQINTCODE(ENTERING_NONPACK)
2135 SET_SEQINTCODE(ILLEGAL_PHASE)
2139 * We have entered an overrun situation. If we have working
2140 * BITBUCKET, flip that on and let the hardware eat any overrun
2141 * data. Otherwise use an overrun buffer in the host to simulate
2144 pkt_handle_overrun_inc_use_count:
2145 inc SCB_FIFO_USE_COUNT;
2147 SET_SEQINTCODE(CFG4OVERRUN)
2149 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) == 0) {
2150 or DFFSXFRCTL, DFFBITBUCKET;
2151 SET_SRC_MODE M_DFF1;
2152 SET_DST_MODE M_DFF1;
2154 call load_overrun_buf;
2155 mvi DFCNTRL, (HDMAEN|SCSIEN|PRELOADEN);
2158 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2159 test DFSTATUS, PRELOAD_AVAIL jz overrun_load_done;
2160 call load_overrun_buf;
2161 or DFCNTRL, PRELOADEN;
2163 test SEQINTSRC, CTXTDONE jnz pkt_overrun_end;
2165 test DFFSXFRCTL, DFFBITBUCKET jz pkt_overrun_end;
2167 test SSTAT2, NONPACKREQ jz return;
2169 or SCB_RESIDUAL_SGPTR, SG_OVERRUN_RESID;
2170 test SEQINTSRC, CTXTDONE jz unexpected_nonpkt_phase;
2171 dec SCB_FIFO_USE_COUNT;
2172 or LONGJMP_ADDR[1], INVALID_ADDR;
2173 test SCB_CONTROL, STATUS_RCVD jnz pkt_complete_scb_if_fifos_idle;
2174 mvi DFFSXFRCTL, CLRCHN ret;
2176 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
2179 * Load a dummy segment if preload space is available.
2181 mov HADDR[0], SHARED_DATA_ADDR;
2182 add HADDR[1], PKT_OVERRUN_BUFOFFSET, SHARED_DATA_ADDR[1];
2185 adc HADDR[2], A, SHARED_DATA_ADDR[2];
2186 adc HADDR[3], A, SHARED_DATA_ADDR[3];
2188 bmov HADDR[4], ALLZEROS, 4;
2189 /* PKT_OVERRUN_BUFSIZE is a multiple of 256 */
2191 mvi HCNT[1], ((PKT_OVERRUN_BUFSIZE >> 8) & 0xFF);
projects / linux-2.6 / blob