2 * This file contains the routines for flushing entries from the
3 * TLB and MMU hash table.
5 * Derived from arch/ppc64/mm/init.c:
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
9 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
10 * Copyright (C) 1996 Paul Mackerras
11 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 * Dave Engebretsen <engebret@us.ibm.com>
17 * Rework for PPC64 port.
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
25 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/percpu.h>
29 #include <linux/hardirq.h>
30 #include <asm/pgalloc.h>
31 #include <asm/tlbflush.h>
35 DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
37 /* This is declared as we are using the more or less generic
38 * include/asm-powerpc/tlb.h file -- tgall
40 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
41 DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
42 unsigned long pte_freelist_forced_free;
44 struct pte_freelist_batch
48 pgtable_free_t tables[0];
51 DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
52 unsigned long pte_freelist_forced_free;
54 #define PTE_FREELIST_SIZE \
55 ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
56 / sizeof(pgtable_free_t))
59 static void pte_free_smp_sync(void *arg)
61 /* Do nothing, just ensure we sync with all CPUs */
65 /* This is only called when we are critically out of memory
66 * (and fail to get a page in pte_free_tlb).
68 static void pgtable_free_now(pgtable_free_t pgf)
70 pte_freelist_forced_free++;
72 smp_call_function(pte_free_smp_sync, NULL, 0, 1);
77 static void pte_free_rcu_callback(struct rcu_head *head)
79 struct pte_freelist_batch *batch =
80 container_of(head, struct pte_freelist_batch, rcu);
83 for (i = 0; i < batch->index; i++)
84 pgtable_free(batch->tables[i]);
86 free_page((unsigned long)batch);
89 static void pte_free_submit(struct pte_freelist_batch *batch)
91 INIT_RCU_HEAD(&batch->rcu);
92 call_rcu(&batch->rcu, pte_free_rcu_callback);
95 void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
97 /* This is safe since tlb_gather_mmu has disabled preemption */
98 cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
99 struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
101 if (atomic_read(&tlb->mm->mm_users) < 2 ||
102 cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
107 if (*batchp == NULL) {
108 *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
109 if (*batchp == NULL) {
110 pgtable_free_now(pgf);
113 (*batchp)->index = 0;
115 (*batchp)->tables[(*batchp)->index++] = pgf;
116 if ((*batchp)->index == PTE_FREELIST_SIZE) {
117 pte_free_submit(*batchp);
123 * A linux PTE was changed and the corresponding hash table entry
124 * neesd to be flushed. This function will either perform the flush
125 * immediately or will batch it up if the current CPU has an active
128 * Must be called from within some kind of spinlock/non-preempt region...
130 void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
131 pte_t *ptep, unsigned long pte, int huge)
133 struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
134 unsigned long vsid, vaddr;
141 /* We mask the address for the base page size. Huge pages will
142 * have applied their own masking already
146 /* Get page size (maybe move back to caller).
148 * NOTE: when using special 64K mappings in 4K environment like
149 * for SPEs, we obtain the page size from the slice, which thus
150 * must still exist (and thus the VMA not reused) at the time
154 #ifdef CONFIG_HUGETLB_PAGE
155 psize = mmu_huge_psize;
158 psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */
161 psize = pte_pagesize_index(mm, addr, pte);
163 /* Build full vaddr */
164 if (!is_kernel_addr(addr)) {
165 vsid = get_vsid(mm->context.id, addr);
168 vsid = get_kernel_vsid(addr);
169 vaddr = (vsid << 28 ) | (addr & 0x0fffffff);
170 rpte = __real_pte(__pte(pte), ptep);
173 * Check if we have an active batch on this CPU. If not, just
174 * flush now and return. For now, we don global invalidates
175 * in that case, might be worth testing the mm cpu mask though
176 * and decide to use local invalidates instead...
178 if (!batch->active) {
179 flush_hash_page(vaddr, rpte, psize, 0);
184 * This can happen when we are in the middle of a TLB batch and
185 * we encounter memory pressure (eg copy_page_range when it tries
186 * to allocate a new pte). If we have to reclaim memory and end
187 * up scanning and resetting referenced bits then our batch context
188 * will change mid stream.
190 * We also need to ensure only one page size is present in a given
193 if (i != 0 && (mm != batch->mm || batch->psize != psize)) {
194 __flush_tlb_pending(batch);
199 batch->psize = psize;
201 batch->pte[i] = rpte;
202 batch->vaddr[i] = vaddr;
204 if (i >= PPC64_TLB_BATCH_NR)
205 __flush_tlb_pending(batch);
209 * This function is called when terminating an mmu batch or when a batch
210 * is full. It will perform the flush of all the entries currently stored
213 * Must be called from within some kind of spinlock/non-preempt region...
215 void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
221 tmp = cpumask_of_cpu(smp_processor_id());
222 if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
225 flush_hash_page(batch->vaddr[0], batch->pte[0],
226 batch->psize, local);
228 flush_hash_range(i, local);
232 void pte_free_finish(void)
234 /* This is safe since tlb_gather_mmu has disabled preemption */
235 struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
239 pte_free_submit(*batchp);