2 * IDE tuning and bus mastering support for the CS5510/CS5520
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
13 * *** This driver is strictly experimental ***
15 * (c) Copyright Red Hat Inc 2002
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
35 #include <linux/module.h>
36 #include <linux/types.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/timer.h>
41 #include <linux/ioport.h>
42 #include <linux/blkdev.h>
43 #include <linux/hdreg.h>
45 #include <linux/interrupt.h>
46 #include <linux/init.h>
47 #include <linux/pci.h>
48 #include <linux/ide.h>
49 #include <linux/dma-mapping.h>
61 static struct pio_clocks cs5520_pio_clocks[]={
69 static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
71 ide_hwif_t *hwif = HWIF(drive);
72 struct pci_dev *pdev = hwif->pci_dev;
73 int controller = drive->dn > 1 ? 1 : 0;
76 /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
78 /* 8bit CAT/CRT - 8bit command timing for channel */
79 pci_write_config_byte(pdev, 0x62 + controller,
80 (cs5520_pio_clocks[pio].recovery << 4) |
81 (cs5520_pio_clocks[pio].assert));
83 /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
85 /* FIXME: should these use address ? */
86 /* Data read timing */
87 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
88 (cs5520_pio_clocks[pio].recovery << 4) |
89 (cs5520_pio_clocks[pio].assert));
90 /* Write command timing */
91 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
92 (cs5520_pio_clocks[pio].recovery << 4) |
93 (cs5520_pio_clocks[pio].assert));
95 /* Set the DMA enable/disable flag */
96 reg = inb(hwif->dma_base + 0x02 + 8*controller);
97 reg |= 1<<((drive->dn&1)+5);
98 outb(reg, hwif->dma_base + 0x02 + 8*controller);
101 static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
103 printk(KERN_ERR "cs55x0: bad ide timing.\n");
105 cs5520_set_pio_mode(drive, 0);
109 * We provide a callback for our nonstandard DMA location
112 static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
114 unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
115 if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
117 ide_setup_dma(hwif, bmide, 8);
121 * We wrap the DMA activate to set the vdma flag. This is needed
122 * so that the IDE DMA layer issues PIO not DMA commands over the
126 static int cs5520_dma_on(ide_drive_t *drive)
132 static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
134 hwif->set_pio_mode = &cs5520_set_pio_mode;
135 hwif->set_dma_mode = &cs5520_set_dma_mode;
137 if (hwif->dma_base == 0) {
138 hwif->drives[1].autotune = hwif->drives[0].autotune = 1;
142 hwif->ide_dma_on = &cs5520_dma_on;
144 /* ATAPI is harder so leave it for now */
146 hwif->ultra_mask = 0;
147 hwif->swdma_mask = 0;
148 hwif->mwdma_mask = 0;
151 #define DECLARE_CS_DEV(name_str) \
154 .init_setup_dma = cs5520_init_setup_dma, \
155 .init_hwif = init_hwif_cs5520, \
156 .autodma = AUTODMA, \
157 .bootable = ON_BOARD, \
158 .host_flags = IDE_HFLAG_ISA_PORTS | \
160 .pio_mask = ATA_PIO4, \
163 static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
164 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
165 /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
169 * The 5510/5520 are a bit weird. They don't quite set up the way
170 * the PCI helper layer expects so we must do much of the set up
174 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
176 ide_hwif_t *hwif = NULL, *mate = NULL;
178 ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
180 ide_setup_pci_noise(dev, d);
182 /* We must not grab the entire device, it has 'ISA' space in its
183 BARS too and we will freak out other bits of the kernel */
184 if (pci_enable_device_bars(dev, 1<<2)) {
185 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
189 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
190 printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
197 * Now the chipset is configured we can let the core
198 * do all the device setup for us
201 ide_pci_setup_ports(dev, d, 14, &index);
203 if ((index.b.low & 0xf0) != 0xf0)
204 hwif = &ide_hwifs[index.b.low];
205 if ((index.b.high & 0xf0) != 0xf0)
206 mate = &ide_hwifs[index.b.high];
209 probe_hwif_init(hwif);
211 probe_hwif_init(mate);
214 ide_proc_register_port(hwif);
216 ide_proc_register_port(mate);
221 static const struct pci_device_id cs5520_pci_tbl[] = {
222 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
223 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
226 MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
228 static struct pci_driver driver = {
230 .id_table = cs5520_pci_tbl,
231 .probe = cs5520_init_one,
234 static int __init cs5520_ide_init(void)
236 return ide_pci_register_driver(&driver);
239 module_init(cs5520_ide_init);
241 MODULE_AUTHOR("Alan Cox");
242 MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
243 MODULE_LICENSE("GPL");