Merge branch 'for-2.6.24' of git://git.secretlab.ca/git/linux-2.6-mpc52xx into merge
[linux-2.6] / drivers / spi / spi_bfin5xx.c
1 /*
2  * File:         drivers/spi/bfin5xx_spi.c
3  * Based on:     N/A
4  * Author:       Luke Yang (Analog Devices Inc.)
5  *
6  * Created:      March. 10th 2006
7  * Description:  SPI controller driver for Blackfin 5xx
8  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
9  *
10  * Modified:
11  *      March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)
12  *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)
13  *
14  * Copyright 2004-2006 Analog Devices Inc.
15  *
16  * This program is free software ;  you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation ;  either version 2, or (at your option)
19  * any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY ;  without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program ;  see the file COPYING.
28  * If not, write to the Free Software Foundation,
29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30  */
31
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/device.h>
35 #include <linux/ioport.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/spi/spi.h>
41 #include <linux/workqueue.h>
42 #include <linux/delay.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/delay.h>
47 #include <asm/dma.h>
48
49 #include <asm/bfin5xx_spi.h>
50
51 MODULE_AUTHOR("Luke Yang");
52 MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");
53 MODULE_LICENSE("GPL");
54
55 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
56
57 #define DEFINE_SPI_REG(reg, off) \
58 static inline u16 read_##reg(void) \
59             { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \
60 static inline void write_##reg(u16 v) \
61             {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\
62              SSYNC();}
63
64 DEFINE_SPI_REG(CTRL, 0x00)
65 DEFINE_SPI_REG(FLAG, 0x04)
66 DEFINE_SPI_REG(STAT, 0x08)
67 DEFINE_SPI_REG(TDBR, 0x0C)
68 DEFINE_SPI_REG(RDBR, 0x10)
69 DEFINE_SPI_REG(BAUD, 0x14)
70 DEFINE_SPI_REG(SHAW, 0x18)
71 #define START_STATE ((void*)0)
72 #define RUNNING_STATE ((void*)1)
73 #define DONE_STATE ((void*)2)
74 #define ERROR_STATE ((void*)-1)
75 #define QUEUE_RUNNING 0
76 #define QUEUE_STOPPED 1
77 int dma_requested;
78
79 struct driver_data {
80         /* Driver model hookup */
81         struct platform_device *pdev;
82
83         /* SPI framework hookup */
84         struct spi_master *master;
85
86         /* BFIN hookup */
87         struct bfin5xx_spi_master *master_info;
88
89         /* Driver message queue */
90         struct workqueue_struct *workqueue;
91         struct work_struct pump_messages;
92         spinlock_t lock;
93         struct list_head queue;
94         int busy;
95         int run;
96
97         /* Message Transfer pump */
98         struct tasklet_struct pump_transfers;
99
100         /* Current message transfer state info */
101         struct spi_message *cur_msg;
102         struct spi_transfer *cur_transfer;
103         struct chip_data *cur_chip;
104         size_t len_in_bytes;
105         size_t len;
106         void *tx;
107         void *tx_end;
108         void *rx;
109         void *rx_end;
110         int dma_mapped;
111         dma_addr_t rx_dma;
112         dma_addr_t tx_dma;
113         size_t rx_map_len;
114         size_t tx_map_len;
115         u8 n_bytes;
116         void (*write) (struct driver_data *);
117         void (*read) (struct driver_data *);
118         void (*duplex) (struct driver_data *);
119 };
120
121 struct chip_data {
122         u16 ctl_reg;
123         u16 baud;
124         u16 flag;
125
126         u8 chip_select_num;
127         u8 n_bytes;
128         u8 width;               /* 0 or 1 */
129         u8 enable_dma;
130         u8 bits_per_word;       /* 8 or 16 */
131         u8 cs_change_per_word;
132         u8 cs_chg_udelay;
133         void (*write) (struct driver_data *);
134         void (*read) (struct driver_data *);
135         void (*duplex) (struct driver_data *);
136 };
137
138 static void bfin_spi_enable(struct driver_data *drv_data)
139 {
140         u16 cr;
141
142         cr = read_CTRL();
143         write_CTRL(cr | BIT_CTL_ENABLE);
144         SSYNC();
145 }
146
147 static void bfin_spi_disable(struct driver_data *drv_data)
148 {
149         u16 cr;
150
151         cr = read_CTRL();
152         write_CTRL(cr & (~BIT_CTL_ENABLE));
153         SSYNC();
154 }
155
156 /* Caculate the SPI_BAUD register value based on input HZ */
157 static u16 hz_to_spi_baud(u32 speed_hz)
158 {
159         u_long sclk = get_sclk();
160         u16 spi_baud = (sclk / (2 * speed_hz));
161
162         if ((sclk % (2 * speed_hz)) > 0)
163                 spi_baud++;
164
165         return spi_baud;
166 }
167
168 static int flush(struct driver_data *drv_data)
169 {
170         unsigned long limit = loops_per_jiffy << 1;
171
172         /* wait for stop and clear stat */
173         while (!(read_STAT() & BIT_STAT_SPIF) && limit--)
174                 continue;
175
176         write_STAT(BIT_STAT_CLR);
177
178         return limit;
179 }
180
181 /* stop controller and re-config current chip*/
182 static void restore_state(struct driver_data *drv_data)
183 {
184         struct chip_data *chip = drv_data->cur_chip;
185
186         /* Clear status and disable clock */
187         write_STAT(BIT_STAT_CLR);
188         bfin_spi_disable(drv_data);
189         dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
190
191 #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
192         dev_dbg(&drv_data->pdev->dev, 
193                 "chip select number is %d\n", chip->chip_select_num);
194         
195         switch (chip->chip_select_num) {
196         case 1:
197                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);
198                 SSYNC();
199                 break;
200
201         case 2:
202         case 3:
203                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);
204                 SSYNC();
205                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
206                 SSYNC();
207                 break;
208
209         case 4:
210                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);
211                 SSYNC();
212                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);
213                 SSYNC();
214                 break;
215
216         case 5:
217                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);
218                 SSYNC();
219                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);
220                 SSYNC();
221                 break;
222
223         case 6:
224                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);
225                 SSYNC();
226                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);
227                 SSYNC();
228                 break;
229
230         case 7:
231                 bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);
232                 SSYNC();
233                 bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);
234                 SSYNC();
235                 break;
236         }
237 #endif
238
239         /* Load the registers */
240         write_CTRL(chip->ctl_reg);
241         write_BAUD(chip->baud);
242         write_FLAG(chip->flag);
243 }
244
245 /* used to kick off transfer in rx mode */
246 static unsigned short dummy_read(void)
247 {
248         unsigned short tmp;
249         tmp = read_RDBR();
250         return tmp;
251 }
252
253 static void null_writer(struct driver_data *drv_data)
254 {
255         u8 n_bytes = drv_data->n_bytes;
256
257         while (drv_data->tx < drv_data->tx_end) {
258                 write_TDBR(0);
259                 while ((read_STAT() & BIT_STAT_TXS))
260                         continue;
261                 drv_data->tx += n_bytes;
262         }
263 }
264
265 static void null_reader(struct driver_data *drv_data)
266 {
267         u8 n_bytes = drv_data->n_bytes;
268         dummy_read();
269
270         while (drv_data->rx < drv_data->rx_end) {
271                 while (!(read_STAT() & BIT_STAT_RXS))
272                         continue;
273                 dummy_read();
274                 drv_data->rx += n_bytes;
275         }
276 }
277
278 static void u8_writer(struct driver_data *drv_data)
279 {
280         dev_dbg(&drv_data->pdev->dev, 
281                 "cr8-s is 0x%x\n", read_STAT());
282         while (drv_data->tx < drv_data->tx_end) {
283                 write_TDBR(*(u8 *) (drv_data->tx));
284                 while (read_STAT() & BIT_STAT_TXS)
285                         continue;
286                 ++drv_data->tx;
287         }
288
289         /* poll for SPI completion before returning */
290         while (!(read_STAT() & BIT_STAT_SPIF))
291                 continue;
292 }
293
294 static void u8_cs_chg_writer(struct driver_data *drv_data)
295 {
296         struct chip_data *chip = drv_data->cur_chip;
297
298         while (drv_data->tx < drv_data->tx_end) {
299                 write_FLAG(chip->flag);
300                 SSYNC();
301
302                 write_TDBR(*(u8 *) (drv_data->tx));
303                 while (read_STAT() & BIT_STAT_TXS)
304                         continue;
305                 while (!(read_STAT() & BIT_STAT_SPIF))
306                         continue;
307                 write_FLAG(0xFF00 | chip->flag);
308                 SSYNC();
309                 if (chip->cs_chg_udelay)
310                         udelay(chip->cs_chg_udelay);
311                 ++drv_data->tx;
312         }
313         write_FLAG(0xFF00);
314         SSYNC();
315 }
316
317 static void u8_reader(struct driver_data *drv_data)
318 {
319         dev_dbg(&drv_data->pdev->dev, 
320                 "cr-8 is 0x%x\n", read_STAT());
321
322         /* clear TDBR buffer before read(else it will be shifted out) */
323         write_TDBR(0xFFFF);
324
325         dummy_read();
326
327         while (drv_data->rx < drv_data->rx_end - 1) {
328                 while (!(read_STAT() & BIT_STAT_RXS))
329                         continue;
330                 *(u8 *) (drv_data->rx) = read_RDBR();
331                 ++drv_data->rx;
332         }
333
334         while (!(read_STAT() & BIT_STAT_RXS))
335                 continue;
336         *(u8 *) (drv_data->rx) = read_SHAW();
337         ++drv_data->rx;
338 }
339
340 static void u8_cs_chg_reader(struct driver_data *drv_data)
341 {
342         struct chip_data *chip = drv_data->cur_chip;
343
344         while (drv_data->rx < drv_data->rx_end) {
345                 write_FLAG(chip->flag);
346                 SSYNC();
347
348                 read_RDBR();    /* kick off */
349                 while (!(read_STAT() & BIT_STAT_RXS))
350                         continue;
351                 while (!(read_STAT() & BIT_STAT_SPIF))
352                         continue;
353                 *(u8 *) (drv_data->rx) = read_SHAW();
354                 write_FLAG(0xFF00 | chip->flag);
355                 SSYNC();
356                 if (chip->cs_chg_udelay)
357                         udelay(chip->cs_chg_udelay);
358                 ++drv_data->rx;
359         }
360         write_FLAG(0xFF00);
361         SSYNC();
362 }
363
364 static void u8_duplex(struct driver_data *drv_data)
365 {
366         /* in duplex mode, clk is triggered by writing of TDBR */
367         while (drv_data->rx < drv_data->rx_end) {
368                 write_TDBR(*(u8 *) (drv_data->tx));
369                 while (!(read_STAT() & BIT_STAT_SPIF))
370                         continue;
371                 while (!(read_STAT() & BIT_STAT_RXS))
372                         continue;
373                 *(u8 *) (drv_data->rx) = read_RDBR();
374                 ++drv_data->rx;
375                 ++drv_data->tx;
376         }
377 }
378
379 static void u8_cs_chg_duplex(struct driver_data *drv_data)
380 {
381         struct chip_data *chip = drv_data->cur_chip;
382
383         while (drv_data->rx < drv_data->rx_end) {
384                 write_FLAG(chip->flag);
385                 SSYNC();
386
387                 write_TDBR(*(u8 *) (drv_data->tx));
388                 while (!(read_STAT() & BIT_STAT_SPIF))
389                         continue;
390                 while (!(read_STAT() & BIT_STAT_RXS))
391                         continue;
392                 *(u8 *) (drv_data->rx) = read_RDBR();
393                 write_FLAG(0xFF00 | chip->flag);
394                 SSYNC();
395                 if (chip->cs_chg_udelay)
396                         udelay(chip->cs_chg_udelay);
397                 ++drv_data->rx;
398                 ++drv_data->tx;
399         }
400         write_FLAG(0xFF00);
401         SSYNC();
402 }
403
404 static void u16_writer(struct driver_data *drv_data)
405 {
406         dev_dbg(&drv_data->pdev->dev, 
407                 "cr16 is 0x%x\n", read_STAT());
408
409         while (drv_data->tx < drv_data->tx_end) {
410                 write_TDBR(*(u16 *) (drv_data->tx));
411                 while ((read_STAT() & BIT_STAT_TXS))
412                         continue;
413                 drv_data->tx += 2;
414         }
415
416         /* poll for SPI completion before returning */
417         while (!(read_STAT() & BIT_STAT_SPIF))
418                 continue;
419 }
420
421 static void u16_cs_chg_writer(struct driver_data *drv_data)
422 {
423         struct chip_data *chip = drv_data->cur_chip;
424
425         while (drv_data->tx < drv_data->tx_end) {
426                 write_FLAG(chip->flag);
427                 SSYNC();
428
429                 write_TDBR(*(u16 *) (drv_data->tx));
430                 while ((read_STAT() & BIT_STAT_TXS))
431                         continue;
432                 while (!(read_STAT() & BIT_STAT_SPIF))
433                         continue;
434                 write_FLAG(0xFF00 | chip->flag);
435                 SSYNC();
436                 if (chip->cs_chg_udelay)
437                         udelay(chip->cs_chg_udelay);
438                 drv_data->tx += 2;
439         }
440         write_FLAG(0xFF00);
441         SSYNC();
442 }
443
444 static void u16_reader(struct driver_data *drv_data)
445 {
446         dev_dbg(&drv_data->pdev->dev,
447                 "cr-16 is 0x%x\n", read_STAT());
448         dummy_read();
449
450         while (drv_data->rx < (drv_data->rx_end - 2)) {
451                 while (!(read_STAT() & BIT_STAT_RXS))
452                         continue;
453                 *(u16 *) (drv_data->rx) = read_RDBR();
454                 drv_data->rx += 2;
455         }
456
457         while (!(read_STAT() & BIT_STAT_RXS))
458                 continue;
459         *(u16 *) (drv_data->rx) = read_SHAW();
460         drv_data->rx += 2;
461 }
462
463 static void u16_cs_chg_reader(struct driver_data *drv_data)
464 {
465         struct chip_data *chip = drv_data->cur_chip;
466
467         while (drv_data->rx < drv_data->rx_end) {
468                 write_FLAG(chip->flag);
469                 SSYNC();
470
471                 read_RDBR();    /* kick off */
472                 while (!(read_STAT() & BIT_STAT_RXS))
473                         continue;
474                 while (!(read_STAT() & BIT_STAT_SPIF))
475                         continue;
476                 *(u16 *) (drv_data->rx) = read_SHAW();
477                 write_FLAG(0xFF00 | chip->flag);
478                 SSYNC();
479                 if (chip->cs_chg_udelay)
480                         udelay(chip->cs_chg_udelay);
481                 drv_data->rx += 2;
482         }
483         write_FLAG(0xFF00);
484         SSYNC();
485 }
486
487 static void u16_duplex(struct driver_data *drv_data)
488 {
489         /* in duplex mode, clk is triggered by writing of TDBR */
490         while (drv_data->tx < drv_data->tx_end) {
491                 write_TDBR(*(u16 *) (drv_data->tx));
492                 while (!(read_STAT() & BIT_STAT_SPIF))
493                         continue;
494                 while (!(read_STAT() & BIT_STAT_RXS))
495                         continue;
496                 *(u16 *) (drv_data->rx) = read_RDBR();
497                 drv_data->rx += 2;
498                 drv_data->tx += 2;
499         }
500 }
501
502 static void u16_cs_chg_duplex(struct driver_data *drv_data)
503 {
504         struct chip_data *chip = drv_data->cur_chip;
505
506         while (drv_data->tx < drv_data->tx_end) {
507                 write_FLAG(chip->flag);
508                 SSYNC();
509
510                 write_TDBR(*(u16 *) (drv_data->tx));
511                 while (!(read_STAT() & BIT_STAT_SPIF))
512                         continue;
513                 while (!(read_STAT() & BIT_STAT_RXS))
514                         continue;
515                 *(u16 *) (drv_data->rx) = read_RDBR();
516                 write_FLAG(0xFF00 | chip->flag);
517                 SSYNC();
518                 if (chip->cs_chg_udelay)
519                         udelay(chip->cs_chg_udelay);
520                 drv_data->rx += 2;
521                 drv_data->tx += 2;
522         }
523         write_FLAG(0xFF00);
524         SSYNC();
525 }
526
527 /* test if ther is more transfer to be done */
528 static void *next_transfer(struct driver_data *drv_data)
529 {
530         struct spi_message *msg = drv_data->cur_msg;
531         struct spi_transfer *trans = drv_data->cur_transfer;
532
533         /* Move to next transfer */
534         if (trans->transfer_list.next != &msg->transfers) {
535                 drv_data->cur_transfer =
536                     list_entry(trans->transfer_list.next,
537                                struct spi_transfer, transfer_list);
538                 return RUNNING_STATE;
539         } else
540                 return DONE_STATE;
541 }
542
543 /*
544  * caller already set message->status;
545  * dma and pio irqs are blocked give finished message back
546  */
547 static void giveback(struct driver_data *drv_data)
548 {
549         struct spi_transfer *last_transfer;
550         unsigned long flags;
551         struct spi_message *msg;
552
553         spin_lock_irqsave(&drv_data->lock, flags);
554         msg = drv_data->cur_msg;
555         drv_data->cur_msg = NULL;
556         drv_data->cur_transfer = NULL;
557         drv_data->cur_chip = NULL;
558         queue_work(drv_data->workqueue, &drv_data->pump_messages);
559         spin_unlock_irqrestore(&drv_data->lock, flags);
560
561         last_transfer = list_entry(msg->transfers.prev,
562                                    struct spi_transfer, transfer_list);
563
564         msg->state = NULL;
565
566         /* disable chip select signal. And not stop spi in autobuffer mode */
567         if (drv_data->tx_dma != 0xFFFF) {
568                 write_FLAG(0xFF00);
569                 bfin_spi_disable(drv_data);
570         }
571
572         if (msg->complete)
573                 msg->complete(msg->context);
574 }
575
576 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
577 {
578         struct driver_data *drv_data = (struct driver_data *)dev_id;
579         struct spi_message *msg = drv_data->cur_msg;
580
581         dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
582         clear_dma_irqstat(CH_SPI);
583
584         /* Wait for DMA to complete */
585         while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN)
586                 continue;
587
588         /*
589          * wait for the last transaction shifted out.  HRM states:
590          * at this point there may still be data in the SPI DMA FIFO waiting
591          * to be transmitted ... software needs to poll TXS in the SPI_STAT
592          * register until it goes low for 2 successive reads
593          */
594         if (drv_data->tx != NULL) {
595                 while ((bfin_read_SPI_STAT() & TXS) ||
596                        (bfin_read_SPI_STAT() & TXS))
597                         continue;
598         }
599
600         while (!(bfin_read_SPI_STAT() & SPIF))
601                 continue;
602
603         bfin_spi_disable(drv_data);
604
605         msg->actual_length += drv_data->len_in_bytes;
606
607         /* Move to next transfer */
608         msg->state = next_transfer(drv_data);
609
610         /* Schedule transfer tasklet */
611         tasklet_schedule(&drv_data->pump_transfers);
612
613         /* free the irq handler before next transfer */
614         dev_dbg(&drv_data->pdev->dev,
615                 "disable dma channel irq%d\n",
616                 CH_SPI);
617         dma_disable_irq(CH_SPI);
618
619         return IRQ_HANDLED;
620 }
621
622 static void pump_transfers(unsigned long data)
623 {
624         struct driver_data *drv_data = (struct driver_data *)data;
625         struct spi_message *message = NULL;
626         struct spi_transfer *transfer = NULL;
627         struct spi_transfer *previous = NULL;
628         struct chip_data *chip = NULL;
629         u8 width;
630         u16 cr, dma_width, dma_config;
631         u32 tranf_success = 1;
632
633         /* Get current state information */
634         message = drv_data->cur_msg;
635         transfer = drv_data->cur_transfer;
636         chip = drv_data->cur_chip;
637
638         /*
639          * if msg is error or done, report it back using complete() callback
640          */
641
642          /* Handle for abort */
643         if (message->state == ERROR_STATE) {
644                 message->status = -EIO;
645                 giveback(drv_data);
646                 return;
647         }
648
649         /* Handle end of message */
650         if (message->state == DONE_STATE) {
651                 message->status = 0;
652                 giveback(drv_data);
653                 return;
654         }
655
656         /* Delay if requested at end of transfer */
657         if (message->state == RUNNING_STATE) {
658                 previous = list_entry(transfer->transfer_list.prev,
659                                       struct spi_transfer, transfer_list);
660                 if (previous->delay_usecs)
661                         udelay(previous->delay_usecs);
662         }
663
664         /* Setup the transfer state based on the type of transfer */
665         if (flush(drv_data) == 0) {
666                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
667                 message->status = -EIO;
668                 giveback(drv_data);
669                 return;
670         }
671
672         if (transfer->tx_buf != NULL) {
673                 drv_data->tx = (void *)transfer->tx_buf;
674                 drv_data->tx_end = drv_data->tx + transfer->len;
675                 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
676                         transfer->tx_buf, drv_data->tx_end);
677         } else {
678                 drv_data->tx = NULL;
679         }
680
681         if (transfer->rx_buf != NULL) {
682                 drv_data->rx = transfer->rx_buf;
683                 drv_data->rx_end = drv_data->rx + transfer->len;
684                 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
685                         transfer->rx_buf, drv_data->rx_end);
686         } else {
687                 drv_data->rx = NULL;
688         }
689
690         drv_data->rx_dma = transfer->rx_dma;
691         drv_data->tx_dma = transfer->tx_dma;
692         drv_data->len_in_bytes = transfer->len;
693
694         width = chip->width;
695         if (width == CFG_SPI_WORDSIZE16) {
696                 drv_data->len = (transfer->len) >> 1;
697         } else {
698                 drv_data->len = transfer->len;
699         }
700         drv_data->write = drv_data->tx ? chip->write : null_writer;
701         drv_data->read = drv_data->rx ? chip->read : null_reader;
702         drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
703         dev_dbg(&drv_data->pdev->dev,
704                 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
705                 drv_data->write, chip->write, null_writer);
706
707         /* speed and width has been set on per message */
708         message->state = RUNNING_STATE;
709         dma_config = 0;
710
711         /* restore spi status for each spi transfer */
712         if (transfer->speed_hz) {
713                 write_BAUD(hz_to_spi_baud(transfer->speed_hz));
714         } else {
715                 write_BAUD(chip->baud);
716         }
717         write_FLAG(chip->flag);
718
719         dev_dbg(&drv_data->pdev->dev,
720                 "now pumping a transfer: width is %d, len is %d\n",
721                 width, transfer->len);
722
723         /*
724          * Try to map dma buffer and do a dma transfer if
725          * successful use different way to r/w according to
726          * drv_data->cur_chip->enable_dma
727          */
728         if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
729
730                 write_STAT(BIT_STAT_CLR);
731                 disable_dma(CH_SPI);
732                 clear_dma_irqstat(CH_SPI);
733                 bfin_spi_disable(drv_data);
734
735                 /* config dma channel */
736                 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
737                 if (width == CFG_SPI_WORDSIZE16) {
738                         set_dma_x_count(CH_SPI, drv_data->len);
739                         set_dma_x_modify(CH_SPI, 2);
740                         dma_width = WDSIZE_16;
741                 } else {
742                         set_dma_x_count(CH_SPI, drv_data->len);
743                         set_dma_x_modify(CH_SPI, 1);
744                         dma_width = WDSIZE_8;
745                 }
746
747                 /* set transfer width,direction. And enable spi */
748                 cr = (read_CTRL() & (~BIT_CTL_TIMOD));
749
750                 /* dirty hack for autobuffer DMA mode */
751                 if (drv_data->tx_dma == 0xFFFF) {
752                         dev_dbg(&drv_data->pdev->dev,
753                                 "doing autobuffer DMA out.\n");
754
755                         /* no irq in autobuffer mode */
756                         dma_config =
757                             (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
758                         set_dma_config(CH_SPI, dma_config);
759                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
760                         enable_dma(CH_SPI);
761                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
762                                    (CFG_SPI_ENABLE << 14));
763
764                         /* just return here, there can only be one transfer in this mode */
765                         message->status = 0;
766                         giveback(drv_data);
767                         return;
768                 }
769
770                 /* In dma mode, rx or tx must be NULL in one transfer */
771                 if (drv_data->rx != NULL) {
772                         /* set transfer mode, and enable SPI */
773                         dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
774
775                         /* disable SPI before write to TDBR */
776                         write_CTRL(cr & ~BIT_CTL_ENABLE);
777
778                         /* clear tx reg soformer data is not shifted out */
779                         write_TDBR(0xFF);
780
781                         set_dma_x_count(CH_SPI, drv_data->len);
782
783                         /* start dma */
784                         dma_enable_irq(CH_SPI);
785                         dma_config = (WNR | RESTART | dma_width | DI_EN);
786                         set_dma_config(CH_SPI, dma_config);
787                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx);
788                         enable_dma(CH_SPI);
789
790                         cr |=
791                             CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE <<
792                                                               14);
793                         /* set transfer mode, and enable SPI */
794                         write_CTRL(cr);
795                 } else if (drv_data->tx != NULL) {
796                         dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
797
798                         /* start dma */
799                         dma_enable_irq(CH_SPI);
800                         dma_config = (RESTART | dma_width | DI_EN);
801                         set_dma_config(CH_SPI, dma_config);
802                         set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx);
803                         enable_dma(CH_SPI);
804
805                         write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) |
806                                    (CFG_SPI_ENABLE << 14));
807
808                 }
809         } else {
810                 /* IO mode write then read */
811                 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
812
813                 write_STAT(BIT_STAT_CLR);
814
815                 if (drv_data->tx != NULL && drv_data->rx != NULL) {
816                         /* full duplex mode */
817                         BUG_ON((drv_data->tx_end - drv_data->tx) !=
818                                (drv_data->rx_end - drv_data->rx));
819                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));  
820                         cr |= CFG_SPI_WRITE | (width << 8) |
821                                 (CFG_SPI_ENABLE << 14);
822                         dev_dbg(&drv_data->pdev->dev,
823                                 "IO duplex: cr is 0x%x\n", cr);
824
825                         write_CTRL(cr);
826                         SSYNC();
827
828                         drv_data->duplex(drv_data);
829
830                         if (drv_data->tx != drv_data->tx_end)
831                                 tranf_success = 0;
832                 } else if (drv_data->tx != NULL) {
833                         /* write only half duplex */
834                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
835                         cr |= CFG_SPI_WRITE | (width << 8) |
836                                 (CFG_SPI_ENABLE << 14);
837                         dev_dbg(&drv_data->pdev->dev, 
838                                 "IO write: cr is 0x%x\n", cr);
839
840                         write_CTRL(cr);
841                         SSYNC();
842
843                         drv_data->write(drv_data);
844
845                         if (drv_data->tx != drv_data->tx_end)
846                                 tranf_success = 0;
847                 } else if (drv_data->rx != NULL) {
848                         /* read only half duplex */
849                         cr = (read_CTRL() & (~BIT_CTL_TIMOD));
850                         cr |= CFG_SPI_READ | (width << 8) |
851                                 (CFG_SPI_ENABLE << 14);
852                         dev_dbg(&drv_data->pdev->dev, 
853                                 "IO read: cr is 0x%x\n", cr);
854
855                         write_CTRL(cr);
856                         SSYNC();
857
858                         drv_data->read(drv_data);
859                         if (drv_data->rx != drv_data->rx_end)
860                                 tranf_success = 0;
861                 }
862
863                 if (!tranf_success) {
864                         dev_dbg(&drv_data->pdev->dev, 
865                                 "IO write error!\n");
866                         message->state = ERROR_STATE;
867                 } else {
868                         /* Update total byte transfered */
869                         message->actual_length += drv_data->len;
870
871                         /* Move to next transfer of this msg */
872                         message->state = next_transfer(drv_data);
873                 }
874
875                 /* Schedule next transfer tasklet */
876                 tasklet_schedule(&drv_data->pump_transfers);
877
878         }
879 }
880
881 /* pop a msg from queue and kick off real transfer */
882 static void pump_messages(struct work_struct *work)
883 {
884         struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages);
885         unsigned long flags;
886
887         /* Lock queue and check for queue work */
888         spin_lock_irqsave(&drv_data->lock, flags);
889         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
890                 /* pumper kicked off but no work to do */
891                 drv_data->busy = 0;
892                 spin_unlock_irqrestore(&drv_data->lock, flags);
893                 return;
894         }
895
896         /* Make sure we are not already running a message */
897         if (drv_data->cur_msg) {
898                 spin_unlock_irqrestore(&drv_data->lock, flags);
899                 return;
900         }
901
902         /* Extract head of queue */
903         drv_data->cur_msg = list_entry(drv_data->queue.next,
904                                        struct spi_message, queue);
905         list_del_init(&drv_data->cur_msg->queue);
906
907         /* Initial message state */
908         drv_data->cur_msg->state = START_STATE;
909         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
910                                             struct spi_transfer, transfer_list);
911
912         /* Setup the SSP using the per chip configuration */
913         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
914         restore_state(drv_data);
915         dev_dbg(&drv_data->pdev->dev,
916                 "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
917                 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
918                 drv_data->cur_chip->ctl_reg);
919         
920         dev_dbg(&drv_data->pdev->dev, 
921                 "the first transfer len is %d\n",
922                 drv_data->cur_transfer->len);
923
924         /* Mark as busy and launch transfers */
925         tasklet_schedule(&drv_data->pump_transfers);
926
927         drv_data->busy = 1;
928         spin_unlock_irqrestore(&drv_data->lock, flags);
929 }
930
931 /*
932  * got a msg to transfer, queue it in drv_data->queue.
933  * And kick off message pumper
934  */
935 static int transfer(struct spi_device *spi, struct spi_message *msg)
936 {
937         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
938         unsigned long flags;
939
940         spin_lock_irqsave(&drv_data->lock, flags);
941
942         if (drv_data->run == QUEUE_STOPPED) {
943                 spin_unlock_irqrestore(&drv_data->lock, flags);
944                 return -ESHUTDOWN;
945         }
946
947         msg->actual_length = 0;
948         msg->status = -EINPROGRESS;
949         msg->state = START_STATE;
950
951         dev_dbg(&spi->dev, "adding an msg in transfer() \n");
952         list_add_tail(&msg->queue, &drv_data->queue);
953
954         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
955                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
956
957         spin_unlock_irqrestore(&drv_data->lock, flags);
958
959         return 0;
960 }
961
962 /* first setup for new devices */
963 static int setup(struct spi_device *spi)
964 {
965         struct bfin5xx_spi_chip *chip_info = NULL;
966         struct chip_data *chip;
967         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
968         u8 spi_flg;
969
970         /* Abort device setup if requested features are not supported */
971         if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
972                 dev_err(&spi->dev, "requested mode not fully supported\n");
973                 return -EINVAL;
974         }
975
976         /* Zero (the default) here means 8 bits */
977         if (!spi->bits_per_word)
978                 spi->bits_per_word = 8;
979
980         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
981                 return -EINVAL;
982
983         /* Only alloc (or use chip_info) on first setup */
984         chip = spi_get_ctldata(spi);
985         if (chip == NULL) {
986                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
987                 if (!chip)
988                         return -ENOMEM;
989
990                 chip->enable_dma = 0;
991                 chip_info = spi->controller_data;
992         }
993
994         /* chip_info isn't always needed */
995         if (chip_info) {
996                 chip->enable_dma = chip_info->enable_dma != 0
997                     && drv_data->master_info->enable_dma;
998                 chip->ctl_reg = chip_info->ctl_reg;
999                 chip->bits_per_word = chip_info->bits_per_word;
1000                 chip->cs_change_per_word = chip_info->cs_change_per_word;
1001                 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1002         }
1003
1004         /* translate common spi framework into our register */
1005         if (spi->mode & SPI_CPOL)
1006                 chip->ctl_reg |= CPOL;
1007         if (spi->mode & SPI_CPHA)
1008                 chip->ctl_reg |= CPHA;
1009         if (spi->mode & SPI_LSB_FIRST)
1010                 chip->ctl_reg |= LSBF;
1011         /* we dont support running in slave mode (yet?) */
1012         chip->ctl_reg |= MSTR;
1013
1014         /*
1015          * if any one SPI chip is registered and wants DMA, request the
1016          * DMA channel for it
1017          */
1018         if (chip->enable_dma && !dma_requested) {
1019                 /* register dma irq handler */
1020                 if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) {
1021                         dev_dbg(&spi->dev,
1022                                 "Unable to request BlackFin SPI DMA channel\n");
1023                         return -ENODEV;
1024                 }
1025                 if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data)
1026                     < 0) {
1027                         dev_dbg(&spi->dev, "Unable to set dma callback\n");
1028                         return -EPERM;
1029                 }
1030                 dma_disable_irq(CH_SPI);
1031                 dma_requested = 1;
1032         }
1033
1034         /*
1035          * Notice: for blackfin, the speed_hz is the value of register
1036          * SPI_BAUD, not the real baudrate
1037          */
1038         chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1039         spi_flg = ~(1 << (spi->chip_select));
1040         chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1041         chip->chip_select_num = spi->chip_select;
1042
1043         switch (chip->bits_per_word) {
1044         case 8:
1045                 chip->n_bytes = 1;
1046                 chip->width = CFG_SPI_WORDSIZE8;
1047                 chip->read = chip->cs_change_per_word ?
1048                         u8_cs_chg_reader : u8_reader;
1049                 chip->write = chip->cs_change_per_word ?
1050                         u8_cs_chg_writer : u8_writer;
1051                 chip->duplex = chip->cs_change_per_word ?
1052                         u8_cs_chg_duplex : u8_duplex;
1053                 break;
1054
1055         case 16:
1056                 chip->n_bytes = 2;
1057                 chip->width = CFG_SPI_WORDSIZE16;
1058                 chip->read = chip->cs_change_per_word ?
1059                         u16_cs_chg_reader : u16_reader;
1060                 chip->write = chip->cs_change_per_word ?
1061                         u16_cs_chg_writer : u16_writer;
1062                 chip->duplex = chip->cs_change_per_word ?
1063                         u16_cs_chg_duplex : u16_duplex;
1064                 break;
1065
1066         default:
1067                 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1068                                 chip->bits_per_word);
1069                 kfree(chip);
1070                 return -ENODEV;
1071         }
1072
1073         dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d,",
1074                         spi->modalias, chip->width, chip->enable_dma);
1075         dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1076                         chip->ctl_reg, chip->flag);
1077
1078         spi_set_ctldata(spi, chip);
1079
1080         return 0;
1081 }
1082
1083 /*
1084  * callback for spi framework.
1085  * clean driver specific data
1086  */
1087 static void cleanup(struct spi_device *spi)
1088 {
1089         struct chip_data *chip = spi_get_ctldata(spi);
1090
1091         kfree(chip);
1092 }
1093
1094 static inline int init_queue(struct driver_data *drv_data)
1095 {
1096         INIT_LIST_HEAD(&drv_data->queue);
1097         spin_lock_init(&drv_data->lock);
1098
1099         drv_data->run = QUEUE_STOPPED;
1100         drv_data->busy = 0;
1101
1102         /* init transfer tasklet */
1103         tasklet_init(&drv_data->pump_transfers,
1104                      pump_transfers, (unsigned long)drv_data);
1105
1106         /* init messages workqueue */
1107         INIT_WORK(&drv_data->pump_messages, pump_messages);
1108         drv_data->workqueue =
1109             create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1110         if (drv_data->workqueue == NULL)
1111                 return -EBUSY;
1112
1113         return 0;
1114 }
1115
1116 static inline int start_queue(struct driver_data *drv_data)
1117 {
1118         unsigned long flags;
1119
1120         spin_lock_irqsave(&drv_data->lock, flags);
1121
1122         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1123                 spin_unlock_irqrestore(&drv_data->lock, flags);
1124                 return -EBUSY;
1125         }
1126
1127         drv_data->run = QUEUE_RUNNING;
1128         drv_data->cur_msg = NULL;
1129         drv_data->cur_transfer = NULL;
1130         drv_data->cur_chip = NULL;
1131         spin_unlock_irqrestore(&drv_data->lock, flags);
1132
1133         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1134
1135         return 0;
1136 }
1137
1138 static inline int stop_queue(struct driver_data *drv_data)
1139 {
1140         unsigned long flags;
1141         unsigned limit = 500;
1142         int status = 0;
1143
1144         spin_lock_irqsave(&drv_data->lock, flags);
1145
1146         /*
1147          * This is a bit lame, but is optimized for the common execution path.
1148          * A wait_queue on the drv_data->busy could be used, but then the common
1149          * execution path (pump_messages) would be required to call wake_up or
1150          * friends on every SPI message. Do this instead
1151          */
1152         drv_data->run = QUEUE_STOPPED;
1153         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1154                 spin_unlock_irqrestore(&drv_data->lock, flags);
1155                 msleep(10);
1156                 spin_lock_irqsave(&drv_data->lock, flags);
1157         }
1158
1159         if (!list_empty(&drv_data->queue) || drv_data->busy)
1160                 status = -EBUSY;
1161
1162         spin_unlock_irqrestore(&drv_data->lock, flags);
1163
1164         return status;
1165 }
1166
1167 static inline int destroy_queue(struct driver_data *drv_data)
1168 {
1169         int status;
1170
1171         status = stop_queue(drv_data);
1172         if (status != 0)
1173                 return status;
1174
1175         destroy_workqueue(drv_data->workqueue);
1176
1177         return 0;
1178 }
1179
1180 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1181 {
1182         struct device *dev = &pdev->dev;
1183         struct bfin5xx_spi_master *platform_info;
1184         struct spi_master *master;
1185         struct driver_data *drv_data = 0;
1186         int status = 0;
1187
1188         platform_info = dev->platform_data;
1189
1190         /* Allocate master with space for drv_data */
1191         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1192         if (!master) {
1193                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1194                 return -ENOMEM;
1195         }
1196         drv_data = spi_master_get_devdata(master);
1197         drv_data->master = master;
1198         drv_data->master_info = platform_info;
1199         drv_data->pdev = pdev;
1200
1201         master->bus_num = pdev->id;
1202         master->num_chipselect = platform_info->num_chipselect;
1203         master->cleanup = cleanup;
1204         master->setup = setup;
1205         master->transfer = transfer;
1206
1207         /* Initial and start queue */
1208         status = init_queue(drv_data);
1209         if (status != 0) {
1210                 dev_err(&pdev->dev, "problem initializing queue\n");
1211                 goto out_error_queue_alloc;
1212         }
1213         status = start_queue(drv_data);
1214         if (status != 0) {
1215                 dev_err(&pdev->dev, "problem starting queue\n");
1216                 goto out_error_queue_alloc;
1217         }
1218
1219         /* Register with the SPI framework */
1220         platform_set_drvdata(pdev, drv_data);
1221         status = spi_register_master(master);
1222         if (status != 0) {
1223                 dev_err(&pdev->dev, "problem registering spi master\n");
1224                 goto out_error_queue_alloc;
1225         }
1226         dev_dbg(&pdev->dev, "controller probe successfully\n");
1227         return status;
1228
1229       out_error_queue_alloc:
1230         destroy_queue(drv_data);
1231         spi_master_put(master);
1232         return status;
1233 }
1234
1235 /* stop hardware and remove the driver */
1236 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1237 {
1238         struct driver_data *drv_data = platform_get_drvdata(pdev);
1239         int status = 0;
1240
1241         if (!drv_data)
1242                 return 0;
1243
1244         /* Remove the queue */
1245         status = destroy_queue(drv_data);
1246         if (status != 0)
1247                 return status;
1248
1249         /* Disable the SSP at the peripheral and SOC level */
1250         bfin_spi_disable(drv_data);
1251
1252         /* Release DMA */
1253         if (drv_data->master_info->enable_dma) {
1254                 if (dma_channel_active(CH_SPI))
1255                         free_dma(CH_SPI);
1256         }
1257
1258         /* Disconnect from the SPI framework */
1259         spi_unregister_master(drv_data->master);
1260
1261         /* Prevent double remove */
1262         platform_set_drvdata(pdev, NULL);
1263
1264         return 0;
1265 }
1266
1267 #ifdef CONFIG_PM
1268 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1269 {
1270         struct driver_data *drv_data = platform_get_drvdata(pdev);
1271         int status = 0;
1272
1273         status = stop_queue(drv_data);
1274         if (status != 0)
1275                 return status;
1276
1277         /* stop hardware */
1278         bfin_spi_disable(drv_data);
1279
1280         return 0;
1281 }
1282
1283 static int bfin5xx_spi_resume(struct platform_device *pdev)
1284 {
1285         struct driver_data *drv_data = platform_get_drvdata(pdev);
1286         int status = 0;
1287
1288         /* Enable the SPI interface */
1289         bfin_spi_enable(drv_data);
1290
1291         /* Start the queue running */
1292         status = start_queue(drv_data);
1293         if (status != 0) {
1294                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1295                 return status;
1296         }
1297
1298         return 0;
1299 }
1300 #else
1301 #define bfin5xx_spi_suspend NULL
1302 #define bfin5xx_spi_resume NULL
1303 #endif                          /* CONFIG_PM */
1304
1305 MODULE_ALIAS("bfin-spi-master");        /* for platform bus hotplug */
1306 static struct platform_driver bfin5xx_spi_driver = {
1307         .driver = {
1308                 .name   = "bfin-spi-master",
1309                 .owner  = THIS_MODULE,
1310         },
1311         .suspend        = bfin5xx_spi_suspend,
1312         .resume         = bfin5xx_spi_resume,
1313         .remove         = __devexit_p(bfin5xx_spi_remove),
1314 };
1315
1316 static int __init bfin5xx_spi_init(void)
1317 {
1318         return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1319 }
1320 module_init(bfin5xx_spi_init);
1321
1322 static void __exit bfin5xx_spi_exit(void)
1323 {
1324         platform_driver_unregister(&bfin5xx_spi_driver);
1325 }
1326 module_exit(bfin5xx_spi_exit);