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   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40
  41 #define RADEON_FIFO_DEBUG       0
  42
  43 static int radeon_do_cleanup_cp(struct drm_device * dev);
  44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  45
  46 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  47 {
  48         u32 ret;
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  50         ret = RADEON_READ(R520_MC_IND_DATA);
  51         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  52         return ret;
  53 }
  54
  55 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  56 {
  57         u32 ret;
  58         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  59         ret = RADEON_READ(RS480_NB_MC_DATA);
  60         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  61         return ret;
  62 }
  63
  64 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  65 {
  66         u32 ret;
  67         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  68         ret = RADEON_READ(RS690_MC_DATA);
  69         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  70         return ret;
  71 }
  72
  73 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  74 {
  75         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  76             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  77                 return RS690_READ_MCIND(dev_priv, addr);
  78         else
  79                 return RS480_READ_MCIND(dev_priv, addr);
  80 }
  81
  82 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  83 {
  84
  85         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  86                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  87         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  88                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  89                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  90         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  91                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  92         else
  93                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  94 }
  95
  96 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  97 {
  98         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  99                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 100         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 101                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 102                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 103         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 104                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 105         else
 106                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 107 }
 108
 109 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 110 {
 111         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 112                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 113         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 114                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 115                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 116         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 117                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 118         else
 119                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 120 }
 121
 122 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 123 {
 124         u32 agp_base_hi = upper_32_bits(agp_base);
 125         u32 agp_base_lo = agp_base & 0xffffffff;
 126
 127         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 128                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 129                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 130         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 131                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 132                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 133                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 134         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 135                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 136                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 137         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 138                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 139                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 140                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 141         } else {
 142                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 143                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 144                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 145         }
 146 }
 147
 148 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 149 {
 150         drm_radeon_private_t *dev_priv = dev->dev_private;
 151
 152         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 153         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 154 }
 155
 156 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 157 {
 158         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 159         return RADEON_READ(RADEON_PCIE_DATA);
 160 }
 161
 162 #if RADEON_FIFO_DEBUG
 163 static void radeon_status(drm_radeon_private_t * dev_priv)
 164 {
 165         printk("%s:\n", __func__);
 166         printk("RBBM_STATUS = 0x%08x\n",
 167                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 168         printk("CP_RB_RTPR = 0x%08x\n",
 169                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 170         printk("CP_RB_WTPR = 0x%08x\n",
 171                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 172         printk("AIC_CNTL = 0x%08x\n",
 173                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 174         printk("AIC_STAT = 0x%08x\n",
 175                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 176         printk("AIC_PT_BASE = 0x%08x\n",
 177                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 178         printk("TLB_ADDR = 0x%08x\n",
 179                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 180         printk("TLB_DATA = 0x%08x\n",
 181                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 182 }
 183 #endif
 184
 185 /* ================================================================
 186  * Engine, FIFO control
 187  */
 188
 189 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 190 {
 191         u32 tmp;
 192         int i;
 193
 194         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 195
 196         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 197                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 198                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 199                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 200
 201                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 202                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 203                               & RADEON_RB3D_DC_BUSY)) {
 204                                 return 0;
 205                         }
 206                         DRM_UDELAY(1);
 207                 }
 208         } else {
 209                 /* don't flush or purge cache here or lockup */
 210                 return 0;
 211         }
 212
 213 #if RADEON_FIFO_DEBUG
 214         DRM_ERROR("failed!\n");
 215         radeon_status(dev_priv);
 216 #endif
 217         return -EBUSY;
 218 }
 219
 220 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 221 {
 222         int i;
 223
 224         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 225
 226         for (i = 0; i < dev_priv->usec_timeout; i++) {
 227                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 228                              & RADEON_RBBM_FIFOCNT_MASK);
 229                 if (slots >= entries)
 230                         return 0;
 231                 DRM_UDELAY(1);
 232         }
 233         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 234                  RADEON_READ(RADEON_RBBM_STATUS),
 235                  RADEON_READ(R300_VAP_CNTL_STATUS));
 236
 237 #if RADEON_FIFO_DEBUG
 238         DRM_ERROR("failed!\n");
 239         radeon_status(dev_priv);
 240 #endif
 241         return -EBUSY;
 242 }
 243
 244 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 245 {
 246         int i, ret;
 247
 248         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 249
 250         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 251         if (ret)
 252                 return ret;
 253
 254         for (i = 0; i < dev_priv->usec_timeout; i++) {
 255                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 256                       & RADEON_RBBM_ACTIVE)) {
 257                         radeon_do_pixcache_flush(dev_priv);
 258                         return 0;
 259                 }
 260                 DRM_UDELAY(1);
 261         }
 262         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 263                  RADEON_READ(RADEON_RBBM_STATUS),
 264                  RADEON_READ(R300_VAP_CNTL_STATUS));
 265
 266 #if RADEON_FIFO_DEBUG
 267         DRM_ERROR("failed!\n");
 268         radeon_status(dev_priv);
 269 #endif
 270         return -EBUSY;
 271 }
 272
 273 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 274 {
 275         uint32_t gb_tile_config, gb_pipe_sel = 0;
 276
 277         /* RS4xx/RS6xx/R4xx/R5xx */
 278         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 279                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 280                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 281         } else {
 282                 /* R3xx */
 283                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 284                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 285                         dev_priv->num_gb_pipes = 2;
 286                 } else {
 287                         /* R3Vxx */
 288                         dev_priv->num_gb_pipes = 1;
 289                 }
 290         }
 291         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 292
 293         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 294
 295         switch (dev_priv->num_gb_pipes) {
 296         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 297         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 298         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 299         default:
 300         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 301         }
 302
 303         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 304                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 305                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 306         }
 307         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 308         radeon_do_wait_for_idle(dev_priv);
 309         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 310         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 311                                                R300_DC_AUTOFLUSH_ENABLE |
 312                                                R300_DC_DC_DISABLE_IGNORE_PE));
 313
 314
 315 }
 316
 317 /* ================================================================
 318  * CP control, initialization
 319  */
 320
 321 /* Load the microcode for the CP */
 322 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 323 {
 324         int i;
 325         DRM_DEBUG("\n");
 326
 327         radeon_do_wait_for_idle(dev_priv);
 328
 329         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 330         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 331             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 332             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 333             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 334             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 335                 DRM_INFO("Loading R100 Microcode\n");
 336                 for (i = 0; i < 256; i++) {
 337                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 338                                      R100_cp_microcode[i][1]);
 339                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 340                                      R100_cp_microcode[i][0]);
 341                 }
 342         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 343                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 344                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 345                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 346                 DRM_INFO("Loading R200 Microcode\n");
 347                 for (i = 0; i < 256; i++) {
 348                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 349                                      R200_cp_microcode[i][1]);
 350                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 351                                      R200_cp_microcode[i][0]);
 352                 }
 353         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 354                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 355                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 356                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 357                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 358                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 359                 DRM_INFO("Loading R300 Microcode\n");
 360                 for (i = 0; i < 256; i++) {
 361                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 362                                      R300_cp_microcode[i][1]);
 363                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 364                                      R300_cp_microcode[i][0]);
 365                 }
 366         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 367                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 368                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 369                 DRM_INFO("Loading R400 Microcode\n");
 370                 for (i = 0; i < 256; i++) {
 371                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 372                                      R420_cp_microcode[i][1]);
 373                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 374                                      R420_cp_microcode[i][0]);
 375                 }
 376         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 377                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 378                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 379                 for (i = 0; i < 256; i++) {
 380                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 381                                      RS690_cp_microcode[i][1]);
 382                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 383                                      RS690_cp_microcode[i][0]);
 384                 }
 385         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 386                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 387                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 388                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 389                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 390                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 391                 DRM_INFO("Loading R500 Microcode\n");
 392                 for (i = 0; i < 256; i++) {
 393                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 394                                      R520_cp_microcode[i][1]);
 395                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 396                                      R520_cp_microcode[i][0]);
 397                 }
 398         }
 399 }
 400
 401 /* Flush any pending commands to the CP.  This should only be used just
 402  * prior to a wait for idle, as it informs the engine that the command
 403  * stream is ending.
 404  */
 405 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 406 {
 407         DRM_DEBUG("\n");
 408 #if 0
 409         u32 tmp;
 410
 411         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 412         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 413 #endif
 414 }
 415
 416 /* Wait for the CP to go idle.
 417  */
 418 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 419 {
 420         RING_LOCALS;
 421         DRM_DEBUG("\n");
 422
 423         BEGIN_RING(6);
 424
 425         RADEON_PURGE_CACHE();
 426         RADEON_PURGE_ZCACHE();
 427         RADEON_WAIT_UNTIL_IDLE();
 428
 429         ADVANCE_RING();
 430         COMMIT_RING();
 431
 432         return radeon_do_wait_for_idle(dev_priv);
 433 }
 434
 435 /* Start the Command Processor.
 436  */
 437 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 438 {
 439         RING_LOCALS;
 440         DRM_DEBUG("\n");
 441
 442         radeon_do_wait_for_idle(dev_priv);
 443
 444         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 445
 446         dev_priv->cp_running = 1;
 447
 448         BEGIN_RING(8);
 449         /* isync can only be written through cp on r5xx write it here */
 450         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 451         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 452                  RADEON_ISYNC_ANY3D_IDLE2D |
 453                  RADEON_ISYNC_WAIT_IDLEGUI |
 454                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 455         RADEON_PURGE_CACHE();
 456         RADEON_PURGE_ZCACHE();
 457         RADEON_WAIT_UNTIL_IDLE();
 458         ADVANCE_RING();
 459         COMMIT_RING();
 460
 461         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 462 }
 463
 464 /* Reset the Command Processor.  This will not flush any pending
 465  * commands, so you must wait for the CP command stream to complete
 466  * before calling this routine.
 467  */
 468 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 469 {
 470         u32 cur_read_ptr;
 471         DRM_DEBUG("\n");
 472
 473         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 474         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 475         SET_RING_HEAD(dev_priv, cur_read_ptr);
 476         dev_priv->ring.tail = cur_read_ptr;
 477 }
 478
 479 /* Stop the Command Processor.  This will not flush any pending
 480  * commands, so you must flush the command stream and wait for the CP
 481  * to go idle before calling this routine.
 482  */
 483 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 484 {
 485         DRM_DEBUG("\n");
 486
 487         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 488
 489         dev_priv->cp_running = 0;
 490 }
 491
 492 /* Reset the engine.  This will stop the CP if it is running.
 493  */
 494 static int radeon_do_engine_reset(struct drm_device * dev)
 495 {
 496         drm_radeon_private_t *dev_priv = dev->dev_private;
 497         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 498         DRM_DEBUG("\n");
 499
 500         radeon_do_pixcache_flush(dev_priv);
 501
 502         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 503                 /* may need something similar for newer chips */
 504                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 505                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 506
 507                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 508                                                     RADEON_FORCEON_MCLKA |
 509                                                     RADEON_FORCEON_MCLKB |
 510                                                     RADEON_FORCEON_YCLKA |
 511                                                     RADEON_FORCEON_YCLKB |
 512                                                     RADEON_FORCEON_MC |
 513                                                     RADEON_FORCEON_AIC));
 514         }
 515
 516         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 517
 518         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 519                                               RADEON_SOFT_RESET_CP |
 520                                               RADEON_SOFT_RESET_HI |
 521                                               RADEON_SOFT_RESET_SE |
 522                                               RADEON_SOFT_RESET_RE |
 523                                               RADEON_SOFT_RESET_PP |
 524                                               RADEON_SOFT_RESET_E2 |
 525                                               RADEON_SOFT_RESET_RB));
 526         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 527         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 528                                               ~(RADEON_SOFT_RESET_CP |
 529                                                 RADEON_SOFT_RESET_HI |
 530                                                 RADEON_SOFT_RESET_SE |
 531                                                 RADEON_SOFT_RESET_RE |
 532                                                 RADEON_SOFT_RESET_PP |
 533                                                 RADEON_SOFT_RESET_E2 |
 534                                                 RADEON_SOFT_RESET_RB)));
 535         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 536
 537         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 538                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 539                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 540                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 541         }
 542
 543         /* setup the raster pipes */
 544         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 545             radeon_init_pipes(dev_priv);
 546
 547         /* Reset the CP ring */
 548         radeon_do_cp_reset(dev_priv);
 549
 550         /* The CP is no longer running after an engine reset */
 551         dev_priv->cp_running = 0;
 552
 553         /* Reset any pending vertex, indirect buffers */
 554         radeon_freelist_reset(dev);
 555
 556         return 0;
 557 }
 558
 559 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 560                                        drm_radeon_private_t *dev_priv,
 561                                        struct drm_file *file_priv)
 562 {
 563         struct drm_radeon_master_private *master_priv;
 564         u32 ring_start, cur_read_ptr;
 565         u32 tmp;
 566
 567         /* Initialize the memory controller. With new memory map, the fb location
 568          * is not changed, it should have been properly initialized already. Part
 569          * of the problem is that the code below is bogus, assuming the GART is
 570          * always appended to the fb which is not necessarily the case
 571          */
 572         if (!dev_priv->new_memmap)
 573                 radeon_write_fb_location(dev_priv,
 574                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 575                              | (dev_priv->fb_location >> 16));
 576
 577 #if __OS_HAS_AGP
 578         if (dev_priv->flags & RADEON_IS_AGP) {
 579                 radeon_write_agp_base(dev_priv, dev->agp->base);
 580
 581                 radeon_write_agp_location(dev_priv,
 582                              (((dev_priv->gart_vm_start - 1 +
 583                                 dev_priv->gart_size) & 0xffff0000) |
 584                               (dev_priv->gart_vm_start >> 16)));
 585
 586                 ring_start = (dev_priv->cp_ring->offset
 587                               - dev->agp->base
 588                               + dev_priv->gart_vm_start);
 589         } else
 590 #endif
 591                 ring_start = (dev_priv->cp_ring->offset
 592                               - (unsigned long)dev->sg->virtual
 593                               + dev_priv->gart_vm_start);
 594
 595         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 596
 597         /* Set the write pointer delay */
 598         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 599
 600         /* Initialize the ring buffer's read and write pointers */
 601         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 602         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 603         SET_RING_HEAD(dev_priv, cur_read_ptr);
 604         dev_priv->ring.tail = cur_read_ptr;
 605
 606 #if __OS_HAS_AGP
 607         if (dev_priv->flags & RADEON_IS_AGP) {
 608                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 609                              dev_priv->ring_rptr->offset
 610                              - dev->agp->base + dev_priv->gart_vm_start);
 611         } else
 612 #endif
 613         {
 614                 struct drm_sg_mem *entry = dev->sg;
 615                 unsigned long tmp_ofs, page_ofs;
 616
 617                 tmp_ofs = dev_priv->ring_rptr->offset -
 618                                 (unsigned long)dev->sg->virtual;
 619                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 620
 621                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 622                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 623                           (unsigned long)entry->busaddr[page_ofs],
 624                           entry->handle + tmp_ofs);
 625         }
 626
 627         /* Set ring buffer size */
 628 #ifdef __BIG_ENDIAN
 629         RADEON_WRITE(RADEON_CP_RB_CNTL,
 630                      RADEON_BUF_SWAP_32BIT |
 631                      (dev_priv->ring.fetch_size_l2ow << 18) |
 632                      (dev_priv->ring.rptr_update_l2qw << 8) |
 633                      dev_priv->ring.size_l2qw);
 634 #else
 635         RADEON_WRITE(RADEON_CP_RB_CNTL,
 636                      (dev_priv->ring.fetch_size_l2ow << 18) |
 637                      (dev_priv->ring.rptr_update_l2qw << 8) |
 638                      dev_priv->ring.size_l2qw);
 639 #endif
 640
 641
 642         /* Initialize the scratch register pointer.  This will cause
 643          * the scratch register values to be written out to memory
 644          * whenever they are updated.
 645          *
 646          * We simply put this behind the ring read pointer, this works
 647          * with PCI GART as well as (whatever kind of) AGP GART
 648          */
 649         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 650                      + RADEON_SCRATCH_REG_OFFSET);
 651
 652         dev_priv->scratch = ((__volatile__ u32 *)
 653                              dev_priv->ring_rptr->handle +
 654                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 655
 656         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 657
 658         /* Turn on bus mastering */
 659         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 660             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 661                 /* rs600/rs690/rs740 */
 662                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 663                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 664         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 665                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 666                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 667                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 668                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 669                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 670                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 671         } /* PCIE cards appears to not need this */
 672
 673         dev_priv->scratch[0] = 0;
 674         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 675
 676         dev_priv->scratch[1] = 0;
 677         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 678
 679         dev_priv->scratch[2] = 0;
 680         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 681
 682         /* reset sarea copies of these */
 683         master_priv = file_priv->master->driver_priv;
 684         if (master_priv->sarea_priv) {
 685                 master_priv->sarea_priv->last_frame = 0;
 686                 master_priv->sarea_priv->last_dispatch = 0;
 687                 master_priv->sarea_priv->last_clear = 0;
 688         }
 689
 690         radeon_do_wait_for_idle(dev_priv);
 691
 692         /* Sync everything up */
 693         RADEON_WRITE(RADEON_ISYNC_CNTL,
 694                      (RADEON_ISYNC_ANY2D_IDLE3D |
 695                       RADEON_ISYNC_ANY3D_IDLE2D |
 696                       RADEON_ISYNC_WAIT_IDLEGUI |
 697                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 698
 699 }
 700
 701 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 702 {
 703         u32 tmp;
 704
 705         /* Start with assuming that writeback doesn't work */
 706         dev_priv->writeback_works = 0;
 707
 708         /* Writeback doesn't seem to work everywhere, test it here and possibly
 709          * enable it if it appears to work
 710          */
 711         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 712         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 713
 714         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 715                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 716                     0xdeadbeef)
 717                         break;
 718                 DRM_UDELAY(1);
 719         }
 720
 721         if (tmp < dev_priv->usec_timeout) {
 722                 dev_priv->writeback_works = 1;
 723                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 724         } else {
 725                 dev_priv->writeback_works = 0;
 726                 DRM_INFO("writeback test failed\n");
 727         }
 728         if (radeon_no_wb == 1) {
 729                 dev_priv->writeback_works = 0;
 730                 DRM_INFO("writeback forced off\n");
 731         }
 732
 733         if (!dev_priv->writeback_works) {
 734                 /* Disable writeback to avoid unnecessary bus master transfer */
 735                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 736                              RADEON_RB_NO_UPDATE);
 737                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 738         }
 739 }
 740
 741 /* Enable or disable IGP GART on the chip */
 742 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 743 {
 744         u32 temp;
 745
 746         if (on) {
 747                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 748                           dev_priv->gart_vm_start,
 749                           (long)dev_priv->gart_info.bus_addr,
 750                           dev_priv->gart_size);
 751
 752                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 753                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 754                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 755                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 756                                                              RS690_BLOCK_GFX_D3_EN));
 757                 else
 758                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 759
 760                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 761                                                                RS480_VA_SIZE_32MB));
 762
 763                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 764                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 765                                                         RS480_TLB_ENABLE |
 766                                                         RS480_GTW_LAC_EN |
 767                                                         RS480_1LEVEL_GART));
 768
 769                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 770                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 771                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 772
 773                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 774                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 775                                                       RS480_REQ_TYPE_SNOOP_DIS));
 776
 777                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 778
 779                 dev_priv->gart_size = 32*1024*1024;
 780                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 781                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 782
 783                 radeon_write_agp_location(dev_priv, temp);
 784
 785                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 786                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 787                                                                RS480_VA_SIZE_32MB));
 788
 789                 do {
 790                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 791                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 792                                 break;
 793                         DRM_UDELAY(1);
 794                 } while (1);
 795
 796                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 797                                 RS480_GART_CACHE_INVALIDATE);
 798
 799                 do {
 800                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 801                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 802                                 break;
 803                         DRM_UDELAY(1);
 804                 } while (1);
 805
 806                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 807         } else {
 808                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 809         }
 810 }
 811
 812 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 813 {
 814         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 815         if (on) {
 816
 817                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 818                           dev_priv->gart_vm_start,
 819                           (long)dev_priv->gart_info.bus_addr,
 820                           dev_priv->gart_size);
 821                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 822                                   dev_priv->gart_vm_start);
 823                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 824                                   dev_priv->gart_info.bus_addr);
 825                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 826                                   dev_priv->gart_vm_start);
 827                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 828                                   dev_priv->gart_vm_start +
 829                                   dev_priv->gart_size - 1);
 830
 831                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 832
 833                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 834                                   RADEON_PCIE_TX_GART_EN);
 835         } else {
 836                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 837                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 838         }
 839 }
 840
 841 /* Enable or disable PCI GART on the chip */
 842 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 843 {
 844         u32 tmp;
 845
 846         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 847             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 848             (dev_priv->flags & RADEON_IS_IGPGART)) {
 849                 radeon_set_igpgart(dev_priv, on);
 850                 return;
 851         }
 852
 853         if (dev_priv->flags & RADEON_IS_PCIE) {
 854                 radeon_set_pciegart(dev_priv, on);
 855                 return;
 856         }
 857
 858         tmp = RADEON_READ(RADEON_AIC_CNTL);
 859
 860         if (on) {
 861                 RADEON_WRITE(RADEON_AIC_CNTL,
 862                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 863
 864                 /* set PCI GART page-table base address
 865                  */
 866                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 867
 868                 /* set address range for PCI address translate
 869                  */
 870                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 871                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 872                              + dev_priv->gart_size - 1);
 873
 874                 /* Turn off AGP aperture -- is this required for PCI GART?
 875                  */
 876                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 877                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 878         } else {
 879                 RADEON_WRITE(RADEON_AIC_CNTL,
 880                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 881         }
 882 }
 883
 884 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 885                              struct drm_file *file_priv)
 886 {
 887         drm_radeon_private_t *dev_priv = dev->dev_private;
 888         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 889
 890         DRM_DEBUG("\n");
 891
 892         /* if we require new memory map but we don't have it fail */
 893         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 894                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 895                 radeon_do_cleanup_cp(dev);
 896                 return -EINVAL;
 897         }
 898
 899         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
 900                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 901                 dev_priv->flags &= ~RADEON_IS_AGP;
 902         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 903                    && !init->is_pci) {
 904                 DRM_DEBUG("Restoring AGP flag\n");
 905                 dev_priv->flags |= RADEON_IS_AGP;
 906         }
 907
 908         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 909                 DRM_ERROR("PCI GART memory not allocated!\n");
 910                 radeon_do_cleanup_cp(dev);
 911                 return -EINVAL;
 912         }
 913
 914         dev_priv->usec_timeout = init->usec_timeout;
 915         if (dev_priv->usec_timeout < 1 ||
 916             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 917                 DRM_DEBUG("TIMEOUT problem!\n");
 918                 radeon_do_cleanup_cp(dev);
 919                 return -EINVAL;
 920         }
 921
 922         /* Enable vblank on CRTC1 for older X servers
 923          */
 924         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 925
 926         switch(init->func) {
 927         case RADEON_INIT_R200_CP:
 928                 dev_priv->microcode_version = UCODE_R200;
 929                 break;
 930         case RADEON_INIT_R300_CP:
 931                 dev_priv->microcode_version = UCODE_R300;
 932                 break;
 933         default:
 934                 dev_priv->microcode_version = UCODE_R100;
 935         }
 936
 937         dev_priv->do_boxes = 0;
 938         dev_priv->cp_mode = init->cp_mode;
 939
 940         /* We don't support anything other than bus-mastering ring mode,
 941          * but the ring can be in either AGP or PCI space for the ring
 942          * read pointer.
 943          */
 944         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 945             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 946                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 947                 radeon_do_cleanup_cp(dev);
 948                 return -EINVAL;
 949         }
 950
 951         switch (init->fb_bpp) {
 952         case 16:
 953                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 954                 break;
 955         case 32:
 956         default:
 957                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 958                 break;
 959         }
 960         dev_priv->front_offset = init->front_offset;
 961         dev_priv->front_pitch = init->front_pitch;
 962         dev_priv->back_offset = init->back_offset;
 963         dev_priv->back_pitch = init->back_pitch;
 964
 965         switch (init->depth_bpp) {
 966         case 16:
 967                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 968                 break;
 969         case 32:
 970         default:
 971                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 972                 break;
 973         }
 974         dev_priv->depth_offset = init->depth_offset;
 975         dev_priv->depth_pitch = init->depth_pitch;
 976
 977         /* Hardware state for depth clears.  Remove this if/when we no
 978          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 979          * all values to prevent unwanted 3D state from slipping through
 980          * and screwing with the clear operation.
 981          */
 982         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 983                                            (dev_priv->color_fmt << 10) |
 984                                            (dev_priv->microcode_version ==
 985                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
 986
 987         dev_priv->depth_clear.rb3d_zstencilcntl =
 988             (dev_priv->depth_fmt |
 989              RADEON_Z_TEST_ALWAYS |
 990              RADEON_STENCIL_TEST_ALWAYS |
 991              RADEON_STENCIL_S_FAIL_REPLACE |
 992              RADEON_STENCIL_ZPASS_REPLACE |
 993              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 994
 995         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 996                                          RADEON_BFACE_SOLID |
 997                                          RADEON_FFACE_SOLID |
 998                                          RADEON_FLAT_SHADE_VTX_LAST |
 999                                          RADEON_DIFFUSE_SHADE_FLAT |
1000                                          RADEON_ALPHA_SHADE_FLAT |
1001                                          RADEON_SPECULAR_SHADE_FLAT |
1002                                          RADEON_FOG_SHADE_FLAT |
1003                                          RADEON_VTX_PIX_CENTER_OGL |
1004                                          RADEON_ROUND_MODE_TRUNC |
1005                                          RADEON_ROUND_PREC_8TH_PIX);
1006
1007
1008         dev_priv->ring_offset = init->ring_offset;
1009         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1010         dev_priv->buffers_offset = init->buffers_offset;
1011         dev_priv->gart_textures_offset = init->gart_textures_offset;
1012
1013         master_priv->sarea = drm_getsarea(dev);
1014         if (!master_priv->sarea) {
1015                 DRM_ERROR("could not find sarea!\n");
1016                 radeon_do_cleanup_cp(dev);
1017                 return -EINVAL;
1018         }
1019
1020         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1021         if (!dev_priv->cp_ring) {
1022                 DRM_ERROR("could not find cp ring region!\n");
1023                 radeon_do_cleanup_cp(dev);
1024                 return -EINVAL;
1025         }
1026         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1027         if (!dev_priv->ring_rptr) {
1028                 DRM_ERROR("could not find ring read pointer!\n");
1029                 radeon_do_cleanup_cp(dev);
1030                 return -EINVAL;
1031         }
1032         dev->agp_buffer_token = init->buffers_offset;
1033         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1034         if (!dev->agp_buffer_map) {
1035                 DRM_ERROR("could not find dma buffer region!\n");
1036                 radeon_do_cleanup_cp(dev);
1037                 return -EINVAL;
1038         }
1039
1040         if (init->gart_textures_offset) {
1041                 dev_priv->gart_textures =
1042                     drm_core_findmap(dev, init->gart_textures_offset);
1043                 if (!dev_priv->gart_textures) {
1044                         DRM_ERROR("could not find GART texture region!\n");
1045                         radeon_do_cleanup_cp(dev);
1046                         return -EINVAL;
1047                 }
1048         }
1049
1050 #if __OS_HAS_AGP
1051         if (dev_priv->flags & RADEON_IS_AGP) {
1052                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1053                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1054                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1055                 if (!dev_priv->cp_ring->handle ||
1056                     !dev_priv->ring_rptr->handle ||
1057                     !dev->agp_buffer_map->handle) {
1058                         DRM_ERROR("could not find ioremap agp regions!\n");
1059                         radeon_do_cleanup_cp(dev);
1060                         return -EINVAL;
1061                 }
1062         } else
1063 #endif
1064         {
1065                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1066                 dev_priv->ring_rptr->handle =
1067                     (void *)dev_priv->ring_rptr->offset;
1068                 dev->agp_buffer_map->handle =
1069                     (void *)dev->agp_buffer_map->offset;
1070
1071                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1072                           dev_priv->cp_ring->handle);
1073                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1074                           dev_priv->ring_rptr->handle);
1075                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1076                           dev->agp_buffer_map->handle);
1077         }
1078
1079         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1080         dev_priv->fb_size =
1081                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1082                 - dev_priv->fb_location;
1083
1084         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1085                                         ((dev_priv->front_offset
1086                                           + dev_priv->fb_location) >> 10));
1087
1088         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1089                                        ((dev_priv->back_offset
1090                                          + dev_priv->fb_location) >> 10));
1091
1092         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1093                                         ((dev_priv->depth_offset
1094                                           + dev_priv->fb_location) >> 10));
1095
1096         dev_priv->gart_size = init->gart_size;
1097
1098         /* New let's set the memory map ... */
1099         if (dev_priv->new_memmap) {
1100                 u32 base = 0;
1101
1102                 DRM_INFO("Setting GART location based on new memory map\n");
1103
1104                 /* If using AGP, try to locate the AGP aperture at the same
1105                  * location in the card and on the bus, though we have to
1106                  * align it down.
1107                  */
1108 #if __OS_HAS_AGP
1109                 if (dev_priv->flags & RADEON_IS_AGP) {
1110                         base = dev->agp->base;
1111                         /* Check if valid */
1112                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1113                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1114                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1115                                          dev->agp->base);
1116                                 base = 0;
1117                         }
1118                 }
1119 #endif
1120                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1121                 if (base == 0) {
1122                         base = dev_priv->fb_location + dev_priv->fb_size;
1123                         if (base < dev_priv->fb_location ||
1124                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1125                                 base = dev_priv->fb_location
1126                                         - dev_priv->gart_size;
1127                 }
1128                 dev_priv->gart_vm_start = base & 0xffc00000u;
1129                 if (dev_priv->gart_vm_start != base)
1130                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1131                                  base, dev_priv->gart_vm_start);
1132         } else {
1133                 DRM_INFO("Setting GART location based on old memory map\n");
1134                 dev_priv->gart_vm_start = dev_priv->fb_location +
1135                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1136         }
1137
1138 #if __OS_HAS_AGP
1139         if (dev_priv->flags & RADEON_IS_AGP)
1140                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1141                                                  - dev->agp->base
1142                                                  + dev_priv->gart_vm_start);
1143         else
1144 #endif
1145                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1146                                         - (unsigned long)dev->sg->virtual
1147                                         + dev_priv->gart_vm_start);
1148
1149         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1150         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1151         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1152                   dev_priv->gart_buffers_offset);
1153
1154         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1155         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1156                               + init->ring_size / sizeof(u32));
1157         dev_priv->ring.size = init->ring_size;
1158         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1159
1160         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1161         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1162
1163         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1164         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1165         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1166
1167         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1168
1169 #if __OS_HAS_AGP
1170         if (dev_priv->flags & RADEON_IS_AGP) {
1171                 /* Turn off PCI GART */
1172                 radeon_set_pcigart(dev_priv, 0);
1173         } else
1174 #endif
1175         {
1176                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1177                 /* if we have an offset set from userspace */
1178                 if (dev_priv->pcigart_offset_set) {
1179                         dev_priv->gart_info.bus_addr =
1180                             dev_priv->pcigart_offset + dev_priv->fb_location;
1181                         dev_priv->gart_info.mapping.offset =
1182                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1183                         dev_priv->gart_info.mapping.size =
1184                             dev_priv->gart_info.table_size;
1185
1186                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1187                         dev_priv->gart_info.addr =
1188                             dev_priv->gart_info.mapping.handle;
1189
1190                         if (dev_priv->flags & RADEON_IS_PCIE)
1191                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1192                         else
1193                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1194                         dev_priv->gart_info.gart_table_location =
1195                             DRM_ATI_GART_FB;
1196
1197                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1198                                   dev_priv->gart_info.addr,
1199                                   dev_priv->pcigart_offset);
1200                 } else {
1201                         if (dev_priv->flags & RADEON_IS_IGPGART)
1202                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1203                         else
1204                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1205                         dev_priv->gart_info.gart_table_location =
1206                             DRM_ATI_GART_MAIN;
1207                         dev_priv->gart_info.addr = NULL;
1208                         dev_priv->gart_info.bus_addr = 0;
1209                         if (dev_priv->flags & RADEON_IS_PCIE) {
1210                                 DRM_ERROR
1211                                     ("Cannot use PCI Express without GART in FB memory\n");
1212                                 radeon_do_cleanup_cp(dev);
1213                                 return -EINVAL;
1214                         }
1215                 }
1216
1217                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1218                         DRM_ERROR("failed to init PCI GART!\n");
1219                         radeon_do_cleanup_cp(dev);
1220                         return -ENOMEM;
1221                 }
1222
1223                 /* Turn on PCI GART */
1224                 radeon_set_pcigart(dev_priv, 1);
1225         }
1226
1227         radeon_cp_load_microcode(dev_priv);
1228         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1229
1230         dev_priv->last_buf = 0;
1231
1232         radeon_do_engine_reset(dev);
1233         radeon_test_writeback(dev_priv);
1234
1235         return 0;
1236 }
1237
1238 static int radeon_do_cleanup_cp(struct drm_device * dev)
1239 {
1240         drm_radeon_private_t *dev_priv = dev->dev_private;
1241         DRM_DEBUG("\n");
1242
1243         /* Make sure interrupts are disabled here because the uninstall ioctl
1244          * may not have been called from userspace and after dev_private
1245          * is freed, it's too late.
1246          */
1247         if (dev->irq_enabled)
1248                 drm_irq_uninstall(dev);
1249
1250 #if __OS_HAS_AGP
1251         if (dev_priv->flags & RADEON_IS_AGP) {
1252                 if (dev_priv->cp_ring != NULL) {
1253                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1254                         dev_priv->cp_ring = NULL;
1255                 }
1256                 if (dev_priv->ring_rptr != NULL) {
1257                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1258                         dev_priv->ring_rptr = NULL;
1259                 }
1260                 if (dev->agp_buffer_map != NULL) {
1261                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1262                         dev->agp_buffer_map = NULL;
1263                 }
1264         } else
1265 #endif
1266         {
1267
1268                 if (dev_priv->gart_info.bus_addr) {
1269                         /* Turn off PCI GART */
1270                         radeon_set_pcigart(dev_priv, 0);
1271                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1272                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1273                 }
1274
1275                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1276                 {
1277                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1278                         dev_priv->gart_info.addr = 0;
1279                 }
1280         }
1281         /* only clear to the start of flags */
1282         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1283
1284         return 0;
1285 }
1286
1287 /* This code will reinit the Radeon CP hardware after a resume from disc.
1288  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1289  * here we make sure that all Radeon hardware initialisation is re-done without
1290  * affecting running applications.
1291  *
1292  * Charl P. Botha <http://cpbotha.net>
1293  */
1294 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1295 {
1296         drm_radeon_private_t *dev_priv = dev->dev_private;
1297
1298         if (!dev_priv) {
1299                 DRM_ERROR("Called with no initialization\n");
1300                 return -EINVAL;
1301         }
1302
1303         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1304
1305 #if __OS_HAS_AGP
1306         if (dev_priv->flags & RADEON_IS_AGP) {
1307                 /* Turn off PCI GART */
1308                 radeon_set_pcigart(dev_priv, 0);
1309         } else
1310 #endif
1311         {
1312                 /* Turn on PCI GART */
1313                 radeon_set_pcigart(dev_priv, 1);
1314         }
1315
1316         radeon_cp_load_microcode(dev_priv);
1317         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1318
1319         radeon_do_engine_reset(dev);
1320         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1321
1322         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1323
1324         return 0;
1325 }
1326
1327 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1328 {
1329         drm_radeon_init_t *init = data;
1330
1331         LOCK_TEST_WITH_RETURN(dev, file_priv);
1332
1333         if (init->func == RADEON_INIT_R300_CP)
1334                 r300_init_reg_flags(dev);
1335
1336         switch (init->func) {
1337         case RADEON_INIT_CP:
1338         case RADEON_INIT_R200_CP:
1339         case RADEON_INIT_R300_CP:
1340                 return radeon_do_init_cp(dev, init, file_priv);
1341         case RADEON_CLEANUP_CP:
1342                 return radeon_do_cleanup_cp(dev);
1343         }
1344
1345         return -EINVAL;
1346 }
1347
1348 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1349 {
1350         drm_radeon_private_t *dev_priv = dev->dev_private;
1351         DRM_DEBUG("\n");
1352
1353         LOCK_TEST_WITH_RETURN(dev, file_priv);
1354
1355         if (dev_priv->cp_running) {
1356                 DRM_DEBUG("while CP running\n");
1357                 return 0;
1358         }
1359         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1360                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1361                           dev_priv->cp_mode);
1362                 return 0;
1363         }
1364
1365         radeon_do_cp_start(dev_priv);
1366
1367         return 0;
1368 }
1369
1370 /* Stop the CP.  The engine must have been idled before calling this
1371  * routine.
1372  */
1373 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1374 {
1375         drm_radeon_private_t *dev_priv = dev->dev_private;
1376         drm_radeon_cp_stop_t *stop = data;
1377         int ret;
1378         DRM_DEBUG("\n");
1379
1380         LOCK_TEST_WITH_RETURN(dev, file_priv);
1381
1382         if (!dev_priv->cp_running)
1383                 return 0;
1384
1385         /* Flush any pending CP commands.  This ensures any outstanding
1386          * commands are exectuted by the engine before we turn it off.
1387          */
1388         if (stop->flush) {
1389                 radeon_do_cp_flush(dev_priv);
1390         }
1391
1392         /* If we fail to make the engine go idle, we return an error
1393          * code so that the DRM ioctl wrapper can try again.
1394          */
1395         if (stop->idle) {
1396                 ret = radeon_do_cp_idle(dev_priv);
1397                 if (ret)
1398                         return ret;
1399         }
1400
1401         /* Finally, we can turn off the CP.  If the engine isn't idle,
1402          * we will get some dropped triangles as they won't be fully
1403          * rendered before the CP is shut down.
1404          */
1405         radeon_do_cp_stop(dev_priv);
1406
1407         /* Reset the engine */
1408         radeon_do_engine_reset(dev);
1409
1410         return 0;
1411 }
1412
1413 void radeon_do_release(struct drm_device * dev)
1414 {
1415         drm_radeon_private_t *dev_priv = dev->dev_private;
1416         int i, ret;
1417
1418         if (dev_priv) {
1419                 if (dev_priv->cp_running) {
1420                         /* Stop the cp */
1421                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1422                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1423 #ifdef __linux__
1424                                 schedule();
1425 #else
1426                                 tsleep(&ret, PZERO, "rdnrel", 1);
1427 #endif
1428                         }
1429                         radeon_do_cp_stop(dev_priv);
1430                         radeon_do_engine_reset(dev);
1431                 }
1432
1433                 /* Disable *all* interrupts */
1434                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1435                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1436
1437                 if (dev_priv->mmio) {   /* remove all surfaces */
1438                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1439                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1440                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1441                                              16 * i, 0);
1442                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1443                                              16 * i, 0);
1444                         }
1445                 }
1446
1447                 /* Free memory heap structures */
1448                 radeon_mem_takedown(&(dev_priv->gart_heap));
1449                 radeon_mem_takedown(&(dev_priv->fb_heap));
1450
1451                 /* deallocate kernel resources */
1452                 radeon_do_cleanup_cp(dev);
1453         }
1454 }
1455
1456 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1457  */
1458 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1459 {
1460         drm_radeon_private_t *dev_priv = dev->dev_private;
1461         DRM_DEBUG("\n");
1462
1463         LOCK_TEST_WITH_RETURN(dev, file_priv);
1464
1465         if (!dev_priv) {
1466                 DRM_DEBUG("called before init done\n");
1467                 return -EINVAL;
1468         }
1469
1470         radeon_do_cp_reset(dev_priv);
1471
1472         /* The CP is no longer running after an engine reset */
1473         dev_priv->cp_running = 0;
1474
1475         return 0;
1476 }
1477
1478 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1479 {
1480         drm_radeon_private_t *dev_priv = dev->dev_private;
1481         DRM_DEBUG("\n");
1482
1483         LOCK_TEST_WITH_RETURN(dev, file_priv);
1484
1485         return radeon_do_cp_idle(dev_priv);
1486 }
1487
1488 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1489  */
1490 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1491 {
1492         return radeon_do_resume_cp(dev, file_priv);
1493 }
1494
1495 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1496 {
1497         DRM_DEBUG("\n");
1498
1499         LOCK_TEST_WITH_RETURN(dev, file_priv);
1500
1501         return radeon_do_engine_reset(dev);
1502 }
1503
1504 /* ================================================================
1505  * Fullscreen mode
1506  */
1507
1508 /* KW: Deprecated to say the least:
1509  */
1510 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1511 {
1512         return 0;
1513 }
1514
1515 /* ================================================================
1516  * Freelist management
1517  */
1518
1519 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1520  *   bufs until freelist code is used.  Note this hides a problem with
1521  *   the scratch register * (used to keep track of last buffer
1522  *   completed) being written to before * the last buffer has actually
1523  *   completed rendering.
1524  *
1525  * KW:  It's also a good way to find free buffers quickly.
1526  *
1527  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1528  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1529  * we essentially have to do this, else old clients will break.
1530  *
1531  * However, it does leave open a potential deadlock where all the
1532  * buffers are held by other clients, which can't release them because
1533  * they can't get the lock.
1534  */
1535
1536 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1537 {
1538         struct drm_device_dma *dma = dev->dma;
1539         drm_radeon_private_t *dev_priv = dev->dev_private;
1540         drm_radeon_buf_priv_t *buf_priv;
1541         struct drm_buf *buf;
1542         int i, t;
1543         int start;
1544
1545         if (++dev_priv->last_buf >= dma->buf_count)
1546                 dev_priv->last_buf = 0;
1547
1548         start = dev_priv->last_buf;
1549
1550         for (t = 0; t < dev_priv->usec_timeout; t++) {
1551                 u32 done_age = GET_SCRATCH(1);
1552                 DRM_DEBUG("done_age = %d\n", done_age);
1553                 for (i = start; i < dma->buf_count; i++) {
1554                         buf = dma->buflist[i];
1555                         buf_priv = buf->dev_private;
1556                         if (buf->file_priv == NULL || (buf->pending &&
1557                                                        buf_priv->age <=
1558                                                        done_age)) {
1559                                 dev_priv->stats.requested_bufs++;
1560                                 buf->pending = 0;
1561                                 return buf;
1562                         }
1563                         start = 0;
1564                 }
1565
1566                 if (t) {
1567                         DRM_UDELAY(1);
1568                         dev_priv->stats.freelist_loops++;
1569                 }
1570         }
1571
1572         DRM_DEBUG("returning NULL!\n");
1573         return NULL;
1574 }
1575
1576 #if 0
1577 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1578 {
1579         struct drm_device_dma *dma = dev->dma;
1580         drm_radeon_private_t *dev_priv = dev->dev_private;
1581         drm_radeon_buf_priv_t *buf_priv;
1582         struct drm_buf *buf;
1583         int i, t;
1584         int start;
1585         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1586
1587         if (++dev_priv->last_buf >= dma->buf_count)
1588                 dev_priv->last_buf = 0;
1589
1590         start = dev_priv->last_buf;
1591         dev_priv->stats.freelist_loops++;
1592
1593         for (t = 0; t < 2; t++) {
1594                 for (i = start; i < dma->buf_count; i++) {
1595                         buf = dma->buflist[i];
1596                         buf_priv = buf->dev_private;
1597                         if (buf->file_priv == 0 || (buf->pending &&
1598                                                     buf_priv->age <=
1599                                                     done_age)) {
1600                                 dev_priv->stats.requested_bufs++;
1601                                 buf->pending = 0;
1602                                 return buf;
1603                         }
1604                 }
1605                 start = 0;
1606         }
1607
1608         return NULL;
1609 }
1610 #endif
1611
1612 void radeon_freelist_reset(struct drm_device * dev)
1613 {
1614         struct drm_device_dma *dma = dev->dma;
1615         drm_radeon_private_t *dev_priv = dev->dev_private;
1616         int i;
1617
1618         dev_priv->last_buf = 0;
1619         for (i = 0; i < dma->buf_count; i++) {
1620                 struct drm_buf *buf = dma->buflist[i];
1621                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1622                 buf_priv->age = 0;
1623         }
1624 }
1625
1626 /* ================================================================
1627  * CP command submission
1628  */
1629
1630 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1631 {
1632         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1633         int i;
1634         u32 last_head = GET_RING_HEAD(dev_priv);
1635
1636         for (i = 0; i < dev_priv->usec_timeout; i++) {
1637                 u32 head = GET_RING_HEAD(dev_priv);
1638
1639                 ring->space = (head - ring->tail) * sizeof(u32);
1640                 if (ring->space <= 0)
1641                         ring->space += ring->size;
1642                 if (ring->space > n)
1643                         return 0;
1644
1645                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1646
1647                 if (head != last_head)
1648                         i = 0;
1649                 last_head = head;
1650
1651                 DRM_UDELAY(1);
1652         }
1653
1654         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1655 #if RADEON_FIFO_DEBUG
1656         radeon_status(dev_priv);
1657         DRM_ERROR("failed!\n");
1658 #endif
1659         return -EBUSY;
1660 }
1661
1662 static int radeon_cp_get_buffers(struct drm_device *dev,
1663                                  struct drm_file *file_priv,
1664                                  struct drm_dma * d)
1665 {
1666         int i;
1667         struct drm_buf *buf;
1668
1669         for (i = d->granted_count; i < d->request_count; i++) {
1670                 buf = radeon_freelist_get(dev);
1671                 if (!buf)
1672                         return -EBUSY;  /* NOTE: broken client */
1673
1674                 buf->file_priv = file_priv;
1675
1676                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1677                                      sizeof(buf->idx)))
1678                         return -EFAULT;
1679                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1680                                      sizeof(buf->total)))
1681                         return -EFAULT;
1682
1683                 d->granted_count++;
1684         }
1685         return 0;
1686 }
1687
1688 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1689 {
1690         struct drm_device_dma *dma = dev->dma;
1691         int ret = 0;
1692         struct drm_dma *d = data;
1693
1694         LOCK_TEST_WITH_RETURN(dev, file_priv);
1695
1696         /* Please don't send us buffers.
1697          */
1698         if (d->send_count != 0) {
1699                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1700                           DRM_CURRENTPID, d->send_count);
1701                 return -EINVAL;
1702         }
1703
1704         /* We'll send you buffers.
1705          */
1706         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1707                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1708                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1709                 return -EINVAL;
1710         }
1711
1712         d->granted_count = 0;
1713
1714         if (d->request_count) {
1715                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1716         }
1717
1718         return ret;
1719 }
1720
1721 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1722 {
1723         drm_radeon_private_t *dev_priv;
1724         int ret = 0;
1725
1726         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1727         if (dev_priv == NULL)
1728                 return -ENOMEM;
1729
1730         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1731         dev->dev_private = (void *)dev_priv;
1732         dev_priv->flags = flags;
1733
1734         switch (flags & RADEON_FAMILY_MASK) {
1735         case CHIP_R100:
1736         case CHIP_RV200:
1737         case CHIP_R200:
1738         case CHIP_R300:
1739         case CHIP_R350:
1740         case CHIP_R420:
1741         case CHIP_R423:
1742         case CHIP_RV410:
1743         case CHIP_RV515:
1744         case CHIP_R520:
1745         case CHIP_RV570:
1746         case CHIP_R580:
1747                 dev_priv->flags |= RADEON_HAS_HIERZ;
1748                 break;
1749         default:
1750                 /* all other chips have no hierarchical z buffer */
1751                 break;
1752         }
1753
1754         if (drm_device_is_agp(dev))
1755                 dev_priv->flags |= RADEON_IS_AGP;
1756         else if (drm_device_is_pcie(dev))
1757                 dev_priv->flags |= RADEON_IS_PCIE;
1758         else
1759                 dev_priv->flags |= RADEON_IS_PCI;
1760
1761         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1762                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1763                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1764         if (ret != 0)
1765                 return ret;
1766
1767         ret = drm_vblank_init(dev, 2);
1768         if (ret) {
1769                 radeon_driver_unload(dev);
1770                 return ret;
1771         }
1772
1773         DRM_DEBUG("%s card detected\n",
1774                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1775         return ret;
1776 }
1777
1778 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1779 {
1780         struct drm_radeon_master_private *master_priv;
1781         unsigned long sareapage;
1782         int ret;
1783
1784         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1785         if (!master_priv)
1786                 return -ENOMEM;
1787
1788         /* prebuild the SAREA */
1789         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1790         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1791                          &master_priv->sarea);
1792         if (ret) {
1793                 DRM_ERROR("SAREA setup failed\n");
1794                 return ret;
1795         }
1796         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1797         master_priv->sarea_priv->pfCurrentPage = 0;
1798
1799         master->driver_priv = master_priv;
1800         return 0;
1801 }
1802
1803 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1804 {
1805         struct drm_radeon_master_private *master_priv = master->driver_priv;
1806
1807         if (!master_priv)
1808                 return;
1809
1810         if (master_priv->sarea_priv &&
1811             master_priv->sarea_priv->pfCurrentPage != 0)
1812                 radeon_cp_dispatch_flip(dev, master);
1813
1814         master_priv->sarea_priv = NULL;
1815         if (master_priv->sarea)
1816                 drm_rmmap_locked(dev, master_priv->sarea);
1817
1818         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1819
1820         master->driver_priv = NULL;
1821 }
1822
1823 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1824  * have to find them.
1825  */
1826 int radeon_driver_firstopen(struct drm_device *dev)
1827 {
1828         int ret;
1829         drm_local_map_t *map;
1830         drm_radeon_private_t *dev_priv = dev->dev_private;
1831
1832         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1833
1834         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1835         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1836                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1837                          _DRM_WRITE_COMBINING, &map);
1838         if (ret != 0)
1839                 return ret;
1840
1841         return 0;
1842 }
1843
1844 int radeon_driver_unload(struct drm_device *dev)
1845 {
1846         drm_radeon_private_t *dev_priv = dev->dev_private;
1847
1848         DRM_DEBUG("\n");
1849
1850         drm_rmmap(dev, dev_priv->mmio);
1851
1852         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1853
1854         dev->dev_private = NULL;
1855         return 0;
1856 }