2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2005 Texas Instruments, Inc.
9 * Richard Woodruff <r-woodruff2@ti.com>
11 * Based on pm.c for omap1
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/suspend.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/err.h>
24 #include <linux/gpio.h>
26 #include <mach/sram.h>
27 #include <mach/clockdomain.h>
28 #include <mach/powerdomain.h>
29 #include <mach/control.h>
30 #include <mach/serial.h>
33 #include "cm-regbits-34xx.h"
34 #include "prm-regbits-34xx.h"
40 struct powerdomain *pwrdm;
43 struct list_head node;
46 static LIST_HEAD(pwrst_list);
48 static void (*_omap_sram_idle)(u32 *addr, int save_state);
50 static struct powerdomain *mpu_pwrdm;
52 /* PRCM Interrupt Handler for wakeups */
53 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
55 u32 wkst, irqstatus_mpu;
59 wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
61 iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
62 fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
63 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
64 cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
65 prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
66 while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
68 cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
69 cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
73 wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
75 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
76 fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
77 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
78 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
79 prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
80 while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
82 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
83 cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
85 wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
87 iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
88 fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
89 cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
90 cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
91 prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
92 while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
94 cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
95 cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
99 wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
101 iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
102 fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
103 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
104 cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
105 prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
106 while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
108 cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
109 cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
112 if (omap_rev() > OMAP3430_REV_ES1_0) {
114 wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
116 iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
118 fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
120 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
122 cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
124 prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
126 while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
129 cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
131 cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
136 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
137 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
138 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
139 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
141 while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
147 static void omap_sram_idle(void)
149 /* Variable to tell what needs to be saved and restored
150 * in omap_sram_idle*/
151 /* save_state = 0 => Nothing to save and restored */
152 /* save_state = 1 => Only L1 and logic lost */
153 /* save_state = 2 => Only L2 lost */
154 /* save_state = 3 => L1, L2 and logic lost */
155 int save_state = 0, mpu_next_state;
157 if (!_omap_sram_idle)
160 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
161 switch (mpu_next_state) {
162 case PWRDM_POWER_RET:
163 /* No need to save context */
168 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
171 omap2_gpio_prepare_for_retention();
172 omap_uart_prepare_idle(0);
173 omap_uart_prepare_idle(1);
174 omap_uart_prepare_idle(2);
176 _omap_sram_idle(NULL, save_state);
179 omap_uart_resume_idle(2);
180 omap_uart_resume_idle(1);
181 omap_uart_resume_idle(0);
182 omap2_gpio_resume_after_retention();
186 * Check if functional clocks are enabled before entering
187 * sleep. This function could be behind CONFIG_PM_DEBUG
188 * when all drivers are configuring their sysconfig registers
189 * properly and using their clocks properly.
191 static int omap3_fclks_active(void)
193 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
194 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
196 fck_core1 = cm_read_mod_reg(CORE_MOD,
198 if (omap_rev() > OMAP3430_REV_ES1_0) {
199 fck_core3 = cm_read_mod_reg(CORE_MOD,
200 OMAP3430ES2_CM_FCLKEN3);
201 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
203 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
206 fck_sgx = cm_read_mod_reg(GFX_MOD,
207 OMAP3430ES2_CM_FCLKEN3);
208 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
210 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
212 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
215 /* Ignore UART clocks. These are handled by UART core (serial.c) */
216 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
217 fck_per &= ~OMAP3430_EN_UART3;
219 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
220 fck_cam | fck_per | fck_usbhost)
225 static int omap3_can_sleep(void)
227 if (!omap_uart_can_sleep())
229 if (omap3_fclks_active())
234 /* This sets pwrdm state (other than mpu & core. Currently only ON &
235 * RET are supported. Function is assuming that clkdm doesn't have
236 * hw_sup mode enabled. */
237 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
240 int sleep_switch = 0;
243 if (pwrdm == NULL || IS_ERR(pwrdm))
246 while (!(pwrdm->pwrsts & (1 << state))) {
247 if (state == PWRDM_POWER_OFF)
252 cur_state = pwrdm_read_next_pwrst(pwrdm);
253 if (cur_state == state)
256 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
257 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
259 pwrdm_wait_transition(pwrdm);
262 ret = pwrdm_set_next_pwrst(pwrdm, state);
264 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
270 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
271 pwrdm_wait_transition(pwrdm);
278 static void omap3_pm_idle(void)
283 if (!omap3_can_sleep())
286 if (omap_irq_pending())
296 static int omap3_pm_prepare(void)
302 static int omap3_pm_suspend(void)
304 struct power_state *pwrst;
307 /* Read current next_pwrsts */
308 list_for_each_entry(pwrst, &pwrst_list, node)
309 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
310 /* Set ones wanted by suspend */
311 list_for_each_entry(pwrst, &pwrst_list, node) {
312 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
314 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
318 omap_uart_prepare_suspend();
322 /* Restore next_pwrsts */
323 list_for_each_entry(pwrst, &pwrst_list, node) {
324 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
325 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
326 if (state > pwrst->next_state) {
327 printk(KERN_INFO "Powerdomain (%s) didn't enter "
329 pwrst->pwrdm->name, pwrst->next_state);
334 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
336 printk(KERN_INFO "Successfully put all powerdomains "
337 "to target state\n");
342 static int omap3_pm_enter(suspend_state_t state)
347 case PM_SUSPEND_STANDBY:
349 ret = omap3_pm_suspend();
358 static void omap3_pm_finish(void)
363 static struct platform_suspend_ops omap_pm_ops = {
364 .prepare = omap3_pm_prepare,
365 .enter = omap3_pm_enter,
366 .finish = omap3_pm_finish,
367 .valid = suspend_valid_only_mem,
372 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
375 * In cases where IVA2 is activated by bootcode, it may prevent
376 * full-chip retention or off-mode because it is not idle. This
377 * function forces the IVA2 into idle state so it can go
378 * into retention/off and thus allow full-chip retention/off.
381 static void __init omap3_iva_idle(void)
383 /* ensure IVA2 clock is disabled */
384 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
386 /* if no clock activity, nothing else to do */
387 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
388 OMAP3430_CLKACTIVITY_IVA2_MASK))
392 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
395 OMAP3430_IVA2_MOD, RM_RSTCTRL);
397 /* Enable IVA2 clock */
398 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
399 OMAP3430_IVA2_MOD, CM_FCLKEN);
401 /* Set IVA2 boot mode to 'idle' */
402 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
403 OMAP343X_CONTROL_IVA2_BOOTMOD);
406 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
408 /* Disable IVA2 clock */
409 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
412 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
415 OMAP3430_IVA2_MOD, RM_RSTCTRL);
418 static void __init prcm_setup_regs(void)
421 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
422 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
423 CORE_MOD, RM_RSTCTRL);
424 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
426 /* XXX Reset all wkdeps. This should be done when initializing
428 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
429 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
430 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
431 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
432 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
433 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
434 if (omap_rev() > OMAP3430_REV_ES1_0) {
435 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
436 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
438 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
441 * Enable interface clock autoidle for all modules.
442 * Note that in the long run this should be done by clockfw
445 OMAP3430ES2_AUTO_MMC3 |
446 OMAP3430ES2_AUTO_ICR |
448 OMAP3430_AUTO_SHA12 |
452 OMAP3430_AUTO_MSPRO |
454 OMAP3430_AUTO_MCSPI4 |
455 OMAP3430_AUTO_MCSPI3 |
456 OMAP3430_AUTO_MCSPI2 |
457 OMAP3430_AUTO_MCSPI1 |
461 OMAP3430_AUTO_UART2 |
462 OMAP3430_AUTO_UART1 |
463 OMAP3430_AUTO_GPT11 |
464 OMAP3430_AUTO_GPT10 |
465 OMAP3430_AUTO_MCBSP5 |
466 OMAP3430_AUTO_MCBSP1 |
467 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
468 OMAP3430_AUTO_MAILBOXES |
469 OMAP3430_AUTO_OMAPCTRL |
470 OMAP3430ES1_AUTO_FSHOSTUSB |
471 OMAP3430_AUTO_HSOTGUSB |
472 OMAP3430ES1_AUTO_D2D | /* This is es1 only */
474 CORE_MOD, CM_AUTOIDLE1);
480 OMAP3430_AUTO_SHA11 |
482 CORE_MOD, CM_AUTOIDLE2);
484 if (omap_rev() > OMAP3430_REV_ES1_0) {
486 OMAP3430ES2_AUTO_USBTLL,
487 CORE_MOD, CM_AUTOIDLE3);
493 OMAP3430_AUTO_GPIO1 |
494 OMAP3430_AUTO_32KSYNC |
495 OMAP3430_AUTO_GPT12 |
497 WKUP_MOD, CM_AUTOIDLE);
510 OMAP3430_AUTO_GPIO6 |
511 OMAP3430_AUTO_GPIO5 |
512 OMAP3430_AUTO_GPIO4 |
513 OMAP3430_AUTO_GPIO3 |
514 OMAP3430_AUTO_GPIO2 |
516 OMAP3430_AUTO_UART3 |
525 OMAP3430_AUTO_MCBSP4 |
526 OMAP3430_AUTO_MCBSP3 |
527 OMAP3430_AUTO_MCBSP2,
531 if (omap_rev() > OMAP3430_REV_ES1_0) {
533 OMAP3430ES2_AUTO_USBHOST,
534 OMAP3430ES2_USBHOST_MOD,
539 * Set all plls to autoidle. This is needed until autoidle is
542 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
543 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
544 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
547 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
548 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
551 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
556 * Enable control of expternal oscillator through
557 * sys_clkreq. In the long run clock framework should
560 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
561 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
563 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
565 /* setup wakup source */
566 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
567 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
569 /* No need to write EN_IO, that is always enabled */
570 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
572 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
573 /* For some reason IO doesn't generate wakeup event even if
574 * it is selected to mpu wakeup goup */
575 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
576 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
581 static int __init pwrdms_setup(struct powerdomain *pwrdm)
583 struct power_state *pwrst;
588 pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
591 pwrst->pwrdm = pwrdm;
592 pwrst->next_state = PWRDM_POWER_RET;
593 list_add(&pwrst->node, &pwrst_list);
595 if (pwrdm_has_hdwr_sar(pwrdm))
596 pwrdm_enable_hdwr_sar(pwrdm);
598 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
602 * Enable hw supervised mode for all clockdomains if it's
603 * supported. Initiate sleep transition for other clockdomains, if
606 static int __init clkdms_setup(struct clockdomain *clkdm)
608 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
609 omap2_clkdm_allow_idle(clkdm);
610 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
611 atomic_read(&clkdm->usecount) == 0)
612 omap2_clkdm_sleep(clkdm);
616 int __init omap3_pm_init(void)
618 struct power_state *pwrst, *tmp;
621 if (!cpu_is_omap34xx())
624 printk(KERN_ERR "Power Management for TI OMAP3.\n");
626 /* XXX prcm_setup_regs needs to be before enabling hw
627 * supervised mode for powerdomains */
630 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
631 (irq_handler_t)prcm_interrupt_handler,
632 IRQF_DISABLED, "prcm", NULL);
634 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
635 INT_34XX_PRCM_MPU_IRQ);
639 ret = pwrdm_for_each(pwrdms_setup);
641 printk(KERN_ERR "Failed to setup powerdomains\n");
645 (void) clkdm_for_each(clkdms_setup);
647 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
648 if (mpu_pwrdm == NULL) {
649 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
653 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
654 omap34xx_cpu_suspend_sz);
656 suspend_set_ops(&omap_pm_ops);
658 pm_idle = omap3_pm_idle;
663 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
664 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
665 list_del(&pwrst->node);
671 late_initcall(omap3_pm_init);