2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_reg.h>
21 #include <linux/clk.h>
24 #include <mach/common.h>
25 #include <mach/board.h>
26 #include <mach/clock.h>
27 #include <mach/control.h>
31 #include "prm-regbits-34xx.h"
33 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
35 #define DEFAULT_TIMEOUT (2 * HZ)
37 struct omap_uart_state {
40 struct timer_list timer;
52 struct plat_serial8250_port *p;
53 struct list_head node;
55 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
58 /* Registers to be saved/restored for OFF-mode */
68 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS];
69 static LIST_HEAD(uart_list);
71 static struct plat_serial8250_port serial_platform_data[] = {
73 .membase = IO_ADDRESS(OMAP_UART1_BASE),
74 .mapbase = OMAP_UART1_BASE,
76 .flags = UPF_BOOT_AUTOCONF,
79 .uartclk = OMAP24XX_BASE_BAUD * 16,
81 .membase = IO_ADDRESS(OMAP_UART2_BASE),
82 .mapbase = OMAP_UART2_BASE,
84 .flags = UPF_BOOT_AUTOCONF,
87 .uartclk = OMAP24XX_BASE_BAUD * 16,
89 .membase = IO_ADDRESS(OMAP_UART3_BASE),
90 .mapbase = OMAP_UART3_BASE,
92 .flags = UPF_BOOT_AUTOCONF,
95 .uartclk = OMAP24XX_BASE_BAUD * 16,
101 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
104 offset <<= up->regshift;
105 return (unsigned int)__raw_readb(up->membase + offset);
108 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
111 offset <<= p->regshift;
112 __raw_writeb(value, p->membase + offset);
116 * Internal UARTs need to be initialized for the 8250 autoconfig to work
117 * properly. Note that the TX watermark initialization may not be needed
118 * once the 8250.c watermark handling code is merged.
120 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
122 struct plat_serial8250_port *p = uart->p;
124 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
125 serial_write_reg(p, UART_OMAP_SCR, 0x08);
126 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
127 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
130 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
132 static int enable_off_mode; /* to be removed by full off-mode patches */
134 static void omap_uart_save_context(struct omap_uart_state *uart)
137 struct plat_serial8250_port *p = uart->p;
139 if (!enable_off_mode)
142 lcr = serial_read_reg(p, UART_LCR);
143 serial_write_reg(p, UART_LCR, 0xBF);
144 uart->dll = serial_read_reg(p, UART_DLL);
145 uart->dlh = serial_read_reg(p, UART_DLM);
146 serial_write_reg(p, UART_LCR, lcr);
147 uart->ier = serial_read_reg(p, UART_IER);
148 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
149 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
150 uart->wer = serial_read_reg(p, UART_OMAP_WER);
152 uart->context_valid = 1;
155 static void omap_uart_restore_context(struct omap_uart_state *uart)
158 struct plat_serial8250_port *p = uart->p;
160 if (!enable_off_mode)
163 if (!uart->context_valid)
166 uart->context_valid = 0;
168 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
169 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
170 efr = serial_read_reg(p, UART_EFR);
171 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
172 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
173 serial_write_reg(p, UART_IER, 0x0);
174 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
175 serial_write_reg(p, UART_DLL, uart->dll);
176 serial_write_reg(p, UART_DLM, uart->dlh);
177 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
178 serial_write_reg(p, UART_IER, uart->ier);
179 serial_write_reg(p, UART_FCR, 0xA1);
180 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
181 serial_write_reg(p, UART_EFR, efr);
182 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
183 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
184 serial_write_reg(p, UART_OMAP_WER, uart->wer);
185 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
186 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
189 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
190 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
191 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
193 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
198 clk_enable(uart->ick);
199 clk_enable(uart->fck);
201 omap_uart_restore_context(uart);
206 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
211 omap_uart_save_context(uart);
213 clk_disable(uart->ick);
214 clk_disable(uart->fck);
217 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
220 struct plat_serial8250_port *p = uart->p;
223 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
229 serial_write_reg(p, UART_OMAP_SYSC, sysc);
232 static void omap_uart_block_sleep(struct omap_uart_state *uart)
234 omap_uart_enable_clocks(uart);
236 omap_uart_smart_idle_enable(uart, 0);
238 mod_timer(&uart->timer, jiffies + uart->timeout);
241 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
246 omap_uart_smart_idle_enable(uart, 1);
248 del_timer(&uart->timer);
251 static void omap_uart_idle_timer(unsigned long data)
253 struct omap_uart_state *uart = (struct omap_uart_state *)data;
255 omap_uart_allow_sleep(uart);
258 void omap_uart_prepare_idle(int num)
260 struct omap_uart_state *uart;
262 list_for_each_entry(uart, &uart_list, node) {
263 if (num == uart->num && uart->can_sleep) {
264 omap_uart_disable_clocks(uart);
270 void omap_uart_resume_idle(int num)
272 struct omap_uart_state *uart;
274 list_for_each_entry(uart, &uart_list, node) {
275 if (num == uart->num) {
276 omap_uart_enable_clocks(uart);
278 /* Check for IO pad wakeup */
279 if (cpu_is_omap34xx() && uart->padconf) {
280 u16 p = omap_ctrl_readw(uart->padconf);
282 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
283 omap_uart_block_sleep(uart);
286 /* Check for normal UART wakeup */
287 if (__raw_readl(uart->wk_st) & uart->wk_mask)
288 omap_uart_block_sleep(uart);
295 void omap_uart_prepare_suspend(void)
297 struct omap_uart_state *uart;
299 list_for_each_entry(uart, &uart_list, node) {
300 omap_uart_allow_sleep(uart);
304 int omap_uart_can_sleep(void)
306 struct omap_uart_state *uart;
309 list_for_each_entry(uart, &uart_list, node) {
313 if (!uart->can_sleep) {
318 /* This UART can now safely sleep. */
319 omap_uart_allow_sleep(uart);
326 * omap_uart_interrupt()
328 * This handler is used only to detect that *any* UART interrupt has
329 * occurred. It does _nothing_ to handle the interrupt. Rather,
330 * any UART interrupt will trigger the inactivity timer so the
331 * UART will not idle or sleep for its timeout period.
334 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
336 struct omap_uart_state *uart = dev_id;
338 omap_uart_block_sleep(uart);
343 static void omap_uart_idle_init(struct omap_uart_state *uart)
346 struct plat_serial8250_port *p = uart->p;
350 uart->timeout = DEFAULT_TIMEOUT;
351 setup_timer(&uart->timer, omap_uart_idle_timer,
352 (unsigned long) uart);
353 mod_timer(&uart->timer, jiffies + uart->timeout);
354 omap_uart_smart_idle_enable(uart, 0);
356 if (cpu_is_omap34xx()) {
357 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
361 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
362 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
365 wk_mask = OMAP3430_ST_UART1_MASK;
369 wk_mask = OMAP3430_ST_UART2_MASK;
373 wk_mask = OMAP3430_ST_UART3_MASK;
377 uart->wk_mask = wk_mask;
378 uart->padconf = padconf;
379 } else if (cpu_is_omap24xx()) {
382 if (cpu_is_omap2430()) {
383 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
384 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
385 } else if (cpu_is_omap2420()) {
386 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
387 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
391 wk_mask = OMAP24XX_ST_UART1_MASK;
394 wk_mask = OMAP24XX_ST_UART2_MASK;
397 wk_mask = OMAP24XX_ST_UART3_MASK;
400 uart->wk_mask = wk_mask;
408 /* Set wake-enable bit */
409 if (uart->wk_en && uart->wk_mask) {
410 v = __raw_readl(uart->wk_en);
412 __raw_writel(v, uart->wk_en);
415 /* Ensure IOPAD wake-enables are set */
416 if (cpu_is_omap34xx() && uart->padconf) {
419 v = omap_ctrl_readw(uart->padconf);
420 v |= OMAP3_PADCONF_WAKEUPENABLE0;
421 omap_ctrl_writew(v, uart->padconf);
424 p->flags |= UPF_SHARE_IRQ;
425 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
426 "serial idle", (void *)uart);
431 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
432 #endif /* CONFIG_PM */
434 void __init omap_serial_init(void)
437 const struct omap_uart_config *info;
441 * Make sure the serial ports are muxed on at this point.
442 * You have to mux them off in device drivers later on
446 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
451 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
452 struct plat_serial8250_port *p = serial_platform_data + i;
453 struct omap_uart_state *uart = &omap_uart[i];
455 if (!(info->enabled_uarts & (1 << i))) {
461 sprintf(name, "uart%d_ick", i+1);
462 uart->ick = clk_get(NULL, name);
463 if (IS_ERR(uart->ick)) {
464 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
468 sprintf(name, "uart%d_fck", i+1);
469 uart->fck = clk_get(NULL, name);
470 if (IS_ERR(uart->fck)) {
471 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
475 if (!uart->ick || !uart->fck)
479 p->private_data = uart;
481 list_add(&uart->node, &uart_list);
483 omap_uart_enable_clocks(uart);
484 omap_uart_reset(uart);
485 omap_uart_idle_init(uart);
489 static struct platform_device serial_device = {
490 .name = "serial8250",
491 .id = PLAT8250_DEV_PLATFORM,
493 .platform_data = serial_platform_data,
497 static int __init omap_init(void)
499 return platform_device_register(&serial_device);
501 arch_initcall(omap_init);