Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable
[linux-2.6] / drivers / net / e1000e / ich8lan.c
1 /*******************************************************************************
2
3   Intel PRO/1000 Linux driver
4   Copyright(c) 1999 - 2008 Intel Corporation.
5
6   This program is free software; you can redistribute it and/or modify it
7   under the terms and conditions of the GNU General Public License,
8   version 2, as published by the Free Software Foundation.
9
10   This program is distributed in the hope it will be useful, but WITHOUT
11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13   more details.
14
15   You should have received a copy of the GNU General Public License along with
16   this program; if not, write to the Free Software Foundation, Inc.,
17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19   The full GNU General Public License is included in this distribution in
20   the file called "COPYING".
21
22   Contact Information:
23   Linux NICS <linux.nics@intel.com>
24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30  * 82562G 10/100 Network Connection
31  * 82562G-2 10/100 Network Connection
32  * 82562GT 10/100 Network Connection
33  * 82562GT-2 10/100 Network Connection
34  * 82562V 10/100 Network Connection
35  * 82562V-2 10/100 Network Connection
36  * 82566DC-2 Gigabit Network Connection
37  * 82566DC Gigabit Network Connection
38  * 82566DM-2 Gigabit Network Connection
39  * 82566DM Gigabit Network Connection
40  * 82566MC Gigabit Network Connection
41  * 82566MM Gigabit Network Connection
42  * 82567LM Gigabit Network Connection
43  * 82567LF Gigabit Network Connection
44  * 82567V Gigabit Network Connection
45  * 82567LM-2 Gigabit Network Connection
46  * 82567LF-2 Gigabit Network Connection
47  * 82567V-2 Gigabit Network Connection
48  * 82567LF-3 Gigabit Network Connection
49  * 82567LM-3 Gigabit Network Connection
50  * 82567LM-4 Gigabit Network Connection
51  */
52
53 #include <linux/netdevice.h>
54 #include <linux/ethtool.h>
55 #include <linux/delay.h>
56 #include <linux/pci.h>
57
58 #include "e1000.h"
59
60 #define ICH_FLASH_GFPREG                0x0000
61 #define ICH_FLASH_HSFSTS                0x0004
62 #define ICH_FLASH_HSFCTL                0x0006
63 #define ICH_FLASH_FADDR                 0x0008
64 #define ICH_FLASH_FDATA0                0x0010
65 #define ICH_FLASH_PR0                   0x0074
66
67 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
68 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
70 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
71 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
72
73 #define ICH_CYCLE_READ                  0
74 #define ICH_CYCLE_WRITE                 2
75 #define ICH_CYCLE_ERASE                 3
76
77 #define FLASH_GFPREG_BASE_MASK          0x1FFF
78 #define FLASH_SECTOR_ADDR_SHIFT         12
79
80 #define ICH_FLASH_SEG_SIZE_256          256
81 #define ICH_FLASH_SEG_SIZE_4K           4096
82 #define ICH_FLASH_SEG_SIZE_8K           8192
83 #define ICH_FLASH_SEG_SIZE_64K          65536
84
85
86 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
87
88 #define E1000_ICH_MNG_IAMT_MODE         0x2
89
90 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
91                                  (ID_LED_DEF1_OFF2 <<  8) | \
92                                  (ID_LED_DEF1_ON2  <<  4) | \
93                                  (ID_LED_DEF1_DEF2))
94
95 #define E1000_ICH_NVM_SIG_WORD          0x13
96 #define E1000_ICH_NVM_SIG_MASK          0xC000
97 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
98 #define E1000_ICH_NVM_SIG_VALUE         0x80
99
100 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
101
102 #define E1000_FEXTNVM_SW_CONFIG         1
103 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
104
105 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
106
107 #define E1000_ICH_RAR_ENTRIES           7
108
109 #define PHY_PAGE_SHIFT 5
110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
111                            ((reg) & MAX_PHY_REG_ADDRESS))
112 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
114
115 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
116 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
117 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
118
119 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
120 /* Offset 04h HSFSTS */
121 union ich8_hws_flash_status {
122         struct ich8_hsfsts {
123                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
124                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
125                 u16 dael       :1; /* bit 2 Direct Access error Log */
126                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
127                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
128                 u16 reserved1  :2; /* bit 13:6 Reserved */
129                 u16 reserved2  :6; /* bit 13:6 Reserved */
130                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
131                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
132         } hsf_status;
133         u16 regval;
134 };
135
136 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
137 /* Offset 06h FLCTL */
138 union ich8_hws_flash_ctrl {
139         struct ich8_hsflctl {
140                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
141                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
142                 u16 reserved   :5;   /* 7:3 Reserved  */
143                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
144                 u16 flockdn    :6;   /* 15:10 Reserved */
145         } hsf_ctrl;
146         u16 regval;
147 };
148
149 /* ICH Flash Region Access Permissions */
150 union ich8_hws_flash_regacc {
151         struct ich8_flracc {
152                 u32 grra      :8; /* 0:7 GbE region Read Access */
153                 u32 grwa      :8; /* 8:15 GbE region Write Access */
154                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
155                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
156         } hsf_flregacc;
157         u16 regval;
158 };
159
160 /* ICH Flash Protected Region */
161 union ich8_flash_protected_range {
162         struct ich8_pr {
163                 u32 base:13;     /* 0:12 Protected Range Base */
164                 u32 reserved1:2; /* 13:14 Reserved */
165                 u32 rpe:1;       /* 15 Read Protection Enable */
166                 u32 limit:13;    /* 16:28 Protected Range Limit */
167                 u32 reserved2:2; /* 29:30 Reserved */
168                 u32 wpe:1;       /* 31 Write Protection Enable */
169         } range;
170         u32 regval;
171 };
172
173 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
174 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
175 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
176 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
177 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
178 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
179                                                 u32 offset, u8 byte);
180 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
181                                          u8 *data);
182 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
183                                          u16 *data);
184 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
185                                          u8 size, u16 *data);
186 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
187 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
188 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
189
190 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
191 {
192         return readw(hw->flash_address + reg);
193 }
194
195 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
196 {
197         return readl(hw->flash_address + reg);
198 }
199
200 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
201 {
202         writew(val, hw->flash_address + reg);
203 }
204
205 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
206 {
207         writel(val, hw->flash_address + reg);
208 }
209
210 #define er16flash(reg)          __er16flash(hw, (reg))
211 #define er32flash(reg)          __er32flash(hw, (reg))
212 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
213 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
214
215 /**
216  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
217  *  @hw: pointer to the HW structure
218  *
219  *  Initialize family-specific PHY parameters and function pointers.
220  **/
221 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
222 {
223         struct e1000_phy_info *phy = &hw->phy;
224         s32 ret_val;
225         u16 i = 0;
226
227         phy->addr                       = 1;
228         phy->reset_delay_us             = 100;
229
230         /*
231          * We may need to do this twice - once for IGP and if that fails,
232          * we'll set BM func pointers and try again
233          */
234         ret_val = e1000e_determine_phy_address(hw);
235         if (ret_val) {
236                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
237                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
238                 ret_val = e1000e_determine_phy_address(hw);
239                 if (ret_val)
240                         return ret_val;
241         }
242
243         phy->id = 0;
244         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
245                (i++ < 100)) {
246                 msleep(1);
247                 ret_val = e1000e_get_phy_id(hw);
248                 if (ret_val)
249                         return ret_val;
250         }
251
252         /* Verify phy id */
253         switch (phy->id) {
254         case IGP03E1000_E_PHY_ID:
255                 phy->type = e1000_phy_igp_3;
256                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
257                 break;
258         case IFE_E_PHY_ID:
259         case IFE_PLUS_E_PHY_ID:
260         case IFE_C_E_PHY_ID:
261                 phy->type = e1000_phy_ife;
262                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
263                 break;
264         case BME1000_E_PHY_ID:
265                 phy->type = e1000_phy_bm;
266                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
267                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
268                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
269                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
270                 break;
271         default:
272                 return -E1000_ERR_PHY;
273                 break;
274         }
275
276         return 0;
277 }
278
279 /**
280  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
281  *  @hw: pointer to the HW structure
282  *
283  *  Initialize family-specific NVM parameters and function
284  *  pointers.
285  **/
286 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
287 {
288         struct e1000_nvm_info *nvm = &hw->nvm;
289         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
290         u32 gfpreg;
291         u32 sector_base_addr;
292         u32 sector_end_addr;
293         u16 i;
294
295         /* Can't read flash registers if the register set isn't mapped. */
296         if (!hw->flash_address) {
297                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
298                 return -E1000_ERR_CONFIG;
299         }
300
301         nvm->type = e1000_nvm_flash_sw;
302
303         gfpreg = er32flash(ICH_FLASH_GFPREG);
304
305         /*
306          * sector_X_addr is a "sector"-aligned address (4096 bytes)
307          * Add 1 to sector_end_addr since this sector is included in
308          * the overall size.
309          */
310         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
311         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
312
313         /* flash_base_addr is byte-aligned */
314         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
315
316         /*
317          * find total size of the NVM, then cut in half since the total
318          * size represents two separate NVM banks.
319          */
320         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
321                                 << FLASH_SECTOR_ADDR_SHIFT;
322         nvm->flash_bank_size /= 2;
323         /* Adjust to word count */
324         nvm->flash_bank_size /= sizeof(u16);
325
326         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
327
328         /* Clear shadow ram */
329         for (i = 0; i < nvm->word_size; i++) {
330                 dev_spec->shadow_ram[i].modified = 0;
331                 dev_spec->shadow_ram[i].value    = 0xFFFF;
332         }
333
334         return 0;
335 }
336
337 /**
338  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
339  *  @hw: pointer to the HW structure
340  *
341  *  Initialize family-specific MAC parameters and function
342  *  pointers.
343  **/
344 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
345 {
346         struct e1000_hw *hw = &adapter->hw;
347         struct e1000_mac_info *mac = &hw->mac;
348
349         /* Set media type function pointer */
350         hw->phy.media_type = e1000_media_type_copper;
351
352         /* Set mta register count */
353         mac->mta_reg_count = 32;
354         /* Set rar entry count */
355         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
356         if (mac->type == e1000_ich8lan)
357                 mac->rar_entry_count--;
358         /* Set if manageability features are enabled. */
359         mac->arc_subsystem_valid = 1;
360
361         /* Enable PCS Lock-loss workaround for ICH8 */
362         if (mac->type == e1000_ich8lan)
363                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
364
365         return 0;
366 }
367
368 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
369 {
370         struct e1000_hw *hw = &adapter->hw;
371         s32 rc;
372
373         rc = e1000_init_mac_params_ich8lan(adapter);
374         if (rc)
375                 return rc;
376
377         rc = e1000_init_nvm_params_ich8lan(hw);
378         if (rc)
379                 return rc;
380
381         rc = e1000_init_phy_params_ich8lan(hw);
382         if (rc)
383                 return rc;
384
385         if ((adapter->hw.mac.type == e1000_ich8lan) &&
386             (adapter->hw.phy.type == e1000_phy_igp_3))
387                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
388
389         return 0;
390 }
391
392 static DEFINE_MUTEX(nvm_mutex);
393 static pid_t nvm_owner_pid = -1;
394 static char nvm_owner_name[TASK_COMM_LEN] = "";
395
396 /**
397  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
398  *  @hw: pointer to the HW structure
399  *
400  *  Acquires the software control flag for performing NVM and PHY
401  *  operations.  This is a function pointer entry point only called by
402  *  read/write routines for the PHY and NVM parts.
403  **/
404 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
405 {
406         u32 extcnf_ctrl;
407         u32 timeout = PHY_CFG_TIMEOUT;
408
409         might_sleep();
410
411         if (!mutex_trylock(&nvm_mutex)) {
412                 WARN(1, KERN_ERR "e1000e mutex contention. Owned by process "
413                      "%s (pid %d), required by process %s (pid %d)\n",
414                      nvm_owner_name, nvm_owner_pid,
415                      current->comm, current->pid);
416
417                 mutex_lock(&nvm_mutex);
418         }
419         nvm_owner_pid = current->pid;
420         strncpy(nvm_owner_name, current->comm, TASK_COMM_LEN);
421
422         while (timeout) {
423                 extcnf_ctrl = er32(EXTCNF_CTRL);
424                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
425                 ew32(EXTCNF_CTRL, extcnf_ctrl);
426
427                 extcnf_ctrl = er32(EXTCNF_CTRL);
428                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
429                         break;
430                 mdelay(1);
431                 timeout--;
432         }
433
434         if (!timeout) {
435                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
436                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
437                 ew32(EXTCNF_CTRL, extcnf_ctrl);
438                 nvm_owner_pid = -1;
439                 strcpy(nvm_owner_name, "");
440                 mutex_unlock(&nvm_mutex);
441                 return -E1000_ERR_CONFIG;
442         }
443
444         return 0;
445 }
446
447 /**
448  *  e1000_release_swflag_ich8lan - Release software control flag
449  *  @hw: pointer to the HW structure
450  *
451  *  Releases the software control flag for performing NVM and PHY operations.
452  *  This is a function pointer entry point only called by read/write
453  *  routines for the PHY and NVM parts.
454  **/
455 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
456 {
457         u32 extcnf_ctrl;
458
459         extcnf_ctrl = er32(EXTCNF_CTRL);
460         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
461         ew32(EXTCNF_CTRL, extcnf_ctrl);
462
463         nvm_owner_pid = -1;
464         strcpy(nvm_owner_name, "");
465         mutex_unlock(&nvm_mutex);
466 }
467
468 /**
469  *  e1000_check_mng_mode_ich8lan - Checks management mode
470  *  @hw: pointer to the HW structure
471  *
472  *  This checks if the adapter has manageability enabled.
473  *  This is a function pointer entry point only called by read/write
474  *  routines for the PHY and NVM parts.
475  **/
476 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
477 {
478         u32 fwsm = er32(FWSM);
479
480         return (fwsm & E1000_FWSM_MODE_MASK) ==
481                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
482 }
483
484 /**
485  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
486  *  @hw: pointer to the HW structure
487  *
488  *  Checks if firmware is blocking the reset of the PHY.
489  *  This is a function pointer entry point only called by
490  *  reset routines.
491  **/
492 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
493 {
494         u32 fwsm;
495
496         fwsm = er32(FWSM);
497
498         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
499 }
500
501 /**
502  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
503  *  @hw: pointer to the HW structure
504  *
505  *  Forces the speed and duplex settings of the PHY.
506  *  This is a function pointer entry point only called by
507  *  PHY setup routines.
508  **/
509 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
510 {
511         struct e1000_phy_info *phy = &hw->phy;
512         s32 ret_val;
513         u16 data;
514         bool link;
515
516         if (phy->type != e1000_phy_ife) {
517                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
518                 return ret_val;
519         }
520
521         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
522         if (ret_val)
523                 return ret_val;
524
525         e1000e_phy_force_speed_duplex_setup(hw, &data);
526
527         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
528         if (ret_val)
529                 return ret_val;
530
531         /* Disable MDI-X support for 10/100 */
532         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
533         if (ret_val)
534                 return ret_val;
535
536         data &= ~IFE_PMC_AUTO_MDIX;
537         data &= ~IFE_PMC_FORCE_MDIX;
538
539         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
540         if (ret_val)
541                 return ret_val;
542
543         hw_dbg(hw, "IFE PMC: %X\n", data);
544
545         udelay(1);
546
547         if (phy->autoneg_wait_to_complete) {
548                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
549
550                 ret_val = e1000e_phy_has_link_generic(hw,
551                                                      PHY_FORCE_LIMIT,
552                                                      100000,
553                                                      &link);
554                 if (ret_val)
555                         return ret_val;
556
557                 if (!link)
558                         hw_dbg(hw, "Link taking longer than expected.\n");
559
560                 /* Try once more */
561                 ret_val = e1000e_phy_has_link_generic(hw,
562                                                      PHY_FORCE_LIMIT,
563                                                      100000,
564                                                      &link);
565                 if (ret_val)
566                         return ret_val;
567         }
568
569         return 0;
570 }
571
572 /**
573  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
574  *  @hw: pointer to the HW structure
575  *
576  *  Resets the PHY
577  *  This is a function pointer entry point called by drivers
578  *  or other shared routines.
579  **/
580 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
581 {
582         struct e1000_phy_info *phy = &hw->phy;
583         u32 i;
584         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
585         s32 ret_val;
586         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
587         u16 word_addr, reg_data, reg_addr, phy_page = 0;
588
589         ret_val = e1000e_phy_hw_reset_generic(hw);
590         if (ret_val)
591                 return ret_val;
592
593         /*
594          * Initialize the PHY from the NVM on ICH platforms.  This
595          * is needed due to an issue where the NVM configuration is
596          * not properly autoloaded after power transitions.
597          * Therefore, after each PHY reset, we will load the
598          * configuration data out of the NVM manually.
599          */
600         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
601                 struct e1000_adapter *adapter = hw->adapter;
602
603                 /* Check if SW needs configure the PHY */
604                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
605                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
606                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
607                 else
608                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
609
610                 data = er32(FEXTNVM);
611                 if (!(data & sw_cfg_mask))
612                         return 0;
613
614                 /* Wait for basic configuration completes before proceeding*/
615                 do {
616                         data = er32(STATUS);
617                         data &= E1000_STATUS_LAN_INIT_DONE;
618                         udelay(100);
619                 } while ((!data) && --loop);
620
621                 /*
622                  * If basic configuration is incomplete before the above loop
623                  * count reaches 0, loading the configuration from NVM will
624                  * leave the PHY in a bad state possibly resulting in no link.
625                  */
626                 if (loop == 0) {
627                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
628                 }
629
630                 /* Clear the Init Done bit for the next init event */
631                 data = er32(STATUS);
632                 data &= ~E1000_STATUS_LAN_INIT_DONE;
633                 ew32(STATUS, data);
634
635                 /*
636                  * Make sure HW does not configure LCD from PHY
637                  * extended configuration before SW configuration
638                  */
639                 data = er32(EXTCNF_CTRL);
640                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
641                         return 0;
642
643                 cnf_size = er32(EXTCNF_SIZE);
644                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
645                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
646                 if (!cnf_size)
647                         return 0;
648
649                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
650                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
651
652                 /* Configure LCD from extended configuration region. */
653
654                 /* cnf_base_addr is in DWORD */
655                 word_addr = (u16)(cnf_base_addr << 1);
656
657                 for (i = 0; i < cnf_size; i++) {
658                         ret_val = e1000_read_nvm(hw,
659                                                 (word_addr + i * 2),
660                                                 1,
661                                                 &reg_data);
662                         if (ret_val)
663                                 return ret_val;
664
665                         ret_val = e1000_read_nvm(hw,
666                                                 (word_addr + i * 2 + 1),
667                                                 1,
668                                                 &reg_addr);
669                         if (ret_val)
670                                 return ret_val;
671
672                         /* Save off the PHY page for future writes. */
673                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
674                                 phy_page = reg_data;
675                                 continue;
676                         }
677
678                         reg_addr |= phy_page;
679
680                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
681                         if (ret_val)
682                                 return ret_val;
683                 }
684         }
685
686         return 0;
687 }
688
689 /**
690  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
691  *  @hw: pointer to the HW structure
692  *
693  *  Populates "phy" structure with various feature states.
694  *  This function is only called by other family-specific
695  *  routines.
696  **/
697 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
698 {
699         struct e1000_phy_info *phy = &hw->phy;
700         s32 ret_val;
701         u16 data;
702         bool link;
703
704         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
705         if (ret_val)
706                 return ret_val;
707
708         if (!link) {
709                 hw_dbg(hw, "Phy info is only valid if link is up\n");
710                 return -E1000_ERR_CONFIG;
711         }
712
713         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
714         if (ret_val)
715                 return ret_val;
716         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
717
718         if (phy->polarity_correction) {
719                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
720                 if (ret_val)
721                         return ret_val;
722         } else {
723                 /* Polarity is forced */
724                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
725                                       ? e1000_rev_polarity_reversed
726                                       : e1000_rev_polarity_normal;
727         }
728
729         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
730         if (ret_val)
731                 return ret_val;
732
733         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
734
735         /* The following parameters are undefined for 10/100 operation. */
736         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
737         phy->local_rx = e1000_1000t_rx_status_undefined;
738         phy->remote_rx = e1000_1000t_rx_status_undefined;
739
740         return 0;
741 }
742
743 /**
744  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
745  *  @hw: pointer to the HW structure
746  *
747  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
748  *  This is a function pointer entry point called by drivers
749  *  or other shared routines.
750  **/
751 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
752 {
753         switch (hw->phy.type) {
754         case e1000_phy_ife:
755                 return e1000_get_phy_info_ife_ich8lan(hw);
756                 break;
757         case e1000_phy_igp_3:
758         case e1000_phy_bm:
759                 return e1000e_get_phy_info_igp(hw);
760                 break;
761         default:
762                 break;
763         }
764
765         return -E1000_ERR_PHY_TYPE;
766 }
767
768 /**
769  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
770  *  @hw: pointer to the HW structure
771  *
772  *  Polarity is determined on the polarity reversal feature being enabled.
773  *  This function is only called by other family-specific
774  *  routines.
775  **/
776 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
777 {
778         struct e1000_phy_info *phy = &hw->phy;
779         s32 ret_val;
780         u16 phy_data, offset, mask;
781
782         /*
783          * Polarity is determined based on the reversal feature being enabled.
784          */
785         if (phy->polarity_correction) {
786                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
787                 mask    = IFE_PESC_POLARITY_REVERSED;
788         } else {
789                 offset  = IFE_PHY_SPECIAL_CONTROL;
790                 mask    = IFE_PSC_FORCE_POLARITY;
791         }
792
793         ret_val = e1e_rphy(hw, offset, &phy_data);
794
795         if (!ret_val)
796                 phy->cable_polarity = (phy_data & mask)
797                                       ? e1000_rev_polarity_reversed
798                                       : e1000_rev_polarity_normal;
799
800         return ret_val;
801 }
802
803 /**
804  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
805  *  @hw: pointer to the HW structure
806  *  @active: TRUE to enable LPLU, FALSE to disable
807  *
808  *  Sets the LPLU D0 state according to the active flag.  When
809  *  activating LPLU this function also disables smart speed
810  *  and vice versa.  LPLU will not be activated unless the
811  *  device autonegotiation advertisement meets standards of
812  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
813  *  This is a function pointer entry point only called by
814  *  PHY setup routines.
815  **/
816 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
817 {
818         struct e1000_phy_info *phy = &hw->phy;
819         u32 phy_ctrl;
820         s32 ret_val = 0;
821         u16 data;
822
823         if (phy->type == e1000_phy_ife)
824                 return ret_val;
825
826         phy_ctrl = er32(PHY_CTRL);
827
828         if (active) {
829                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
830                 ew32(PHY_CTRL, phy_ctrl);
831
832                 /*
833                  * Call gig speed drop workaround on LPLU before accessing
834                  * any PHY registers
835                  */
836                 if ((hw->mac.type == e1000_ich8lan) &&
837                     (hw->phy.type == e1000_phy_igp_3))
838                         e1000e_gig_downshift_workaround_ich8lan(hw);
839
840                 /* When LPLU is enabled, we should disable SmartSpeed */
841                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
842                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
843                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
844                 if (ret_val)
845                         return ret_val;
846         } else {
847                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
848                 ew32(PHY_CTRL, phy_ctrl);
849
850                 /*
851                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
852                  * during Dx states where the power conservation is most
853                  * important.  During driver activity we should enable
854                  * SmartSpeed, so performance is maintained.
855                  */
856                 if (phy->smart_speed == e1000_smart_speed_on) {
857                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
858                                            &data);
859                         if (ret_val)
860                                 return ret_val;
861
862                         data |= IGP01E1000_PSCFR_SMART_SPEED;
863                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
864                                            data);
865                         if (ret_val)
866                                 return ret_val;
867                 } else if (phy->smart_speed == e1000_smart_speed_off) {
868                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
869                                            &data);
870                         if (ret_val)
871                                 return ret_val;
872
873                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
874                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
875                                            data);
876                         if (ret_val)
877                                 return ret_val;
878                 }
879         }
880
881         return 0;
882 }
883
884 /**
885  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
886  *  @hw: pointer to the HW structure
887  *  @active: TRUE to enable LPLU, FALSE to disable
888  *
889  *  Sets the LPLU D3 state according to the active flag.  When
890  *  activating LPLU this function also disables smart speed
891  *  and vice versa.  LPLU will not be activated unless the
892  *  device autonegotiation advertisement meets standards of
893  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
894  *  This is a function pointer entry point only called by
895  *  PHY setup routines.
896  **/
897 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
898 {
899         struct e1000_phy_info *phy = &hw->phy;
900         u32 phy_ctrl;
901         s32 ret_val;
902         u16 data;
903
904         phy_ctrl = er32(PHY_CTRL);
905
906         if (!active) {
907                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
908                 ew32(PHY_CTRL, phy_ctrl);
909                 /*
910                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
911                  * during Dx states where the power conservation is most
912                  * important.  During driver activity we should enable
913                  * SmartSpeed, so performance is maintained.
914                  */
915                 if (phy->smart_speed == e1000_smart_speed_on) {
916                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
917                                            &data);
918                         if (ret_val)
919                                 return ret_val;
920
921                         data |= IGP01E1000_PSCFR_SMART_SPEED;
922                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
923                                            data);
924                         if (ret_val)
925                                 return ret_val;
926                 } else if (phy->smart_speed == e1000_smart_speed_off) {
927                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
928                                            &data);
929                         if (ret_val)
930                                 return ret_val;
931
932                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
933                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
934                                            data);
935                         if (ret_val)
936                                 return ret_val;
937                 }
938         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
939                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
940                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
941                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
942                 ew32(PHY_CTRL, phy_ctrl);
943
944                 /*
945                  * Call gig speed drop workaround on LPLU before accessing
946                  * any PHY registers
947                  */
948                 if ((hw->mac.type == e1000_ich8lan) &&
949                     (hw->phy.type == e1000_phy_igp_3))
950                         e1000e_gig_downshift_workaround_ich8lan(hw);
951
952                 /* When LPLU is enabled, we should disable SmartSpeed */
953                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
954                 if (ret_val)
955                         return ret_val;
956
957                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
958                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
959         }
960
961         return 0;
962 }
963
964 /**
965  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
966  *  @hw: pointer to the HW structure
967  *  @bank:  pointer to the variable that returns the active bank
968  *
969  *  Reads signature byte from the NVM using the flash access registers.
970  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
971  **/
972 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
973 {
974         u32 eecd;
975         struct e1000_nvm_info *nvm = &hw->nvm;
976         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
977         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
978         u8 sig_byte = 0;
979         s32 ret_val = 0;
980
981         switch (hw->mac.type) {
982         case e1000_ich8lan:
983         case e1000_ich9lan:
984                 eecd = er32(EECD);
985                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
986                     E1000_EECD_SEC1VAL_VALID_MASK) {
987                         if (eecd & E1000_EECD_SEC1VAL)
988                                 *bank = 1;
989                         else
990                                 *bank = 0;
991
992                         return 0;
993                 }
994                 hw_dbg(hw, "Unable to determine valid NVM bank via EEC - "
995                        "reading flash signature\n");
996                 /* fall-thru */
997         default:
998                 /* set bank to 0 in case flash read fails */
999                 *bank = 0;
1000
1001                 /* Check bank 0 */
1002                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1003                                                         &sig_byte);
1004                 if (ret_val)
1005                         return ret_val;
1006                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1007                     E1000_ICH_NVM_SIG_VALUE) {
1008                         *bank = 0;
1009                         return 0;
1010                 }
1011
1012                 /* Check bank 1 */
1013                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1014                                                         bank1_offset,
1015                                                         &sig_byte);
1016                 if (ret_val)
1017                         return ret_val;
1018                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1019                     E1000_ICH_NVM_SIG_VALUE) {
1020                         *bank = 1;
1021                         return 0;
1022                 }
1023
1024                 hw_dbg(hw, "ERROR: No valid NVM bank present\n");
1025                 return -E1000_ERR_NVM;
1026         }
1027
1028         return 0;
1029 }
1030
1031 /**
1032  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1033  *  @hw: pointer to the HW structure
1034  *  @offset: The offset (in bytes) of the word(s) to read.
1035  *  @words: Size of data to read in words
1036  *  @data: Pointer to the word(s) to read at offset.
1037  *
1038  *  Reads a word(s) from the NVM using the flash access registers.
1039  **/
1040 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1041                                   u16 *data)
1042 {
1043         struct e1000_nvm_info *nvm = &hw->nvm;
1044         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1045         u32 act_offset;
1046         s32 ret_val;
1047         u32 bank = 0;
1048         u16 i, word;
1049
1050         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1051             (words == 0)) {
1052                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1053                 return -E1000_ERR_NVM;
1054         }
1055
1056         ret_val = e1000_acquire_swflag_ich8lan(hw);
1057         if (ret_val)
1058                 goto out;
1059
1060         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1061         if (ret_val)
1062                 goto release;
1063
1064         act_offset = (bank) ? nvm->flash_bank_size : 0;
1065         act_offset += offset;
1066
1067         for (i = 0; i < words; i++) {
1068                 if ((dev_spec->shadow_ram) &&
1069                     (dev_spec->shadow_ram[offset+i].modified)) {
1070                         data[i] = dev_spec->shadow_ram[offset+i].value;
1071                 } else {
1072                         ret_val = e1000_read_flash_word_ich8lan(hw,
1073                                                                 act_offset + i,
1074                                                                 &word);
1075                         if (ret_val)
1076                                 break;
1077                         data[i] = word;
1078                 }
1079         }
1080
1081 release:
1082         e1000_release_swflag_ich8lan(hw);
1083
1084 out:
1085         if (ret_val)
1086                 hw_dbg(hw, "NVM read error: %d\n", ret_val);
1087
1088         return ret_val;
1089 }
1090
1091 /**
1092  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1093  *  @hw: pointer to the HW structure
1094  *
1095  *  This function does initial flash setup so that a new read/write/erase cycle
1096  *  can be started.
1097  **/
1098 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1099 {
1100         union ich8_hws_flash_status hsfsts;
1101         s32 ret_val = -E1000_ERR_NVM;
1102         s32 i = 0;
1103
1104         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1105
1106         /* Check if the flash descriptor is valid */
1107         if (hsfsts.hsf_status.fldesvalid == 0) {
1108                 hw_dbg(hw, "Flash descriptor invalid.  "
1109                          "SW Sequencing must be used.");
1110                 return -E1000_ERR_NVM;
1111         }
1112
1113         /* Clear FCERR and DAEL in hw status by writing 1 */
1114         hsfsts.hsf_status.flcerr = 1;
1115         hsfsts.hsf_status.dael = 1;
1116
1117         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1118
1119         /*
1120          * Either we should have a hardware SPI cycle in progress
1121          * bit to check against, in order to start a new cycle or
1122          * FDONE bit should be changed in the hardware so that it
1123          * is 1 after hardware reset, which can then be used as an
1124          * indication whether a cycle is in progress or has been
1125          * completed.
1126          */
1127
1128         if (hsfsts.hsf_status.flcinprog == 0) {
1129                 /*
1130                  * There is no cycle running at present,
1131                  * so we can start a cycle
1132                  * Begin by setting Flash Cycle Done.
1133                  */
1134                 hsfsts.hsf_status.flcdone = 1;
1135                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1136                 ret_val = 0;
1137         } else {
1138                 /*
1139                  * otherwise poll for sometime so the current
1140                  * cycle has a chance to end before giving up.
1141                  */
1142                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1143                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1144                         if (hsfsts.hsf_status.flcinprog == 0) {
1145                                 ret_val = 0;
1146                                 break;
1147                         }
1148                         udelay(1);
1149                 }
1150                 if (ret_val == 0) {
1151                         /*
1152                          * Successful in waiting for previous cycle to timeout,
1153                          * now set the Flash Cycle Done.
1154                          */
1155                         hsfsts.hsf_status.flcdone = 1;
1156                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1157                 } else {
1158                         hw_dbg(hw, "Flash controller busy, cannot get access");
1159                 }
1160         }
1161
1162         return ret_val;
1163 }
1164
1165 /**
1166  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1167  *  @hw: pointer to the HW structure
1168  *  @timeout: maximum time to wait for completion
1169  *
1170  *  This function starts a flash cycle and waits for its completion.
1171  **/
1172 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1173 {
1174         union ich8_hws_flash_ctrl hsflctl;
1175         union ich8_hws_flash_status hsfsts;
1176         s32 ret_val = -E1000_ERR_NVM;
1177         u32 i = 0;
1178
1179         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1180         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1181         hsflctl.hsf_ctrl.flcgo = 1;
1182         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1183
1184         /* wait till FDONE bit is set to 1 */
1185         do {
1186                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1187                 if (hsfsts.hsf_status.flcdone == 1)
1188                         break;
1189                 udelay(1);
1190         } while (i++ < timeout);
1191
1192         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1193                 return 0;
1194
1195         return ret_val;
1196 }
1197
1198 /**
1199  *  e1000_read_flash_word_ich8lan - Read word from flash
1200  *  @hw: pointer to the HW structure
1201  *  @offset: offset to data location
1202  *  @data: pointer to the location for storing the data
1203  *
1204  *  Reads the flash word at offset into data.  Offset is converted
1205  *  to bytes before read.
1206  **/
1207 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1208                                          u16 *data)
1209 {
1210         /* Must convert offset into bytes. */
1211         offset <<= 1;
1212
1213         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1214 }
1215
1216 /**
1217  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1218  *  @hw: pointer to the HW structure
1219  *  @offset: The offset of the byte to read.
1220  *  @data: Pointer to a byte to store the value read.
1221  *
1222  *  Reads a single byte from the NVM using the flash access registers.
1223  **/
1224 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1225                                          u8 *data)
1226 {
1227         s32 ret_val;
1228         u16 word = 0;
1229
1230         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1231         if (ret_val)
1232                 return ret_val;
1233
1234         *data = (u8)word;
1235
1236         return 0;
1237 }
1238
1239 /**
1240  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1241  *  @hw: pointer to the HW structure
1242  *  @offset: The offset (in bytes) of the byte or word to read.
1243  *  @size: Size of data to read, 1=byte 2=word
1244  *  @data: Pointer to the word to store the value read.
1245  *
1246  *  Reads a byte or word from the NVM using the flash access registers.
1247  **/
1248 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1249                                          u8 size, u16 *data)
1250 {
1251         union ich8_hws_flash_status hsfsts;
1252         union ich8_hws_flash_ctrl hsflctl;
1253         u32 flash_linear_addr;
1254         u32 flash_data = 0;
1255         s32 ret_val = -E1000_ERR_NVM;
1256         u8 count = 0;
1257
1258         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1259                 return -E1000_ERR_NVM;
1260
1261         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1262                             hw->nvm.flash_base_addr;
1263
1264         do {
1265                 udelay(1);
1266                 /* Steps */
1267                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1268                 if (ret_val != 0)
1269                         break;
1270
1271                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1272                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1273                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1274                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1275                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1276
1277                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1278
1279                 ret_val = e1000_flash_cycle_ich8lan(hw,
1280                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1281
1282                 /*
1283                  * Check if FCERR is set to 1, if set to 1, clear it
1284                  * and try the whole sequence a few more times, else
1285                  * read in (shift in) the Flash Data0, the order is
1286                  * least significant byte first msb to lsb
1287                  */
1288                 if (ret_val == 0) {
1289                         flash_data = er32flash(ICH_FLASH_FDATA0);
1290                         if (size == 1) {
1291                                 *data = (u8)(flash_data & 0x000000FF);
1292                         } else if (size == 2) {
1293                                 *data = (u16)(flash_data & 0x0000FFFF);
1294                         }
1295                         break;
1296                 } else {
1297                         /*
1298                          * If we've gotten here, then things are probably
1299                          * completely hosed, but if the error condition is
1300                          * detected, it won't hurt to give it another try...
1301                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1302                          */
1303                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1304                         if (hsfsts.hsf_status.flcerr == 1) {
1305                                 /* Repeat for some time before giving up. */
1306                                 continue;
1307                         } else if (hsfsts.hsf_status.flcdone == 0) {
1308                                 hw_dbg(hw, "Timeout error - flash cycle "
1309                                          "did not complete.");
1310                                 break;
1311                         }
1312                 }
1313         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1314
1315         return ret_val;
1316 }
1317
1318 /**
1319  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1320  *  @hw: pointer to the HW structure
1321  *  @offset: The offset (in bytes) of the word(s) to write.
1322  *  @words: Size of data to write in words
1323  *  @data: Pointer to the word(s) to write at offset.
1324  *
1325  *  Writes a byte or word to the NVM using the flash access registers.
1326  **/
1327 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1328                                    u16 *data)
1329 {
1330         struct e1000_nvm_info *nvm = &hw->nvm;
1331         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1332         s32 ret_val;
1333         u16 i;
1334
1335         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1336             (words == 0)) {
1337                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1338                 return -E1000_ERR_NVM;
1339         }
1340
1341         ret_val = e1000_acquire_swflag_ich8lan(hw);
1342         if (ret_val)
1343                 return ret_val;
1344
1345         for (i = 0; i < words; i++) {
1346                 dev_spec->shadow_ram[offset+i].modified = 1;
1347                 dev_spec->shadow_ram[offset+i].value = data[i];
1348         }
1349
1350         e1000_release_swflag_ich8lan(hw);
1351
1352         return 0;
1353 }
1354
1355 /**
1356  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1357  *  @hw: pointer to the HW structure
1358  *
1359  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1360  *  which writes the checksum to the shadow ram.  The changes in the shadow
1361  *  ram are then committed to the EEPROM by processing each bank at a time
1362  *  checking for the modified bit and writing only the pending changes.
1363  *  After a successful commit, the shadow ram is cleared and is ready for
1364  *  future writes.
1365  **/
1366 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1367 {
1368         struct e1000_nvm_info *nvm = &hw->nvm;
1369         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1370         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1371         s32 ret_val;
1372         u16 data;
1373
1374         ret_val = e1000e_update_nvm_checksum_generic(hw);
1375         if (ret_val)
1376                 goto out;
1377
1378         if (nvm->type != e1000_nvm_flash_sw)
1379                 goto out;
1380
1381         ret_val = e1000_acquire_swflag_ich8lan(hw);
1382         if (ret_val)
1383                 goto out;
1384
1385         /*
1386          * We're writing to the opposite bank so if we're on bank 1,
1387          * write to bank 0 etc.  We also need to erase the segment that
1388          * is going to be written
1389          */
1390         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1391         if (ret_val) {
1392                 e1000_release_swflag_ich8lan(hw);
1393                 goto out;
1394         }
1395
1396         if (bank == 0) {
1397                 new_bank_offset = nvm->flash_bank_size;
1398                 old_bank_offset = 0;
1399                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1400                 if (ret_val) {
1401                         e1000_release_swflag_ich8lan(hw);
1402                         goto out;
1403                 }
1404         } else {
1405                 old_bank_offset = nvm->flash_bank_size;
1406                 new_bank_offset = 0;
1407                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1408                 if (ret_val) {
1409                         e1000_release_swflag_ich8lan(hw);
1410                         goto out;
1411                 }
1412         }
1413
1414         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1415                 /*
1416                  * Determine whether to write the value stored
1417                  * in the other NVM bank or a modified value stored
1418                  * in the shadow RAM
1419                  */
1420                 if (dev_spec->shadow_ram[i].modified) {
1421                         data = dev_spec->shadow_ram[i].value;
1422                 } else {
1423                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
1424                                                                 old_bank_offset,
1425                                                                 &data);
1426                         if (ret_val)
1427                                 break;
1428                 }
1429
1430                 /*
1431                  * If the word is 0x13, then make sure the signature bits
1432                  * (15:14) are 11b until the commit has completed.
1433                  * This will allow us to write 10b which indicates the
1434                  * signature is valid.  We want to do this after the write
1435                  * has completed so that we don't mark the segment valid
1436                  * while the write is still in progress
1437                  */
1438                 if (i == E1000_ICH_NVM_SIG_WORD)
1439                         data |= E1000_ICH_NVM_SIG_MASK;
1440
1441                 /* Convert offset to bytes. */
1442                 act_offset = (i + new_bank_offset) << 1;
1443
1444                 udelay(100);
1445                 /* Write the bytes to the new bank. */
1446                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1447                                                                act_offset,
1448                                                                (u8)data);
1449                 if (ret_val)
1450                         break;
1451
1452                 udelay(100);
1453                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1454                                                           act_offset + 1,
1455                                                           (u8)(data >> 8));
1456                 if (ret_val)
1457                         break;
1458         }
1459
1460         /*
1461          * Don't bother writing the segment valid bits if sector
1462          * programming failed.
1463          */
1464         if (ret_val) {
1465                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1466                 hw_dbg(hw, "Flash commit failed.\n");
1467                 e1000_release_swflag_ich8lan(hw);
1468                 goto out;
1469         }
1470
1471         /*
1472          * Finally validate the new segment by setting bit 15:14
1473          * to 10b in word 0x13 , this can be done without an
1474          * erase as well since these bits are 11 to start with
1475          * and we need to change bit 14 to 0b
1476          */
1477         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1478         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1479         if (ret_val) {
1480                 e1000_release_swflag_ich8lan(hw);
1481                 goto out;
1482         }
1483         data &= 0xBFFF;
1484         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1485                                                        act_offset * 2 + 1,
1486                                                        (u8)(data >> 8));
1487         if (ret_val) {
1488                 e1000_release_swflag_ich8lan(hw);
1489                 goto out;
1490         }
1491
1492         /*
1493          * And invalidate the previously valid segment by setting
1494          * its signature word (0x13) high_byte to 0b. This can be
1495          * done without an erase because flash erase sets all bits
1496          * to 1's. We can write 1's to 0's without an erase
1497          */
1498         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1499         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1500         if (ret_val) {
1501                 e1000_release_swflag_ich8lan(hw);
1502                 goto out;
1503         }
1504
1505         /* Great!  Everything worked, we can now clear the cached entries. */
1506         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1507                 dev_spec->shadow_ram[i].modified = 0;
1508                 dev_spec->shadow_ram[i].value = 0xFFFF;
1509         }
1510
1511         e1000_release_swflag_ich8lan(hw);
1512
1513         /*
1514          * Reload the EEPROM, or else modifications will not appear
1515          * until after the next adapter reset.
1516          */
1517         e1000e_reload_nvm(hw);
1518         msleep(10);
1519
1520 out:
1521         if (ret_val)
1522                 hw_dbg(hw, "NVM update error: %d\n", ret_val);
1523
1524         return ret_val;
1525 }
1526
1527 /**
1528  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1529  *  @hw: pointer to the HW structure
1530  *
1531  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1532  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1533  *  calculated, in which case we need to calculate the checksum and set bit 6.
1534  **/
1535 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1536 {
1537         s32 ret_val;
1538         u16 data;
1539
1540         /*
1541          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1542          * needs to be fixed.  This bit is an indication that the NVM
1543          * was prepared by OEM software and did not calculate the
1544          * checksum...a likely scenario.
1545          */
1546         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1547         if (ret_val)
1548                 return ret_val;
1549
1550         if ((data & 0x40) == 0) {
1551                 data |= 0x40;
1552                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1553                 if (ret_val)
1554                         return ret_val;
1555                 ret_val = e1000e_update_nvm_checksum(hw);
1556                 if (ret_val)
1557                         return ret_val;
1558         }
1559
1560         return e1000e_validate_nvm_checksum_generic(hw);
1561 }
1562
1563 /**
1564  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1565  *  @hw: pointer to the HW structure
1566  *
1567  *  To prevent malicious write/erase of the NVM, set it to be read-only
1568  *  so that the hardware ignores all write/erase cycles of the NVM via
1569  *  the flash control registers.  The shadow-ram copy of the NVM will
1570  *  still be updated, however any updates to this copy will not stick
1571  *  across driver reloads.
1572  **/
1573 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1574 {
1575         union ich8_flash_protected_range pr0;
1576         union ich8_hws_flash_status hsfsts;
1577         u32 gfpreg;
1578         s32 ret_val;
1579
1580         ret_val = e1000_acquire_swflag_ich8lan(hw);
1581         if (ret_val)
1582                 return;
1583
1584         gfpreg = er32flash(ICH_FLASH_GFPREG);
1585
1586         /* Write-protect GbE Sector of NVM */
1587         pr0.regval = er32flash(ICH_FLASH_PR0);
1588         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1589         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1590         pr0.range.wpe = true;
1591         ew32flash(ICH_FLASH_PR0, pr0.regval);
1592
1593         /*
1594          * Lock down a subset of GbE Flash Control Registers, e.g.
1595          * PR0 to prevent the write-protection from being lifted.
1596          * Once FLOCKDN is set, the registers protected by it cannot
1597          * be written until FLOCKDN is cleared by a hardware reset.
1598          */
1599         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1600         hsfsts.hsf_status.flockdn = true;
1601         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1602
1603         e1000_release_swflag_ich8lan(hw);
1604 }
1605
1606 /**
1607  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1608  *  @hw: pointer to the HW structure
1609  *  @offset: The offset (in bytes) of the byte/word to read.
1610  *  @size: Size of data to read, 1=byte 2=word
1611  *  @data: The byte(s) to write to the NVM.
1612  *
1613  *  Writes one/two bytes to the NVM using the flash access registers.
1614  **/
1615 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1616                                           u8 size, u16 data)
1617 {
1618         union ich8_hws_flash_status hsfsts;
1619         union ich8_hws_flash_ctrl hsflctl;
1620         u32 flash_linear_addr;
1621         u32 flash_data = 0;
1622         s32 ret_val;
1623         u8 count = 0;
1624
1625         if (size < 1 || size > 2 || data > size * 0xff ||
1626             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1627                 return -E1000_ERR_NVM;
1628
1629         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1630                             hw->nvm.flash_base_addr;
1631
1632         do {
1633                 udelay(1);
1634                 /* Steps */
1635                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1636                 if (ret_val)
1637                         break;
1638
1639                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1640                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1641                 hsflctl.hsf_ctrl.fldbcount = size -1;
1642                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1643                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1644
1645                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1646
1647                 if (size == 1)
1648                         flash_data = (u32)data & 0x00FF;
1649                 else
1650                         flash_data = (u32)data;
1651
1652                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1653
1654                 /*
1655                  * check if FCERR is set to 1 , if set to 1, clear it
1656                  * and try the whole sequence a few more times else done
1657                  */
1658                 ret_val = e1000_flash_cycle_ich8lan(hw,
1659                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1660                 if (!ret_val)
1661                         break;
1662
1663                 /*
1664                  * If we're here, then things are most likely
1665                  * completely hosed, but if the error condition
1666                  * is detected, it won't hurt to give it another
1667                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1668                  */
1669                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1670                 if (hsfsts.hsf_status.flcerr == 1)
1671                         /* Repeat for some time before giving up. */
1672                         continue;
1673                 if (hsfsts.hsf_status.flcdone == 0) {
1674                         hw_dbg(hw, "Timeout error - flash cycle "
1675                                  "did not complete.");
1676                         break;
1677                 }
1678         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1679
1680         return ret_val;
1681 }
1682
1683 /**
1684  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1685  *  @hw: pointer to the HW structure
1686  *  @offset: The index of the byte to read.
1687  *  @data: The byte to write to the NVM.
1688  *
1689  *  Writes a single byte to the NVM using the flash access registers.
1690  **/
1691 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1692                                           u8 data)
1693 {
1694         u16 word = (u16)data;
1695
1696         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1697 }
1698
1699 /**
1700  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1701  *  @hw: pointer to the HW structure
1702  *  @offset: The offset of the byte to write.
1703  *  @byte: The byte to write to the NVM.
1704  *
1705  *  Writes a single byte to the NVM using the flash access registers.
1706  *  Goes through a retry algorithm before giving up.
1707  **/
1708 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1709                                                 u32 offset, u8 byte)
1710 {
1711         s32 ret_val;
1712         u16 program_retries;
1713
1714         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1715         if (!ret_val)
1716                 return ret_val;
1717
1718         for (program_retries = 0; program_retries < 100; program_retries++) {
1719                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1720                 udelay(100);
1721                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1722                 if (!ret_val)
1723                         break;
1724         }
1725         if (program_retries == 100)
1726                 return -E1000_ERR_NVM;
1727
1728         return 0;
1729 }
1730
1731 /**
1732  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1733  *  @hw: pointer to the HW structure
1734  *  @bank: 0 for first bank, 1 for second bank, etc.
1735  *
1736  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1737  *  bank N is 4096 * N + flash_reg_addr.
1738  **/
1739 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1740 {
1741         struct e1000_nvm_info *nvm = &hw->nvm;
1742         union ich8_hws_flash_status hsfsts;
1743         union ich8_hws_flash_ctrl hsflctl;
1744         u32 flash_linear_addr;
1745         /* bank size is in 16bit words - adjust to bytes */
1746         u32 flash_bank_size = nvm->flash_bank_size * 2;
1747         s32 ret_val;
1748         s32 count = 0;
1749         s32 iteration;
1750         s32 sector_size;
1751         s32 j;
1752
1753         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1754
1755         /*
1756          * Determine HW Sector size: Read BERASE bits of hw flash status
1757          * register
1758          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1759          *     consecutive sectors.  The start index for the nth Hw sector
1760          *     can be calculated as = bank * 4096 + n * 256
1761          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1762          *     The start index for the nth Hw sector can be calculated
1763          *     as = bank * 4096
1764          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1765          *     (ich9 only, otherwise error condition)
1766          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1767          */
1768         switch (hsfsts.hsf_status.berasesz) {
1769         case 0:
1770                 /* Hw sector size 256 */
1771                 sector_size = ICH_FLASH_SEG_SIZE_256;
1772                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1773                 break;
1774         case 1:
1775                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1776                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1777                 break;
1778         case 2:
1779                 if (hw->mac.type == e1000_ich9lan) {
1780                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1781                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1782                 } else {
1783                         return -E1000_ERR_NVM;
1784                 }
1785                 break;
1786         case 3:
1787                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1788                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1789                 break;
1790         default:
1791                 return -E1000_ERR_NVM;
1792         }
1793
1794         /* Start with the base address, then add the sector offset. */
1795         flash_linear_addr = hw->nvm.flash_base_addr;
1796         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1797
1798         for (j = 0; j < iteration ; j++) {
1799                 do {
1800                         /* Steps */
1801                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1802                         if (ret_val)
1803                                 return ret_val;
1804
1805                         /*
1806                          * Write a value 11 (block Erase) in Flash
1807                          * Cycle field in hw flash control
1808                          */
1809                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1810                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1811                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1812
1813                         /*
1814                          * Write the last 24 bits of an index within the
1815                          * block into Flash Linear address field in Flash
1816                          * Address.
1817                          */
1818                         flash_linear_addr += (j * sector_size);
1819                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1820
1821                         ret_val = e1000_flash_cycle_ich8lan(hw,
1822                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1823                         if (ret_val == 0)
1824                                 break;
1825
1826                         /*
1827                          * Check if FCERR is set to 1.  If 1,
1828                          * clear it and try the whole sequence
1829                          * a few more times else Done
1830                          */
1831                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1832                         if (hsfsts.hsf_status.flcerr == 1)
1833                                 /* repeat for some time before giving up */
1834                                 continue;
1835                         else if (hsfsts.hsf_status.flcdone == 0)
1836                                 return ret_val;
1837                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1838         }
1839
1840         return 0;
1841 }
1842
1843 /**
1844  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1845  *  @hw: pointer to the HW structure
1846  *  @data: Pointer to the LED settings
1847  *
1848  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1849  *  settings is all 0's or F's, set the LED default to a valid LED default
1850  *  setting.
1851  **/
1852 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1853 {
1854         s32 ret_val;
1855
1856         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1857         if (ret_val) {
1858                 hw_dbg(hw, "NVM Read Error\n");
1859                 return ret_val;
1860         }
1861
1862         if (*data == ID_LED_RESERVED_0000 ||
1863             *data == ID_LED_RESERVED_FFFF)
1864                 *data = ID_LED_DEFAULT_ICH8LAN;
1865
1866         return 0;
1867 }
1868
1869 /**
1870  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1871  *  @hw: pointer to the HW structure
1872  *
1873  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1874  *  register, so the the bus width is hard coded.
1875  **/
1876 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1877 {
1878         struct e1000_bus_info *bus = &hw->bus;
1879         s32 ret_val;
1880
1881         ret_val = e1000e_get_bus_info_pcie(hw);
1882
1883         /*
1884          * ICH devices are "PCI Express"-ish.  They have
1885          * a configuration space, but do not contain
1886          * PCI Express Capability registers, so bus width
1887          * must be hardcoded.
1888          */
1889         if (bus->width == e1000_bus_width_unknown)
1890                 bus->width = e1000_bus_width_pcie_x1;
1891
1892         return ret_val;
1893 }
1894
1895 /**
1896  *  e1000_reset_hw_ich8lan - Reset the hardware
1897  *  @hw: pointer to the HW structure
1898  *
1899  *  Does a full reset of the hardware which includes a reset of the PHY and
1900  *  MAC.
1901  **/
1902 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1903 {
1904         u32 ctrl, icr, kab;
1905         s32 ret_val;
1906
1907         /*
1908          * Prevent the PCI-E bus from sticking if there is no TLP connection
1909          * on the last TLP read/write transaction when MAC is reset.
1910          */
1911         ret_val = e1000e_disable_pcie_master(hw);
1912         if (ret_val) {
1913                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1914         }
1915
1916         hw_dbg(hw, "Masking off all interrupts\n");
1917         ew32(IMC, 0xffffffff);
1918
1919         /*
1920          * Disable the Transmit and Receive units.  Then delay to allow
1921          * any pending transactions to complete before we hit the MAC
1922          * with the global reset.
1923          */
1924         ew32(RCTL, 0);
1925         ew32(TCTL, E1000_TCTL_PSP);
1926         e1e_flush();
1927
1928         msleep(10);
1929
1930         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1931         if (hw->mac.type == e1000_ich8lan) {
1932                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1933                 ew32(PBA, E1000_PBA_8K);
1934                 /* Set Packet Buffer Size to 16k. */
1935                 ew32(PBS, E1000_PBS_16K);
1936         }
1937
1938         ctrl = er32(CTRL);
1939
1940         if (!e1000_check_reset_block(hw)) {
1941                 /*
1942                  * PHY HW reset requires MAC CORE reset at the same
1943                  * time to make sure the interface between MAC and the
1944                  * external PHY is reset.
1945                  */
1946                 ctrl |= E1000_CTRL_PHY_RST;
1947         }
1948         ret_val = e1000_acquire_swflag_ich8lan(hw);
1949         /* Whether or not the swflag was acquired, we need to reset the part */
1950         hw_dbg(hw, "Issuing a global reset to ich8lan\n");
1951         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1952         msleep(20);
1953
1954         if (!ret_val) {
1955                 /* release the swflag because it is not reset by
1956                  * hardware reset
1957                  */
1958                 e1000_release_swflag_ich8lan(hw);
1959         }
1960
1961         ret_val = e1000e_get_auto_rd_done(hw);
1962         if (ret_val) {
1963                 /*
1964                  * When auto config read does not complete, do not
1965                  * return with an error. This can happen in situations
1966                  * where there is no eeprom and prevents getting link.
1967                  */
1968                 hw_dbg(hw, "Auto Read Done did not complete\n");
1969         }
1970
1971         ew32(IMC, 0xffffffff);
1972         icr = er32(ICR);
1973
1974         kab = er32(KABGTXD);
1975         kab |= E1000_KABGTXD_BGSQLBIAS;
1976         ew32(KABGTXD, kab);
1977
1978         return ret_val;
1979 }
1980
1981 /**
1982  *  e1000_init_hw_ich8lan - Initialize the hardware
1983  *  @hw: pointer to the HW structure
1984  *
1985  *  Prepares the hardware for transmit and receive by doing the following:
1986  *   - initialize hardware bits
1987  *   - initialize LED identification
1988  *   - setup receive address registers
1989  *   - setup flow control
1990  *   - setup transmit descriptors
1991  *   - clear statistics
1992  **/
1993 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1994 {
1995         struct e1000_mac_info *mac = &hw->mac;
1996         u32 ctrl_ext, txdctl, snoop;
1997         s32 ret_val;
1998         u16 i;
1999
2000         e1000_initialize_hw_bits_ich8lan(hw);
2001
2002         /* Initialize identification LED */
2003         ret_val = e1000e_id_led_init(hw);
2004         if (ret_val) {
2005                 hw_dbg(hw, "Error initializing identification LED\n");
2006                 return ret_val;
2007         }
2008
2009         /* Setup the receive address. */
2010         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2011
2012         /* Zero out the Multicast HASH table */
2013         hw_dbg(hw, "Zeroing the MTA\n");
2014         for (i = 0; i < mac->mta_reg_count; i++)
2015                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2016
2017         /* Setup link and flow control */
2018         ret_val = e1000_setup_link_ich8lan(hw);
2019
2020         /* Set the transmit descriptor write-back policy for both queues */
2021         txdctl = er32(TXDCTL(0));
2022         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2023                  E1000_TXDCTL_FULL_TX_DESC_WB;
2024         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2025                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2026         ew32(TXDCTL(0), txdctl);
2027         txdctl = er32(TXDCTL(1));
2028         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2029                  E1000_TXDCTL_FULL_TX_DESC_WB;
2030         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2031                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2032         ew32(TXDCTL(1), txdctl);
2033
2034         /*
2035          * ICH8 has opposite polarity of no_snoop bits.
2036          * By default, we should use snoop behavior.
2037          */
2038         if (mac->type == e1000_ich8lan)
2039                 snoop = PCIE_ICH8_SNOOP_ALL;
2040         else
2041                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2042         e1000e_set_pcie_no_snoop(hw, snoop);
2043
2044         ctrl_ext = er32(CTRL_EXT);
2045         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2046         ew32(CTRL_EXT, ctrl_ext);
2047
2048         /*
2049          * Clear all of the statistics registers (clear on read).  It is
2050          * important that we do this after we have tried to establish link
2051          * because the symbol error count will increment wildly if there
2052          * is no link.
2053          */
2054         e1000_clear_hw_cntrs_ich8lan(hw);
2055
2056         return 0;
2057 }
2058 /**
2059  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2060  *  @hw: pointer to the HW structure
2061  *
2062  *  Sets/Clears required hardware bits necessary for correctly setting up the
2063  *  hardware for transmit and receive.
2064  **/
2065 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2066 {
2067         u32 reg;
2068
2069         /* Extended Device Control */
2070         reg = er32(CTRL_EXT);
2071         reg |= (1 << 22);
2072         ew32(CTRL_EXT, reg);
2073
2074         /* Transmit Descriptor Control 0 */
2075         reg = er32(TXDCTL(0));
2076         reg |= (1 << 22);
2077         ew32(TXDCTL(0), reg);
2078
2079         /* Transmit Descriptor Control 1 */
2080         reg = er32(TXDCTL(1));
2081         reg |= (1 << 22);
2082         ew32(TXDCTL(1), reg);
2083
2084         /* Transmit Arbitration Control 0 */
2085         reg = er32(TARC(0));
2086         if (hw->mac.type == e1000_ich8lan)
2087                 reg |= (1 << 28) | (1 << 29);
2088         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2089         ew32(TARC(0), reg);
2090
2091         /* Transmit Arbitration Control 1 */
2092         reg = er32(TARC(1));
2093         if (er32(TCTL) & E1000_TCTL_MULR)
2094                 reg &= ~(1 << 28);
2095         else
2096                 reg |= (1 << 28);
2097         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2098         ew32(TARC(1), reg);
2099
2100         /* Device Status */
2101         if (hw->mac.type == e1000_ich8lan) {
2102                 reg = er32(STATUS);
2103                 reg &= ~(1 << 31);
2104                 ew32(STATUS, reg);
2105         }
2106 }
2107
2108 /**
2109  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2110  *  @hw: pointer to the HW structure
2111  *
2112  *  Determines which flow control settings to use, then configures flow
2113  *  control.  Calls the appropriate media-specific link configuration
2114  *  function.  Assuming the adapter has a valid link partner, a valid link
2115  *  should be established.  Assumes the hardware has previously been reset
2116  *  and the transmitter and receiver are not enabled.
2117  **/
2118 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2119 {
2120         s32 ret_val;
2121
2122         if (e1000_check_reset_block(hw))
2123                 return 0;
2124
2125         /*
2126          * ICH parts do not have a word in the NVM to determine
2127          * the default flow control setting, so we explicitly
2128          * set it to full.
2129          */
2130         if (hw->fc.requested_mode == e1000_fc_default)
2131                 hw->fc.requested_mode = e1000_fc_full;
2132
2133         /*
2134          * Save off the requested flow control mode for use later.  Depending
2135          * on the link partner's capabilities, we may or may not use this mode.
2136          */
2137         hw->fc.current_mode = hw->fc.requested_mode;
2138
2139         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n",
2140                 hw->fc.current_mode);
2141
2142         /* Continue to configure the copper link. */
2143         ret_val = e1000_setup_copper_link_ich8lan(hw);
2144         if (ret_val)
2145                 return ret_val;
2146
2147         ew32(FCTTV, hw->fc.pause_time);
2148
2149         return e1000e_set_fc_watermarks(hw);
2150 }
2151
2152 /**
2153  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2154  *  @hw: pointer to the HW structure
2155  *
2156  *  Configures the kumeran interface to the PHY to wait the appropriate time
2157  *  when polling the PHY, then call the generic setup_copper_link to finish
2158  *  configuring the copper link.
2159  **/
2160 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2161 {
2162         u32 ctrl;
2163         s32 ret_val;
2164         u16 reg_data;
2165
2166         ctrl = er32(CTRL);
2167         ctrl |= E1000_CTRL_SLU;
2168         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2169         ew32(CTRL, ctrl);
2170
2171         /*
2172          * Set the mac to wait the maximum time between each iteration
2173          * and increase the max iterations when polling the phy;
2174          * this fixes erroneous timeouts at 10Mbps.
2175          */
2176         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2177         if (ret_val)
2178                 return ret_val;
2179         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2180         if (ret_val)
2181                 return ret_val;
2182         reg_data |= 0x3F;
2183         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2184         if (ret_val)
2185                 return ret_val;
2186
2187         if (hw->phy.type == e1000_phy_igp_3) {
2188                 ret_val = e1000e_copper_link_setup_igp(hw);
2189                 if (ret_val)
2190                         return ret_val;
2191         } else if (hw->phy.type == e1000_phy_bm) {
2192                 ret_val = e1000e_copper_link_setup_m88(hw);
2193                 if (ret_val)
2194                         return ret_val;
2195         }
2196
2197         if (hw->phy.type == e1000_phy_ife) {
2198                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2199                 if (ret_val)
2200                         return ret_val;
2201
2202                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2203
2204                 switch (hw->phy.mdix) {
2205                 case 1:
2206                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2207                         break;
2208                 case 2:
2209                         reg_data |= IFE_PMC_FORCE_MDIX;
2210                         break;
2211                 case 0:
2212                 default:
2213                         reg_data |= IFE_PMC_AUTO_MDIX;
2214                         break;
2215                 }
2216                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2217                 if (ret_val)
2218                         return ret_val;
2219         }
2220         return e1000e_setup_copper_link(hw);
2221 }
2222
2223 /**
2224  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2225  *  @hw: pointer to the HW structure
2226  *  @speed: pointer to store current link speed
2227  *  @duplex: pointer to store the current link duplex
2228  *
2229  *  Calls the generic get_speed_and_duplex to retrieve the current link
2230  *  information and then calls the Kumeran lock loss workaround for links at
2231  *  gigabit speeds.
2232  **/
2233 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2234                                           u16 *duplex)
2235 {
2236         s32 ret_val;
2237
2238         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2239         if (ret_val)
2240                 return ret_val;
2241
2242         if ((hw->mac.type == e1000_ich8lan) &&
2243             (hw->phy.type == e1000_phy_igp_3) &&
2244             (*speed == SPEED_1000)) {
2245                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2246         }
2247
2248         return ret_val;
2249 }
2250
2251 /**
2252  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2253  *  @hw: pointer to the HW structure
2254  *
2255  *  Work-around for 82566 Kumeran PCS lock loss:
2256  *  On link status change (i.e. PCI reset, speed change) and link is up and
2257  *  speed is gigabit-
2258  *    0) if workaround is optionally disabled do nothing
2259  *    1) wait 1ms for Kumeran link to come up
2260  *    2) check Kumeran Diagnostic register PCS lock loss bit
2261  *    3) if not set the link is locked (all is good), otherwise...
2262  *    4) reset the PHY
2263  *    5) repeat up to 10 times
2264  *  Note: this is only called for IGP3 copper when speed is 1gb.
2265  **/
2266 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2267 {
2268         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2269         u32 phy_ctrl;
2270         s32 ret_val;
2271         u16 i, data;
2272         bool link;
2273
2274         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2275                 return 0;
2276
2277         /*
2278          * Make sure link is up before proceeding.  If not just return.
2279          * Attempting this while link is negotiating fouled up link
2280          * stability
2281          */
2282         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2283         if (!link)
2284                 return 0;
2285
2286         for (i = 0; i < 10; i++) {
2287                 /* read once to clear */
2288                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2289                 if (ret_val)
2290                         return ret_val;
2291                 /* and again to get new status */
2292                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2293                 if (ret_val)
2294                         return ret_val;
2295
2296                 /* check for PCS lock */
2297                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2298                         return 0;
2299
2300                 /* Issue PHY reset */
2301                 e1000_phy_hw_reset(hw);
2302                 mdelay(5);
2303         }
2304         /* Disable GigE link negotiation */
2305         phy_ctrl = er32(PHY_CTRL);
2306         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2307                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2308         ew32(PHY_CTRL, phy_ctrl);
2309
2310         /*
2311          * Call gig speed drop workaround on Gig disable before accessing
2312          * any PHY registers
2313          */
2314         e1000e_gig_downshift_workaround_ich8lan(hw);
2315
2316         /* unable to acquire PCS lock */
2317         return -E1000_ERR_PHY;
2318 }
2319
2320 /**
2321  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2322  *  @hw: pointer to the HW structure
2323  *  @state: boolean value used to set the current Kumeran workaround state
2324  *
2325  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2326  *  /disabled - FALSE).
2327  **/
2328 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2329                                                  bool state)
2330 {
2331         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2332
2333         if (hw->mac.type != e1000_ich8lan) {
2334                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2335                 return;
2336         }
2337
2338         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2339 }
2340
2341 /**
2342  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2343  *  @hw: pointer to the HW structure
2344  *
2345  *  Workaround for 82566 power-down on D3 entry:
2346  *    1) disable gigabit link
2347  *    2) write VR power-down enable
2348  *    3) read it back
2349  *  Continue if successful, else issue LCD reset and repeat
2350  **/
2351 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2352 {
2353         u32 reg;
2354         u16 data;
2355         u8  retry = 0;
2356
2357         if (hw->phy.type != e1000_phy_igp_3)
2358                 return;
2359
2360         /* Try the workaround twice (if needed) */
2361         do {
2362                 /* Disable link */
2363                 reg = er32(PHY_CTRL);
2364                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2365                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2366                 ew32(PHY_CTRL, reg);
2367
2368                 /*
2369                  * Call gig speed drop workaround on Gig disable before
2370                  * accessing any PHY registers
2371                  */
2372                 if (hw->mac.type == e1000_ich8lan)
2373                         e1000e_gig_downshift_workaround_ich8lan(hw);
2374
2375                 /* Write VR power-down enable */
2376                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2377                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2378                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2379
2380                 /* Read it back and test */
2381                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2382                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2383                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2384                         break;
2385
2386                 /* Issue PHY reset and repeat at most one more time */
2387                 reg = er32(CTRL);
2388                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2389                 retry++;
2390         } while (retry);
2391 }
2392
2393 /**
2394  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2395  *  @hw: pointer to the HW structure
2396  *
2397  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2398  *  LPLU, Gig disable, MDIC PHY reset):
2399  *    1) Set Kumeran Near-end loopback
2400  *    2) Clear Kumeran Near-end loopback
2401  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2402  **/
2403 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2404 {
2405         s32 ret_val;
2406         u16 reg_data;
2407
2408         if ((hw->mac.type != e1000_ich8lan) ||
2409             (hw->phy.type != e1000_phy_igp_3))
2410                 return;
2411
2412         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2413                                       &reg_data);
2414         if (ret_val)
2415                 return;
2416         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2417         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2418                                        reg_data);
2419         if (ret_val)
2420                 return;
2421         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2422         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2423                                        reg_data);
2424 }
2425
2426 /**
2427  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2428  *  @hw: pointer to the HW structure
2429  *
2430  *  During S0 to Sx transition, it is possible the link remains at gig
2431  *  instead of negotiating to a lower speed.  Before going to Sx, set
2432  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2433  *  to a lower speed.
2434  *
2435  *  Should only be called for ICH9 and ICH10 devices.
2436  **/
2437 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2438 {
2439         u32 phy_ctrl;
2440
2441         if ((hw->mac.type == e1000_ich10lan) ||
2442             (hw->mac.type == e1000_ich9lan)) {
2443                 phy_ctrl = er32(PHY_CTRL);
2444                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2445                             E1000_PHY_CTRL_GBE_DISABLE;
2446                 ew32(PHY_CTRL, phy_ctrl);
2447         }
2448
2449         return;
2450 }
2451
2452 /**
2453  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2454  *  @hw: pointer to the HW structure
2455  *
2456  *  Return the LED back to the default configuration.
2457  **/
2458 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2459 {
2460         if (hw->phy.type == e1000_phy_ife)
2461                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2462
2463         ew32(LEDCTL, hw->mac.ledctl_default);
2464         return 0;
2465 }
2466
2467 /**
2468  *  e1000_led_on_ich8lan - Turn LEDs on
2469  *  @hw: pointer to the HW structure
2470  *
2471  *  Turn on the LEDs.
2472  **/
2473 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2474 {
2475         if (hw->phy.type == e1000_phy_ife)
2476                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2477                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2478
2479         ew32(LEDCTL, hw->mac.ledctl_mode2);
2480         return 0;
2481 }
2482
2483 /**
2484  *  e1000_led_off_ich8lan - Turn LEDs off
2485  *  @hw: pointer to the HW structure
2486  *
2487  *  Turn off the LEDs.
2488  **/
2489 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2490 {
2491         if (hw->phy.type == e1000_phy_ife)
2492                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2493                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2494
2495         ew32(LEDCTL, hw->mac.ledctl_mode1);
2496         return 0;
2497 }
2498
2499 /**
2500  *  e1000_get_cfg_done_ich8lan - Read config done bit
2501  *  @hw: pointer to the HW structure
2502  *
2503  *  Read the management control register for the config done bit for
2504  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
2505  *  to read the config done bit, so an error is *ONLY* logged and returns
2506  *  E1000_SUCCESS.  If we were to return with error, EEPROM-less silicon
2507  *  would not be able to be reset or change link.
2508  **/
2509 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
2510 {
2511         u32 bank = 0;
2512
2513         e1000e_get_cfg_done(hw);
2514
2515         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
2516         if (hw->mac.type != e1000_ich10lan) {
2517                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
2518                     (hw->phy.type == e1000_phy_igp_3)) {
2519                         e1000e_phy_init_script_igp3(hw);
2520                 }
2521         } else {
2522                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
2523                         /* Maybe we should do a basic PHY config */
2524                         hw_dbg(hw, "EEPROM not present\n");
2525                         return -E1000_ERR_CONFIG;
2526                 }
2527         }
2528
2529         return 0;
2530 }
2531
2532 /**
2533  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2534  *  @hw: pointer to the HW structure
2535  *
2536  *  Clears hardware counters specific to the silicon family and calls
2537  *  clear_hw_cntrs_generic to clear all general purpose counters.
2538  **/
2539 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2540 {
2541         u32 temp;
2542
2543         e1000e_clear_hw_cntrs_base(hw);
2544
2545         temp = er32(ALGNERRC);
2546         temp = er32(RXERRC);
2547         temp = er32(TNCRS);
2548         temp = er32(CEXTERR);
2549         temp = er32(TSCTC);
2550         temp = er32(TSCTFC);
2551
2552         temp = er32(MGTPRC);
2553         temp = er32(MGTPDC);
2554         temp = er32(MGTPTC);
2555
2556         temp = er32(IAC);
2557         temp = er32(ICRXOC);
2558
2559 }
2560
2561 static struct e1000_mac_operations ich8_mac_ops = {
2562         .check_mng_mode         = e1000_check_mng_mode_ich8lan,
2563         .check_for_link         = e1000e_check_for_copper_link,
2564         .cleanup_led            = e1000_cleanup_led_ich8lan,
2565         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2566         .get_bus_info           = e1000_get_bus_info_ich8lan,
2567         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2568         .led_on                 = e1000_led_on_ich8lan,
2569         .led_off                = e1000_led_off_ich8lan,
2570         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2571         .reset_hw               = e1000_reset_hw_ich8lan,
2572         .init_hw                = e1000_init_hw_ich8lan,
2573         .setup_link             = e1000_setup_link_ich8lan,
2574         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2575 };
2576
2577 static struct e1000_phy_operations ich8_phy_ops = {
2578         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2579         .check_reset_block      = e1000_check_reset_block_ich8lan,
2580         .commit_phy             = NULL,
2581         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2582         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
2583         .get_cable_length       = e1000e_get_cable_length_igp_2,
2584         .get_phy_info           = e1000_get_phy_info_ich8lan,
2585         .read_phy_reg           = e1000e_read_phy_reg_igp,
2586         .release_phy            = e1000_release_swflag_ich8lan,
2587         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2588         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2589         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2590         .write_phy_reg          = e1000e_write_phy_reg_igp,
2591 };
2592
2593 static struct e1000_nvm_operations ich8_nvm_ops = {
2594         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2595         .read_nvm               = e1000_read_nvm_ich8lan,
2596         .release_nvm            = e1000_release_swflag_ich8lan,
2597         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2598         .valid_led_default      = e1000_valid_led_default_ich8lan,
2599         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2600         .write_nvm              = e1000_write_nvm_ich8lan,
2601 };
2602
2603 struct e1000_info e1000_ich8_info = {
2604         .mac                    = e1000_ich8lan,
2605         .flags                  = FLAG_HAS_WOL
2606                                   | FLAG_IS_ICH
2607                                   | FLAG_RX_CSUM_ENABLED
2608                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2609                                   | FLAG_HAS_AMT
2610                                   | FLAG_HAS_FLASH
2611                                   | FLAG_APME_IN_WUC,
2612         .pba                    = 8,
2613         .get_variants           = e1000_get_variants_ich8lan,
2614         .mac_ops                = &ich8_mac_ops,
2615         .phy_ops                = &ich8_phy_ops,
2616         .nvm_ops                = &ich8_nvm_ops,
2617 };
2618
2619 struct e1000_info e1000_ich9_info = {
2620         .mac                    = e1000_ich9lan,
2621         .flags                  = FLAG_HAS_JUMBO_FRAMES
2622                                   | FLAG_IS_ICH
2623                                   | FLAG_HAS_WOL
2624                                   | FLAG_RX_CSUM_ENABLED
2625                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2626                                   | FLAG_HAS_AMT
2627                                   | FLAG_HAS_ERT
2628                                   | FLAG_HAS_FLASH
2629                                   | FLAG_APME_IN_WUC,
2630         .pba                    = 10,
2631         .get_variants           = e1000_get_variants_ich8lan,
2632         .mac_ops                = &ich8_mac_ops,
2633         .phy_ops                = &ich8_phy_ops,
2634         .nvm_ops                = &ich8_nvm_ops,
2635 };
2636
2637 struct e1000_info e1000_ich10_info = {
2638         .mac                    = e1000_ich10lan,
2639         .flags                  = FLAG_HAS_JUMBO_FRAMES
2640                                   | FLAG_IS_ICH
2641                                   | FLAG_HAS_WOL
2642                                   | FLAG_RX_CSUM_ENABLED
2643                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2644                                   | FLAG_HAS_AMT
2645                                   | FLAG_HAS_ERT
2646                                   | FLAG_HAS_FLASH
2647                                   | FLAG_APME_IN_WUC,
2648         .pba                    = 10,
2649         .get_variants           = e1000_get_variants_ich8lan,
2650         .mac_ops                = &ich8_mac_ops,
2651         .phy_ops                = &ich8_phy_ops,
2652         .nvm_ops                = &ich8_nvm_ops,
2653 };